stephen mathenge
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Level_estimation_Maesurement
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SX1276_LoRaRadio.cpp
00001 /** 00002 / _____) _ | | 00003 ( (____ _____ ____ _| |_ _____ ____| |__ 00004 \____ \| ___ | (_ _) ___ |/ ___) _ \ 00005 _____) ) ____| | | || |_| ____( (___| | | | 00006 (______/|_____)_|_|_| \__)_____)\____)_| |_| 00007 (C)2013 Semtech 00008 ___ _____ _ ___ _ _____ ___ ___ ___ ___ 00009 / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| 00010 \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| 00011 |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| 00012 embedded.connectivity.solutions=============== 00013 00014 Description: LoRaWAN stack layer that controls both MAC and PHY underneath 00015 00016 License: Revised BSD License, see LICENSE.TXT file include in the project 00017 00018 Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) 00019 00020 Copyright (c) 2017, Arm Limited and affiliates. 00021 00022 SPDX-License-Identifier: BSD-3-Clause 00023 */ 00024 00025 #include <stdio.h> 00026 #include <math.h> //rint 00027 #include <string.h> 00028 #include "mbed.h" 00029 #include "SX1276_LoRaRadio.h" 00030 #include "sx1276Regs-Fsk.h" 00031 #include "sx1276Regs-LoRa.h" 00032 00033 #ifdef DEVICE_SPI 00034 00035 /*! 00036 * Sync word for Private LoRa networks 00037 */ 00038 #define LORA_MAC_PRIVATE_SYNCWORD 0x12 00039 00040 /*! 00041 * Sync word for Public LoRa networks 00042 */ 00043 #define LORA_MAC_PUBLIC_SYNCWORD 0x34 00044 00045 /*! 00046 * SX1276 definitions 00047 */ 00048 #define XTAL_FREQ 32000000 00049 #define FREQ_STEP 61.03515625 00050 00051 /*! 00052 * Constant values need to compute the RSSI value 00053 */ 00054 #define RSSI_OFFSET_LF -164.0 00055 #define RSSI_OFFSET_HF -157.0 00056 #define RF_MID_BAND_THRESH 525000000 00057 00058 00059 /*! 00060 * FSK bandwidth definition 00061 */ 00062 typedef struct 00063 { 00064 uint32_t bandwidth; 00065 uint8_t register_value; 00066 } fsk_bw_t; 00067 00068 /*! 00069 * Radio registers definition 00070 */ 00071 typedef struct 00072 { 00073 uint8_t modem; 00074 uint8_t addr; 00075 uint8_t value; 00076 } radio_registers_t; 00077 00078 #define RADIO_INIT_REGISTERS_VALUE \ 00079 { \ 00080 { MODEM_FSK , REG_LNA , 0x23 },\ 00081 { MODEM_FSK , REG_RXCONFIG , 0x1E },\ 00082 { MODEM_FSK , REG_RSSICONFIG , 0xD2 },\ 00083 { MODEM_FSK , REG_AFCFEI , 0x01 },\ 00084 { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },\ 00085 { MODEM_FSK , REG_OSC , 0x07 },\ 00086 { MODEM_FSK , REG_SYNCCONFIG , 0x12 },\ 00087 { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },\ 00088 { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },\ 00089 { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },\ 00090 { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },\ 00091 { MODEM_FSK , REG_FIFOTHRESH , 0x8F },\ 00092 { MODEM_FSK , REG_IMAGECAL , 0x02 },\ 00093 { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },\ 00094 { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },\ 00095 { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },\ 00096 } 00097 00098 static const fsk_bw_t fsk_bandwidths[] = 00099 { 00100 { 2600 , 0x17 }, 00101 { 3100 , 0x0F }, 00102 { 3900 , 0x07 }, 00103 { 5200 , 0x16 }, 00104 { 6300 , 0x0E }, 00105 { 7800 , 0x06 }, 00106 { 10400 , 0x15 }, 00107 { 12500 , 0x0D }, 00108 { 15600 , 0x05 }, 00109 { 20800 , 0x14 }, 00110 { 25000 , 0x0C }, 00111 { 31300 , 0x04 }, 00112 { 41700 , 0x13 }, 00113 { 50000 , 0x0B }, 00114 { 62500 , 0x03 }, 00115 { 83333 , 0x12 }, 00116 { 100000, 0x0A }, 00117 { 125000, 0x02 }, 00118 { 166700, 0x11 }, 00119 { 200000, 0x09 }, 00120 { 250000, 0x01 }, 00121 { 300000, 0x00 }, // Invalid bandwidth 00122 }; 00123 00124 /** 00125 * SPI read/write masks 00126 */ 00127 #define SPI_WRITE_CMD 0x80 00128 #define SPI_READ_CMD 0x7F 00129 00130 /** 00131 * Signals 00132 */ 00133 #define SIG_DIO0 0x01 00134 #define SIG_DIO1 0x02 00135 #define SIG_DIO2 0x04 00136 #define SIG_DIO3 0x08 00137 #define SIG_DIO4 0x10 00138 #define SIG_DIO5 0x20 00139 #define SIG_TIMOUT 0x40 00140 00141 /** 00142 * Radio hardware registers initialization 00143 */ 00144 static const radio_registers_t radio_reg_init[] = RADIO_INIT_REGISTERS_VALUE; 00145 00146 enum RadioVariant { 00147 SX1276UNDEFINED = 0, 00148 SX1276MB1LAS, 00149 SX1276MB1MAS 00150 }; 00151 00152 #ifdef MBED_SX1276_LORA_RADIO_SPI_FREQUENCY 00153 #define SPI_FREQUENCY MBED_SX1276_LORA_RADIO_SPI_FREQUENCY 00154 #else 00155 #define SPI_FREQUENCY 8000000 00156 #endif 00157 00158 /** 00159 * Constructor 00160 */ 00161 SX1276_LoRaRadio::SX1276_LoRaRadio(PinName spi_mosi, 00162 PinName spi_miso, 00163 PinName spi_sclk, 00164 PinName nss, 00165 PinName reset, 00166 PinName dio0, 00167 PinName dio1, 00168 PinName dio2, 00169 PinName dio3, 00170 PinName dio4, 00171 PinName dio5, 00172 PinName rf_switch_ctl1, 00173 PinName rf_switch_ctl2, 00174 PinName txctl, 00175 PinName rxctl, 00176 PinName antswitch, 00177 PinName pwr_amp_ctl, 00178 PinName tcxo) 00179 : _spi(spi_mosi, spi_miso, spi_sclk), 00180 _chip_select(nss, 1), 00181 _reset_ctl(reset), 00182 _dio0_ctl(dio0), _dio1_ctl(dio1), _dio2_ctl(dio2), _dio3_ctl(dio3), _dio4_ctl(dio4), _dio5_ctl(dio5), 00183 _rf_switch_ctl1(rf_switch_ctl1, 0), _rf_switch_ctl2(rf_switch_ctl2, 0), 00184 _txctl(txctl, 0), _rxctl(rxctl, 0), 00185 _ant_switch(antswitch, PIN_INPUT, PullUp, 0), 00186 _pwr_amp_ctl(pwr_amp_ctl), 00187 _tcxo(tcxo) 00188 00189 #ifdef MBED_CONF_RTOS_PRESENT 00190 , irq_thread(osPriorityRealtime, 1024) 00191 #endif 00192 { 00193 _rf_ctrls.ant_switch = antswitch; 00194 _rf_ctrls.pwr_amp_ctl = pwr_amp_ctl; 00195 _rf_ctrls.rf_switch_ctl1 = rf_switch_ctl1; 00196 _rf_ctrls.rf_switch_ctl2 = rf_switch_ctl2; 00197 _rf_ctrls.rxctl = rxctl; 00198 _rf_ctrls.txctl = txctl; 00199 _rf_ctrls.tcxo = tcxo; 00200 00201 _dio4_pin = dio4; 00202 _dio5_pin = dio5; 00203 00204 _radio_events = NULL; 00205 00206 if (tcxo != NC) { 00207 _tcxo = 1; 00208 } 00209 00210 #ifdef MBED_CONF_RTOS_PRESENT 00211 irq_thread.start(mbed::callback(this, &SX1276_LoRaRadio::rf_irq_task)); 00212 #endif 00213 } 00214 00215 /** 00216 * Destructor 00217 */ 00218 SX1276_LoRaRadio::~SX1276_LoRaRadio() 00219 { 00220 00221 } 00222 00223 /***************************************************************************** 00224 * Public APIs * 00225 ****************************************************************************/ 00226 /** 00227 * Acquire lock 00228 */ 00229 void SX1276_LoRaRadio::lock(void) 00230 { 00231 mutex.lock(); 00232 } 00233 00234 /** 00235 * Release lock 00236 */ 00237 void SX1276_LoRaRadio::unlock(void) 00238 { 00239 mutex.unlock(); 00240 } 00241 00242 /** 00243 * Initializes radio module 00244 */ 00245 void SX1276_LoRaRadio::init_radio(radio_events_t *events) 00246 { 00247 _radio_events = events; 00248 00249 // Reset the radio transceiver 00250 radio_reset(); 00251 00252 // Setup radio variant type 00253 set_sx1276_variant_type(); 00254 00255 // setup SPI frequency 00256 // default is 8MHz although, configurable through 00257 // SPI_FREQUENCY macro 00258 setup_spi(); 00259 00260 // Calibrate radio receiver chain 00261 rx_chain_calibration(); 00262 00263 // set radio mode to sleep 00264 set_operation_mode(RF_OPMODE_SLEEP); 00265 00266 // Setup radio registers to defaults 00267 setup_registers(); 00268 00269 // set modem type - defaults to FSK here 00270 set_modem(MODEM_FSK); 00271 00272 // set state to be idle 00273 _rf_settings.state = RF_IDLE; 00274 00275 // Setup interrupts on DIO pins 00276 setup_interrupts(); 00277 } 00278 00279 /** 00280 * Can be used by application/stack or the driver itself 00281 */ 00282 void SX1276_LoRaRadio::radio_reset() 00283 { 00284 _reset_ctl.output(); 00285 _reset_ctl = 0; 00286 wait_ms(2); 00287 _reset_ctl.input(); 00288 wait_ms(6); 00289 } 00290 00291 /** 00292 * TODO: The purpose of this API is unclear. 00293 * Need to start an internal discussion. 00294 */ 00295 bool SX1276_LoRaRadio::check_rf_frequency(uint32_t frequency) 00296 { 00297 // Implement check. Currently all frequencies are supported ? What band ? 00298 return true; 00299 } 00300 00301 /** 00302 * Returns current status of the radio state machine 00303 */ 00304 uint8_t SX1276_LoRaRadio::get_status(void) 00305 { 00306 return _rf_settings.state; 00307 } 00308 00309 /** 00310 * Sets up carrier frequency 00311 */ 00312 void SX1276_LoRaRadio::set_channel(uint32_t freq) 00313 { 00314 _rf_settings.channel = freq; 00315 freq = (uint32_t) ((double) freq / (double) FREQ_STEP); 00316 write_to_register(REG_FRFMSB, (uint8_t) ((freq >> 16) & 0xFF)); 00317 write_to_register(REG_FRFMID, (uint8_t) ((freq >> 8) & 0xFF)); 00318 write_to_register(REG_FRFLSB, (uint8_t) (freq & 0xFF)); 00319 } 00320 00321 /** 00322 * Generates 32 bit random number based upon RSSI monitoring 00323 * Used for various calculation by the stack for example dev nonce 00324 * 00325 * When this API is used modem is set in LoRa mode and all interrupts are 00326 * masked. If the user had been using FSK mode, it should be noted that a 00327 * change of mode is required again because the registers have changed. 00328 * In addition to that RX and TX configuration APIs should be called again in 00329 * order to have correct desires setup. 00330 */ 00331 uint32_t SX1276_LoRaRadio::random( void ) 00332 { 00333 uint8_t i; 00334 uint32_t rnd = 0; 00335 00336 /* 00337 * Radio setup for random number generation 00338 */ 00339 set_modem( MODEM_LORA ); 00340 00341 // Disable LoRa modem interrupts 00342 write_to_register( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | 00343 RFLR_IRQFLAGS_RXDONE | 00344 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00345 RFLR_IRQFLAGS_VALIDHEADER | 00346 RFLR_IRQFLAGS_TXDONE | 00347 RFLR_IRQFLAGS_CADDONE | 00348 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00349 RFLR_IRQFLAGS_CADDETECTED ); 00350 00351 // Set radio in continuous reception 00352 set_operation_mode(RF_OPMODE_RECEIVER); 00353 00354 for (i = 0; i < 32; i++) { 00355 wait_ms(1); 00356 // Unfiltered RSSI value reading. Only takes the LSB value 00357 rnd |= ((uint32_t) read_register( REG_LR_RSSIWIDEBAND) & 0x01) << i; 00358 } 00359 00360 sleep(); 00361 00362 return rnd; 00363 } 00364 00365 /** 00366 * Sets up receiver related configurations 00367 * 00368 * Must be called before setting the radio in rx mode 00369 */ 00370 void SX1276_LoRaRadio::set_rx_config(radio_modems_t modem, uint32_t bandwidth, 00371 uint32_t datarate, uint8_t coderate, 00372 uint32_t bandwidth_afc, 00373 uint16_t preamble_len, 00374 uint16_t symb_timeout, bool fix_len, 00375 uint8_t payload_len, bool crc_on, 00376 bool freq_hop_on, uint8_t hop_period, 00377 bool iq_inverted, bool rx_continuous) 00378 { 00379 set_modem(modem); 00380 00381 switch (modem) { 00382 case MODEM_FSK: 00383 _rf_settings.fsk.bandwidth = bandwidth; 00384 _rf_settings.fsk.datarate = datarate; 00385 _rf_settings.fsk.bandwidth_afc = bandwidth_afc; 00386 _rf_settings.fsk.fix_len = fix_len; 00387 _rf_settings.fsk.payload_len = payload_len; 00388 _rf_settings.fsk.crc_on = crc_on; 00389 _rf_settings.fsk.iq_inverted = iq_inverted; 00390 _rf_settings.fsk.rx_continuous = rx_continuous; 00391 _rf_settings.fsk.preamble_len = preamble_len; 00392 _rf_settings.fsk.rx_single_timeout = symb_timeout 00393 * ((1.0 / (double) datarate) * 8.0) * 1e3; 00394 00395 datarate = (uint16_t) ((double) XTAL_FREQ / (double) datarate); 00396 write_to_register(REG_BITRATEMSB, (uint8_t) (datarate >> 8)); 00397 write_to_register(REG_BITRATELSB, (uint8_t) (datarate & 0xFF)); 00398 00399 write_to_register(REG_RXBW, get_fsk_bw_reg_val(bandwidth)); 00400 write_to_register(REG_AFCBW, get_fsk_bw_reg_val(bandwidth_afc)); 00401 00402 write_to_register(REG_PREAMBLEMSB, 00403 (uint8_t) ((preamble_len >> 8) & 0xFF)); 00404 write_to_register(REG_PREAMBLELSB, (uint8_t) (preamble_len & 0xFF)); 00405 00406 if (fix_len == 1) { 00407 write_to_register(REG_PAYLOADLENGTH, payload_len); 00408 } else { 00409 write_to_register(REG_PAYLOADLENGTH, 0xFF); // Set payload length to the maximum 00410 } 00411 00412 write_to_register( 00413 REG_PACKETCONFIG1, 00414 (read_register(REG_PACKETCONFIG1) 00415 & RF_PACKETCONFIG1_CRC_MASK 00416 & RF_PACKETCONFIG1_PACKETFORMAT_MASK) 00417 | ((fix_len == 1) ? 00418 RF_PACKETCONFIG1_PACKETFORMAT_FIXED : 00419 RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE) 00420 | (crc_on << 4)); 00421 00422 // TODO why packet mode 2 ? 00423 write_to_register(REG_PACKETCONFIG2, (read_register(REG_PACKETCONFIG2) 00424 | RF_PACKETCONFIG2_DATAMODE_PACKET)); 00425 00426 break; 00427 00428 case MODEM_LORA: 00429 00430 if (bandwidth > 2) { 00431 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00432 while (1) 00433 ; 00434 // TODO Return a proper error from here 00435 } 00436 00437 // stupid hack. TODO think something better 00438 bandwidth+=7; 00439 00440 _rf_settings.lora.bandwidth = bandwidth; 00441 _rf_settings.lora.datarate = datarate; 00442 _rf_settings.lora.coderate = coderate; 00443 _rf_settings.lora.preamble_len = preamble_len; 00444 _rf_settings.lora.fix_len = fix_len; 00445 _rf_settings.lora.payload_len = payload_len; 00446 _rf_settings.lora.crc_on = crc_on; 00447 _rf_settings.lora.freq_hop_on = freq_hop_on; 00448 _rf_settings.lora.hop_period = hop_period; 00449 _rf_settings.lora.iq_inverted = iq_inverted; 00450 _rf_settings.lora.rx_continuous = rx_continuous; 00451 00452 if (datarate > 12) { 00453 datarate = 12; 00454 } else if (datarate < 6) { 00455 datarate = 6; 00456 } 00457 00458 if (((bandwidth == 7) && ((datarate == 11) || (datarate == 12))) 00459 || ((bandwidth == 8) && (datarate == 12))) { 00460 _rf_settings.lora.low_datarate_optimize = 0x01; 00461 } else { 00462 _rf_settings.lora.low_datarate_optimize = 0x00; 00463 } 00464 00465 write_to_register(REG_LR_MODEMCONFIG1, (read_register( REG_LR_MODEMCONFIG1) 00466 & RFLR_MODEMCONFIG1_BW_MASK 00467 & RFLR_MODEMCONFIG1_CODINGRATE_MASK 00468 & RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK) 00469 | (bandwidth << 4) 00470 | (coderate << 1) | fix_len); 00471 00472 write_to_register(REG_LR_MODEMCONFIG2, (read_register( REG_LR_MODEMCONFIG2) 00473 & RFLR_MODEMCONFIG2_SF_MASK 00474 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 00475 & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK) 00476 | (datarate << 4) 00477 | (crc_on << 2) 00478 | ((symb_timeout >> 8) 00479 & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK)); 00480 00481 write_to_register(REG_LR_MODEMCONFIG3, (read_register( REG_LR_MODEMCONFIG3) 00482 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK) 00483 | (_rf_settings.lora.low_datarate_optimize << 3)); 00484 00485 write_to_register(REG_LR_SYMBTIMEOUTLSB, (uint8_t) (symb_timeout & 0xFF)); 00486 00487 write_to_register(REG_LR_PREAMBLEMSB, (uint8_t) ((preamble_len >> 8) & 0xFF)); 00488 write_to_register(REG_LR_PREAMBLELSB, (uint8_t) (preamble_len & 0xFF)); 00489 00490 if (fix_len == 1) { 00491 write_to_register(REG_LR_PAYLOADLENGTH, payload_len); 00492 } 00493 00494 if (_rf_settings.lora.freq_hop_on == true) { 00495 write_to_register(REG_LR_PLLHOP, (read_register( REG_LR_PLLHOP) 00496 & RFLR_PLLHOP_FASTHOP_MASK) 00497 | RFLR_PLLHOP_FASTHOP_ON); 00498 write_to_register(REG_LR_HOPPERIOD,_rf_settings.lora.hop_period); 00499 } 00500 00501 if ((bandwidth == 9) && (_rf_settings.channel > RF_MID_BAND_THRESH)) { 00502 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00503 write_to_register(REG_LR_TEST36, 0x02); 00504 write_to_register(REG_LR_TEST3A, 0x64); 00505 } else if (bandwidth == 9) { 00506 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00507 write_to_register(REG_LR_TEST36, 0x02); 00508 write_to_register(REG_LR_TEST3A, 0x7F); 00509 } else { 00510 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth 00511 write_to_register(REG_LR_TEST36, 0x03); 00512 } 00513 00514 if (datarate == 6) { 00515 write_to_register(REG_LR_DETECTOPTIMIZE, (read_register(REG_LR_DETECTOPTIMIZE) 00516 & RFLR_DETECTIONOPTIMIZE_MASK) 00517 | RFLR_DETECTIONOPTIMIZE_SF6); 00518 write_to_register(REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF6); 00519 } else { 00520 write_to_register(REG_LR_DETECTOPTIMIZE, (read_register(REG_LR_DETECTOPTIMIZE) 00521 & RFLR_DETECTIONOPTIMIZE_MASK) 00522 | RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12); 00523 write_to_register(REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF7_TO_SF12); 00524 } 00525 break; 00526 00527 default: 00528 break; 00529 } 00530 } 00531 00532 /** 00533 * Sets up transmitter related configuration 00534 * 00535 * Must be called before putting the radio module in Tx mode or trying 00536 * to send 00537 */ 00538 void SX1276_LoRaRadio::set_tx_config(radio_modems_t modem, int8_t power, 00539 uint32_t fdev, uint32_t bandwidth, 00540 uint32_t datarate, uint8_t coderate, 00541 uint16_t preamble_len, bool fix_len, 00542 bool crc_on, bool freq_hop_on, 00543 uint8_t hop_period, bool iq_inverted, 00544 uint32_t timeout) 00545 { 00546 set_modem(modem); 00547 set_rf_tx_power(power); 00548 00549 switch (modem) { 00550 case MODEM_FSK: 00551 _rf_settings.fsk.power = power; 00552 _rf_settings.fsk.f_dev = fdev; 00553 _rf_settings.fsk.bandwidth = bandwidth; 00554 _rf_settings.fsk.datarate = datarate; 00555 _rf_settings.fsk.preamble_len = preamble_len; 00556 _rf_settings.fsk.fix_len = fix_len; 00557 _rf_settings.fsk.crc_on = crc_on; 00558 _rf_settings.fsk.iq_inverted = iq_inverted; 00559 _rf_settings.fsk.tx_timeout = timeout; 00560 00561 fdev = (uint16_t) ((double) fdev / (double) FREQ_STEP); 00562 write_to_register( REG_FDEVMSB, (uint8_t) (fdev >> 8)); 00563 write_to_register( REG_FDEVLSB, (uint8_t) (fdev & 0xFF)); 00564 00565 datarate = (uint16_t) ((double) XTAL_FREQ / (double) datarate); 00566 write_to_register( REG_BITRATEMSB, (uint8_t) (datarate >> 8)); 00567 write_to_register( REG_BITRATELSB, (uint8_t) (datarate & 0xFF)); 00568 00569 write_to_register( REG_PREAMBLEMSB, (preamble_len >> 8) & 0x00FF); 00570 write_to_register( REG_PREAMBLELSB, preamble_len & 0xFF); 00571 00572 write_to_register(REG_PACKETCONFIG1, 00573 (read_register( REG_PACKETCONFIG1) & 00574 RF_PACKETCONFIG1_CRC_MASK & 00575 RF_PACKETCONFIG1_PACKETFORMAT_MASK) 00576 | ((fix_len == 1) ? 00577 RF_PACKETCONFIG1_PACKETFORMAT_FIXED : 00578 RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE) 00579 | (crc_on << 4)); 00580 write_to_register(REG_PACKETCONFIG2, 00581 (read_register( REG_PACKETCONFIG2) 00582 | RF_PACKETCONFIG2_DATAMODE_PACKET)); 00583 00584 break; 00585 00586 case MODEM_LORA: 00587 _rf_settings.lora.power = power; 00588 if (bandwidth > 2) { 00589 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00590 while (1) 00591 ; 00592 } 00593 bandwidth += 7; 00594 _rf_settings.lora.bandwidth = bandwidth; 00595 _rf_settings.lora.datarate = datarate; 00596 _rf_settings.lora.coderate = coderate; 00597 _rf_settings.lora.preamble_len = preamble_len; 00598 _rf_settings.lora.fix_len = fix_len; 00599 _rf_settings.lora.freq_hop_on = freq_hop_on; 00600 _rf_settings.lora.hop_period = hop_period; 00601 _rf_settings.lora.crc_on = crc_on; 00602 _rf_settings.lora.iq_inverted = iq_inverted; 00603 _rf_settings.lora.tx_timeout = timeout; 00604 00605 if (datarate > 12) { 00606 datarate = 12; 00607 } else if (datarate < 6) { 00608 datarate = 6; 00609 } 00610 if (((bandwidth == 7) && ((datarate == 11) || (datarate == 12))) 00611 || ((bandwidth == 8) && (datarate == 12))) { 00612 _rf_settings.lora.low_datarate_optimize = 0x01; 00613 } else { 00614 _rf_settings.lora.low_datarate_optimize = 0x00; 00615 } 00616 00617 if (_rf_settings.lora.freq_hop_on == true) { 00618 write_to_register(REG_LR_PLLHOP, (read_register(REG_LR_PLLHOP) 00619 & RFLR_PLLHOP_FASTHOP_MASK) 00620 | RFLR_PLLHOP_FASTHOP_ON); 00621 write_to_register( REG_LR_HOPPERIOD, _rf_settings.lora.hop_period); 00622 } 00623 00624 write_to_register(REG_LR_MODEMCONFIG1, (read_register( REG_LR_MODEMCONFIG1) 00625 & RFLR_MODEMCONFIG1_BW_MASK 00626 & RFLR_MODEMCONFIG1_CODINGRATE_MASK 00627 & RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK) | (bandwidth << 4) 00628 | (coderate << 1) | fix_len); 00629 00630 write_to_register(REG_LR_MODEMCONFIG2, (read_register( REG_LR_MODEMCONFIG2) 00631 & RFLR_MODEMCONFIG2_SF_MASK 00632 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK) 00633 | (datarate << 4) 00634 | (crc_on << 2)); 00635 00636 write_to_register(REG_LR_MODEMCONFIG3, (read_register(REG_LR_MODEMCONFIG3) 00637 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK) 00638 | (_rf_settings.lora.low_datarate_optimize << 3)); 00639 00640 write_to_register(REG_LR_PREAMBLEMSB, (preamble_len >> 8) & 0x00FF); 00641 write_to_register(REG_LR_PREAMBLELSB, preamble_len & 0xFF); 00642 00643 if (datarate == 6) { 00644 write_to_register(REG_LR_DETECTOPTIMIZE, (read_register( REG_LR_DETECTOPTIMIZE) 00645 & RFLR_DETECTIONOPTIMIZE_MASK) | RFLR_DETECTIONOPTIMIZE_SF6); 00646 write_to_register(REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF6); 00647 } else { 00648 write_to_register(REG_LR_DETECTOPTIMIZE, (read_register( REG_LR_DETECTOPTIMIZE) 00649 & RFLR_DETECTIONOPTIMIZE_MASK) | RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12); 00650 write_to_register( REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF7_TO_SF12); 00651 } 00652 00653 break; 00654 } 00655 } 00656 00657 /** 00658 * Calculates time on Air i.e., dwell time for a single packet 00659 * 00660 * Crucial for the stack in order to calculate dwell time so as to control 00661 * duty cycling. 00662 */ 00663 uint32_t SX1276_LoRaRadio::time_on_air(radio_modems_t modem, uint8_t pkt_len) 00664 { 00665 uint32_t airTime = 0; 00666 00667 switch (modem) { 00668 case MODEM_FSK: 00669 airTime = 00670 rint((8 * (_rf_settings.fsk.preamble_len 00671 + ((read_register( REG_SYNCCONFIG) 00672 & ~RF_SYNCCONFIG_SYNCSIZE_MASK) + 1) 00673 + ((_rf_settings.fsk.fix_len == 0x01) ? 00674 0.0 : 1.0) 00675 + (((read_register( REG_PACKETCONFIG1) 00676 & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK) 00677 != 0x00) ? 1.0 : 0) + pkt_len 00678 + ((_rf_settings.fsk.crc_on == 0x01) ? 00679 2.0 : 0)) 00680 / _rf_settings.fsk.datarate) * 1e3); 00681 00682 break; 00683 case MODEM_LORA: 00684 double bw = 0.0; 00685 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported 00686 switch (_rf_settings.lora.bandwidth) { 00687 //case 0: // 7.8 kHz 00688 // bw = 78e2; 00689 // break; 00690 //case 1: // 10.4 kHz 00691 // bw = 104e2; 00692 // break; 00693 //case 2: // 15.6 kHz 00694 // bw = 156e2; 00695 // break; 00696 //case 3: // 20.8 kHz 00697 // bw = 208e2; 00698 // break; 00699 //case 4: // 31.2 kHz 00700 // bw = 312e2; 00701 // break; 00702 //case 5: // 41.4 kHz 00703 // bw = 414e2; 00704 // break; 00705 //case 6: // 62.5 kHz 00706 // bw = 625e2; 00707 // break; 00708 case 7: // 125 kHz 00709 bw = 125e3; 00710 break; 00711 case 8: // 250 kHz 00712 bw = 250e3; 00713 break; 00714 case 9: // 500 kHz 00715 bw = 500e3; 00716 break; 00717 } 00718 00719 // Symbol rate : time for one symbol (secs) 00720 double rs = bw / (1 << _rf_settings.lora.datarate); 00721 double ts = 1 / rs; 00722 // time of preamble 00723 double tPreamble = (_rf_settings.lora.preamble_len + 4.25) * ts; 00724 // Symbol length of payload and time 00725 double tmp = ceil((8 * pkt_len - 4 * _rf_settings.lora.datarate + 28 00726 + 16 * _rf_settings.lora.crc_on 00727 - (_rf_settings.lora.fix_len ? 20 : 0)) 00728 / (double) (4 00729 * (_rf_settings.lora.datarate 00730 - ((_rf_settings.lora.low_datarate_optimize > 0) 00731 ? 2 : 0)))) 00732 * (_rf_settings.lora.coderate + 4); 00733 double nPayload = 8 + ((tmp > 0) ? tmp : 0); 00734 double tPayload = nPayload * ts; 00735 // Time on air 00736 double tOnAir = tPreamble + tPayload; 00737 // return ms secs 00738 airTime = floor(tOnAir * 1e3 + 0.999); 00739 00740 break; 00741 } 00742 00743 return airTime; 00744 } 00745 00746 /** 00747 * Prepares and sends the radio packet out in the air 00748 */ 00749 void SX1276_LoRaRadio::send(uint8_t *buffer, uint8_t size) 00750 { 00751 uint32_t tx_timeout = 0; 00752 00753 switch (_rf_settings.modem) { 00754 case MODEM_FSK: 00755 _rf_settings.fsk_packet_handler.nb_bytes = 0; 00756 _rf_settings.fsk_packet_handler.size = size; 00757 00758 if (_rf_settings.fsk.fix_len == false) { 00759 write_fifo((uint8_t*) &size, 1); 00760 } else { 00761 write_to_register(REG_PAYLOADLENGTH, size); 00762 } 00763 00764 if ((size > 0) && (size <= 64)) { 00765 _rf_settings.fsk_packet_handler.chunk_size = size; 00766 } else { 00767 memcpy(_data_buffer, buffer, size); 00768 _rf_settings.fsk_packet_handler.chunk_size = 32; 00769 } 00770 00771 // Write payload buffer 00772 write_fifo(buffer, _rf_settings.fsk_packet_handler.chunk_size); 00773 _rf_settings.fsk_packet_handler.nb_bytes += 00774 _rf_settings.fsk_packet_handler.chunk_size; 00775 tx_timeout = _rf_settings.fsk.tx_timeout; 00776 00777 break; 00778 00779 case MODEM_LORA: 00780 if (_rf_settings.lora.iq_inverted == true) { 00781 write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) 00782 & RFLR_INVERTIQ_TX_MASK 00783 & RFLR_INVERTIQ_RX_MASK) 00784 | RFLR_INVERTIQ_RX_OFF 00785 | RFLR_INVERTIQ_TX_ON)); 00786 write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON); 00787 } else { 00788 write_to_register(REG_LR_INVERTIQ, ((read_register( REG_LR_INVERTIQ) 00789 & RFLR_INVERTIQ_TX_MASK 00790 & RFLR_INVERTIQ_RX_MASK) 00791 | RFLR_INVERTIQ_RX_OFF 00792 | RFLR_INVERTIQ_TX_OFF)); 00793 write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF); 00794 } 00795 00796 _rf_settings.lora_packet_handler.size = size; 00797 00798 // Initializes the payload size 00799 write_to_register(REG_LR_PAYLOADLENGTH, size); 00800 00801 // Full buffer used for Tx 00802 write_to_register(REG_LR_FIFOTXBASEADDR, 0); 00803 write_to_register(REG_LR_FIFOADDRPTR, 0); 00804 00805 // FIFO operations can not take place in Sleep mode 00806 if ((read_register( REG_OPMODE) & ~RF_OPMODE_MASK) == RF_OPMODE_SLEEP) { 00807 standby(); 00808 wait_ms(1); 00809 } 00810 // write_to_register payload buffer 00811 write_fifo(buffer, size); 00812 tx_timeout = _rf_settings.lora.tx_timeout; 00813 00814 break; 00815 } 00816 00817 transmit(tx_timeout); 00818 } 00819 00820 /** 00821 * sets the radio module to sleep 00822 */ 00823 00824 void SX1276_LoRaRadio::sleep() 00825 { 00826 // stop timers 00827 tx_timeout_timer.detach(); 00828 rx_timeout_timer.detach(); 00829 00830 // put module in sleep mode 00831 set_operation_mode(RF_OPMODE_SLEEP); 00832 } 00833 00834 /** 00835 * Put radio in Standby mode 00836 */ 00837 void SX1276_LoRaRadio::standby( void ) 00838 { 00839 tx_timeout_timer.detach(); 00840 rx_timeout_timer.detach(); 00841 00842 set_operation_mode(RF_OPMODE_STANDBY); 00843 _rf_settings.state = RF_IDLE; 00844 } 00845 00846 /** 00847 * Sets the radio module in receive mode 00848 * 00849 * A DIO4 interrupt let's the state machine know that a preamble is detected 00850 * and finally a DIO0 interrupt let's the state machine know that a packet is 00851 * ready to be read from the FIFO 00852 */ 00853 void SX1276_LoRaRadio::receive(uint32_t timeout) 00854 { 00855 switch (_rf_settings.modem) { 00856 case MODEM_FSK: 00857 if (timeout == 0 && _rf_settings.fsk.rx_continuous == false) { 00858 // user messed up probably timeout was 0 but mode was not 00859 // continuous, force it to be continuous 00860 _rf_settings.fsk.rx_continuous = true; 00861 } 00862 00863 // DIO0=PayloadReady 00864 // DIO1=FifoLevel 00865 // DIO2=SyncAddr 00866 // DIO3=FifoEmpty 00867 // DIO4=Preamble 00868 // DIO5=ModeReady 00869 write_to_register(REG_DIOMAPPING1, (read_register( REG_DIOMAPPING1) 00870 & RF_DIOMAPPING1_DIO0_MASK 00871 & RF_DIOMAPPING1_DIO1_MASK 00872 & RF_DIOMAPPING1_DIO2_MASK) 00873 | RF_DIOMAPPING1_DIO0_00 00874 | RF_DIOMAPPING1_DIO1_00 00875 | RF_DIOMAPPING1_DIO2_11); 00876 00877 write_to_register(REG_DIOMAPPING2, (read_register( REG_DIOMAPPING2) 00878 & RF_DIOMAPPING2_DIO4_MASK 00879 & RF_DIOMAPPING2_MAP_MASK) 00880 | RF_DIOMAPPING2_DIO4_11 00881 | RF_DIOMAPPING2_MAP_PREAMBLEDETECT); 00882 00883 _rf_settings.fsk_packet_handler.fifo_thresh = 00884 read_register(REG_FIFOTHRESH) & 0x3F; 00885 00886 write_to_register(REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON 00887 | RF_RXCONFIG_AGCAUTO_ON 00888 | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT); 00889 00890 _rf_settings.fsk_packet_handler.preamble_detected = 0; 00891 _rf_settings.fsk_packet_handler.sync_word_detected = 0; 00892 _rf_settings.fsk_packet_handler.nb_bytes = 0; 00893 _rf_settings.fsk_packet_handler.size = 0; 00894 00895 break; 00896 00897 case MODEM_LORA: 00898 if (timeout == 0 && _rf_settings.lora.rx_continuous == false) { 00899 // user messed up probably timeout was 0 but mode was not 00900 // continuous, force it to be continuous 00901 _rf_settings.lora.rx_continuous = true; 00902 } 00903 if (_rf_settings.lora.iq_inverted == true) { 00904 write_to_register(REG_LR_INVERTIQ, ((read_register( REG_LR_INVERTIQ) 00905 & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK) 00906 | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF)); 00907 write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON); 00908 } else { 00909 write_to_register(REG_LR_INVERTIQ, ((read_register( REG_LR_INVERTIQ) 00910 & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK) 00911 | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF)); 00912 write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF); 00913 } 00914 00915 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal 00916 if (_rf_settings.lora.bandwidth < 9) { 00917 write_to_register(REG_LR_DETECTOPTIMIZE, 00918 read_register(REG_LR_DETECTOPTIMIZE) & 0x7F); 00919 write_to_register(REG_LR_TEST30, 0x00); 00920 switch (_rf_settings.lora.bandwidth) { 00921 case 0: // 7.8 kHz 00922 write_to_register( REG_LR_TEST2F, 0x48); 00923 set_channel(_rf_settings.channel + 7.81e3); 00924 break; 00925 case 1: // 10.4 kHz 00926 write_to_register( REG_LR_TEST2F, 0x44); 00927 set_channel(_rf_settings.channel + 10.42e3); 00928 break; 00929 case 2: // 15.6 kHz 00930 write_to_register( REG_LR_TEST2F, 0x44); 00931 set_channel(_rf_settings.channel + 15.62e3); 00932 break; 00933 case 3: // 20.8 kHz 00934 write_to_register( REG_LR_TEST2F, 0x44); 00935 set_channel(_rf_settings.channel + 20.83e3); 00936 break; 00937 case 4: // 31.2 kHz 00938 write_to_register( REG_LR_TEST2F, 0x44); 00939 set_channel(_rf_settings.channel + 31.25e3); 00940 break; 00941 case 5: // 41.4 kHz 00942 write_to_register( REG_LR_TEST2F, 0x44); 00943 set_channel(_rf_settings.channel + 41.67e3); 00944 break; 00945 case 6: // 62.5 kHz 00946 write_to_register( REG_LR_TEST2F, 0x40); 00947 break; 00948 case 7: // 125 kHz 00949 write_to_register( REG_LR_TEST2F, 0x40); 00950 break; 00951 case 8: // 250 kHz 00952 write_to_register( REG_LR_TEST2F, 0x40); 00953 break; 00954 } 00955 } else { 00956 write_to_register( REG_LR_DETECTOPTIMIZE, 00957 read_register( REG_LR_DETECTOPTIMIZE) | 0x80); 00958 } 00959 00960 if (_rf_settings.lora.freq_hop_on == true) { 00961 write_to_register(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_VALIDHEADER 00962 | RFLR_IRQFLAGS_TXDONE 00963 | RFLR_IRQFLAGS_CADDONE 00964 | RFLR_IRQFLAGS_CADDETECTED); 00965 00966 // DIO0=RxDone, DIO2=FhssChangeChannel 00967 write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) 00968 & RFLR_DIOMAPPING1_DIO0_MASK 00969 & RFLR_DIOMAPPING1_DIO2_MASK) 00970 | RFLR_DIOMAPPING1_DIO0_00 00971 | RFLR_DIOMAPPING1_DIO2_00); 00972 } else { 00973 write_to_register(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_VALIDHEADER 00974 | RFLR_IRQFLAGS_TXDONE 00975 | RFLR_IRQFLAGS_CADDONE 00976 | RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 00977 | RFLR_IRQFLAGS_CADDETECTED); 00978 00979 // DIO0=RxDone 00980 write_to_register(REG_DIOMAPPING1, (read_register( REG_DIOMAPPING1) 00981 & RFLR_DIOMAPPING1_DIO0_MASK) 00982 | RFLR_DIOMAPPING1_DIO0_00); 00983 } 00984 write_to_register(REG_LR_FIFORXBASEADDR, 0); 00985 write_to_register(REG_LR_FIFOADDRPTR, 0); 00986 00987 break; 00988 } 00989 00990 memset(_data_buffer, 0, (size_t) MAX_DATA_BUFFER_SIZE_SX1276); 00991 00992 _rf_settings.state = RF_RX_RUNNING; 00993 00994 if (timeout != 0) { 00995 rx_timeout_timer.attach_us( 00996 callback(this, &SX1276_LoRaRadio::timeout_irq_isr), 00997 timeout * 1e3); 00998 } 00999 01000 if (_rf_settings.modem == MODEM_FSK) { 01001 set_operation_mode(RF_OPMODE_RECEIVER); 01002 01003 if (_rf_settings.fsk.rx_continuous == false) { 01004 rx_timeout_sync_word.attach_us( 01005 callback(this, &SX1276_LoRaRadio::timeout_irq_isr), 01006 _rf_settings.fsk.rx_single_timeout * 1e3); 01007 } 01008 01009 return; 01010 } 01011 01012 // If mode is LoRa set mode 01013 if (_rf_settings.lora.rx_continuous == true) { 01014 set_operation_mode(RFLR_OPMODE_RECEIVER); 01015 } else { 01016 set_operation_mode(RFLR_OPMODE_RECEIVER_SINGLE); 01017 } 01018 } 01019 01020 01021 /** 01022 * Perform carrier sensing 01023 * 01024 * Checks for a certain time if the RSSI is above a given threshold. 01025 * This threshold determines if there is already a transmission going on 01026 * in the channel or not. 01027 * 01028 */ 01029 bool SX1276_LoRaRadio::perform_carrier_sense(radio_modems_t modem, 01030 uint32_t freq, 01031 int16_t rssi_threshold, 01032 uint32_t max_carrier_sense_time) 01033 { 01034 bool status = true; 01035 int16_t rssi = 0; 01036 01037 set_modem(modem); 01038 set_channel(freq); 01039 set_operation_mode(RF_OPMODE_RECEIVER); 01040 01041 // hold on a bit, radio turn-around time 01042 wait_ms(1); 01043 01044 Timer elapsed_time; 01045 elapsed_time.start(); 01046 01047 // Perform carrier sense for maxCarrierSenseTime 01048 while (elapsed_time.read_ms() < (int)max_carrier_sense_time) { 01049 rssi = get_rssi(modem); 01050 01051 if (rssi > rssi_threshold) { 01052 status = false; 01053 break; 01054 } 01055 } 01056 01057 sleep(); 01058 return status; 01059 } 01060 01061 /** 01062 * TODO: Making sure if this API is valid only for LoRa modulation ? 01063 * 01064 * Indicates if the node is part of a private or public network 01065 */ 01066 void SX1276_LoRaRadio::set_public_network(bool enable) 01067 { 01068 set_modem(MODEM_LORA); 01069 01070 _rf_settings.lora.public_network = enable; 01071 if (enable == true) { 01072 // Change lora modem SyncWord 01073 write_to_register(REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD); 01074 } else { 01075 // Change lora modem SyncWord 01076 write_to_register(REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD); 01077 } 01078 01079 } 01080 01081 /** 01082 * Puts a limit on the size of payload the module can handle 01083 * By default it is MAX, i.e., 256 bytes 01084 */ 01085 void SX1276_LoRaRadio::set_max_payload_length(radio_modems_t modem, uint8_t max) 01086 { 01087 set_modem(modem); 01088 01089 switch (modem) { 01090 case MODEM_FSK: 01091 if (_rf_settings.fsk.fix_len == false) { 01092 write_to_register(REG_PAYLOADLENGTH, max); 01093 } 01094 break; 01095 case MODEM_LORA: 01096 write_to_register(REG_LR_PAYLOADMAXLENGTH, max); 01097 break; 01098 } 01099 } 01100 01101 /** 01102 * Channel Activity detection (can be done only in LoRa mode) 01103 * 01104 * If any activity on the channel is detected, an interrupt is asserted on 01105 * DIO3. A callback will be generated to the stack/application upon the 01106 * assertion of DIO3. 01107 */ 01108 void SX1276_LoRaRadio::start_cad() 01109 { 01110 uint8_t reg_val; 01111 01112 switch (_rf_settings.modem) { 01113 case MODEM_FSK: 01114 break; 01115 case MODEM_LORA: 01116 write_to_register(REG_LR_IRQFLAGSMASK, 01117 RFLR_IRQFLAGS_RXTIMEOUT | 01118 RFLR_IRQFLAGS_RXDONE | 01119 RFLR_IRQFLAGS_PAYLOADCRCERROR | 01120 RFLR_IRQFLAGS_VALIDHEADER | 01121 RFLR_IRQFLAGS_TXDONE | 01122 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL); 01123 01124 // DIO3=CADDone 01125 reg_val = read_register(REG_DIOMAPPING1); 01126 write_to_register(REG_DIOMAPPING1, (reg_val & 01127 RFLR_DIOMAPPING1_DIO3_MASK) | 01128 RFLR_DIOMAPPING1_DIO3_00); 01129 01130 set_operation_mode(RFLR_OPMODE_CAD); 01131 01132 _rf_settings.state = RF_CAD; 01133 01134 break; 01135 default: 01136 break; 01137 } 01138 } 01139 01140 /** 01141 * Set transmission in continuous wave mode 01142 */ 01143 void SX1276_LoRaRadio::set_tx_continuous_wave(uint32_t freq, int8_t power, 01144 uint16_t time) 01145 { 01146 uint8_t reg_val; 01147 01148 set_channel(freq); 01149 set_tx_config(MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, time); 01150 reg_val = read_register(REG_PACKETCONFIG2); 01151 01152 write_to_register( REG_PACKETCONFIG2, (reg_val & RF_PACKETCONFIG2_DATAMODE_MASK ) ); 01153 // Disable radio interrupts 01154 write_to_register( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 ); 01155 write_to_register( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 ); 01156 01157 _rf_settings.state = RF_TX_RUNNING; 01158 tx_timeout_timer.attach_us(callback(this, &SX1276_LoRaRadio::timeout_irq_isr), time*1e3); 01159 set_operation_mode(RF_OPMODE_TRANSMITTER); 01160 } 01161 01162 /***************************************************************************** 01163 * Private APIs * 01164 ****************************************************************************/ 01165 #ifdef MBED_CONF_RTOS_PRESENT 01166 /** 01167 * Thread task handling IRQs 01168 */ 01169 void SX1276_LoRaRadio::rf_irq_task(void) 01170 { 01171 for (;;) { 01172 osEvent event = irq_thread.signal_wait(0, osWaitForever); 01173 if (event.status != osEventSignal) { 01174 continue; 01175 } 01176 01177 lock(); 01178 if (event.value.signals & SIG_DIO0) { 01179 handle_dio0_irq(); 01180 } 01181 if (event.value.signals & SIG_DIO1) { 01182 handle_dio1_irq(); 01183 } 01184 if (event.value.signals & SIG_DIO2) { 01185 handle_dio2_irq(); 01186 } 01187 if (event.value.signals & SIG_DIO3) { 01188 handle_dio3_irq(); 01189 } 01190 if (event.value.signals & SIG_DIO4) { 01191 handle_dio4_irq(); 01192 } 01193 if (event.value.signals & SIG_DIO5) { 01194 handle_dio5_irq(); 01195 } 01196 if (event.value.signals & SIG_TIMOUT) { 01197 handle_timeout_irq(); 01198 } 01199 unlock(); 01200 } 01201 } 01202 #endif 01203 01204 /** 01205 * Writes a single byte to a given register 01206 */ 01207 void SX1276_LoRaRadio::write_to_register(uint8_t addr, uint8_t data) 01208 { 01209 write_to_register(addr, &data, 1); 01210 } 01211 01212 /** 01213 * Writes multiple bytes to a given register 01214 */ 01215 void SX1276_LoRaRadio::write_to_register(uint8_t addr, uint8_t *data, uint8_t size) 01216 { 01217 // set chip-select low 01218 _chip_select = 0; 01219 01220 // set write command 01221 _spi.write(addr | SPI_WRITE_CMD); 01222 01223 // write data 01224 for (uint8_t i = 0; i < size; i++) { 01225 _spi.write(data[i]); 01226 } 01227 01228 // set chip-select high 01229 _chip_select = 1; 01230 } 01231 01232 /** 01233 * Reads the value of a single register 01234 */ 01235 uint8_t SX1276_LoRaRadio::read_register(uint8_t addr) 01236 { 01237 uint8_t data; 01238 read_register(addr, &data, 1); 01239 return data; 01240 } 01241 01242 /** 01243 * Reads multiple values from a given register 01244 */ 01245 void SX1276_LoRaRadio::read_register(uint8_t addr, uint8_t *buffer, uint8_t size) 01246 { 01247 // set chip-select low 01248 _chip_select = 0; 01249 01250 // set read command 01251 _spi.write(addr & SPI_READ_CMD); 01252 01253 // read buffers 01254 for (uint8_t i = 0; i < size; i++) { 01255 buffer[i] = _spi.write(0); 01256 } 01257 01258 // set chip-select high 01259 _chip_select = 1; 01260 } 01261 01262 /** 01263 * Writes to FIIO provided by the chip 01264 */ 01265 void SX1276_LoRaRadio::write_fifo(uint8_t *buffer, uint8_t size) 01266 { 01267 write_to_register(0, buffer, size); 01268 } 01269 01270 /** 01271 * Reads from the FIFO provided by the chip 01272 */ 01273 void SX1276_LoRaRadio::read_fifo(uint8_t *buffer, uint8_t size) 01274 { 01275 read_register(0, buffer, size); 01276 } 01277 01278 /** 01279 * Sets up operation mode 01280 */ 01281 void SX1276_LoRaRadio::set_operation_mode(uint8_t mode) 01282 { 01283 if (mode == RF_OPMODE_SLEEP) { 01284 set_low_power_mode(); 01285 } else { 01286 set_low_power_mode(); 01287 set_antenna_switch(mode); 01288 } 01289 01290 write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RF_OPMODE_MASK) | mode); 01291 } 01292 01293 /** 01294 * Sets the modem type to use 01295 * 01296 * At initialization FSK is chosen. Later stack or application 01297 * can choose to change. 01298 */ 01299 void SX1276_LoRaRadio::set_modem(uint8_t modem ) 01300 { 01301 if ((read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_ON) != 0 ) { 01302 _rf_settings.modem = MODEM_LORA; 01303 } else { 01304 _rf_settings.modem = MODEM_FSK; 01305 } 01306 01307 if(_rf_settings.modem == modem ) { 01308 // if the modem is already set 01309 return; 01310 } 01311 01312 _rf_settings.modem = modem; 01313 01314 switch(_rf_settings.modem) 01315 { 01316 default: 01317 case MODEM_FSK: 01318 // before changing modem mode, put the module to sleep 01319 sleep(); 01320 write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK) 01321 | RFLR_OPMODE_LONGRANGEMODE_OFF); 01322 01323 // Datasheet Tables 28, 29 DIO mapping 01324 write_to_register(REG_DIOMAPPING1, 0x00); // sets DIO0-DI03 in default mode 01325 write_to_register(REG_DIOMAPPING2, 0x30); // bits 4-5 are turned on i.e., 01326 // DIO5 and DIO4=ModeReady 01327 break; 01328 case MODEM_LORA: 01329 sleep(); 01330 write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK) 01331 | RFLR_OPMODE_LONGRANGEMODE_ON); 01332 01333 // Datasheet Tables 17 DIO mapping for LoRa 01334 // set to defaults 01335 write_to_register(REG_DIOMAPPING1, 0x00); // DIO0 - DIO3 defaults 01336 write_to_register(REG_DIOMAPPING2, 0x00); // DIO4 - DIO5 defaults 01337 01338 break; 01339 } 01340 } 01341 01342 /** 01343 * Set the radio module variant 01344 */ 01345 void SX1276_LoRaRadio::set_sx1276_variant_type() 01346 { 01347 if (_rf_ctrls.ant_switch != NC) { 01348 _ant_switch.input(); 01349 wait_ms(1); 01350 if (_ant_switch == 1) { 01351 radio_variant = SX1276MB1LAS; 01352 } else { 01353 radio_variant = SX1276MB1MAS; 01354 } 01355 _ant_switch.output(); 01356 wait_ms(1); 01357 } else { 01358 radio_variant = SX1276UNDEFINED; 01359 } 01360 } 01361 01362 /** 01363 * Sets up frequency for SPI module 01364 * Reference DataSheet: 4.3 SPI Interface 01365 */ 01366 void SX1276_LoRaRadio::setup_spi() 01367 { 01368 // SPI bus frequency 01369 uint32_t spi_freq = SPI_FREQUENCY; 01370 01371 // Hold chip-select high 01372 _chip_select = 1; 01373 _spi.format(8, 0); 01374 01375 #if defined (TARGET_KL25Z) 01376 //bus-clock frequency is halved -> double the SPI frequency to compensate 01377 _spi.frequency(spi_freq * 2); 01378 #else 01379 // otherwise use default SPI frequency which is 8 MHz 01380 _spi.frequency(spi_freq); 01381 #endif 01382 // 100 us wait to settle down 01383 wait(0.1); 01384 } 01385 01386 /** 01387 * Sets the radio registers to defaults 01388 */ 01389 void SX1276_LoRaRadio::setup_registers() 01390 { 01391 for (unsigned int i = 0; i < sizeof(radio_reg_init) / sizeof(radio_registers_t); i++) { 01392 set_modem(radio_reg_init[i].modem); 01393 write_to_register(radio_reg_init[i].addr, radio_reg_init[i].value); 01394 } 01395 } 01396 01397 /** 01398 * Performs the Rx chain calibration for LF and HF bands 01399 * 01400 * Must be called just after the reset so all registers are at their 01401 * default values. 01402 */ 01403 void SX1276_LoRaRadio::rx_chain_calibration(void) 01404 { 01405 uint8_t regPaConfigInitVal; 01406 uint32_t initialFreq; 01407 01408 // Save context 01409 regPaConfigInitVal = read_register( REG_PACONFIG ); 01410 initialFreq = ( double )( ( ( uint32_t )this->read_register( REG_FRFMSB ) << 16 ) | 01411 ( ( uint32_t )this->read_register( REG_FRFMID ) << 8 ) | 01412 ( ( uint32_t )this->read_register( REG_FRFLSB ) ) ) * ( double )FREQ_STEP; 01413 01414 // Cut the PA just in case, RFO output, power = -1 dBm 01415 write_to_register( REG_PACONFIG, 0x00 ); 01416 01417 // Launch Rx chain calibration for LF band 01418 write_to_register (REG_IMAGECAL, (read_register(REG_IMAGECAL) 01419 & RF_IMAGECAL_IMAGECAL_MASK) 01420 | RF_IMAGECAL_IMAGECAL_START); 01421 while((read_register(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_RUNNING ) 01422 == RF_IMAGECAL_IMAGECAL_RUNNING ) 01423 { 01424 } 01425 01426 // Sets a Frequency in HF band 01427 set_channel(868000000); 01428 01429 // Launch Rx chain calibration for HF band 01430 write_to_register (REG_IMAGECAL, (read_register(REG_IMAGECAL) 01431 & RF_IMAGECAL_IMAGECAL_MASK ) 01432 | RF_IMAGECAL_IMAGECAL_START ); 01433 while((read_register(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_RUNNING ) 01434 == RF_IMAGECAL_IMAGECAL_RUNNING ) 01435 { 01436 // do nothing, just wait while rf image frequency calibration is done 01437 } 01438 01439 // Restore context 01440 write_to_register( REG_PACONFIG, regPaConfigInitVal ); 01441 set_channel(initialFreq); 01442 } 01443 01444 /** 01445 * Gets FSK bandwidth values 01446 * 01447 * Gives either normal bandwidths or bandwidths for 01448 * AFC (auto frequency correction) 01449 */ 01450 uint8_t SX1276_LoRaRadio::get_fsk_bw_reg_val(uint32_t bandwidth) 01451 { 01452 uint8_t i; 01453 01454 for (i = 0; i < (sizeof(fsk_bandwidths) / sizeof(fsk_bw_t)) - 1; i++) { 01455 if ((bandwidth >= fsk_bandwidths[i].bandwidth) 01456 && (bandwidth < fsk_bandwidths[i + 1].bandwidth)) { 01457 return fsk_bandwidths[i].register_value; 01458 } 01459 } 01460 // ERROR: Value not found 01461 // This should never happen 01462 while (1); 01463 } 01464 01465 uint8_t SX1276_LoRaRadio::get_pa_conf_reg(uint32_t channel) 01466 { 01467 if (radio_variant == SX1276UNDEFINED) { 01468 return RF_PACONFIG_PASELECT_PABOOST; 01469 } else if (channel > RF_MID_BAND_THRESH) { 01470 if (radio_variant == SX1276MB1LAS) { 01471 return RF_PACONFIG_PASELECT_PABOOST; 01472 } else { 01473 return RF_PACONFIG_PASELECT_RFO; 01474 } 01475 } else { 01476 return RF_PACONFIG_PASELECT_RFO; 01477 } 01478 } 01479 01480 /** 01481 * Sets the transmit power for the module 01482 */ 01483 void SX1276_LoRaRadio::set_rf_tx_power(int8_t power) 01484 { 01485 01486 uint8_t paConfig = 0; 01487 uint8_t paDac = 0; 01488 01489 paConfig = read_register(REG_PACONFIG); 01490 paDac = read_register(REG_PADAC); 01491 01492 paConfig = (paConfig & RF_PACONFIG_PASELECT_MASK) | get_pa_conf_reg(_rf_settings.channel); 01493 paConfig = (paConfig & RF_PACONFIG_MAX_POWER_MASK) | 0x70; 01494 01495 if ((paConfig & RF_PACONFIG_PASELECT_PABOOST) == RF_PACONFIG_PASELECT_PABOOST) { 01496 if (power > 17) { 01497 paDac = (paDac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_ON; 01498 } else { 01499 paDac = (paDac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_OFF; 01500 } 01501 if ((paDac & RF_PADAC_20DBM_ON) == RF_PADAC_20DBM_ON) { 01502 if (power < 5) { 01503 power = 5; 01504 } 01505 if (power > 20) { 01506 power = 20; 01507 } 01508 paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK) 01509 | (uint8_t) ((uint16_t) (power - 5) & 0x0F); 01510 } else { 01511 if (power < 2) { 01512 power = 2; 01513 } 01514 if (power > 17) { 01515 power = 17; 01516 } 01517 paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK) 01518 | (uint8_t) ((uint16_t) (power - 2) & 0x0F); 01519 } 01520 } else { 01521 if (power < -1) { 01522 power = -1; 01523 } 01524 if (power > 14) { 01525 power = 14; 01526 } 01527 paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK) 01528 | (uint8_t) ((uint16_t) (power + 1) & 0x0F); 01529 } 01530 write_to_register( REG_PACONFIG, paConfig); 01531 write_to_register( REG_PADAC, paDac); 01532 } 01533 01534 /** 01535 * Actual TX - Transmit routine 01536 * 01537 * A DIO0 interrupt let the state machine know that a a packet is 01538 * successfully sent, otherwise a TxTimeout is invoked. 01539 * TxTimeout should never happen in normal circumstances as the radio should 01540 * be able to send a packet out in the air no matter what. 01541 */ 01542 void SX1276_LoRaRadio::transmit(uint32_t timeout) 01543 { 01544 switch (_rf_settings.modem) { 01545 01546 case MODEM_FSK: 01547 // DIO0=PacketSent 01548 // DIO1=FifoEmpty 01549 // DIO2=FifoFull 01550 // DIO3=FifoEmpty 01551 // DIO4=LowBat 01552 // DIO5=ModeReady 01553 write_to_register(REG_DIOMAPPING1,(read_register(REG_DIOMAPPING1) & 01554 RF_DIOMAPPING1_DIO0_MASK & 01555 RF_DIOMAPPING1_DIO1_MASK & 01556 RF_DIOMAPPING1_DIO2_MASK) | 01557 RF_DIOMAPPING1_DIO1_01); 01558 01559 write_to_register(REG_DIOMAPPING2, (read_register(REG_DIOMAPPING2) & 01560 RF_DIOMAPPING2_DIO4_MASK & 01561 RF_DIOMAPPING2_MAP_MASK)); 01562 _rf_settings.fsk_packet_handler.fifo_thresh = 01563 read_register(REG_FIFOTHRESH) & 0x3F; 01564 01565 break; 01566 01567 case MODEM_LORA: 01568 01569 if (_rf_settings.lora.freq_hop_on == true) { 01570 write_to_register(REG_LR_IRQFLAGSMASK, 01571 RFLR_IRQFLAGS_RXTIMEOUT | 01572 RFLR_IRQFLAGS_RXDONE | 01573 RFLR_IRQFLAGS_PAYLOADCRCERROR | 01574 RFLR_IRQFLAGS_VALIDHEADER | 01575 RFLR_IRQFLAGS_CADDONE | 01576 RFLR_IRQFLAGS_CADDETECTED); 01577 01578 // DIO0=tx_done, DIO2=fhss_change_channel 01579 01580 write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) & 01581 RFLR_DIOMAPPING1_DIO0_MASK & 01582 RFLR_DIOMAPPING1_DIO2_MASK) | 01583 RFLR_DIOMAPPING1_DIO0_01 | 01584 RFLR_DIOMAPPING1_DIO2_00); 01585 } else { 01586 write_to_register(REG_LR_IRQFLAGSMASK, 01587 RFLR_IRQFLAGS_RXTIMEOUT | 01588 RFLR_IRQFLAGS_RXDONE | 01589 RFLR_IRQFLAGS_PAYLOADCRCERROR | 01590 RFLR_IRQFLAGS_VALIDHEADER | 01591 RFLR_IRQFLAGS_CADDONE | 01592 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 01593 RFLR_IRQFLAGS_CADDETECTED); 01594 01595 // DIO0=tx_done 01596 write_to_register(REG_DIOMAPPING1,(read_register(REG_DIOMAPPING1) & 01597 RFLR_DIOMAPPING1_DIO0_MASK) | 01598 RFLR_DIOMAPPING1_DIO0_01); 01599 } 01600 01601 break; 01602 } 01603 01604 _rf_settings.state = RF_TX_RUNNING; 01605 tx_timeout_timer.attach_us(callback(this, 01606 &SX1276_LoRaRadio::timeout_irq_isr), timeout*1e3); 01607 set_operation_mode(RF_OPMODE_TRANSMITTER); 01608 } 01609 01610 /** 01611 * Get RSSI from the module 01612 */ 01613 int16_t SX1276_LoRaRadio::get_rssi(radio_modems_t modem) 01614 { 01615 int16_t rssi = 0; 01616 01617 switch (modem) { 01618 case MODEM_FSK: 01619 rssi = -(read_register(REG_RSSIVALUE) >> 1); 01620 break; 01621 case MODEM_LORA: 01622 if (_rf_settings.channel > RF_MID_BAND_THRESH) { 01623 rssi = RSSI_OFFSET_HF + read_register(REG_LR_RSSIVALUE); 01624 } else { 01625 rssi = RSSI_OFFSET_LF + read_register(REG_LR_RSSIVALUE); 01626 } 01627 break; 01628 default: 01629 rssi = -1; 01630 break; 01631 } 01632 return rssi; 01633 } 01634 01635 /** 01636 * Sets the module in low power mode by disconnecting 01637 * TX and RX submodules, turning off power amplifier etc. 01638 */ 01639 void SX1276_LoRaRadio::set_low_power_mode() 01640 { 01641 01642 if (_rf_ctrls.rf_switch_ctl1 != NC) { 01643 _rf_switch_ctl1 = 0; 01644 } 01645 01646 if (_rf_ctrls.rf_switch_ctl2 != NC) { 01647 _rf_switch_ctl2 = 0; 01648 } 01649 01650 if (_rf_ctrls.pwr_amp_ctl != NC) { 01651 _pwr_amp_ctl = 0; 01652 } 01653 01654 if (_rf_ctrls.txctl != NC) { 01655 _txctl = 0; 01656 } 01657 01658 if (_rf_ctrls.txctl != NC) { 01659 _rxctl = 0; 01660 } 01661 01662 if (_rf_ctrls.ant_switch != NC) { 01663 _ant_switch = 0; 01664 } 01665 } 01666 01667 /** 01668 * Attaches ISRs to interrupt pins 01669 */ 01670 void SX1276_LoRaRadio::setup_interrupts() 01671 { 01672 _dio0_ctl.rise(callback(this, &SX1276_LoRaRadio::dio0_irq_isr)); 01673 _dio1_ctl.rise(callback(this, &SX1276_LoRaRadio::dio1_irq_isr)); 01674 _dio2_ctl.rise(callback(this, &SX1276_LoRaRadio::dio2_irq_isr)); 01675 _dio3_ctl.rise(callback(this, &SX1276_LoRaRadio::dio3_irq_isr)); 01676 if (_dio4_pin != NC) { 01677 _dio4_ctl.rise(callback(this, &SX1276_LoRaRadio::dio4_irq_isr)); 01678 } 01679 if (_dio5_pin != NC) { 01680 _dio5_ctl.rise(callback(this, &SX1276_LoRaRadio::dio5_irq_isr)); 01681 } 01682 } 01683 01684 /** 01685 * Sets up radio latch position according to the 01686 * radio mode 01687 */ 01688 void SX1276_LoRaRadio::set_antenna_switch(uint8_t mode) 01689 { 01690 // here we got to do ifdef for changing controls 01691 // as some pins might be NC 01692 switch (mode) { 01693 case RFLR_OPMODE_TRANSMITTER: 01694 if (_rf_ctrls.rf_switch_ctl1 != NC 01695 && _rf_ctrls.rf_switch_ctl2 != NC) { 01696 // module is in transmit mode and RF latch switches 01697 // are connected. Check if power amplifier boost is 01698 // setup or not 01699 if ((read_register(REG_PACONFIG) & RF_PACONFIG_PASELECT_PABOOST) 01700 == RF_PACONFIG_PASELECT_PABOOST) { 01701 _rf_switch_ctl1 = 1; 01702 _rf_switch_ctl2 = 0; 01703 } else { 01704 // power amplifier not selected 01705 _rf_switch_ctl1 = 0; 01706 _rf_switch_ctl2 = 1; 01707 } 01708 } 01709 if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) { 01710 // module is in transmit mode and tx/rx submodule control 01711 // pins are connected 01712 if (_rf_ctrls.pwr_amp_ctl != NC) { 01713 if (read_register(REG_PACONFIG) & RF_PACONFIG_PASELECT_PABOOST) { 01714 _pwr_amp_ctl = 1; 01715 _txctl = 0; 01716 } else { 01717 _pwr_amp_ctl = 0; 01718 _txctl = 1; 01719 } 01720 } else { 01721 _txctl = 1; 01722 } 01723 _rxctl = 0; 01724 } 01725 if (_rf_ctrls.ant_switch != NC){ 01726 _ant_switch = 1; 01727 } 01728 break; 01729 case RFLR_OPMODE_RECEIVER: 01730 case RFLR_OPMODE_RECEIVER_SINGLE: 01731 case RFLR_OPMODE_CAD: 01732 if (_rf_ctrls.rf_switch_ctl1 != NC 01733 && _rf_ctrls.rf_switch_ctl2 != NC) { 01734 // radio is in reception or CAD mode and RF latch switches 01735 // are connected 01736 _rf_switch_ctl1 = 1; 01737 _rf_switch_ctl2 = 1; 01738 } 01739 if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) { 01740 _txctl = 0; 01741 _rxctl = 1; 01742 } 01743 if (_rf_ctrls.ant_switch != NC) { 01744 _ant_switch = 0; 01745 } 01746 if (_rf_ctrls.pwr_amp_ctl != NC) { 01747 _pwr_amp_ctl = 0; 01748 } 01749 break; 01750 default: 01751 // Enforce default case when any connected control pin is kept low. 01752 if (_rf_ctrls.rf_switch_ctl1 != NC 01753 && _rf_ctrls.rf_switch_ctl2 != NC) { 01754 // radio is in reception or CAD mode and RF latch switches 01755 // are connected 01756 _rf_switch_ctl1 = 0; 01757 _rf_switch_ctl2 = 0; 01758 } 01759 if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) { 01760 _txctl = 0; 01761 _rxctl = 0; 01762 } 01763 if (_rf_ctrls.ant_switch != NC) { 01764 _ant_switch = 0; 01765 } 01766 if (_rf_ctrls.pwr_amp_ctl != NC) { 01767 _pwr_amp_ctl = 0; 01768 } 01769 break; 01770 } 01771 } 01772 01773 /***************************************************************************** 01774 * Interrupt service routines (ISRs) - set signals to the irq_thread * 01775 ****************************************************************************/ 01776 void SX1276_LoRaRadio::dio0_irq_isr() 01777 { 01778 #ifdef MBED_CONF_RTOS_PRESENT 01779 irq_thread.signal_set(SIG_DIO0); 01780 #else 01781 handle_dio0_irq(); 01782 #endif 01783 } 01784 01785 void SX1276_LoRaRadio::dio1_irq_isr() 01786 { 01787 #ifdef MBED_CONF_RTOS_PRESENT 01788 irq_thread.signal_set(SIG_DIO1); 01789 #else 01790 handle_dio1_irq(); 01791 #endif 01792 } 01793 01794 void SX1276_LoRaRadio::dio2_irq_isr() 01795 { 01796 #ifdef MBED_CONF_RTOS_PRESENT 01797 irq_thread.signal_set(SIG_DIO2); 01798 #else 01799 handle_dio2_irq(); 01800 #endif 01801 } 01802 01803 void SX1276_LoRaRadio::dio3_irq_isr() 01804 { 01805 #ifdef MBED_CONF_RTOS_PRESENT 01806 irq_thread.signal_set(SIG_DIO3); 01807 #else 01808 handle_dio3_irq(); 01809 #endif 01810 } 01811 01812 void SX1276_LoRaRadio::dio4_irq_isr() 01813 { 01814 #ifdef MBED_CONF_RTOS_PRESENT 01815 irq_thread.signal_set(SIG_DIO4); 01816 #else 01817 handle_dio4_irq(); 01818 #endif 01819 } 01820 01821 void SX1276_LoRaRadio::dio5_irq_isr() 01822 { 01823 #ifdef MBED_CONF_RTOS_PRESENT 01824 irq_thread.signal_set(SIG_DIO5); 01825 #else 01826 handle_dio5_irq(); 01827 #endif 01828 } 01829 01830 // This is not a hardware interrupt 01831 // we invoke it ourselves based upon 01832 // our timers 01833 void SX1276_LoRaRadio::timeout_irq_isr() 01834 { 01835 #ifdef MBED_CONF_RTOS_PRESENT 01836 irq_thread.signal_set(SIG_TIMOUT); 01837 #else 01838 handle_timeout_irq(); 01839 #endif 01840 } 01841 01842 /****************************************************************************** 01843 * Interrupt Handlers * 01844 *****************************************************************************/ 01845 01846 void SX1276_LoRaRadio::handle_dio0_irq() 01847 { 01848 volatile uint8_t irqFlags = 0; 01849 01850 switch (_rf_settings.state) { 01851 case RF_RX_RUNNING: 01852 switch (_rf_settings.modem) { 01853 case MODEM_FSK: 01854 if (_rf_settings.fsk.crc_on == true) { 01855 irqFlags = read_register(REG_IRQFLAGS2); 01856 if ((irqFlags & RF_IRQFLAGS2_CRCOK) 01857 != RF_IRQFLAGS2_CRCOK) { 01858 // Clear Irqs 01859 write_to_register(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 01860 RF_IRQFLAGS1_PREAMBLEDETECT | 01861 RF_IRQFLAGS1_SYNCADDRESSMATCH); 01862 write_to_register(REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN); 01863 01864 01865 if (_rf_settings.fsk.rx_continuous == false) { 01866 rx_timeout_sync_word.detach(); 01867 _rf_settings.state = RF_IDLE; 01868 } else { 01869 // Continuous mode restart Rx chain 01870 write_to_register(REG_RXCONFIG, 01871 read_register(REG_RXCONFIG) | 01872 RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK); 01873 } 01874 01875 rx_timeout_timer.detach(); 01876 01877 if ((_radio_events != NULL) 01878 && (_radio_events->rx_error)) { 01879 _radio_events->rx_error(); 01880 } 01881 _rf_settings.fsk_packet_handler.preamble_detected = 0; 01882 _rf_settings.fsk_packet_handler.sync_word_detected = 0; 01883 _rf_settings.fsk_packet_handler.nb_bytes = 0; 01884 _rf_settings.fsk_packet_handler.size = 0; 01885 // break from here, a CRC error happened, RX_ERROR 01886 // was notified. No need to go any further 01887 break; 01888 } 01889 } 01890 01891 // Read received packet size 01892 if ((_rf_settings.fsk_packet_handler.size == 0) 01893 && (_rf_settings.fsk_packet_handler.nb_bytes == 0)) { 01894 if (_rf_settings.fsk.fix_len == false) { 01895 read_fifo((uint8_t*) &_rf_settings.fsk_packet_handler.size, 1); 01896 } else { 01897 _rf_settings.fsk_packet_handler.size = read_register(REG_PAYLOADLENGTH); 01898 } 01899 read_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes, 01900 _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes); 01901 _rf_settings.fsk_packet_handler.nb_bytes += 01902 (_rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes); 01903 } else { 01904 read_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes, 01905 _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes); 01906 _rf_settings.fsk_packet_handler.nb_bytes += 01907 (_rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes); 01908 } 01909 01910 if (_rf_settings.fsk.rx_continuous == false) { 01911 _rf_settings.state = RF_IDLE; 01912 rx_timeout_sync_word.detach(); 01913 } else { 01914 // Continuous mode restart Rx chain 01915 write_to_register(REG_RXCONFIG, read_register(REG_RXCONFIG) 01916 | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK); 01917 } 01918 01919 rx_timeout_timer.detach(); 01920 01921 if ((_radio_events != NULL) && (_radio_events->rx_done)) { 01922 _radio_events->rx_done( 01923 _data_buffer, 01924 _rf_settings.fsk_packet_handler.size, 01925 _rf_settings.fsk_packet_handler.rssi_value, 0); 01926 } 01927 _rf_settings.fsk_packet_handler.preamble_detected = 0; 01928 _rf_settings.fsk_packet_handler.sync_word_detected = 0; 01929 _rf_settings.fsk_packet_handler.nb_bytes = 0; 01930 _rf_settings.fsk_packet_handler.size = 0; 01931 break; 01932 01933 case MODEM_LORA: { 01934 int8_t snr = 0; 01935 01936 // Clear Irq 01937 write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE); 01938 01939 irqFlags = read_register(REG_LR_IRQFLAGS); 01940 if ((irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK) 01941 == RFLR_IRQFLAGS_PAYLOADCRCERROR) { 01942 // Clear Irq 01943 write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR); 01944 01945 if (_rf_settings.lora.rx_continuous == false) { 01946 _rf_settings.state = RF_IDLE; 01947 } 01948 rx_timeout_timer.detach(); 01949 01950 if ((_radio_events != NULL) 01951 && (_radio_events->rx_error)) { 01952 _radio_events->rx_error(); 01953 } 01954 break; 01955 } 01956 01957 _rf_settings.lora_packet_handler.snr_value = read_register( 01958 REG_LR_PKTSNRVALUE); 01959 if (_rf_settings.lora_packet_handler.snr_value & 0x80) // The SNR sign bit is 1 01960 { 01961 // Invert and divide by 4 01962 snr = ((~_rf_settings.lora_packet_handler.snr_value + 1) 01963 & 0xFF) >> 2; 01964 snr = -snr; 01965 } else { 01966 // Divide by 4 01967 snr = 01968 (_rf_settings.lora_packet_handler.snr_value 01969 & 0xFF) >> 2; 01970 } 01971 01972 int16_t rssi = read_register( REG_LR_PKTRSSIVALUE); 01973 if (snr < 0) { 01974 if (_rf_settings.channel > RF_MID_BAND_THRESH) { 01975 _rf_settings.lora_packet_handler.rssi_value = 01976 RSSI_OFFSET_HF + rssi + (rssi >> 4) + snr; 01977 } else { 01978 _rf_settings.lora_packet_handler.rssi_value = 01979 RSSI_OFFSET_LF + rssi + (rssi >> 4) + snr; 01980 } 01981 } else { 01982 if (_rf_settings.channel > RF_MID_BAND_THRESH) { 01983 _rf_settings.lora_packet_handler.rssi_value = 01984 RSSI_OFFSET_HF + rssi + (rssi >> 4); 01985 } else { 01986 _rf_settings.lora_packet_handler.rssi_value = 01987 RSSI_OFFSET_LF + rssi + (rssi >> 4); 01988 } 01989 } 01990 01991 _rf_settings.lora_packet_handler.size = read_register(REG_LR_RXNBBYTES); 01992 read_fifo(_data_buffer, _rf_settings.lora_packet_handler.size); 01993 01994 if (_rf_settings.lora.rx_continuous == false) { 01995 _rf_settings.state = RF_IDLE; 01996 } 01997 rx_timeout_timer.detach(); 01998 01999 if ((_radio_events != NULL) && (_radio_events->rx_done)) { 02000 _radio_events->rx_done(_data_buffer, 02001 _rf_settings.lora_packet_handler.size, 02002 _rf_settings.lora_packet_handler.rssi_value, 02003 _rf_settings.lora_packet_handler.snr_value); 02004 } 02005 } 02006 break; 02007 default: 02008 break; 02009 } 02010 break; 02011 case RF_TX_RUNNING: 02012 tx_timeout_timer.detach(); 02013 // TxDone interrupt 02014 switch (_rf_settings.modem) { 02015 case MODEM_LORA: 02016 // Clear Irq 02017 write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE); 02018 // Intentional fall through 02019 case MODEM_FSK: 02020 default: 02021 _rf_settings.state = RF_IDLE; 02022 if ((_radio_events != NULL) 02023 && (_radio_events->tx_done)) { 02024 _radio_events->tx_done(); 02025 } 02026 break; 02027 } 02028 break; 02029 default: 02030 break; 02031 } 02032 } 02033 02034 void SX1276_LoRaRadio::handle_dio1_irq() 02035 { 02036 switch (_rf_settings.state) { 02037 case RF_RX_RUNNING: 02038 switch (_rf_settings.modem) { 02039 case MODEM_FSK: 02040 // FifoLevel interrupt 02041 // Read received packet size 02042 if ((_rf_settings.fsk_packet_handler.size == 0) 02043 && (_rf_settings.fsk_packet_handler.nb_bytes == 0)) { 02044 if (_rf_settings.fsk.fix_len == false) { 02045 read_fifo((uint8_t*) &_rf_settings.fsk_packet_handler.size, 1); 02046 } else { 02047 _rf_settings.fsk_packet_handler.size = 02048 read_register(REG_PAYLOADLENGTH); 02049 } 02050 } 02051 02052 if ((_rf_settings.fsk_packet_handler.size 02053 - _rf_settings.fsk_packet_handler.nb_bytes) 02054 > _rf_settings.fsk_packet_handler.fifo_thresh) { 02055 read_fifo((_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes), 02056 _rf_settings.fsk_packet_handler.fifo_thresh); 02057 _rf_settings.fsk_packet_handler.nb_bytes += 02058 _rf_settings.fsk_packet_handler.fifo_thresh; 02059 } else { 02060 read_fifo((_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes), 02061 _rf_settings.fsk_packet_handler.size 02062 - _rf_settings.fsk_packet_handler.nb_bytes); 02063 _rf_settings.fsk_packet_handler.nb_bytes += 02064 (_rf_settings.fsk_packet_handler.size 02065 - _rf_settings.fsk_packet_handler.nb_bytes); 02066 } 02067 02068 break; 02069 02070 case MODEM_LORA: 02071 // Sync time out 02072 rx_timeout_timer.detach(); 02073 // Clear Irq 02074 write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT); 02075 _rf_settings.state = RF_IDLE; 02076 if ((_radio_events != NULL) 02077 && (_radio_events->rx_timeout)) { 02078 _radio_events->rx_timeout(); 02079 } 02080 break; 02081 default: 02082 break; 02083 } 02084 02085 break; 02086 02087 case RF_TX_RUNNING: 02088 switch (_rf_settings.modem) { 02089 case MODEM_FSK: 02090 // FifoLevel interrupt 02091 if ((_rf_settings.fsk_packet_handler.size 02092 - _rf_settings.fsk_packet_handler.nb_bytes) 02093 > _rf_settings.fsk_packet_handler.chunk_size) { 02094 write_fifo((_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes), 02095 _rf_settings.fsk_packet_handler.chunk_size); 02096 _rf_settings.fsk_packet_handler.nb_bytes += 02097 _rf_settings.fsk_packet_handler.chunk_size; 02098 } else { 02099 // Write the last chunk of data 02100 write_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes, 02101 _rf_settings.fsk_packet_handler.size 02102 - _rf_settings.fsk_packet_handler.nb_bytes); 02103 _rf_settings.fsk_packet_handler.nb_bytes += 02104 _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes; 02105 } 02106 02107 break; 02108 02109 case MODEM_LORA: 02110 break; 02111 default: 02112 break; 02113 } 02114 break; 02115 default: 02116 break; 02117 } 02118 } 02119 02120 void SX1276_LoRaRadio::handle_dio2_irq(void) 02121 { 02122 switch (_rf_settings.state) { 02123 case RF_RX_RUNNING: 02124 switch (_rf_settings.modem) { 02125 case MODEM_FSK: 02126 // DIO4 must have been asserted to set preamble_detected to true 02127 if ((_rf_settings.fsk_packet_handler.preamble_detected == 1) 02128 && (_rf_settings.fsk_packet_handler.sync_word_detected == 0)) { 02129 if (_rf_settings.fsk.rx_continuous == false) { 02130 rx_timeout_sync_word.detach(); 02131 } 02132 02133 _rf_settings.fsk_packet_handler.sync_word_detected = 1; 02134 02135 _rf_settings.fsk_packet_handler.rssi_value = 02136 -(read_register(REG_RSSIVALUE) >> 1); 02137 02138 _rf_settings.fsk_packet_handler.afc_value = 02139 (int32_t) (double) (((uint16_t) read_register( 02140 REG_AFCMSB) << 8) 02141 | (uint16_t) read_register( REG_AFCLSB)) 02142 * (double) FREQ_STEP; 02143 _rf_settings.fsk_packet_handler.rx_gain = 02144 (read_register( REG_LNA) >> 5) & 0x07; 02145 } 02146 02147 break; 02148 02149 case MODEM_LORA: 02150 if (_rf_settings.lora.freq_hop_on == true) { 02151 // Clear Irq 02152 write_to_register(REG_LR_IRQFLAGS, 02153 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL); 02154 02155 if ((_radio_events != NULL) 02156 && (_radio_events->fhss_change_channel)) { 02157 _radio_events->fhss_change_channel( 02158 (read_register(REG_LR_HOPCHANNEL) 02159 & RFLR_HOPCHANNEL_CHANNEL_MASK)); 02160 } 02161 } 02162 02163 break; 02164 02165 default: 02166 break; 02167 } 02168 02169 break; 02170 02171 case RF_TX_RUNNING: 02172 switch (_rf_settings.modem) { 02173 case MODEM_FSK: 02174 break; 02175 case MODEM_LORA: 02176 if (_rf_settings.lora.freq_hop_on == true) { 02177 // Clear Irq 02178 write_to_register(REG_LR_IRQFLAGS, 02179 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL); 02180 02181 if ((_radio_events != NULL) 02182 && (_radio_events->fhss_change_channel)) { 02183 _radio_events->fhss_change_channel( 02184 (read_register(REG_LR_HOPCHANNEL) 02185 & RFLR_HOPCHANNEL_CHANNEL_MASK)); 02186 } 02187 } 02188 break; 02189 default: 02190 break; 02191 } 02192 break; 02193 default: 02194 break; 02195 } 02196 } 02197 02198 void SX1276_LoRaRadio::handle_dio3_irq(void) 02199 { 02200 switch (_rf_settings.modem) { 02201 case MODEM_FSK: 02202 break; 02203 case MODEM_LORA: 02204 if ((read_register(REG_LR_IRQFLAGS) & RFLR_IRQFLAGS_CADDETECTED) 02205 == RFLR_IRQFLAGS_CADDETECTED) { 02206 // Clear Irq 02207 write_to_register(REG_LR_IRQFLAGS, 02208 RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE); 02209 if ((_radio_events != NULL) 02210 && (_radio_events->cad_done)) { 02211 _radio_events->cad_done(true); 02212 } 02213 } else { 02214 // Clear Irq 02215 write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE); 02216 if ((_radio_events != NULL) 02217 && (_radio_events->cad_done)) { 02218 _radio_events->cad_done(false); 02219 } 02220 } 02221 break; 02222 default: 02223 break; 02224 } 02225 } 02226 02227 void SX1276_LoRaRadio::handle_dio4_irq(void) 02228 { 02229 // is asserted when a preamble is detected (FSK modem only) 02230 switch (_rf_settings.modem) { 02231 case MODEM_FSK: { 02232 if (_rf_settings.fsk_packet_handler.preamble_detected == 0) { 02233 _rf_settings.fsk_packet_handler.preamble_detected = 1; 02234 } 02235 } 02236 break; 02237 case MODEM_LORA: 02238 break; 02239 default: 02240 break; 02241 } 02242 } 02243 02244 void SX1276_LoRaRadio::handle_dio5_irq() 02245 { 02246 switch (_rf_settings.modem) { 02247 case MODEM_FSK: 02248 break; 02249 case MODEM_LORA: 02250 break; 02251 default: 02252 break; 02253 } 02254 } 02255 02256 02257 void SX1276_LoRaRadio::handle_timeout_irq() 02258 { 02259 switch (_rf_settings.state) { 02260 case RF_RX_RUNNING: 02261 if (_rf_settings.modem == MODEM_FSK) { 02262 _rf_settings.fsk_packet_handler.preamble_detected = 0; 02263 _rf_settings.fsk_packet_handler.sync_word_detected = 0; 02264 _rf_settings.fsk_packet_handler.nb_bytes = 0; 02265 _rf_settings.fsk_packet_handler.size = 0; 02266 02267 // Clear Irqs 02268 write_to_register(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 02269 RF_IRQFLAGS1_PREAMBLEDETECT | 02270 RF_IRQFLAGS1_SYNCADDRESSMATCH); 02271 write_to_register( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN); 02272 02273 if (_rf_settings.fsk.rx_continuous == true) { 02274 // Continuous mode restart Rx chain 02275 write_to_register( REG_RXCONFIG, 02276 read_register(REG_RXCONFIG) | 02277 RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK); 02278 } else { 02279 _rf_settings.state = RF_IDLE; 02280 rx_timeout_sync_word.attach_us( 02281 callback(this, &SX1276_LoRaRadio::timeout_irq_isr), 02282 _rf_settings.fsk.rx_single_timeout * 1e3); 02283 } 02284 } 02285 02286 if ((_radio_events != NULL) 02287 && (_radio_events->rx_timeout)) { 02288 _radio_events->rx_timeout(); 02289 } 02290 02291 break; 02292 02293 case RF_TX_RUNNING: 02294 // Tx timeout shouldn't happen. 02295 // But it has been observed that when it happens it is a result of a 02296 // corrupted SPI transfer 02297 // The workaround is to put the radio in a known state. 02298 // Thus, we re-initialize it. 02299 02300 // Reset the radio 02301 radio_reset(); 02302 02303 // Initialize radio default values 02304 set_operation_mode(RF_OPMODE_SLEEP); 02305 02306 setup_registers(); 02307 02308 set_modem(MODEM_FSK); 02309 02310 // Restore previous network type setting. 02311 set_public_network(_rf_settings.lora.public_network); 02312 02313 _rf_settings.state = RF_IDLE; 02314 if ((_radio_events != NULL) 02315 && (_radio_events->tx_timeout)) { 02316 _radio_events->tx_timeout(); 02317 } 02318 break; 02319 default: 02320 break; 02321 } 02322 } 02323 // EOF 02324 02325 #endif //DEVICE_SPI 02326
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