stephen mathenge
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Level_estimation_Maesurement
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SX1272_LoRaRadio.cpp
00001 /** 00002 / _____) _ | | 00003 ( (____ _____ ____ _| |_ _____ ____| |__ 00004 \____ \| ___ | (_ _) ___ |/ ___) _ \ 00005 _____) ) ____| | | || |_| ____( (___| | | | 00006 (______/|_____)_|_|_| \__)_____)\____)_| |_| 00007 (C)2013 Semtech 00008 ___ _____ _ ___ _ _____ ___ ___ ___ ___ 00009 / __|_ _/_\ / __| |/ / __/ _ \| _ \/ __| __| 00010 \__ \ | |/ _ \ (__| ' <| _| (_) | / (__| _| 00011 |___/ |_/_/ \_\___|_|\_\_| \___/|_|_\\___|___| 00012 embedded.connectivity.solutions=============== 00013 00014 Description: Radio driver for Semtech SX1272 LoRa radio chip. Implements LoRaRadio class. 00015 00016 License: Revised BSD License, see LICENSE.TXT file include in the project 00017 00018 Maintainer: Miguel Luis ( Semtech ), Gregory Cristian ( Semtech ) and Daniel Jaeckle ( STACKFORCE ) 00019 00020 00021 Copyright (c) 2017, Arm Limited and affiliates. 00022 00023 SPDX-License-Identifier: BSD-3-Clause 00024 */ 00025 00026 #include <stdio.h> 00027 #include <math.h> //rint 00028 #include <string.h> 00029 #include "mbed.h" 00030 00031 #include "SX1272_LoRaRadio.h" 00032 #include "sx1272Regs-Fsk.h" 00033 #include "sx1272Regs-LoRa.h" 00034 00035 #ifdef DEVICE_SPI 00036 00037 #if defined(FEATURE_COMMON_PAL) 00038 #include "mbed_trace.h" 00039 #define TRACE_GROUP "LRAD" 00040 #else 00041 #define tr_debug(...) (void(0)) //dummies if feature common pal is not added 00042 #define tr_info(...) (void(0)) //dummies if feature common pal is not added 00043 #define tr_error(...) (void(0)) //dummies if feature common pal is not added 00044 #endif //defined(FEATURE_COMMON_PAL) 00045 00046 #ifdef MBED_SX1272_LORA_RADIO_SPI_FREQUENCY 00047 #define SPI_FREQUENCY MBED_SX1272_LORA_RADIO_SPI_FREQUENCY 00048 #else 00049 #define SPI_FREQUENCY 8000000 00050 #endif 00051 00052 // Sync word for Private LoRa networks 00053 #define LORA_MAC_PRIVATE_SYNCWORD 0x12 00054 // Sync word for Public LoRa networks 00055 #define LORA_MAC_PUBLIC_SYNCWORD 0x34 00056 00057 // SX1272 definitions 00058 #define XTAL_FREQ 32000000 00059 #define FREQ_STEP 61.03515625 00060 00061 00062 00063 enum RadioVariant { 00064 SX1272UNDEFINED = 0, 00065 SX1272MB2XAS, 00066 SX1272MB1DCS 00067 }; 00068 00069 /*! 00070 * FSK bandwidth definition 00071 */ 00072 typedef struct 00073 { 00074 uint32_t bandwidth; 00075 uint8_t register_value; 00076 } fsk_bw_t; 00077 00078 /*! 00079 * Radio registers definition 00080 */ 00081 typedef struct 00082 { 00083 modem_type modem; 00084 uint8_t addr; 00085 uint8_t value; 00086 } radio_registers_t; 00087 00088 /*! 00089 * Constant values need to compute the RSSI value 00090 */ 00091 #define RSSI_OFFSET -139 00092 00093 #define RADIO_INIT_REGISTERS_VALUE \ 00094 { \ 00095 { MODEM_FSK , REG_LNA , 0x23 },\ 00096 { MODEM_FSK , REG_RXCONFIG , 0x1E },\ 00097 { MODEM_FSK , REG_RSSICONFIG , 0xD2 },\ 00098 { MODEM_FSK , REG_AFCFEI , 0x01 },\ 00099 { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },\ 00100 { MODEM_FSK , REG_OSC , 0x07 },\ 00101 { MODEM_FSK , REG_SYNCCONFIG , 0x12 },\ 00102 { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },\ 00103 { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },\ 00104 { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },\ 00105 { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },\ 00106 { MODEM_FSK , REG_FIFOTHRESH , 0x8F },\ 00107 { MODEM_FSK , REG_IMAGECAL , 0x02 },\ 00108 { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },\ 00109 { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },\ 00110 { MODEM_LORA, REG_LR_DETECTOPTIMIZE , 0x43 },\ 00111 { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },\ 00112 } 00113 00114 const fsk_bw_t fsk_bandwidths[] = 00115 { 00116 { 2600 , 0x17 }, 00117 { 3100 , 0x0F }, 00118 { 3900 , 0x07 }, 00119 { 5200 , 0x16 }, 00120 { 6300 , 0x0E }, 00121 { 7800 , 0x06 }, 00122 { 10400 , 0x15 }, 00123 { 12500 , 0x0D }, 00124 { 15600 , 0x05 }, 00125 { 20800 , 0x14 }, 00126 { 25000 , 0x0C }, 00127 { 31300 , 0x04 }, 00128 { 41700 , 0x13 }, 00129 { 50000 , 0x0B }, 00130 { 62500 , 0x03 }, 00131 { 83333 , 0x12 }, 00132 { 100000, 0x0A }, 00133 { 125000, 0x02 }, 00134 { 166700, 0x11 }, 00135 { 200000, 0x09 }, 00136 { 250000, 0x01 }, 00137 { 300000, 0x00 }, // Invalid bandwidth 00138 }; 00139 00140 /** 00141 * SPI read/write masks 00142 */ 00143 #define SPI_WRITE_CMD 0x80 00144 #define SPI_READ_CMD 0x7F 00145 00146 /** 00147 * Signals 00148 */ 00149 #define SIG_DIO0 0x01 00150 #define SIG_DIO1 0x02 00151 #define SIG_DIO2 0x04 00152 #define SIG_DIO3 0x08 00153 #define SIG_DIO4 0x10 00154 #define SIG_DIO5 0x20 00155 #define SIG_TIMOUT 0x40 00156 00157 /** 00158 * Radio hardware registers initialization 00159 */ 00160 static const radio_registers_t radio_reg_init[] = RADIO_INIT_REGISTERS_VALUE; 00161 00162 00163 /** 00164 * Constructor 00165 */ 00166 SX1272_LoRaRadio::SX1272_LoRaRadio(PinName spi_mosi, 00167 PinName spi_miso, 00168 PinName spi_sclk, 00169 PinName nss, 00170 PinName reset, 00171 PinName dio0, 00172 PinName dio1, 00173 PinName dio2, 00174 PinName dio3, 00175 PinName dio4, 00176 PinName dio5, 00177 PinName rf_switch_ctl1, 00178 PinName rf_switch_ctl2, 00179 PinName txctl, 00180 PinName rxctl, 00181 PinName antswitch, 00182 PinName pwr_amp_ctl, 00183 PinName tcxo) 00184 : _spi(spi_mosi, spi_miso, spi_sclk), 00185 _chip_select(nss, 1), 00186 _reset_ctl(reset), 00187 _dio0_ctl(dio0), _dio1_ctl(dio1), _dio2_ctl(dio2), _dio3_ctl(dio3), _dio4_ctl(dio4), _dio5_ctl(dio5), 00188 _rf_switch_ctl1(rf_switch_ctl1, 0), _rf_switch_ctl2(rf_switch_ctl2, 0), _txctl(txctl, 0), _rxctl(rxctl, 0), 00189 _ant_switch(antswitch, PIN_INPUT, PullUp, 0), 00190 _pwr_amp_ctl(pwr_amp_ctl), 00191 _tcxo(tcxo) 00192 00193 #ifdef MBED_CONF_RTOS_PRESENT 00194 , irq_thread(osPriorityRealtime, 1024) 00195 #endif 00196 { 00197 _rf_ctrls.ant_switch = antswitch; 00198 _rf_ctrls.pwr_amp_ctl = pwr_amp_ctl; 00199 _rf_ctrls.rf_switch_ctl1 = rf_switch_ctl1; 00200 _rf_ctrls.rf_switch_ctl2 = rf_switch_ctl2; 00201 _rf_ctrls.rxctl = rxctl; 00202 _rf_ctrls.txctl = txctl; 00203 00204 _dio4_pin = dio4; 00205 _dio5_pin = dio5; 00206 00207 _radio_events = NULL; 00208 00209 if (tcxo != NC) { 00210 _tcxo = 1; 00211 } 00212 00213 radio_is_active = false; 00214 00215 #ifdef MBED_CONF_RTOS_PRESENT 00216 irq_thread.start(mbed::callback(this, &SX1272_LoRaRadio::rf_irq_task)); 00217 #endif 00218 } 00219 00220 /** 00221 * Destructor 00222 */ 00223 SX1272_LoRaRadio::~SX1272_LoRaRadio() 00224 { 00225 00226 } 00227 00228 /***************************************************************************** 00229 * Public APIs * 00230 ****************************************************************************/ 00231 00232 /** 00233 * Acquire lock 00234 */ 00235 void SX1272_LoRaRadio::lock(void) 00236 { 00237 mutex.lock(); 00238 } 00239 00240 /** 00241 * Release lock 00242 */ 00243 void SX1272_LoRaRadio::unlock(void) 00244 { 00245 mutex.unlock(); 00246 } 00247 00248 /** 00249 * Initializes radio module 00250 */ 00251 void SX1272_LoRaRadio::init_radio(radio_events_t *events) 00252 { 00253 _radio_events = events; 00254 00255 // Reset the radio transceiver 00256 radio_reset(); 00257 00258 // Setup radio variant type 00259 set_sx1272_variant_type(); 00260 00261 // setup SPI frequency 00262 // default is 8MHz although, configurable through 00263 // SPI_FREQUENCY macro 00264 setup_spi(); 00265 00266 // set radio mode to sleep 00267 set_operation_mode(RF_OPMODE_SLEEP); 00268 00269 // Setup radio registers to defaults 00270 setup_registers(); 00271 00272 // set modem type - defaults to FSK here 00273 set_modem(MODEM_FSK); 00274 00275 // set state to be idle 00276 _rf_settings.state = RF_IDLE; 00277 00278 // Setup interrupts on DIO pins 00279 setup_interrupts(); 00280 } 00281 00282 /** 00283 * TODO: The purpose of this API is unclear. 00284 * Need to start an internal discussion. 00285 */ 00286 bool SX1272_LoRaRadio::check_rf_frequency(uint32_t frequency) 00287 { 00288 // Implement check. Currently all frequencies are supported ? What band ? 00289 return true; 00290 } 00291 00292 /** 00293 * Sets up carrier frequency 00294 */ 00295 void SX1272_LoRaRadio::set_channel(uint32_t freq) 00296 { 00297 _rf_settings.channel = freq; 00298 freq = (uint32_t) ((double) freq / (double) FREQ_STEP); 00299 write_to_register(REG_FRFMSB, (uint8_t) ((freq >> 16) & 0xFF)); 00300 write_to_register(REG_FRFMID, (uint8_t) ((freq >> 8) & 0xFF)); 00301 write_to_register(REG_FRFLSB, (uint8_t) (freq & 0xFF)); 00302 } 00303 00304 /** 00305 * Returns current status of the radio state machine 00306 */ 00307 uint8_t SX1272_LoRaRadio::get_status(void) 00308 { 00309 return _rf_settings.state; 00310 } 00311 00312 /** 00313 * sets the radio module to sleep 00314 */ 00315 00316 void SX1272_LoRaRadio::sleep() 00317 { 00318 // stop timers 00319 tx_timeout_timer.detach(); 00320 rx_timeout_timer.detach(); 00321 00322 // put module in sleep mode 00323 set_operation_mode(RF_OPMODE_SLEEP); 00324 } 00325 00326 /** 00327 * Sets up operation mode 00328 */ 00329 void SX1272_LoRaRadio::set_operation_mode(uint8_t mode) 00330 { 00331 if (mode == RF_OPMODE_SLEEP) { 00332 set_low_power_mode(true); 00333 } else { 00334 set_low_power_mode(false); 00335 set_antenna_switch(mode); 00336 } 00337 00338 write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RF_OPMODE_MASK) | mode); 00339 } 00340 00341 /** 00342 * Sets the modem type to use 00343 * 00344 * At initialization FSK is chosen. Later stack or application 00345 * can choose to change. 00346 */ 00347 void SX1272_LoRaRadio::set_modem(uint8_t modem ) 00348 { 00349 if ((read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_ON) != 0 ) { 00350 _rf_settings.modem = MODEM_LORA; 00351 } else { 00352 _rf_settings.modem = MODEM_FSK; 00353 } 00354 00355 if(_rf_settings.modem == modem ) { 00356 // if the modem is already set 00357 return; 00358 } 00359 00360 _rf_settings.modem = modem; 00361 00362 switch(_rf_settings.modem) 00363 { 00364 default: 00365 case MODEM_FSK: 00366 // before changing modem mode, put the module to sleep 00367 sleep(); 00368 write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK) 00369 | RFLR_OPMODE_LONGRANGEMODE_OFF); 00370 00371 // Datasheet Tables 28, 29 DIO mapping 00372 write_to_register(REG_DIOMAPPING1, 0x00); // sets DIO0-DI03 in default mode 00373 write_to_register(REG_DIOMAPPING2, 0x30); // bits 4-5 are turned on i.e., 00374 // DIO5 and DIO4=ModeReady 00375 break; 00376 case MODEM_LORA: 00377 sleep(); 00378 write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK) 00379 | RFLR_OPMODE_LONGRANGEMODE_ON); 00380 00381 // Datasheet Tables 17 DIO mapping for LoRa 00382 // set to defaults 00383 write_to_register(REG_DIOMAPPING1, 0x00); // DIO0 - DIO3 defaults 00384 write_to_register(REG_DIOMAPPING2, 0x00); // DIO4 - DIO5 defaults 00385 00386 break; 00387 } 00388 } 00389 00390 /** 00391 * Can be used by application/stack or the driver itself 00392 * Ref: Datasheet 7.2.2 Manual Reset 00393 */ 00394 void SX1272_LoRaRadio::radio_reset() 00395 { 00396 _reset_ctl.output(); 00397 _reset_ctl = 0; 00398 wait_ms(2); 00399 _reset_ctl.input(); 00400 wait_ms(6); 00401 } 00402 00403 /** 00404 * Sets up receiver related configurations 00405 * 00406 * Must be called before setting the radio in rx mode 00407 */ 00408 void SX1272_LoRaRadio::set_rx_config(radio_modems_t modem, uint32_t bandwidth, 00409 uint32_t datarate, uint8_t coderate, 00410 uint32_t bandwidth_afc, uint16_t preamble_len, 00411 uint16_t symb_timeout, bool fix_len, 00412 uint8_t payload_len, 00413 bool crc_on, bool freq_hop_on, uint8_t hop_period, 00414 bool iq_inverted, bool rx_continuous) 00415 { 00416 set_modem(modem); 00417 00418 switch (modem) { 00419 case MODEM_FSK: 00420 _rf_settings.fsk.bandwidth = bandwidth; 00421 _rf_settings.fsk.datarate = datarate; 00422 _rf_settings.fsk.bandwidth_afc = bandwidth_afc; 00423 _rf_settings.fsk.fix_len = fix_len; 00424 _rf_settings.fsk.payload_len = payload_len; 00425 _rf_settings.fsk.crc_on = crc_on; 00426 _rf_settings.fsk.iq_inverted = iq_inverted; 00427 _rf_settings.fsk.rx_continuous = rx_continuous; 00428 _rf_settings.fsk.preamble_len = preamble_len; 00429 _rf_settings.fsk.rx_single_timeout = 00430 symb_timeout * ((1.0 / (double) datarate) * 8.0) * 1e3; 00431 00432 datarate = (uint16_t) ((double) XTAL_FREQ / (double) datarate); 00433 write_to_register(REG_BITRATEMSB, (uint8_t) (datarate >> 8)); 00434 write_to_register(REG_BITRATELSB, (uint8_t) (datarate & 0xFF)); 00435 00436 write_to_register(REG_RXBW, get_fsk_bw_reg_val(bandwidth)); 00437 write_to_register(REG_AFCBW, get_fsk_bw_reg_val(bandwidth_afc)); 00438 00439 write_to_register(REG_PREAMBLEMSB, (uint8_t) ((preamble_len >> 8) & 0xFF)); 00440 write_to_register(REG_PREAMBLELSB, (uint8_t) (preamble_len & 0xFF)); 00441 00442 if (fix_len == 1) { 00443 write_to_register(REG_PAYLOADLENGTH, payload_len); 00444 } else { 00445 write_to_register(REG_PAYLOADLENGTH, 0xFF); // Set payload length to the maximum 00446 } 00447 00448 write_to_register(REG_PACKETCONFIG1, (read_register(REG_PACKETCONFIG1) & RF_PACKETCONFIG1_CRC_MASK 00449 & RF_PACKETCONFIG1_PACKETFORMAT_MASK) 00450 | ((fix_len == 1) ? 00451 RF_PACKETCONFIG1_PACKETFORMAT_FIXED : 00452 RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE) 00453 | (crc_on << 4)); 00454 00455 // TODO why packet mode 2 ? 00456 write_to_register(REG_PACKETCONFIG2, (read_register(REG_PACKETCONFIG2) | RF_PACKETCONFIG2_DATAMODE_PACKET)); 00457 00458 break; 00459 00460 case MODEM_LORA: 00461 _rf_settings.lora.bandwidth = bandwidth; 00462 _rf_settings.lora.datarate = datarate; 00463 _rf_settings.lora.coderate = coderate; 00464 _rf_settings.lora.preamble_len = preamble_len; 00465 _rf_settings.lora.fix_len = fix_len; 00466 _rf_settings.lora.payload_len = payload_len; 00467 _rf_settings.lora.crc_on = crc_on; 00468 _rf_settings.lora.freq_hop_on = freq_hop_on; 00469 _rf_settings.lora.hop_period = hop_period; 00470 _rf_settings.lora.iq_inverted = iq_inverted; 00471 _rf_settings.lora.rx_continuous = rx_continuous; 00472 00473 if (datarate > 12) { 00474 datarate = 12; 00475 } else if (datarate < 6) { 00476 datarate = 6; 00477 } 00478 00479 if (((bandwidth == 0) && ((datarate == 11) || (datarate == 12))) 00480 || ((bandwidth == 1) && (datarate == 12))) { 00481 _rf_settings.lora.low_datarate_optimize = 0x01; 00482 } else { 00483 _rf_settings.lora.low_datarate_optimize = 0x00; 00484 } 00485 00486 write_to_register(REG_LR_MODEMCONFIG1, (read_register(REG_LR_MODEMCONFIG1) & RFLR_MODEMCONFIG1_BW_MASK 00487 & RFLR_MODEMCONFIG1_CODINGRATE_MASK 00488 & RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 00489 & RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK & RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK) 00490 | (bandwidth << 6) 00491 | (coderate << 3) | (fix_len << 2) | (crc_on << 1) 00492 | _rf_settings.lora.low_datarate_optimize); 00493 00494 write_to_register(REG_LR_MODEMCONFIG2, (read_register(REG_LR_MODEMCONFIG2) & RFLR_MODEMCONFIG2_SF_MASK 00495 & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK) 00496 | (datarate << 4) 00497 | ((symb_timeout >> 8) 00498 & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK)); 00499 00500 write_to_register(REG_LR_SYMBTIMEOUTLSB, (uint8_t) (symb_timeout & 0xFF)); 00501 00502 write_to_register(REG_LR_PREAMBLEMSB, (uint8_t) ((preamble_len >> 8) & 0xFF)); 00503 write_to_register(REG_LR_PREAMBLELSB, (uint8_t) (preamble_len & 0xFF)); 00504 00505 if (fix_len == 1) { 00506 write_to_register(REG_LR_PAYLOADLENGTH, payload_len); 00507 } 00508 00509 if (_rf_settings.lora.freq_hop_on == true) { 00510 write_to_register( REG_LR_PLLHOP, (read_register(REG_LR_PLLHOP) & RFLR_PLLHOP_FASTHOP_MASK) 00511 | RFLR_PLLHOP_FASTHOP_ON); 00512 write_to_register( REG_LR_HOPPERIOD, _rf_settings.lora.hop_period); 00513 } 00514 00515 if (datarate == 6) { 00516 write_to_register( REG_LR_DETECTOPTIMIZE, (read_register(REG_LR_DETECTOPTIMIZE) & RFLR_DETECTIONOPTIMIZE_MASK) 00517 | RFLR_DETECTIONOPTIMIZE_SF6); 00518 write_to_register( REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF6); 00519 } else { 00520 write_to_register(REG_LR_DETECTOPTIMIZE, (read_register(REG_LR_DETECTOPTIMIZE) & RFLR_DETECTIONOPTIMIZE_MASK) 00521 | RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12); 00522 write_to_register( REG_LR_DETECTIONTHRESHOLD, RFLR_DETECTIONTHRESH_SF7_TO_SF12); 00523 } 00524 00525 break; 00526 00527 default: 00528 break; 00529 } 00530 } 00531 00532 /** 00533 * Sets up transmitter related configuration 00534 * 00535 * Must be called before putting the radio module in Tx mode or trying 00536 * to send 00537 */ 00538 void SX1272_LoRaRadio::set_tx_config(radio_modems_t modem, int8_t power, 00539 uint32_t fdev, uint32_t bandwidth, 00540 uint32_t datarate, uint8_t coderate, 00541 uint16_t preamble_len, bool fix_len, 00542 bool crc_on, bool freq_hop_on, 00543 uint8_t hop_period, bool iq_inverted, 00544 uint32_t timeout) 00545 { 00546 set_modem(modem); 00547 set_rf_tx_power(power); 00548 00549 switch (modem) { 00550 case MODEM_FSK: 00551 _rf_settings.fsk.power = power; 00552 _rf_settings.fsk.f_dev = fdev; 00553 _rf_settings.fsk.bandwidth = bandwidth; 00554 _rf_settings.fsk.datarate = datarate; 00555 _rf_settings.fsk.preamble_len = preamble_len; 00556 _rf_settings.fsk.fix_len = fix_len; 00557 _rf_settings.fsk.crc_on = crc_on; 00558 _rf_settings.fsk.iq_inverted = iq_inverted; 00559 _rf_settings.fsk.tx_timeout = timeout; 00560 00561 fdev = (uint16_t) ((double) fdev / (double) FREQ_STEP); 00562 write_to_register( REG_FDEVMSB, (uint8_t) (fdev >> 8)); 00563 write_to_register( REG_FDEVLSB, (uint8_t) (fdev & 0xFF)); 00564 00565 datarate = (uint16_t) ((double) XTAL_FREQ / (double) datarate); 00566 write_to_register( REG_BITRATEMSB, (uint8_t) (datarate >> 8)); 00567 write_to_register( REG_BITRATELSB, (uint8_t) (datarate & 0xFF)); 00568 00569 write_to_register( REG_PREAMBLEMSB, (preamble_len >> 8) & 0x00FF); 00570 write_to_register( REG_PREAMBLELSB, preamble_len & 0xFF); 00571 00572 00573 write_to_register(REG_PACKETCONFIG1, (read_register(REG_PACKETCONFIG1) 00574 & RF_PACKETCONFIG1_CRC_MASK 00575 & RF_PACKETCONFIG1_PACKETFORMAT_MASK) 00576 | ((fix_len == 1) ? 00577 RF_PACKETCONFIG1_PACKETFORMAT_FIXED : 00578 RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE) 00579 | (crc_on << 4)); 00580 00581 //cfg_mode = read_register(REG_PACKETCONFIG2); 00582 write_to_register(REG_PACKETCONFIG2, read_register(REG_PACKETCONFIG2) 00583 | RF_PACKETCONFIG2_DATAMODE_PACKET); 00584 00585 break; 00586 00587 case MODEM_LORA: 00588 _rf_settings.lora.power = power; 00589 _rf_settings.lora.bandwidth = bandwidth; 00590 _rf_settings.lora.datarate = datarate; 00591 _rf_settings.lora.coderate = coderate; 00592 _rf_settings.lora.preamble_len = preamble_len; 00593 _rf_settings.lora.fix_len = fix_len; 00594 _rf_settings.lora.freq_hop_on = freq_hop_on; 00595 _rf_settings.lora.hop_period = hop_period; 00596 _rf_settings.lora.crc_on = crc_on; 00597 _rf_settings.lora.iq_inverted = iq_inverted; 00598 _rf_settings.lora.tx_timeout = timeout; 00599 00600 if (datarate > 12) { 00601 datarate = 12; 00602 } else if (datarate < 6) { 00603 datarate = 6; 00604 } 00605 if (((bandwidth == 0) && ((datarate == 11) || (datarate == 12))) 00606 || ((bandwidth == 1) && (datarate == 12))) { 00607 _rf_settings.lora.low_datarate_optimize = 0x01; 00608 } else { 00609 _rf_settings.lora.low_datarate_optimize = 0x00; 00610 } 00611 00612 if (_rf_settings.lora.freq_hop_on == true) { 00613 write_to_register(REG_LR_PLLHOP, (read_register(REG_LR_PLLHOP) 00614 & RFLR_PLLHOP_FASTHOP_MASK) 00615 | RFLR_PLLHOP_FASTHOP_ON); 00616 write_to_register(REG_LR_HOPPERIOD, _rf_settings.lora.hop_period); 00617 } 00618 00619 write_to_register(REG_LR_MODEMCONFIG1, (read_register(REG_LR_MODEMCONFIG1) & 00620 RFLR_MODEMCONFIG1_BW_MASK & 00621 RFLR_MODEMCONFIG1_CODINGRATE_MASK & 00622 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK & 00623 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK & 00624 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK) 00625 | (bandwidth << 6) | (coderate << 3) 00626 | (fix_len << 2) | (crc_on << 1) 00627 | _rf_settings.lora.low_datarate_optimize); 00628 00629 write_to_register(REG_LR_MODEMCONFIG2, 00630 (read_register(REG_LR_MODEMCONFIG2) & 00631 RFLR_MODEMCONFIG2_SF_MASK) | (datarate << 4)); 00632 00633 write_to_register( REG_LR_PREAMBLEMSB, (preamble_len >> 8) & 0x00FF); 00634 write_to_register( REG_LR_PREAMBLELSB, preamble_len & 0xFF); 00635 00636 if (datarate == 6) { 00637 write_to_register(REG_LR_DETECTOPTIMIZE, 00638 (read_register(REG_LR_DETECTOPTIMIZE) & 00639 RFLR_DETECTIONOPTIMIZE_MASK) | 00640 RFLR_DETECTIONOPTIMIZE_SF6); 00641 write_to_register( REG_LR_DETECTIONTHRESHOLD, 00642 RFLR_DETECTIONTHRESH_SF6); 00643 } else { 00644 write_to_register(REG_LR_DETECTOPTIMIZE, 00645 (read_register(REG_LR_DETECTOPTIMIZE) & 00646 RFLR_DETECTIONOPTIMIZE_MASK) | 00647 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12); 00648 write_to_register(REG_LR_DETECTIONTHRESHOLD, 00649 RFLR_DETECTIONTHRESH_SF7_TO_SF12); 00650 } 00651 00652 break; 00653 } 00654 } 00655 00656 /** 00657 * Calculates time on Air i.e., dwell time for a single packet 00658 * 00659 * Crucial for the stack in order to calculate dwell time so as to control 00660 * duty cycling. 00661 */ 00662 uint32_t SX1272_LoRaRadio::time_on_air(radio_modems_t modem, uint8_t pkt_len) 00663 { 00664 uint32_t airtime = 0; 00665 00666 switch (modem) { 00667 case MODEM_FSK: { 00668 airtime = rint((8 * (_rf_settings.fsk.preamble_len 00669 + ((read_register( REG_SYNCCONFIG) 00670 & ~RF_SYNCCONFIG_SYNCSIZE_MASK) + 1) 00671 + ((_rf_settings.fsk.fix_len == 0x01) ? 00672 0.0 : 1.0) 00673 + (((read_register( REG_PACKETCONFIG1) 00674 & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK) 00675 != 0x00) ? 1.0 : 0) + pkt_len 00676 + ((_rf_settings.fsk.crc_on == 0x01) ? 00677 2.0 : 0)) 00678 / _rf_settings.fsk.datarate) * 1e3); 00679 } 00680 break; 00681 case MODEM_LORA: { 00682 double bw = 0.0; 00683 switch (_rf_settings.lora.bandwidth) { 00684 case 0: // 125 kHz 00685 bw = 125e3; 00686 break; 00687 case 1: // 250 kHz 00688 bw = 250e3; 00689 break; 00690 case 2: // 500 kHz 00691 bw = 500e3; 00692 break; 00693 } 00694 00695 // Symbol rate : time for one symbol (secs) 00696 double rs = bw / (1 << _rf_settings.lora.datarate); 00697 double ts = 1 / rs; 00698 // time of preamble 00699 double preamble_time = (_rf_settings.lora.preamble_len + 4.25) * ts; 00700 // Symbol length of payload and time 00701 double tmp = ceil((8 * pkt_len - 4 * _rf_settings.lora.datarate + 28 00702 + 16 * _rf_settings.lora.crc_on - 00703 (_rf_settings.lora.fix_len ? 20 : 0)) 00704 / (double) (4 * (_rf_settings.lora.datarate - 00705 ((_rf_settings.lora.low_datarate_optimize 00706 > 0) ? 2 : 0)))) * 00707 (_rf_settings.lora.coderate + 4); 00708 double n_payload = 8 + ((tmp > 0) ? tmp : 0); 00709 double t_payload = n_payload * ts; 00710 // Time on air 00711 double t_onair = preamble_time + t_payload; 00712 // return ms secs 00713 airtime = floor(t_onair * 1e3 + 0.999); 00714 } 00715 break; 00716 } 00717 return airtime; 00718 } 00719 00720 /** 00721 * Prepares and sends the radio packet out in the air 00722 */ 00723 void SX1272_LoRaRadio::send(uint8_t *buffer, uint8_t size) 00724 { 00725 uint32_t tx_timeout = 0; 00726 00727 switch (_rf_settings.modem) { 00728 case MODEM_FSK: 00729 00730 _rf_settings.fsk_packet_handler.nb_bytes = 0; 00731 _rf_settings.fsk_packet_handler.size = size; 00732 00733 // FIFO operations can not take place in Sleep mode 00734 if ((read_register(REG_OPMODE) & ~RF_OPMODE_MASK) == RF_OPMODE_SLEEP) { 00735 standby(); 00736 wait_ms(1); 00737 } 00738 00739 if (_rf_settings.fsk.fix_len == false) { 00740 write_fifo((uint8_t *) &size, 1); 00741 } else { 00742 write_to_register(REG_PAYLOADLENGTH, size); 00743 } 00744 00745 if ((size > 0) && (size <= 64)) { 00746 _rf_settings.fsk_packet_handler.chunk_size = size; 00747 } else { 00748 memcpy(_data_buffer, buffer, size); 00749 _rf_settings.fsk_packet_handler.chunk_size = 32; 00750 } 00751 00752 // write payload buffer 00753 write_fifo(buffer, _rf_settings.fsk_packet_handler.chunk_size); 00754 _rf_settings.fsk_packet_handler.nb_bytes += 00755 _rf_settings.fsk_packet_handler.chunk_size; 00756 tx_timeout = _rf_settings.fsk.tx_timeout; 00757 00758 break; 00759 case MODEM_LORA: 00760 if (_rf_settings.lora.iq_inverted == true) { 00761 write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) & 00762 RFLR_INVERTIQ_TX_MASK & 00763 RFLR_INVERTIQ_RX_MASK) | 00764 RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON)); 00765 write_to_register(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON); 00766 } else { 00767 write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) & 00768 RFLR_INVERTIQ_TX_MASK & 00769 RFLR_INVERTIQ_RX_MASK) | 00770 RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF)); 00771 write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF); 00772 } 00773 00774 _rf_settings.lora_packet_handler.size = size; 00775 00776 // Initializes the payload size 00777 write_to_register(REG_LR_PAYLOADLENGTH, size); 00778 00779 // Full buffer used for Tx 00780 write_to_register(REG_LR_FIFOTXBASEADDR, 0); 00781 write_to_register(REG_LR_FIFOADDRPTR, 0); 00782 00783 // FIFO operations can not take place in Sleep mode 00784 if ((read_register(REG_OPMODE) & ~RF_OPMODE_MASK) == RF_OPMODE_SLEEP) { 00785 standby(); 00786 wait_ms(1); 00787 } 00788 // write payload buffer 00789 write_fifo(buffer, size); 00790 tx_timeout = _rf_settings.lora.tx_timeout; 00791 00792 break; 00793 } 00794 00795 // transmit 00796 transmit(tx_timeout); 00797 } 00798 00799 /** 00800 * Actual TX - Transmit routine 00801 * 00802 * A DIO0 interrupt let the state machine know that a a packet is 00803 * successfully sent, otherwise a TxTimeout is invoked. 00804 * TxTimeout should never happen in normal circumstances as the radio should 00805 * be able to send a packet out in the air no matter what. 00806 */ 00807 void SX1272_LoRaRadio::transmit(uint32_t timeout) 00808 { 00809 switch (_rf_settings.modem) { 00810 00811 case MODEM_FSK: 00812 // DIO0=PacketSent 00813 // DIO1=FifoEmpty 00814 // DIO2=FifoFull 00815 // DIO3=FifoEmpty 00816 // DIO4=LowBat 00817 // DIO5=ModeReady 00818 write_to_register(REG_DIOMAPPING1,(read_register(REG_DIOMAPPING1) & 00819 RF_DIOMAPPING1_DIO0_MASK & 00820 RF_DIOMAPPING1_DIO1_MASK & 00821 RF_DIOMAPPING1_DIO2_MASK) | 00822 RF_DIOMAPPING1_DIO1_01); 00823 00824 write_to_register(REG_DIOMAPPING2, (read_register(REG_DIOMAPPING2) & 00825 RF_DIOMAPPING2_DIO4_MASK & 00826 RF_DIOMAPPING2_MAP_MASK)); 00827 _rf_settings.fsk_packet_handler.fifo_thresh = 00828 read_register(REG_FIFOTHRESH) & 0x3F; 00829 00830 break; 00831 00832 case MODEM_LORA: 00833 00834 if (_rf_settings.lora.freq_hop_on == true) { 00835 write_to_register(REG_LR_IRQFLAGSMASK, 00836 RFLR_IRQFLAGS_RXTIMEOUT | 00837 RFLR_IRQFLAGS_RXDONE | 00838 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00839 RFLR_IRQFLAGS_VALIDHEADER | 00840 RFLR_IRQFLAGS_CADDONE | 00841 RFLR_IRQFLAGS_CADDETECTED); 00842 00843 // DIO0=tx_done, DIO2=fhss_change_channel 00844 00845 write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) & 00846 RFLR_DIOMAPPING1_DIO0_MASK & 00847 RFLR_DIOMAPPING1_DIO2_MASK) | 00848 RFLR_DIOMAPPING1_DIO0_01 | 00849 RFLR_DIOMAPPING1_DIO2_00); 00850 } else { 00851 write_to_register(REG_LR_IRQFLAGSMASK, 00852 RFLR_IRQFLAGS_RXTIMEOUT | 00853 RFLR_IRQFLAGS_RXDONE | 00854 RFLR_IRQFLAGS_PAYLOADCRCERROR | 00855 RFLR_IRQFLAGS_VALIDHEADER | 00856 RFLR_IRQFLAGS_CADDONE | 00857 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00858 RFLR_IRQFLAGS_CADDETECTED); 00859 00860 // DIO0=tx_done 00861 write_to_register(REG_DIOMAPPING1,(read_register(REG_DIOMAPPING1) & 00862 RFLR_DIOMAPPING1_DIO0_MASK) | 00863 RFLR_DIOMAPPING1_DIO0_01); 00864 } 00865 00866 break; 00867 } 00868 00869 _rf_settings.state = RF_TX_RUNNING; 00870 tx_timeout_timer.attach_us(callback(this, &SX1272_LoRaRadio::timeout_irq_isr), timeout*1e3); 00871 set_operation_mode(RF_OPMODE_TRANSMITTER); 00872 } 00873 00874 /** 00875 * Sets the radio module in receive mode 00876 * 00877 * A DIO4 interrupt let's the state machine know that a preamble is detected 00878 * and finally a DIO0 interrupt let's the state machine know that a packet is 00879 * ready to be read from the FIFO 00880 */ 00881 void SX1272_LoRaRadio::receive(uint32_t timeout) 00882 { 00883 switch (_rf_settings.modem) { 00884 case MODEM_FSK: 00885 if (timeout == 0 && _rf_settings.fsk.rx_continuous == false) { 00886 // user messed up probably timeout was 0 but mode was not 00887 // continuous, force it to be continuous 00888 _rf_settings.fsk.rx_continuous = true; 00889 } 00890 00891 // DIO0=PayloadReady 00892 // DIO1=FifoLevel 00893 // DIO2=SyncAddr 00894 // DIO3=FifoEmpty 00895 // DIO4=Preamble 00896 // DIO5=ModeReady 00897 write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) & 00898 RF_DIOMAPPING1_DIO0_MASK & 00899 RF_DIOMAPPING1_DIO1_MASK & 00900 RF_DIOMAPPING1_DIO2_MASK) | 00901 RF_DIOMAPPING1_DIO0_00 | 00902 RF_DIOMAPPING1_DIO1_00 | 00903 RF_DIOMAPPING1_DIO2_11); 00904 00905 write_to_register(REG_DIOMAPPING2, (read_register(REG_DIOMAPPING2) & 00906 RF_DIOMAPPING2_DIO4_MASK & 00907 RF_DIOMAPPING2_MAP_MASK) | 00908 RF_DIOMAPPING2_DIO4_11 | 00909 RF_DIOMAPPING2_MAP_PREAMBLEDETECT); 00910 00911 _rf_settings.fsk_packet_handler.fifo_thresh = 00912 read_register(REG_FIFOTHRESH) & 0x3F; 00913 00914 write_to_register(REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | 00915 RF_RXCONFIG_AGCAUTO_ON | 00916 RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT); 00917 00918 _rf_settings.fsk_packet_handler.preamble_detected = 0; 00919 _rf_settings.fsk_packet_handler.sync_word_detected = 0; 00920 _rf_settings.fsk_packet_handler.nb_bytes = 0; 00921 _rf_settings.fsk_packet_handler.size = 0; 00922 00923 break; 00924 00925 case MODEM_LORA: 00926 if (timeout == 0 && _rf_settings.lora.rx_continuous == false) { 00927 // user messed up probably timeout was 0 but mode was not 00928 // continuous, force it to be continuous 00929 _rf_settings.lora.rx_continuous = true; 00930 } 00931 00932 if (_rf_settings.lora.iq_inverted == true) { 00933 write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) & 00934 RFLR_INVERTIQ_TX_MASK & 00935 RFLR_INVERTIQ_RX_MASK) | 00936 RFLR_INVERTIQ_RX_ON | 00937 RFLR_INVERTIQ_TX_OFF)); 00938 write_to_register(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON); 00939 } else { 00940 write_to_register(REG_LR_INVERTIQ, ((read_register(REG_LR_INVERTIQ) & 00941 RFLR_INVERTIQ_TX_MASK & 00942 RFLR_INVERTIQ_RX_MASK) | 00943 RFLR_INVERTIQ_RX_OFF | 00944 RFLR_INVERTIQ_TX_OFF)); 00945 write_to_register( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF); 00946 } 00947 00948 if (_rf_settings.lora.freq_hop_on == true) { 00949 write_to_register(REG_LR_IRQFLAGSMASK, 00950 RFLR_IRQFLAGS_VALIDHEADER | 00951 RFLR_IRQFLAGS_TXDONE | 00952 RFLR_IRQFLAGS_CADDONE | 00953 RFLR_IRQFLAGS_CADDETECTED); 00954 00955 // DIO0=rx_done, DIO2=fhss_change_channel 00956 write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) & 00957 RFLR_DIOMAPPING1_DIO0_MASK & 00958 RFLR_DIOMAPPING1_DIO2_MASK) | 00959 RFLR_DIOMAPPING1_DIO0_00 | 00960 RFLR_DIOMAPPING1_DIO2_00); 00961 } else { 00962 write_to_register(REG_LR_IRQFLAGSMASK, 00963 RFLR_IRQFLAGS_VALIDHEADER | 00964 RFLR_IRQFLAGS_TXDONE | 00965 RFLR_IRQFLAGS_CADDONE | 00966 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | 00967 RFLR_IRQFLAGS_CADDETECTED); 00968 00969 // DIO0=rx_done 00970 write_to_register(REG_DIOMAPPING1, (read_register(REG_DIOMAPPING1) & 00971 RFLR_DIOMAPPING1_DIO0_MASK) | 00972 RFLR_DIOMAPPING1_DIO0_00); 00973 } 00974 00975 write_to_register(REG_LR_FIFORXBASEADDR, 0); 00976 write_to_register(REG_LR_FIFOADDRPTR, 0); 00977 00978 break; 00979 } 00980 00981 memset(_data_buffer, 0, (size_t) MAX_DATA_BUFFER_SIZE_SX172); 00982 00983 _rf_settings.state = RF_RX_RUNNING; 00984 00985 if (timeout != 0) { 00986 rx_timeout_timer.attach_us(callback(this, 00987 &SX1272_LoRaRadio::timeout_irq_isr), 00988 timeout*1e3); 00989 } 00990 00991 if (_rf_settings.modem == MODEM_FSK) { 00992 set_operation_mode(RF_OPMODE_RECEIVER); 00993 00994 if (_rf_settings.fsk.rx_continuous == false) { 00995 rx_timeout_sync_word.attach_us(callback(this, 00996 &SX1272_LoRaRadio::timeout_irq_isr), 00997 _rf_settings.fsk.rx_single_timeout * 1e3); 00998 } 00999 01000 return; 01001 } 01002 01003 // If mode is LoRa set mode 01004 if (_rf_settings.lora.rx_continuous == true) { 01005 set_operation_mode(RFLR_OPMODE_RECEIVER); 01006 } else { 01007 set_operation_mode(RFLR_OPMODE_RECEIVER_SINGLE); 01008 } 01009 } 01010 01011 /** 01012 * Puts a limit on the size of payload the module can handle 01013 * By default it is MAX, i.e., 256 bytes 01014 */ 01015 void SX1272_LoRaRadio::set_max_payload_length(radio_modems_t modem, uint8_t max) 01016 { 01017 set_modem(modem); 01018 01019 switch (modem) { 01020 case MODEM_FSK: 01021 if (_rf_settings.fsk.fix_len == false) { 01022 write_to_register(REG_PAYLOADLENGTH, max); 01023 } 01024 break; 01025 case MODEM_LORA: 01026 write_to_register(REG_LR_PAYLOADMAXLENGTH, max); 01027 break; 01028 } 01029 } 01030 01031 /** 01032 * TODO: Making sure if this API is valid only for LoRa modulation ? 01033 * 01034 * Indicates if the node is part of a private or public network 01035 */ 01036 void SX1272_LoRaRadio::set_public_network(bool enable) 01037 { 01038 set_modem(MODEM_LORA); 01039 01040 _rf_settings.lora.public_network = enable; 01041 if (enable == true) { 01042 // Change lora modem SyncWord 01043 write_to_register(REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD); 01044 } else { 01045 // Change lora modem SyncWord 01046 write_to_register(REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD); 01047 } 01048 01049 } 01050 01051 /** 01052 * Perform carrier sensing 01053 * 01054 * Checks for a certain time if the RSSI is above a given threshold. 01055 * This threshold determines if there is already a transmission going on 01056 * in the channel or not. 01057 * 01058 */ 01059 bool SX1272_LoRaRadio::perform_carrier_sense(radio_modems_t modem, 01060 uint32_t freq, 01061 int16_t rssi_threshold, 01062 uint32_t max_carrier_sense_time) 01063 { 01064 bool status = true; 01065 int16_t rssi = 0; 01066 01067 set_modem(modem); 01068 set_channel(freq); 01069 set_operation_mode(RF_OPMODE_RECEIVER); 01070 01071 // hold on a bit, radio turn-around time 01072 wait_ms(1); 01073 01074 Timer elapsed_time; 01075 elapsed_time.start(); 01076 01077 // Perform carrier sense for maxCarrierSenseTime 01078 while (elapsed_time.read_ms() < (int)max_carrier_sense_time) { 01079 rssi = get_rssi(modem); 01080 01081 if (rssi > rssi_threshold) { 01082 status = false; 01083 break; 01084 } 01085 } 01086 01087 sleep(); 01088 return status; 01089 } 01090 01091 /** 01092 * Channel Activity detection (can be done only in LoRa mode) 01093 * 01094 * If any activity on the channel is detected, an interrupt is asserted on 01095 * DIO3. A callback will be generated to the stack/application upon the 01096 * assertion of DIO3. 01097 */ 01098 void SX1272_LoRaRadio::start_cad() 01099 { 01100 uint8_t reg_val; 01101 01102 switch (_rf_settings.modem) { 01103 case MODEM_FSK: 01104 break; 01105 case MODEM_LORA: 01106 write_to_register(REG_LR_IRQFLAGSMASK, 01107 RFLR_IRQFLAGS_RXTIMEOUT | 01108 RFLR_IRQFLAGS_RXDONE | 01109 RFLR_IRQFLAGS_PAYLOADCRCERROR | 01110 RFLR_IRQFLAGS_VALIDHEADER | 01111 RFLR_IRQFLAGS_TXDONE | 01112 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL); 01113 01114 // DIO3=CADDone 01115 reg_val = read_register(REG_DIOMAPPING1); 01116 write_to_register(REG_DIOMAPPING1, (reg_val & 01117 RFLR_DIOMAPPING1_DIO3_MASK) | 01118 RFLR_DIOMAPPING1_DIO3_00); 01119 01120 set_operation_mode(RFLR_OPMODE_CAD); 01121 01122 _rf_settings.state = RF_CAD; 01123 01124 break; 01125 default: 01126 break; 01127 } 01128 } 01129 01130 /** 01131 * Set transmission in continuous wave mode 01132 */ 01133 void SX1272_LoRaRadio::set_tx_continuous_wave(uint32_t freq, int8_t power, 01134 uint16_t time) 01135 { 01136 uint8_t reg_val; 01137 01138 set_channel(freq); 01139 set_tx_config(MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, time); 01140 reg_val = read_register(REG_PACKETCONFIG2); 01141 01142 write_to_register( REG_PACKETCONFIG2, (reg_val & RF_PACKETCONFIG2_DATAMODE_MASK ) ); 01143 // Disable radio interrupts 01144 write_to_register( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 ); 01145 write_to_register( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 ); 01146 01147 _rf_settings.state = RF_TX_RUNNING; 01148 tx_timeout_timer.attach_us(callback(this, &SX1272_LoRaRadio::timeout_irq_isr), time*1e3); 01149 set_operation_mode(RF_OPMODE_TRANSMITTER); 01150 } 01151 01152 /** 01153 * Put radio in Standby mode 01154 */ 01155 void SX1272_LoRaRadio::standby( void ) 01156 { 01157 tx_timeout_timer.detach(); 01158 rx_timeout_timer.detach(); 01159 01160 set_operation_mode(RF_OPMODE_STANDBY); 01161 _rf_settings.state = RF_IDLE; 01162 } 01163 01164 /** 01165 * Generates 32 bit random number based upon RSSI monitoring 01166 * Used for various calculation by the stack for example dev nonce 01167 * 01168 * When this API is used modem is set in LoRa mode and all interrupts are 01169 * masked. If the user had been using FSK mode, it should be noted that a 01170 * change of mode is required again because the registers have changed. 01171 * In addition to that RX and TX configuration APIs should be called again in 01172 * order to have correct desires setup. 01173 */ 01174 uint32_t SX1272_LoRaRadio::random() 01175 { 01176 uint8_t i; 01177 uint32_t rnd = 0; 01178 01179 // Set LoRa modem ON 01180 set_modem(MODEM_LORA); 01181 01182 // Disable LoRa modem interrupts, i.e., mask all interrupts 01183 write_to_register(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT | RFLR_IRQFLAGS_RXDONE 01184 | RFLR_IRQFLAGS_PAYLOADCRCERROR | RFLR_IRQFLAGS_VALIDHEADER 01185 | RFLR_IRQFLAGS_TXDONE | RFLR_IRQFLAGS_CADDONE 01186 | RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL | RFLR_IRQFLAGS_CADDETECTED); 01187 01188 // Set radio in continuous reception 01189 set_operation_mode(RF_OPMODE_RECEIVER); 01190 01191 for (i = 0; i < 32; i++) { 01192 wait_ms(1); 01193 // Unfiltered RSSI value reading. Only takes the LSB value 01194 rnd |= ((uint32_t) read_register(REG_LR_RSSIWIDEBAND) & 0x01) << i; 01195 } 01196 01197 sleep(); 01198 01199 return rnd; 01200 } 01201 01202 01203 /***************************************************************************** 01204 * Private APIs * 01205 ****************************************************************************/ 01206 #ifdef MBED_CONF_RTOS_PRESENT 01207 /** 01208 * Thread task handling IRQs 01209 */ 01210 void SX1272_LoRaRadio::rf_irq_task(void) 01211 { 01212 for (;;) { 01213 osEvent event = irq_thread.signal_wait(0, osWaitForever); 01214 if (event.status != osEventSignal) { 01215 continue; 01216 } 01217 01218 lock(); 01219 if (event.value.signals & SIG_DIO0) { 01220 handle_dio0_irq(); 01221 } 01222 if (event.value.signals & SIG_DIO1) { 01223 handle_dio1_irq(); 01224 } 01225 if (event.value.signals & SIG_DIO2) { 01226 handle_dio2_irq(); 01227 } 01228 if (event.value.signals & SIG_DIO3) { 01229 handle_dio3_irq(); 01230 } 01231 if (event.value.signals & SIG_DIO4) { 01232 handle_dio4_irq(); 01233 } 01234 if (event.value.signals & SIG_DIO5) { 01235 handle_dio5_irq(); 01236 } 01237 if (event.value.signals & SIG_TIMOUT) { 01238 handle_timeout_irq(); 01239 } 01240 unlock(); 01241 } 01242 } 01243 #endif 01244 01245 /** 01246 * Writes a single byte to a given register 01247 */ 01248 void SX1272_LoRaRadio::write_to_register(uint8_t addr, uint8_t data) 01249 { 01250 write_to_register(addr, &data, 1); 01251 } 01252 01253 /** 01254 * Writes multiple bytes to a given register 01255 */ 01256 void SX1272_LoRaRadio::write_to_register(uint8_t addr, uint8_t *data, uint8_t size) 01257 { 01258 // set chip-select low 01259 _chip_select = 0; 01260 01261 // set write command 01262 _spi.write(addr | SPI_WRITE_CMD); 01263 01264 // write data 01265 for (uint8_t i = 0; i < size; i++) { 01266 _spi.write(data[i]); 01267 } 01268 01269 // set chip-select high 01270 _chip_select = 1; 01271 } 01272 01273 /** 01274 * Reads the value of a single register 01275 */ 01276 uint8_t SX1272_LoRaRadio::read_register(uint8_t addr) 01277 { 01278 uint8_t data; 01279 read_register(addr, &data, 1); 01280 return data; 01281 } 01282 01283 /** 01284 * Reads multiple values from a given register 01285 */ 01286 void SX1272_LoRaRadio::read_register(uint8_t addr, uint8_t *buffer, uint8_t size) 01287 { 01288 // set chip-select low 01289 _chip_select = 0; 01290 01291 // set read command 01292 _spi.write(addr & SPI_READ_CMD); 01293 01294 // read buffers 01295 for (uint8_t i = 0; i < size; i++) { 01296 buffer[i] = _spi.write(0); 01297 } 01298 01299 // set chip-select high 01300 _chip_select = 1; 01301 } 01302 01303 /** 01304 * Writes to FIIO provided by the chip 01305 */ 01306 void SX1272_LoRaRadio::write_fifo(uint8_t *buffer, uint8_t size) 01307 { 01308 write_to_register(0, buffer, size); 01309 } 01310 01311 /** 01312 * Reads from the FIFO provided by the chip 01313 */ 01314 void SX1272_LoRaRadio::read_fifo(uint8_t *buffer, uint8_t size) 01315 { 01316 read_register(0, buffer, size); 01317 } 01318 01319 /** 01320 * Gets FSK bandwidth values 01321 * 01322 * Gives either normal bandwidths or bandwidths for 01323 * AFC (auto frequency correction) 01324 */ 01325 uint8_t SX1272_LoRaRadio::get_fsk_bw_reg_val(uint32_t bandwidth) 01326 { 01327 uint8_t i; 01328 01329 for (i = 0; i < (sizeof(fsk_bandwidths) / sizeof(fsk_bw_t)) - 1; i++) { 01330 if ((bandwidth >= fsk_bandwidths[i].bandwidth) 01331 && (bandwidth < fsk_bandwidths[i + 1].bandwidth)) { 01332 return fsk_bandwidths[i].register_value; 01333 } 01334 } 01335 // ERROR: Value not found 01336 // This should never happen 01337 while (1); 01338 } 01339 01340 /** 01341 * Sets the radio modules to default position (off) 01342 * 01343 * Historically they were being called as Antenna switches, so we kept the name. 01344 * In essence these are control latches over duplexer which either let 01345 * TX submodule or RX submodule circuitry enabled at a time. 01346 */ 01347 void SX1272_LoRaRadio::default_antenna_switch_ctrls() 01348 { 01349 if (_rf_ctrls.pwr_amp_ctl != NC) { 01350 _pwr_amp_ctl = 0; 01351 } 01352 01353 if (_rf_ctrls.rf_switch_ctl1 != NC && _rf_ctrls.rf_switch_ctl2 != NC) { 01354 _rf_switch_ctl1 = 0; 01355 _rf_switch_ctl2 = 0; 01356 } 01357 01358 if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) { 01359 _txctl = 0; 01360 _rxctl = 0; 01361 } 01362 } 01363 01364 /** 01365 * Gets the power amplifier configuration register 01366 */ 01367 uint8_t SX1272_LoRaRadio::get_pa_conf_reg() 01368 { 01369 if (radio_variant == SX1272UNDEFINED) { 01370 return RF_PACONFIG_PASELECT_PABOOST; 01371 } else if (radio_variant == SX1272MB1DCS) { 01372 return RF_PACONFIG_PASELECT_PABOOST; 01373 } else { 01374 return RF_PACONFIG_PASELECT_RFO; 01375 } 01376 } 01377 01378 /** 01379 * Get RSSI from the module 01380 */ 01381 int16_t SX1272_LoRaRadio::get_rssi(radio_modems_t modem) 01382 { 01383 int16_t rssi = 0; 01384 01385 switch( modem ) 01386 { 01387 case MODEM_FSK: 01388 rssi = -(read_register(REG_RSSIVALUE) >> 1 ); 01389 break; 01390 case MODEM_LORA: 01391 rssi = RSSI_OFFSET + read_register(REG_LR_RSSIVALUE); 01392 break; 01393 default: 01394 rssi = -1; 01395 break; 01396 } 01397 return rssi; 01398 } 01399 01400 /** 01401 * Sets the transmit power for the module 01402 */ 01403 #if defined ( TARGET_MOTE_L152RC ) 01404 static const uint8_t pa_boost_table[20] = {0, 0, 0, 0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15}; 01405 static const uint8_t RFO_table[11] = {1, 1, 1, 2, 2, 3, 4, 5, 6, 8, 9}; 01406 #endif 01407 01408 void SX1272_LoRaRadio::set_rf_tx_power(int8_t power) 01409 { 01410 uint8_t pa_config = 0; 01411 uint8_t pa_dac = 0; 01412 01413 pa_config = read_register(REG_PACONFIG); 01414 pa_dac = read_register(REG_PADAC); 01415 01416 #if defined ( TARGET_MOTE_L152RC ) 01417 if(power > 19) { 01418 pa_config = (pa_config & RF_PACONFIG_PASELECT_MASK) | RF_PACONFIG_PASELECT_RFO; 01419 pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK) | RFO_table[power - 20]; 01420 } 01421 else 01422 { 01423 pa_config = (pa_config & RF_PACONFIG_PASELECT_MASK) | RF_PACONFIG_PASELECT_PABOOST; 01424 pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK) | pa_boost_table[power]; 01425 } 01426 #else 01427 pa_config = (pa_config & RF_PACONFIG_PASELECT_MASK) | get_pa_conf_reg(); 01428 01429 if ((pa_config & RF_PACONFIG_PASELECT_PABOOST) 01430 == RF_PACONFIG_PASELECT_PABOOST) { 01431 if (power > 17) { 01432 pa_dac = (pa_dac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_ON; 01433 } else { 01434 pa_dac = (pa_dac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_OFF; 01435 } 01436 if ((pa_dac & RF_PADAC_20DBM_ON) == RF_PADAC_20DBM_ON) { 01437 if (power < 5) { 01438 power = 5; 01439 } 01440 if (power > 20) { 01441 power = 20; 01442 } 01443 pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK) 01444 | (uint8_t) ((uint16_t) (power - 5) & 0x0F); 01445 } else { 01446 if (power < 2) { 01447 power = 2; 01448 } 01449 if (power > 17) { 01450 power = 17; 01451 } 01452 pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK) 01453 | (uint8_t) ((uint16_t) (power - 2) & 0x0F); 01454 } 01455 } else { 01456 if (power < -1) { 01457 power = -1; 01458 } 01459 if (power > 14) { 01460 power = 14; 01461 } 01462 pa_config = (pa_config & RFLR_PACONFIG_OUTPUTPOWER_MASK) 01463 | (uint8_t) ((uint16_t) (power + 1) & 0x0F); 01464 } 01465 #endif 01466 write_to_register(REG_PACONFIG, pa_config); 01467 write_to_register(REG_PADAC, pa_dac); 01468 } 01469 01470 /** 01471 * Sets the radio registers to defaults 01472 */ 01473 void SX1272_LoRaRadio::setup_registers() 01474 { 01475 for (unsigned int i = 0; i < sizeof(radio_reg_init) / sizeof(radio_registers_t); i++) { 01476 set_modem(radio_reg_init[i].modem); 01477 write_to_register(radio_reg_init[i].addr, radio_reg_init[i].value); 01478 } 01479 } 01480 01481 /** 01482 * Set the radio module variant 01483 */ 01484 void SX1272_LoRaRadio::set_sx1272_variant_type() 01485 { 01486 if (_rf_ctrls.ant_switch != NC){ 01487 _ant_switch.input(); 01488 wait_ms(1); 01489 if (_ant_switch == 1) { 01490 radio_variant = SX1272MB1DCS; 01491 } else { 01492 radio_variant = SX1272MB2XAS; 01493 } 01494 _ant_switch.output(); 01495 wait_ms(1); 01496 } else { 01497 radio_variant = SX1272UNDEFINED; 01498 } 01499 } 01500 01501 /** 01502 * Sets up radio latch position according to the 01503 * radio mode 01504 */ 01505 void SX1272_LoRaRadio::set_antenna_switch(uint8_t mode) 01506 { 01507 // here we got to do ifdef for changing controls 01508 // as some pins might be NC 01509 switch (mode) { 01510 case RFLR_OPMODE_TRANSMITTER: 01511 if (_rf_ctrls.rf_switch_ctl1 != NC 01512 && _rf_ctrls.rf_switch_ctl2 != NC) { 01513 // module is in transmit mode and RF latch switches 01514 // are connected. Check if power amplifier boost is 01515 // setup or not 01516 if ((read_register(REG_PACONFIG) & RF_PACONFIG_PASELECT_PABOOST) 01517 == RF_PACONFIG_PASELECT_PABOOST) { 01518 _rf_switch_ctl1 = 1; 01519 _rf_switch_ctl2 = 0; 01520 } else { 01521 // power amplifier not selected 01522 _rf_switch_ctl1 = 0; 01523 _rf_switch_ctl2 = 1; 01524 } 01525 } else if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) { 01526 // module is in transmit mode and tx/rx submodule control 01527 // pins are connected 01528 _txctl = 1; 01529 _rxctl = 0; 01530 } else if (_rf_ctrls.ant_switch != NC){ 01531 _ant_switch = 1; 01532 } else { 01533 // None of the control pins are connected. 01534 } 01535 break; 01536 case RFLR_OPMODE_RECEIVER: 01537 case RFLR_OPMODE_RECEIVER_SINGLE: 01538 case RFLR_OPMODE_CAD: 01539 if (_rf_ctrls.rf_switch_ctl1 != NC 01540 && _rf_ctrls.rf_switch_ctl2 != NC) { 01541 // radio is in reception or CAD mode and RF latch switches 01542 // are connected 01543 _rf_switch_ctl1 = 1; 01544 _rf_switch_ctl2 = 1; 01545 } else if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) { 01546 _txctl = 0; 01547 _rxctl = 1; 01548 } else if (_rf_ctrls.ant_switch != NC) { 01549 _ant_switch = 0; 01550 } else { 01551 // None of the control pins are connected. 01552 } 01553 break; 01554 default: 01555 // Enforce default case when any connected control pin is kept low. 01556 if (_rf_ctrls.rf_switch_ctl1 != NC 01557 && _rf_ctrls.rf_switch_ctl2 != NC) { 01558 // radio is in reception or CAD mode and RF latch switches 01559 // are connected 01560 _rf_switch_ctl1 = 0; 01561 _rf_switch_ctl2 = 0; 01562 } else if (_rf_ctrls.txctl != NC && _rf_ctrls.rxctl != NC) { 01563 _txctl = 0; 01564 _rxctl = 0; 01565 } else if (_rf_ctrls.ant_switch != NC) { 01566 _ant_switch = 0; 01567 } else { 01568 // None of the control pins are connected. 01569 } 01570 break; 01571 } 01572 } 01573 01574 /** 01575 * Sets up frequency for SPI module 01576 * Reference DataSheet: 4.3 SPI Interface 01577 */ 01578 void SX1272_LoRaRadio::setup_spi() 01579 { 01580 // SPI bus frequency 01581 uint32_t spi_freq = SPI_FREQUENCY; 01582 01583 // Hold chip-select high 01584 _chip_select = 1; 01585 _spi.format(8, 0); 01586 01587 #if defined (TARGET_KL25Z) 01588 //bus-clock frequency is halved -> double the SPI frequency to compensate 01589 _spi.frequency(spi_freq * 2); 01590 #else 01591 // otherwise use default SPI frequency which is 8 MHz 01592 _spi.frequency(spi_freq); 01593 #endif 01594 // 100 us wait to settle down 01595 wait(0.1); 01596 } 01597 01598 /** 01599 * Attaches ISRs to interrupt pins 01600 */ 01601 void SX1272_LoRaRadio::setup_interrupts() 01602 { 01603 _dio0_ctl.rise(callback(this, &SX1272_LoRaRadio::dio0_irq_isr)); 01604 _dio1_ctl.rise(callback(this, &SX1272_LoRaRadio::dio1_irq_isr)); 01605 _dio2_ctl.rise(callback(this, &SX1272_LoRaRadio::dio2_irq_isr)); 01606 _dio3_ctl.rise(callback(this, &SX1272_LoRaRadio::dio3_irq_isr)); 01607 if (_dio4_pin != NC) { 01608 _dio4_ctl.rise(callback(this, &SX1272_LoRaRadio::dio4_irq_isr)); 01609 } 01610 if (_dio5_pin != NC) { 01611 _dio5_ctl.rise(callback(this, &SX1272_LoRaRadio::dio5_irq_isr)); 01612 } 01613 } 01614 01615 /** 01616 * Sets the module in low power mode by disconnecting 01617 * TX and RX submodules, turning off power amplifier etc. 01618 */ 01619 void SX1272_LoRaRadio::set_low_power_mode(bool status) 01620 { 01621 if (radio_is_active != status) { 01622 radio_is_active = status; 01623 01624 if (status == false) { 01625 if (_rf_ctrls.rf_switch_ctl1 != NC) { 01626 _rf_switch_ctl1 = 0; 01627 } 01628 if (_rf_ctrls.rf_switch_ctl2 != NC) { 01629 _rf_switch_ctl2 = 0; 01630 } 01631 01632 if (_rf_ctrls.pwr_amp_ctl != NC) { 01633 _pwr_amp_ctl = 0; 01634 } 01635 01636 if (_rf_ctrls.txctl != NC) { 01637 _txctl = 0; 01638 } 01639 01640 if (_rf_ctrls.txctl != NC) { 01641 _rxctl = 0; 01642 } 01643 01644 if (_rf_ctrls.ant_switch != NC) { 01645 _ant_switch = 0; 01646 } 01647 } else { 01648 default_antenna_switch_ctrls(); 01649 } 01650 } 01651 } 01652 01653 /***************************************************************************** 01654 * Interrupt service routines (ISRs) - set signals to the irq_thread * 01655 ****************************************************************************/ 01656 void SX1272_LoRaRadio::dio0_irq_isr() 01657 { 01658 #ifdef MBED_CONF_RTOS_PRESENT 01659 irq_thread.signal_set(SIG_DIO0); 01660 #else 01661 handle_dio0_irq(); 01662 #endif 01663 } 01664 01665 void SX1272_LoRaRadio::dio1_irq_isr() 01666 { 01667 #ifdef MBED_CONF_RTOS_PRESENT 01668 irq_thread.signal_set(SIG_DIO1); 01669 #else 01670 handle_dio1_irq(); 01671 #endif 01672 } 01673 01674 void SX1272_LoRaRadio::dio2_irq_isr() 01675 { 01676 #ifdef MBED_CONF_RTOS_PRESENT 01677 irq_thread.signal_set(SIG_DIO2); 01678 #else 01679 handle_dio2_irq(); 01680 #endif 01681 } 01682 01683 void SX1272_LoRaRadio::dio3_irq_isr() 01684 { 01685 #ifdef MBED_CONF_RTOS_PRESENT 01686 irq_thread.signal_set(SIG_DIO3); 01687 #else 01688 handle_dio3_irq(); 01689 #endif 01690 } 01691 01692 void SX1272_LoRaRadio::dio4_irq_isr() 01693 { 01694 #ifdef MBED_CONF_RTOS_PRESENT 01695 irq_thread.signal_set(SIG_DIO4); 01696 #else 01697 handle_dio4_irq(); 01698 #endif 01699 } 01700 01701 void SX1272_LoRaRadio::dio5_irq_isr() 01702 { 01703 #ifdef MBED_CONF_RTOS_PRESENT 01704 irq_thread.signal_set(SIG_DIO5); 01705 #else 01706 handle_dio5_irq(); 01707 #endif 01708 } 01709 01710 // This is not a hardware interrupt 01711 // we invoke it ourselves based upon 01712 // our timers 01713 void SX1272_LoRaRadio::timeout_irq_isr() 01714 { 01715 #ifdef MBED_CONF_RTOS_PRESENT 01716 irq_thread.signal_set(SIG_TIMOUT); 01717 #else 01718 handle_timeout_irq(); 01719 #endif 01720 } 01721 01722 /****************************************************************************** 01723 * Interrupt Handlers * 01724 *****************************************************************************/ 01725 01726 void SX1272_LoRaRadio::handle_dio0_irq() 01727 { 01728 volatile uint8_t irqFlags = 0; 01729 01730 switch (_rf_settings.state) { 01731 case RF_RX_RUNNING: 01732 switch (_rf_settings.modem) { 01733 case MODEM_FSK: 01734 if (_rf_settings.fsk.crc_on == true) { 01735 irqFlags = read_register(REG_IRQFLAGS2); 01736 if ((irqFlags & RF_IRQFLAGS2_CRCOK) 01737 != RF_IRQFLAGS2_CRCOK) { 01738 // Clear Irqs 01739 write_to_register(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 01740 RF_IRQFLAGS1_PREAMBLEDETECT | 01741 RF_IRQFLAGS1_SYNCADDRESSMATCH); 01742 write_to_register(REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN); 01743 01744 01745 if (_rf_settings.fsk.rx_continuous == false) { 01746 rx_timeout_sync_word.detach(); 01747 _rf_settings.state = RF_IDLE; 01748 } else { 01749 // Continuous mode restart Rx chain 01750 write_to_register(REG_RXCONFIG, 01751 read_register(REG_RXCONFIG) | 01752 RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK); 01753 } 01754 01755 rx_timeout_timer.detach(); 01756 01757 if ((_radio_events != NULL) 01758 && (_radio_events->rx_error)) { 01759 _radio_events->rx_error(); 01760 } 01761 _rf_settings.fsk_packet_handler.preamble_detected = 0; 01762 _rf_settings.fsk_packet_handler.sync_word_detected = 0; 01763 _rf_settings.fsk_packet_handler.nb_bytes = 0; 01764 _rf_settings.fsk_packet_handler.size = 0; 01765 // break from here, a CRC error happened, RX_ERROR 01766 // was notified. No need to go any further 01767 break; 01768 } 01769 } 01770 01771 // Read received packet size 01772 if ((_rf_settings.fsk_packet_handler.size == 0) 01773 && (_rf_settings.fsk_packet_handler.nb_bytes == 0)) { 01774 if (_rf_settings.fsk.fix_len == false) { 01775 read_fifo((uint8_t*) &_rf_settings.fsk_packet_handler.size, 1); 01776 } else { 01777 _rf_settings.fsk_packet_handler.size = read_register(REG_PAYLOADLENGTH); 01778 } 01779 read_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes, 01780 _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes); 01781 _rf_settings.fsk_packet_handler.nb_bytes += 01782 (_rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes); 01783 } else { 01784 read_fifo(_data_buffer + _rf_settings.fsk_packet_handler.nb_bytes, 01785 _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes); 01786 _rf_settings.fsk_packet_handler.nb_bytes += 01787 (_rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes); 01788 } 01789 01790 if (_rf_settings.fsk.rx_continuous == false) { 01791 _rf_settings.state = RF_IDLE; 01792 rx_timeout_sync_word.detach(); 01793 } else { 01794 // Continuous mode restart Rx chain 01795 write_to_register(REG_RXCONFIG, read_register(REG_RXCONFIG) 01796 | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK); 01797 } 01798 01799 rx_timeout_timer.detach(); 01800 01801 if ((_radio_events != NULL) && (_radio_events->rx_done)) { 01802 _radio_events->rx_done( 01803 _data_buffer, 01804 _rf_settings.fsk_packet_handler.size, 01805 _rf_settings.fsk_packet_handler.rssi_value, 0); 01806 } 01807 _rf_settings.fsk_packet_handler.preamble_detected = 0; 01808 _rf_settings.fsk_packet_handler.sync_word_detected = 0; 01809 _rf_settings.fsk_packet_handler.nb_bytes = 0; 01810 _rf_settings.fsk_packet_handler.size = 0; 01811 break; 01812 case MODEM_LORA: { 01813 int8_t snr = 0; 01814 01815 // Clear Irq 01816 write_to_register(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE); 01817 01818 irqFlags = read_register(REG_LR_IRQFLAGS); 01819 if ((irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK) 01820 == RFLR_IRQFLAGS_PAYLOADCRCERROR) { 01821 // Clear Irq 01822 write_to_register(REG_LR_IRQFLAGS, 01823 RFLR_IRQFLAGS_PAYLOADCRCERROR); 01824 01825 if (_rf_settings.lora.rx_continuous == false) { 01826 _rf_settings.state = RF_IDLE; 01827 } 01828 rx_timeout_timer.detach(); 01829 01830 if ((_radio_events != NULL) 01831 && (_radio_events->rx_error)) { 01832 _radio_events->rx_error(); 01833 } 01834 break; 01835 } 01836 01837 _rf_settings.lora_packet_handler.snr_value = read_register(REG_LR_PKTSNRVALUE); 01838 if (_rf_settings.lora_packet_handler.snr_value & 0x80) // The SNR sign bit is 1 01839 { 01840 // Invert and divide by 4 01841 snr = ((~_rf_settings.lora_packet_handler.snr_value + 1) & 0xFF) >> 2; 01842 snr = -snr; 01843 } else { 01844 // Divide by 4 01845 snr =(_rf_settings.lora_packet_handler.snr_value & 0xFF) >> 2; 01846 } 01847 01848 int16_t rssi = read_register(REG_LR_PKTRSSIVALUE); 01849 if (snr < 0) { 01850 _rf_settings.lora_packet_handler.rssi_value = 01851 RSSI_OFFSET + rssi + (rssi >> 4) + snr; 01852 } else { 01853 _rf_settings.lora_packet_handler.rssi_value = 01854 RSSI_OFFSET + rssi + (rssi >> 4); 01855 } 01856 01857 _rf_settings.lora_packet_handler.size = read_register(REG_LR_RXNBBYTES); 01858 read_fifo(_data_buffer, _rf_settings.lora_packet_handler.size); 01859 01860 if (_rf_settings.lora.rx_continuous == false) { 01861 _rf_settings.state = RF_IDLE; 01862 } 01863 rx_timeout_timer.detach(); 01864 01865 if ((_radio_events != NULL) 01866 && (_radio_events->rx_done)) { 01867 _radio_events->rx_done( 01868 _data_buffer, 01869 _rf_settings.lora_packet_handler.size, 01870 _rf_settings.lora_packet_handler.rssi_value, 01871 _rf_settings.lora_packet_handler.snr_value); 01872 } 01873 } 01874 break; 01875 default: 01876 break; 01877 } 01878 break; 01879 case RF_TX_RUNNING: 01880 tx_timeout_timer.detach(); 01881 // TxDone interrupt 01882 switch (_rf_settings.modem) { 01883 case MODEM_LORA: 01884 // Clear Irq 01885 write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE); 01886 // Intentional fall through 01887 case MODEM_FSK: 01888 default: 01889 _rf_settings.state = RF_IDLE; 01890 if ((_radio_events != NULL) 01891 && (_radio_events->tx_done)) { 01892 _radio_events->tx_done(); 01893 } 01894 break; 01895 } 01896 break; 01897 default: 01898 break; 01899 } 01900 } 01901 01902 void SX1272_LoRaRadio::handle_dio1_irq() 01903 { 01904 01905 switch(_rf_settings.state ) 01906 { 01907 case RF_RX_RUNNING: 01908 switch(_rf_settings.modem ) { 01909 case MODEM_FSK: 01910 // FifoLevel interrupt 01911 // Read received packet size 01912 if( ( _rf_settings.fsk_packet_handler.size == 0 ) && ( _rf_settings.fsk_packet_handler.nb_bytes == 0 ) ) 01913 { 01914 if( _rf_settings.fsk.fix_len == false ) 01915 { 01916 read_fifo( ( uint8_t* )&_rf_settings.fsk_packet_handler.size, 1 ); 01917 } 01918 else 01919 { 01920 _rf_settings.fsk_packet_handler.size = read_register(REG_PAYLOADLENGTH); 01921 } 01922 } 01923 01924 if( ( _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes ) > _rf_settings.fsk_packet_handler.fifo_thresh ) 01925 { 01926 read_fifo( ( _data_buffer + _rf_settings.fsk_packet_handler.nb_bytes ), _rf_settings.fsk_packet_handler.fifo_thresh ); 01927 _rf_settings.fsk_packet_handler.nb_bytes += _rf_settings.fsk_packet_handler.fifo_thresh; 01928 } 01929 else 01930 { 01931 read_fifo( ( _data_buffer + _rf_settings.fsk_packet_handler.nb_bytes ), _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes ); 01932 _rf_settings.fsk_packet_handler.nb_bytes += ( _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes ); 01933 } 01934 break; 01935 case MODEM_LORA: 01936 // Sync time out 01937 rx_timeout_timer.detach( ); 01938 _rf_settings.state = RF_IDLE; 01939 if ((_radio_events != NULL) && (_radio_events->rx_timeout)) { 01940 _radio_events->rx_timeout(); 01941 } 01942 break; 01943 default: 01944 break; 01945 } 01946 break; 01947 case RF_TX_RUNNING: 01948 switch( _rf_settings.modem ) 01949 { 01950 case MODEM_FSK: 01951 // FifoLevel interrupt 01952 if( ( _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes ) > _rf_settings.fsk_packet_handler.chunk_size ) 01953 { 01954 write_fifo(( _data_buffer + _rf_settings.fsk_packet_handler.nb_bytes ), _rf_settings.fsk_packet_handler.chunk_size ); 01955 _rf_settings.fsk_packet_handler.nb_bytes += _rf_settings.fsk_packet_handler.chunk_size; 01956 } 01957 else 01958 { 01959 // Write the last chunk of data 01960 write_fifo( _data_buffer + _rf_settings.fsk_packet_handler.nb_bytes, _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes ); 01961 _rf_settings.fsk_packet_handler.nb_bytes += _rf_settings.fsk_packet_handler.size - _rf_settings.fsk_packet_handler.nb_bytes; 01962 } 01963 break; 01964 case MODEM_LORA: 01965 break; 01966 default: 01967 break; 01968 } 01969 break; 01970 default: 01971 break; 01972 } 01973 } 01974 01975 void SX1272_LoRaRadio::handle_dio2_irq(void) 01976 { 01977 switch(_rf_settings.state ) 01978 { 01979 case RF_RX_RUNNING: 01980 switch( _rf_settings.modem ) 01981 { 01982 case MODEM_FSK: 01983 01984 // DIO4 must have been asserted to set preamble_detected to true 01985 if( ( _rf_settings.fsk_packet_handler.preamble_detected == 1 ) && ( _rf_settings.fsk_packet_handler.sync_word_detected == 0 ) ) 01986 { 01987 if (_rf_settings.fsk.rx_continuous == false) { 01988 rx_timeout_sync_word.detach( ); 01989 } 01990 01991 _rf_settings.fsk_packet_handler.sync_word_detected = 1; 01992 01993 _rf_settings.fsk_packet_handler.rssi_value = -( read_register( REG_RSSIVALUE ) >> 1 ); 01994 01995 _rf_settings.fsk_packet_handler.afc_value = ( int32_t )( double )( ( ( uint16_t )read_register( REG_AFCMSB ) << 8 ) | 01996 ( uint16_t )read_register( REG_AFCLSB ) ) * 01997 ( double )FREQ_STEP; 01998 _rf_settings.fsk_packet_handler.rx_gain = ( read_register( REG_LNA ) >> 5 ) & 0x07; 01999 } 02000 break; 02001 case MODEM_LORA: 02002 if( _rf_settings.lora.freq_hop_on == true ) 02003 { 02004 // Clear Irq 02005 write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); 02006 02007 if( ( _radio_events != NULL ) && (_radio_events->fhss_change_channel ) ) 02008 { 02009 _radio_events->fhss_change_channel((read_register( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK )); 02010 } 02011 } 02012 break; 02013 default: 02014 break; 02015 } 02016 break; 02017 case RF_TX_RUNNING: 02018 switch( _rf_settings.modem ) 02019 { 02020 case MODEM_FSK: 02021 break; 02022 case MODEM_LORA: 02023 if( _rf_settings.lora.freq_hop_on == true ) 02024 { 02025 // Clear Irq 02026 write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); 02027 02028 if( (_radio_events != NULL ) && ( _radio_events->fhss_change_channel ) ) 02029 { 02030 _radio_events->fhss_change_channel((read_register( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK )); 02031 } 02032 } 02033 break; 02034 default: 02035 break; 02036 } 02037 break; 02038 default: 02039 break; 02040 } 02041 } 02042 02043 void SX1272_LoRaRadio::handle_dio3_irq( void ) 02044 { 02045 switch( _rf_settings.modem ) 02046 { 02047 case MODEM_FSK: 02048 break; 02049 case MODEM_LORA: 02050 if( ( read_register( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED ) 02051 { 02052 // Clear Irq 02053 write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE ); 02054 if( ( _radio_events != NULL ) && ( _radio_events->cad_done ) ) 02055 { 02056 _radio_events->cad_done( true ); 02057 } 02058 } 02059 else 02060 { 02061 // Clear Irq 02062 write_to_register( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE ); 02063 if( ( _radio_events != NULL ) && ( _radio_events->cad_done ) ) 02064 { 02065 _radio_events->cad_done( false ); 02066 } 02067 } 02068 break; 02069 default: 02070 break; 02071 } 02072 } 02073 02074 void SX1272_LoRaRadio::handle_dio4_irq(void) 02075 { 02076 // is asserted when a preamble is detected (FSK modem only) 02077 switch (_rf_settings.modem) { 02078 case MODEM_FSK: { 02079 if (_rf_settings.fsk_packet_handler.preamble_detected == 0) { 02080 _rf_settings.fsk_packet_handler.preamble_detected = 1; 02081 } 02082 } 02083 break; 02084 case MODEM_LORA: 02085 break; 02086 default: 02087 break; 02088 } 02089 } 02090 02091 void SX1272_LoRaRadio::handle_dio5_irq() 02092 { 02093 switch( _rf_settings.modem ) 02094 { 02095 case MODEM_FSK: 02096 break; 02097 case MODEM_LORA: 02098 break; 02099 default: 02100 break; 02101 } 02102 } 02103 02104 02105 void SX1272_LoRaRadio::handle_timeout_irq() 02106 { 02107 switch(_rf_settings.state ) 02108 { 02109 case RF_RX_RUNNING: 02110 if( _rf_settings.modem == MODEM_FSK ) { 02111 _rf_settings.fsk_packet_handler.preamble_detected = 0; 02112 _rf_settings.fsk_packet_handler.sync_word_detected = 0; 02113 _rf_settings.fsk_packet_handler.nb_bytes = 0; 02114 _rf_settings.fsk_packet_handler.size = 0; 02115 02116 // Clear Irqs 02117 write_to_register(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI | 02118 RF_IRQFLAGS1_PREAMBLEDETECT | 02119 RF_IRQFLAGS1_SYNCADDRESSMATCH); 02120 write_to_register( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN); 02121 02122 if( _rf_settings.fsk.rx_continuous == true ) 02123 { 02124 // Continuous mode restart Rx chain 02125 write_to_register( REG_RXCONFIG, read_register(REG_RXCONFIG) | 02126 RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK); 02127 } 02128 else 02129 { 02130 _rf_settings.state = RF_IDLE; 02131 rx_timeout_sync_word.attach_us(callback(this, &SX1272_LoRaRadio::timeout_irq_isr), 02132 _rf_settings.fsk.rx_single_timeout * 1e3); 02133 } 02134 } 02135 02136 if((_radio_events != NULL) && (_radio_events->rx_timeout)) { 02137 _radio_events->rx_timeout(); 02138 } 02139 02140 break; 02141 02142 case RF_TX_RUNNING: 02143 // Tx timeout shouldn't happen. 02144 // But it has been observed that when it happens it is a result of a 02145 // corrupted SPI transfer 02146 // The workaround is to put the radio in a known state. 02147 // Thus, we re-initialize it. 02148 02149 // Reset the radio 02150 radio_reset( ); 02151 02152 // Initialize radio default values 02153 set_operation_mode( RF_OPMODE_SLEEP ); 02154 02155 setup_registers(); 02156 02157 set_modem(MODEM_FSK); 02158 02159 // Restore previous network type setting. 02160 set_public_network(_rf_settings.lora.public_network); 02161 02162 _rf_settings.state = RF_IDLE; 02163 if( ( _radio_events != NULL ) && ( _radio_events->tx_timeout ) ) 02164 { 02165 _radio_events->tx_timeout( ); 02166 } 02167 break; 02168 default: 02169 break; 02170 } 02171 } 02172 02173 #endif //DEVICE_SPI 02174
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