Vergil Cola / Mbed OS MQTTGateway2

Fork of my original MQTTGateway

Dependencies:   mbed-http

easy-connect/stm-spirit1-rf-driver/source/radio_spi.cpp@0:a1734fe1ec4b, 2017-04-08 (annotated)

Committer:
vpcola
Date:
Sat Apr 08 14:43:14 2017 +0000
Revision:
0:a1734fe1ec4b
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vpcola 0:a1734fe1ec4b 1 /**
vpcola 0:a1734fe1ec4b 2 ******************************************************************************
vpcola 0:a1734fe1ec4b 3 * @file radio_spi.c
vpcola 0:a1734fe1ec4b 4 * @author System Lab - NOIDA
vpcola 0:a1734fe1ec4b 5 * @version V1.0.0
vpcola 0:a1734fe1ec4b 6 * @date 15-May-2014
vpcola 0:a1734fe1ec4b 7 * @brief This file provides code for the configuration of the SPI instances.
vpcola 0:a1734fe1ec4b 8 ******************************************************************************
vpcola 0:a1734fe1ec4b 9 * @attention
vpcola 0:a1734fe1ec4b 10 *
vpcola 0:a1734fe1ec4b 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
vpcola 0:a1734fe1ec4b 12 *
vpcola 0:a1734fe1ec4b 13 * Redistribution and use in source and binary forms, with or without modification,
vpcola 0:a1734fe1ec4b 14 * are permitted provided that the following conditions are met:
vpcola 0:a1734fe1ec4b 15 * 1. Redistributions of source code must retain the above copyright notice,
vpcola 0:a1734fe1ec4b 16 * this list of conditions and the following disclaimer.
vpcola 0:a1734fe1ec4b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
vpcola 0:a1734fe1ec4b 18 * this list of conditions and the following disclaimer in the documentation
vpcola 0:a1734fe1ec4b 19 * and/or other materials provided with the distribution.
vpcola 0:a1734fe1ec4b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
vpcola 0:a1734fe1ec4b 21 * may be used to endorse or promote products derived from this software
vpcola 0:a1734fe1ec4b 22 * without specific prior written permission.
vpcola 0:a1734fe1ec4b 23 *
vpcola 0:a1734fe1ec4b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
vpcola 0:a1734fe1ec4b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
vpcola 0:a1734fe1ec4b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vpcola 0:a1734fe1ec4b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
vpcola 0:a1734fe1ec4b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
vpcola 0:a1734fe1ec4b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
vpcola 0:a1734fe1ec4b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
vpcola 0:a1734fe1ec4b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
vpcola 0:a1734fe1ec4b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
vpcola 0:a1734fe1ec4b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vpcola 0:a1734fe1ec4b 34 *
vpcola 0:a1734fe1ec4b 35 ******************************************************************************
vpcola 0:a1734fe1ec4b 36 */
vpcola 0:a1734fe1ec4b 37
vpcola 0:a1734fe1ec4b 38
vpcola 0:a1734fe1ec4b 39 /* Includes ------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 40 #include "radio_spi.h"
vpcola 0:a1734fe1ec4b 41
vpcola 0:a1734fe1ec4b 42 #include "SimpleSpirit1.h"
vpcola 0:a1734fe1ec4b 43
vpcola 0:a1734fe1ec4b 44
vpcola 0:a1734fe1ec4b 45 /**
vpcola 0:a1734fe1ec4b 46 * @addtogroup BSP
vpcola 0:a1734fe1ec4b 47 * @{
vpcola 0:a1734fe1ec4b 48 */
vpcola 0:a1734fe1ec4b 49
vpcola 0:a1734fe1ec4b 50
vpcola 0:a1734fe1ec4b 51 /**
vpcola 0:a1734fe1ec4b 52 * @addtogroup X-NUCLEO-IDS02Ax
vpcola 0:a1734fe1ec4b 53 * @{
vpcola 0:a1734fe1ec4b 54 */
vpcola 0:a1734fe1ec4b 55
vpcola 0:a1734fe1ec4b 56
vpcola 0:a1734fe1ec4b 57 /**
vpcola 0:a1734fe1ec4b 58 * @defgroup RADIO_SPI_Private_TypesDefinitions RADIO_SPI Private Types Definitions
vpcola 0:a1734fe1ec4b 59 * @{
vpcola 0:a1734fe1ec4b 60 */
vpcola 0:a1734fe1ec4b 61
vpcola 0:a1734fe1ec4b 62 /**
vpcola 0:a1734fe1ec4b 63 * @}
vpcola 0:a1734fe1ec4b 64 */
vpcola 0:a1734fe1ec4b 65
vpcola 0:a1734fe1ec4b 66
vpcola 0:a1734fe1ec4b 67 /**
vpcola 0:a1734fe1ec4b 68 * @defgroup RADIO_SPI_Private_Defines RADIO_SPI Private Defines
vpcola 0:a1734fe1ec4b 69 * @{
vpcola 0:a1734fe1ec4b 70 */
vpcola 0:a1734fe1ec4b 71
vpcola 0:a1734fe1ec4b 72 /**
vpcola 0:a1734fe1ec4b 73 * @}
vpcola 0:a1734fe1ec4b 74 */
vpcola 0:a1734fe1ec4b 75
vpcola 0:a1734fe1ec4b 76
vpcola 0:a1734fe1ec4b 77 /**
vpcola 0:a1734fe1ec4b 78 * @defgroup RADIO_SPI_Private_Macros RADIO_SPI Private Macros
vpcola 0:a1734fe1ec4b 79 * @{
vpcola 0:a1734fe1ec4b 80 */
vpcola 0:a1734fe1ec4b 81
vpcola 0:a1734fe1ec4b 82 /**
vpcola 0:a1734fe1ec4b 83 * @}
vpcola 0:a1734fe1ec4b 84 */
vpcola 0:a1734fe1ec4b 85
vpcola 0:a1734fe1ec4b 86
vpcola 0:a1734fe1ec4b 87 /**
vpcola 0:a1734fe1ec4b 88 * @defgroup RADIO_SPI_Private_Variables RADIO_SPI Private Variables
vpcola 0:a1734fe1ec4b 89 * @{
vpcola 0:a1734fe1ec4b 90 */
vpcola 0:a1734fe1ec4b 91
vpcola 0:a1734fe1ec4b 92 /**
vpcola 0:a1734fe1ec4b 93 * @}
vpcola 0:a1734fe1ec4b 94 */
vpcola 0:a1734fe1ec4b 95
vpcola 0:a1734fe1ec4b 96
vpcola 0:a1734fe1ec4b 97 /**
vpcola 0:a1734fe1ec4b 98 * @defgroup RADIO_SPI_Private_FunctionPrototypes RADIO_SPI Private Function Prototypes
vpcola 0:a1734fe1ec4b 99 * @{
vpcola 0:a1734fe1ec4b 100 */
vpcola 0:a1734fe1ec4b 101
vpcola 0:a1734fe1ec4b 102 /**
vpcola 0:a1734fe1ec4b 103 * @}
vpcola 0:a1734fe1ec4b 104 */
vpcola 0:a1734fe1ec4b 105
vpcola 0:a1734fe1ec4b 106 /**
vpcola 0:a1734fe1ec4b 107 * @defgroup RADIO_SPI_Private_Functions RADIO_SPI Private Functions
vpcola 0:a1734fe1ec4b 108 * @{
vpcola 0:a1734fe1ec4b 109 */
vpcola 0:a1734fe1ec4b 110
vpcola 0:a1734fe1ec4b 111 /**
vpcola 0:a1734fe1ec4b 112 * @}
vpcola 0:a1734fe1ec4b 113 */
vpcola 0:a1734fe1ec4b 114
vpcola 0:a1734fe1ec4b 115 /**
vpcola 0:a1734fe1ec4b 116 * @brief Write single or multiple RF Transceivers register
vpcola 0:a1734fe1ec4b 117 * @param cRegAddress: base register's address to be write
vpcola 0:a1734fe1ec4b 118 * @param cNbBytes: number of registers and bytes to be write
vpcola 0:a1734fe1ec4b 119 * @param pcBuffer: pointer to the buffer of values have to be written into registers
vpcola 0:a1734fe1ec4b 120 * @retval StatusBytes
vpcola 0:a1734fe1ec4b 121 */
vpcola 0:a1734fe1ec4b 122 StatusBytes SdkEvalSpiWriteRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:a1734fe1ec4b 123 {
vpcola 0:a1734fe1ec4b 124 return SimpleSpirit1::Instance().SdkEvalSpiWriteRegisters(cRegAddress, cNbBytes, pcBuffer);
vpcola 0:a1734fe1ec4b 125 }
vpcola 0:a1734fe1ec4b 126
vpcola 0:a1734fe1ec4b 127 StatusBytes SimpleSpirit1::SdkEvalSpiWriteRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:a1734fe1ec4b 128 {
vpcola 0:a1734fe1ec4b 129 uint8_t aHeader[2] = {0};
vpcola 0:a1734fe1ec4b 130 uint16_t tmpstatus = 0x0000;
vpcola 0:a1734fe1ec4b 131 StatusBytes *pStatus=(StatusBytes *)&tmpstatus;
vpcola 0:a1734fe1ec4b 132
vpcola 0:a1734fe1ec4b 133 /* Built the aHeader bytes */
vpcola 0:a1734fe1ec4b 134 aHeader[0] = WRITE_HEADER;
vpcola 0:a1734fe1ec4b 135 aHeader[1] = cRegAddress;
vpcola 0:a1734fe1ec4b 136
vpcola 0:a1734fe1ec4b 137 /* Puts the SPI chip select low to start the transaction */
vpcola 0:a1734fe1ec4b 138 chip_sync_select();
vpcola 0:a1734fe1ec4b 139
vpcola 0:a1734fe1ec4b 140 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:a1734fe1ec4b 141 tmpstatus = _spi.write(aHeader[0]);
vpcola 0:a1734fe1ec4b 142 tmpstatus = tmpstatus << 8;
vpcola 0:a1734fe1ec4b 143
vpcola 0:a1734fe1ec4b 144 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:a1734fe1ec4b 145 tmpstatus |= _spi.write(aHeader[1]);
vpcola 0:a1734fe1ec4b 146
vpcola 0:a1734fe1ec4b 147 /* Writes the registers according to the number of bytes */
vpcola 0:a1734fe1ec4b 148 for (int index = 0; index < cNbBytes; index++)
vpcola 0:a1734fe1ec4b 149 {
vpcola 0:a1734fe1ec4b 150 _spi.write(pcBuffer[index]);
vpcola 0:a1734fe1ec4b 151 }
vpcola 0:a1734fe1ec4b 152
vpcola 0:a1734fe1ec4b 153 /* Puts the SPI chip select high to end the transaction */
vpcola 0:a1734fe1ec4b 154 chip_sync_unselect();
vpcola 0:a1734fe1ec4b 155
vpcola 0:a1734fe1ec4b 156 return *pStatus;
vpcola 0:a1734fe1ec4b 157 }
vpcola 0:a1734fe1ec4b 158
vpcola 0:a1734fe1ec4b 159
vpcola 0:a1734fe1ec4b 160 /**
vpcola 0:a1734fe1ec4b 161 * @brief Read single or multiple SPIRIT1 register
vpcola 0:a1734fe1ec4b 162 * @param cRegAddress: base register's address to be read
vpcola 0:a1734fe1ec4b 163 * @param cNbBytes: number of registers and bytes to be read
vpcola 0:a1734fe1ec4b 164 * @param pcBuffer: pointer to the buffer of registers' values read
vpcola 0:a1734fe1ec4b 165 * @retval StatusBytes
vpcola 0:a1734fe1ec4b 166 */
vpcola 0:a1734fe1ec4b 167 StatusBytes SdkEvalSpiReadRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:a1734fe1ec4b 168 {
vpcola 0:a1734fe1ec4b 169 return SimpleSpirit1::Instance().SdkEvalSpiReadRegisters(cRegAddress, cNbBytes, pcBuffer);
vpcola 0:a1734fe1ec4b 170 }
vpcola 0:a1734fe1ec4b 171
vpcola 0:a1734fe1ec4b 172 StatusBytes SimpleSpirit1::SdkEvalSpiReadRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:a1734fe1ec4b 173 {
vpcola 0:a1734fe1ec4b 174 uint16_t tmpstatus = 0x00;
vpcola 0:a1734fe1ec4b 175 StatusBytes *pStatus = (StatusBytes *)&tmpstatus;
vpcola 0:a1734fe1ec4b 176
vpcola 0:a1734fe1ec4b 177 uint8_t aHeader[2] = {0};
vpcola 0:a1734fe1ec4b 178
vpcola 0:a1734fe1ec4b 179 /* Built the aHeader bytes */
vpcola 0:a1734fe1ec4b 180 aHeader[0] = READ_HEADER;
vpcola 0:a1734fe1ec4b 181 aHeader[1] = cRegAddress;
vpcola 0:a1734fe1ec4b 182
vpcola 0:a1734fe1ec4b 183 /* Put the SPI chip select low to start the transaction */
vpcola 0:a1734fe1ec4b 184 chip_sync_select();
vpcola 0:a1734fe1ec4b 185
vpcola 0:a1734fe1ec4b 186 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:a1734fe1ec4b 187 tmpstatus = _spi.write(aHeader[0]);
vpcola 0:a1734fe1ec4b 188 tmpstatus = tmpstatus << 8;
vpcola 0:a1734fe1ec4b 189
vpcola 0:a1734fe1ec4b 190 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:a1734fe1ec4b 191 tmpstatus |= _spi.write(aHeader[1]);
vpcola 0:a1734fe1ec4b 192
vpcola 0:a1734fe1ec4b 193 for (int index = 0; index < cNbBytes; index++)
vpcola 0:a1734fe1ec4b 194 {
vpcola 0:a1734fe1ec4b 195 pcBuffer[index] = _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 196 }
vpcola 0:a1734fe1ec4b 197
vpcola 0:a1734fe1ec4b 198 /* Put the SPI chip select high to end the transaction */
vpcola 0:a1734fe1ec4b 199 chip_sync_unselect();
vpcola 0:a1734fe1ec4b 200
vpcola 0:a1734fe1ec4b 201 return *pStatus;
vpcola 0:a1734fe1ec4b 202 }
vpcola 0:a1734fe1ec4b 203
vpcola 0:a1734fe1ec4b 204
vpcola 0:a1734fe1ec4b 205 /**
vpcola 0:a1734fe1ec4b 206 * @brief Send a command
vpcola 0:a1734fe1ec4b 207 * @param cCommandCode: command code to be sent
vpcola 0:a1734fe1ec4b 208 * @retval StatusBytes
vpcola 0:a1734fe1ec4b 209 */
vpcola 0:a1734fe1ec4b 210 StatusBytes SdkEvalSpiCommandStrobes(uint8_t cCommandCode)
vpcola 0:a1734fe1ec4b 211 {
vpcola 0:a1734fe1ec4b 212 return SimpleSpirit1::Instance().SdkEvalSpiCommandStrobes(cCommandCode);
vpcola 0:a1734fe1ec4b 213 }
vpcola 0:a1734fe1ec4b 214
vpcola 0:a1734fe1ec4b 215 StatusBytes SimpleSpirit1::SdkEvalSpiCommandStrobes(uint8_t cCommandCode)
vpcola 0:a1734fe1ec4b 216 {
vpcola 0:a1734fe1ec4b 217 uint8_t aHeader[2] = {0};
vpcola 0:a1734fe1ec4b 218 uint16_t tmpstatus = 0x0000;
vpcola 0:a1734fe1ec4b 219
vpcola 0:a1734fe1ec4b 220 StatusBytes *pStatus = (StatusBytes *)&tmpstatus;
vpcola 0:a1734fe1ec4b 221
vpcola 0:a1734fe1ec4b 222 /* Built the aHeader bytes */
vpcola 0:a1734fe1ec4b 223 aHeader[0] = COMMAND_HEADER;
vpcola 0:a1734fe1ec4b 224 aHeader[1] = cCommandCode;
vpcola 0:a1734fe1ec4b 225
vpcola 0:a1734fe1ec4b 226 /* Puts the SPI chip select low to start the transaction */
vpcola 0:a1734fe1ec4b 227 chip_sync_select();
vpcola 0:a1734fe1ec4b 228
vpcola 0:a1734fe1ec4b 229 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:a1734fe1ec4b 230 tmpstatus = _spi.write(aHeader[0]);
vpcola 0:a1734fe1ec4b 231 tmpstatus = tmpstatus<<8;
vpcola 0:a1734fe1ec4b 232
vpcola 0:a1734fe1ec4b 233 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:a1734fe1ec4b 234 tmpstatus |= _spi.write(aHeader[1]);
vpcola 0:a1734fe1ec4b 235
vpcola 0:a1734fe1ec4b 236 /* Puts the SPI chip select high to end the transaction */
vpcola 0:a1734fe1ec4b 237 chip_sync_unselect();
vpcola 0:a1734fe1ec4b 238
vpcola 0:a1734fe1ec4b 239 return *pStatus;
vpcola 0:a1734fe1ec4b 240 }
vpcola 0:a1734fe1ec4b 241
vpcola 0:a1734fe1ec4b 242
vpcola 0:a1734fe1ec4b 243 /**
vpcola 0:a1734fe1ec4b 244 * @brief Write data into TX FIFO
vpcola 0:a1734fe1ec4b 245 * @param cNbBytes: number of bytes to be written into TX FIFO
vpcola 0:a1734fe1ec4b 246 * @param pcBuffer: pointer to data to write
vpcola 0:a1734fe1ec4b 247 * @retval StatusBytes
vpcola 0:a1734fe1ec4b 248 */
vpcola 0:a1734fe1ec4b 249 StatusBytes SdkEvalSpiWriteFifo(uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:a1734fe1ec4b 250 {
vpcola 0:a1734fe1ec4b 251 return SimpleSpirit1::Instance().SdkEvalSpiWriteFifo(cNbBytes, pcBuffer);
vpcola 0:a1734fe1ec4b 252 }
vpcola 0:a1734fe1ec4b 253
vpcola 0:a1734fe1ec4b 254 StatusBytes SimpleSpirit1::SdkEvalSpiWriteFifo(uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:a1734fe1ec4b 255 {
vpcola 0:a1734fe1ec4b 256 uint16_t tmpstatus = 0x0000;
vpcola 0:a1734fe1ec4b 257 StatusBytes *pStatus = (StatusBytes *)&tmpstatus;
vpcola 0:a1734fe1ec4b 258
vpcola 0:a1734fe1ec4b 259 uint8_t aHeader[2] = {0};
vpcola 0:a1734fe1ec4b 260
vpcola 0:a1734fe1ec4b 261 /* Built the aHeader bytes */
vpcola 0:a1734fe1ec4b 262 aHeader[0] = WRITE_HEADER;
vpcola 0:a1734fe1ec4b 263 aHeader[1] = LINEAR_FIFO_ADDRESS;
vpcola 0:a1734fe1ec4b 264
vpcola 0:a1734fe1ec4b 265 /* Put the SPI chip select low to start the transaction */
vpcola 0:a1734fe1ec4b 266 chip_sync_select();
vpcola 0:a1734fe1ec4b 267
vpcola 0:a1734fe1ec4b 268 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:a1734fe1ec4b 269 tmpstatus = _spi.write(aHeader[0]);
vpcola 0:a1734fe1ec4b 270 tmpstatus = tmpstatus<<8;
vpcola 0:a1734fe1ec4b 271
vpcola 0:a1734fe1ec4b 272 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:a1734fe1ec4b 273 tmpstatus |= _spi.write(aHeader[1]);
vpcola 0:a1734fe1ec4b 274
vpcola 0:a1734fe1ec4b 275 /* Writes the registers according to the number of bytes */
vpcola 0:a1734fe1ec4b 276 for (int index = 0; index < cNbBytes; index++)
vpcola 0:a1734fe1ec4b 277 {
vpcola 0:a1734fe1ec4b 278 _spi.write(pcBuffer[index]);
vpcola 0:a1734fe1ec4b 279 }
vpcola 0:a1734fe1ec4b 280
vpcola 0:a1734fe1ec4b 281 /* Put the SPI chip select high to end the transaction */
vpcola 0:a1734fe1ec4b 282 chip_sync_unselect();
vpcola 0:a1734fe1ec4b 283
vpcola 0:a1734fe1ec4b 284 return *pStatus;
vpcola 0:a1734fe1ec4b 285 }
vpcola 0:a1734fe1ec4b 286
vpcola 0:a1734fe1ec4b 287 /**
vpcola 0:a1734fe1ec4b 288 * @brief Read data from RX FIFO
vpcola 0:a1734fe1ec4b 289 * @param cNbBytes: number of bytes to read from RX FIFO
vpcola 0:a1734fe1ec4b 290 * @param pcBuffer: pointer to data read from RX FIFO
vpcola 0:a1734fe1ec4b 291 * @retval StatusBytes
vpcola 0:a1734fe1ec4b 292 */
vpcola 0:a1734fe1ec4b 293 StatusBytes SdkEvalSpiReadFifo(uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:a1734fe1ec4b 294 {
vpcola 0:a1734fe1ec4b 295 return SimpleSpirit1::Instance().SdkEvalSpiReadFifo(cNbBytes, pcBuffer);
vpcola 0:a1734fe1ec4b 296 }
vpcola 0:a1734fe1ec4b 297
vpcola 0:a1734fe1ec4b 298 StatusBytes SimpleSpirit1::SdkEvalSpiReadFifo(uint8_t cNbBytes, uint8_t* pcBuffer)
vpcola 0:a1734fe1ec4b 299 {
vpcola 0:a1734fe1ec4b 300 uint16_t tmpstatus = 0x0000;
vpcola 0:a1734fe1ec4b 301 StatusBytes *pStatus = (StatusBytes *)&tmpstatus;
vpcola 0:a1734fe1ec4b 302
vpcola 0:a1734fe1ec4b 303 uint8_t aHeader[2];
vpcola 0:a1734fe1ec4b 304
vpcola 0:a1734fe1ec4b 305 /* Built the aHeader bytes */
vpcola 0:a1734fe1ec4b 306 aHeader[0]=READ_HEADER;
vpcola 0:a1734fe1ec4b 307 aHeader[1]=LINEAR_FIFO_ADDRESS;
vpcola 0:a1734fe1ec4b 308
vpcola 0:a1734fe1ec4b 309 /* Put the SPI chip select low to start the transaction */
vpcola 0:a1734fe1ec4b 310 chip_sync_select();
vpcola 0:a1734fe1ec4b 311
vpcola 0:a1734fe1ec4b 312 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:a1734fe1ec4b 313 tmpstatus = _spi.write(aHeader[0]);
vpcola 0:a1734fe1ec4b 314 tmpstatus = tmpstatus<<8;
vpcola 0:a1734fe1ec4b 315
vpcola 0:a1734fe1ec4b 316 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
vpcola 0:a1734fe1ec4b 317 tmpstatus |= _spi.write(aHeader[1]);
vpcola 0:a1734fe1ec4b 318
vpcola 0:a1734fe1ec4b 319 for (int index = 0; index < cNbBytes; index++)
vpcola 0:a1734fe1ec4b 320 {
vpcola 0:a1734fe1ec4b 321 pcBuffer[index] = _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 322 }
vpcola 0:a1734fe1ec4b 323
vpcola 0:a1734fe1ec4b 324 /* Put the SPI chip select high to end the transaction */
vpcola 0:a1734fe1ec4b 325 chip_sync_unselect();
vpcola 0:a1734fe1ec4b 326
vpcola 0:a1734fe1ec4b 327 return *pStatus;
vpcola 0:a1734fe1ec4b 328 }
vpcola 0:a1734fe1ec4b 329
vpcola 0:a1734fe1ec4b 330
vpcola 0:a1734fe1ec4b 331 /**
vpcola 0:a1734fe1ec4b 332 * @}
vpcola 0:a1734fe1ec4b 333 */
vpcola 0:a1734fe1ec4b 334
vpcola 0:a1734fe1ec4b 335 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/