Vergil Cola / Mbed OS MQTTGateway2

Fork of my original MQTTGateway

Dependencies:   mbed-http

easy-connect/mcr20a-rf-driver/source/MCR20Overwrites.h@0:a1734fe1ec4b, 2017-04-08 (annotated)

Committer:
vpcola
Date:
Sat Apr 08 14:43:14 2017 +0000
Revision:
0:a1734fe1ec4b
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vpcola 0:a1734fe1ec4b 1 /*!
vpcola 0:a1734fe1ec4b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
vpcola 0:a1734fe1ec4b 3 * All rights reserved.
vpcola 0:a1734fe1ec4b 4 *
vpcola 0:a1734fe1ec4b 5 * \file MCR20Overwrites.h
vpcola 0:a1734fe1ec4b 6 * Description: Overwrites header file for MCR20 Register values
vpcola 0:a1734fe1ec4b 7 *
vpcola 0:a1734fe1ec4b 8 * Redistribution and use in source and binary forms, with or without modification,
vpcola 0:a1734fe1ec4b 9 * are permitted provided that the following conditions are met:
vpcola 0:a1734fe1ec4b 10 *
vpcola 0:a1734fe1ec4b 11 * o Redistributions of source code must retain the above copyright notice, this list
vpcola 0:a1734fe1ec4b 12 * of conditions and the following disclaimer.
vpcola 0:a1734fe1ec4b 13 *
vpcola 0:a1734fe1ec4b 14 * o Redistributions in binary form must reproduce the above copyright notice, this
vpcola 0:a1734fe1ec4b 15 * list of conditions and the following disclaimer in the documentation and/or
vpcola 0:a1734fe1ec4b 16 * other materials provided with the distribution.
vpcola 0:a1734fe1ec4b 17 *
vpcola 0:a1734fe1ec4b 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
vpcola 0:a1734fe1ec4b 19 * contributors may be used to endorse or promote products derived from this
vpcola 0:a1734fe1ec4b 20 * software without specific prior written permission.
vpcola 0:a1734fe1ec4b 21 *
vpcola 0:a1734fe1ec4b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
vpcola 0:a1734fe1ec4b 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
vpcola 0:a1734fe1ec4b 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vpcola 0:a1734fe1ec4b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
vpcola 0:a1734fe1ec4b 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
vpcola 0:a1734fe1ec4b 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
vpcola 0:a1734fe1ec4b 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
vpcola 0:a1734fe1ec4b 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
vpcola 0:a1734fe1ec4b 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
vpcola 0:a1734fe1ec4b 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vpcola 0:a1734fe1ec4b 32 */
vpcola 0:a1734fe1ec4b 33
vpcola 0:a1734fe1ec4b 34 #ifndef OVERWRITES_H_
vpcola 0:a1734fe1ec4b 35 #define OVERWRITES_H_
vpcola 0:a1734fe1ec4b 36
vpcola 0:a1734fe1ec4b 37 typedef struct overwrites_tag {
vpcola 0:a1734fe1ec4b 38 char address;
vpcola 0:a1734fe1ec4b 39 char data;
vpcola 0:a1734fe1ec4b 40 }overwrites_t;
vpcola 0:a1734fe1ec4b 41
vpcola 0:a1734fe1ec4b 42
vpcola 0:a1734fe1ec4b 43 /*****************************************************************************************************************/
vpcola 0:a1734fe1ec4b 44 // This file is created exclusively for use with the transceiver 2.0 silicon
vpcola 0:a1734fe1ec4b 45 // and is provided for the world to use. It contains a list of all
vpcola 0:a1734fe1ec4b 46 // known overwrite values. Overwrite values are non-default register
vpcola 0:a1734fe1ec4b 47 // values that configure the transceiver device to a more optimally performing
vpcola 0:a1734fe1ec4b 48 // posture. It is expected that low level software (i.e. PHY) will
vpcola 0:a1734fe1ec4b 49 // consume this file as a #include, and transfer the contents to the
vpcola 0:a1734fe1ec4b 50 // the indicated addresses in the transceiver's memory space. This file has
vpcola 0:a1734fe1ec4b 51 // at least one required entry, that being its own version current version
vpcola 0:a1734fe1ec4b 52 // number, to be stored at transceiver's location 0x3B the
vpcola 0:a1734fe1ec4b 53 // OVERWRITES_VERSION_NUMBER register. The RAM register is provided in
vpcola 0:a1734fe1ec4b 54 // the transceiver address space to assist in future debug efforts. The
vpcola 0:a1734fe1ec4b 55 // analyst may read this location (once device has been booted with
vpcola 0:a1734fe1ec4b 56 // mysterious software) and have a good indication of what register
vpcola 0:a1734fe1ec4b 57 // overwrites were performed (with all versions of the overwrites.h file
vpcola 0:a1734fe1ec4b 58 // being archived forever at the Compass location shown above.
vpcola 0:a1734fe1ec4b 59 //
vpcola 0:a1734fe1ec4b 60 // The transceiver has an indirect register (IAR) space. Write access to this space
vpcola 0:a1734fe1ec4b 61 // requires 3 or more writes:
vpcola 0:a1734fe1ec4b 62 // 1st) the first write is an index value to the indirect (write Bit7=0, register access Bit 6=0) + 0x3E
vpcola 0:a1734fe1ec4b 63 // 2nd) IAR Register #0x00 - 0xFF.
vpcola 0:a1734fe1ec4b 64 // 3rd) The data to write
vpcola 0:a1734fe1ec4b 65 // nth) Burst mode additional data if required.
vpcola 0:a1734fe1ec4b 66 //
vpcola 0:a1734fe1ec4b 67 // Write access to direct space requires only a single address, data pair.
vpcola 0:a1734fe1ec4b 68
vpcola 0:a1734fe1ec4b 69 overwrites_t const overwrites_direct[] ={
vpcola 0:a1734fe1ec4b 70 {0x3B, 0x0C}, //version 0C: new value for ACKDELAY targeting 198us (23 May, 2013, Larry Roshak)
vpcola 0:a1734fe1ec4b 71 {0x23, 0x17} //PA_PWR new default Power Step is "23"
vpcola 0:a1734fe1ec4b 72 };
vpcola 0:a1734fe1ec4b 73
vpcola 0:a1734fe1ec4b 74 overwrites_t const overwrites_indirect[] ={
vpcola 0:a1734fe1ec4b 75 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:a1734fe1ec4b 76 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:a1734fe1ec4b 77 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:a1734fe1ec4b 78 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:a1734fe1ec4b 79 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 80 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 81 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 82 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 83 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 84 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 85 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 86 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 87 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 88 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 89 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 90 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
vpcola 0:a1734fe1ec4b 91 {0x52, 0x55}, //AGC_THR1 RSSI tune up
vpcola 0:a1734fe1ec4b 92 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
vpcola 0:a1734fe1ec4b 93 {0x66, 0x5F}, //ATT_RSSI1 tune up
vpcola 0:a1734fe1ec4b 94 {0x67, 0x8F}, //ATT_RSSI2 tune up
vpcola 0:a1734fe1ec4b 95 {0x68, 0x61}, //RSSI_OFFSET
vpcola 0:a1734fe1ec4b 96 {0x78, 0x03}, //CHF_PMAGAIN
vpcola 0:a1734fe1ec4b 97 {0x22, 0x50}, //CCA1_THRESH
vpcola 0:a1734fe1ec4b 98 {0x4D, 0x13}, //CORR_NVAL moved from 0x14 to 0x13 for 0.5 dB improved Rx Sensitivity
vpcola 0:a1734fe1ec4b 99 {0x39, 0x3D} //ACKDELAY new value targeting a delay of 198us (23 May, 2013, Larry Roshak)
vpcola 0:a1734fe1ec4b 100 };
vpcola 0:a1734fe1ec4b 101
vpcola 0:a1734fe1ec4b 102
vpcola 0:a1734fe1ec4b 103 /* begin of deprecated versions
vpcola 0:a1734fe1ec4b 104
vpcola 0:a1734fe1ec4b 105 ==VERSION 1==
vpcola 0:a1734fe1ec4b 106 (version 1 is empty)
vpcola 0:a1734fe1ec4b 107
vpcola 0:a1734fe1ec4b 108 ==VERSION 2==
vpcola 0:a1734fe1ec4b 109 overwrites_t const overwrites_indirect[] ={
vpcola 0:a1734fe1ec4b 110 {0x31, 0x02} //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:a1734fe1ec4b 111 };
vpcola 0:a1734fe1ec4b 112
vpcola 0:a1734fe1ec4b 113 ==VERSION 3==
vpcola 0:a1734fe1ec4b 114 overwrites_t const overwrites_indirect[] ={
vpcola 0:a1734fe1ec4b 115 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:a1734fe1ec4b 116 {0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3
vpcola 0:a1734fe1ec4b 117 {0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:a1734fe1ec4b 118 };
vpcola 0:a1734fe1ec4b 119
vpcola 0:a1734fe1ec4b 120 ==VERSION 4==
vpcola 0:a1734fe1ec4b 121 overwrites_t const overwrites_direct[] ={
vpcola 0:a1734fe1ec4b 122 {0x3B, 0x04} //version 04 is the current version: update PA_COILTUNING default
vpcola 0:a1734fe1ec4b 123 };
vpcola 0:a1734fe1ec4b 124
vpcola 0:a1734fe1ec4b 125 overwrites_t const overwrites_indirect[] ={
vpcola 0:a1734fe1ec4b 126 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:a1734fe1ec4b 127 {0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3
vpcola 0:a1734fe1ec4b 128 {0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:a1734fe1ec4b 129 {0x8A, 0x71} //PA_TUNING: override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:a1734fe1ec4b 130 };
vpcola 0:a1734fe1ec4b 131
vpcola 0:a1734fe1ec4b 132 ==VERSION 5==
vpcola 0:a1734fe1ec4b 133 overwrites_t const overwrites_direct[] ={
vpcola 0:a1734fe1ec4b 134 {0x3B, 0x05} //version 05: updates Channel Filter Register set (21 Dec 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 135 };
vpcola 0:a1734fe1ec4b 136
vpcola 0:a1734fe1ec4b 137 overwrites_t const overwrites_indirect[] ={
vpcola 0:a1734fe1ec4b 138 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:a1734fe1ec4b 139 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:a1734fe1ec4b 140 {0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:a1734fe1ec4b 141 {0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:a1734fe1ec4b 142 {0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 143 {0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 144 {0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 145 {0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 146 {0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 147 {0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 148 {0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 149 {0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 150 {0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 151 {0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 152 {0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 153 };
vpcola 0:a1734fe1ec4b 154
vpcola 0:a1734fe1ec4b 155 ==VERSION 6==
vpcola 0:a1734fe1ec4b 156 overwrites_t const overwrites_direct[] ={
vpcola 0:a1734fe1ec4b 157 {0x3B, 0x06} //version 06: disable PA calibration
vpcola 0:a1734fe1ec4b 158 };
vpcola 0:a1734fe1ec4b 159
vpcola 0:a1734fe1ec4b 160 overwrites_t const overwrites_indirect[] ={
vpcola 0:a1734fe1ec4b 161 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:a1734fe1ec4b 162 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:a1734fe1ec4b 163 {0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:a1734fe1ec4b 164 {0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:a1734fe1ec4b 165 {0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 166 {0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 167 {0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 168 {0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 169 {0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 170 {0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 171 {0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 172 {0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 173 {0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 174 {0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 175 {0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 176 {0x64, 0x28} //PA_CAL_DIS=1 Disabled PA calibration
vpcola 0:a1734fe1ec4b 177 };
vpcola 0:a1734fe1ec4b 178
vpcola 0:a1734fe1ec4b 179 ==VERSION 7==
vpcola 0:a1734fe1ec4b 180 overwrites_t const overwrites_direct[] ={
vpcola 0:a1734fe1ec4b 181 {0x3B, 0x07} //version 07: updated registers for ED/RSSI
vpcola 0:a1734fe1ec4b 182 };
vpcola 0:a1734fe1ec4b 183
vpcola 0:a1734fe1ec4b 184 overwrites_t const overwrites_indirect[] ={
vpcola 0:a1734fe1ec4b 185 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:a1734fe1ec4b 186 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:a1734fe1ec4b 187 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:a1734fe1ec4b 188 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:a1734fe1ec4b 189 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 190 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 191 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 192 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 193 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 194 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 195 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 196 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 197 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 198 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 199 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 200 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
vpcola 0:a1734fe1ec4b 201 {0x52, 0x73}, //AGC_THR1 RSSI tune up
vpcola 0:a1734fe1ec4b 202 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
vpcola 0:a1734fe1ec4b 203 {0x66, 0x5F}, //ATT_RSSI1 tune up
vpcola 0:a1734fe1ec4b 204 {0x67, 0x8F}, //ATT_RSSI2 tune up
vpcola 0:a1734fe1ec4b 205 {0x68, 0x60}, //RSSI_OFFSET
vpcola 0:a1734fe1ec4b 206 {0x69, 0x65} //RSSI_SLOPE
vpcola 0:a1734fe1ec4b 207 };
vpcola 0:a1734fe1ec4b 208
vpcola 0:a1734fe1ec4b 209
vpcola 0:a1734fe1ec4b 210 ==VERSION 8==
vpcola 0:a1734fe1ec4b 211 overwrites_t const overwrites_direct[] ={
vpcola 0:a1734fe1ec4b 212 {0x3B, 0x08} //version 08: updated registers for ED/RSSI
vpcola 0:a1734fe1ec4b 213 };
vpcola 0:a1734fe1ec4b 214
vpcola 0:a1734fe1ec4b 215 overwrites_t const overwrites_indirect[] ={
vpcola 0:a1734fe1ec4b 216 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:a1734fe1ec4b 217 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:a1734fe1ec4b 218 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:a1734fe1ec4b 219 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:a1734fe1ec4b 220 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 221 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 222 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 223 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 224 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 225 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 226 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 227 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 228 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 229 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 230 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 231 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
vpcola 0:a1734fe1ec4b 232 {0x52, 0x73}, //AGC_THR1 RSSI tune up
vpcola 0:a1734fe1ec4b 233 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
vpcola 0:a1734fe1ec4b 234 {0x66, 0x5F}, //ATT_RSSI1 tune up
vpcola 0:a1734fe1ec4b 235 {0x67, 0x8F}, //ATT_RSSI2 tune up
vpcola 0:a1734fe1ec4b 236 {0x69, 0x65} //RSSI_SLOPE
vpcola 0:a1734fe1ec4b 237 {0x68, 0x61}, //RSSI_OFFSET
vpcola 0:a1734fe1ec4b 238 {0x78, 0x03} //CHF_PMAGAIN
vpcola 0:a1734fe1ec4b 239 };
vpcola 0:a1734fe1ec4b 240
vpcola 0:a1734fe1ec4b 241
vpcola 0:a1734fe1ec4b 242 ==VERSION 9==
vpcola 0:a1734fe1ec4b 243 overwrites_t const overwrites_direct[] ={
vpcola 0:a1734fe1ec4b 244 {0x3B, 0x09} //version 09: updated registers for ED/RSSI and PowerStep
vpcola 0:a1734fe1ec4b 245 {0x23, 0x17} //PA_PWR new default value
vpcola 0:a1734fe1ec4b 246 };
vpcola 0:a1734fe1ec4b 247
vpcola 0:a1734fe1ec4b 248 overwrites_t const overwrites_indirect[] ={
vpcola 0:a1734fe1ec4b 249 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:a1734fe1ec4b 250 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:a1734fe1ec4b 251 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:a1734fe1ec4b 252 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:a1734fe1ec4b 253 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 254 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 255 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 256 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 257 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 258 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 259 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 260 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 261 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 262 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 263 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 264 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
vpcola 0:a1734fe1ec4b 265 {0x52, 0x55}, //AGC_THR1 RSSI tune up
vpcola 0:a1734fe1ec4b 266 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
vpcola 0:a1734fe1ec4b 267 {0x66, 0x5F}, //ATT_RSSI1 tune up
vpcola 0:a1734fe1ec4b 268 {0x67, 0x8F}, //ATT_RSSI2 tune up
vpcola 0:a1734fe1ec4b 269 {0x68, 0x61}, //RSSI_OFFSET
vpcola 0:a1734fe1ec4b 270 {0x78, 0x03} //CHF_PMAGAIN
vpcola 0:a1734fe1ec4b 271 };
vpcola 0:a1734fe1ec4b 272
vpcola 0:a1734fe1ec4b 273 ==VERSION A==
vpcola 0:a1734fe1ec4b 274 overwrites_t const overwrites_direct[] ={
vpcola 0:a1734fe1ec4b 275 {0x3B, 0x0A} //version 0A: updated registers for CCA
vpcola 0:a1734fe1ec4b 276 {0x23, 0x17} //PA_PWR new default Power Step is "23"
vpcola 0:a1734fe1ec4b 277 };
vpcola 0:a1734fe1ec4b 278
vpcola 0:a1734fe1ec4b 279 overwrites_t const overwrites_indirect[] ={
vpcola 0:a1734fe1ec4b 280 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
vpcola 0:a1734fe1ec4b 281 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
vpcola 0:a1734fe1ec4b 282 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
vpcola 0:a1734fe1ec4b 283 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
vpcola 0:a1734fe1ec4b 284 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 285 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 286 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 287 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 288 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 289 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 290 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 291 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 292 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 293 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 294 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
vpcola 0:a1734fe1ec4b 295 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
vpcola 0:a1734fe1ec4b 296 {0x52, 0x55}, //AGC_THR1 RSSI tune up
vpcola 0:a1734fe1ec4b 297 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
vpcola 0:a1734fe1ec4b 298 {0x66, 0x5F}, //ATT_RSSI1 tune up
vpcola 0:a1734fe1ec4b 299 {0x67, 0x8F}, //ATT_RSSI2 tune up
vpcola 0:a1734fe1ec4b 300 {0x68, 0x61}, //RSSI_OFFSET
vpcola 0:a1734fe1ec4b 301 {0x78, 0x03} //CHF_PMAGAIN
vpcola 0:a1734fe1ec4b 302 {0x22, 0x50} //CCA1_THRESH
vpcola 0:a1734fe1ec4b 303 };
vpcola 0:a1734fe1ec4b 304
vpcola 0:a1734fe1ec4b 305 end of deprecated versions */
vpcola 0:a1734fe1ec4b 306
vpcola 0:a1734fe1ec4b 307
vpcola 0:a1734fe1ec4b 308 #endif //OVERWRITES_H_
vpcola 0:a1734fe1ec4b 309