Vergil Cola / Mbed OS MQTTGateway2

Fork of my original MQTTGateway

Dependencies:   mbed-http

sd-driver/features/filesystem/sd/SDBlockDevice.cpp@0:a1734fe1ec4b, 2017-04-08 (annotated)

Committer:
vpcola
Date:
Sat Apr 08 14:43:14 2017 +0000
Revision:
0:a1734fe1ec4b
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vpcola 0:a1734fe1ec4b 1 /* mbed Microcontroller Library
vpcola 0:a1734fe1ec4b 2 * Copyright (c) 2006-2012 ARM Limited
vpcola 0:a1734fe1ec4b 3 *
vpcola 0:a1734fe1ec4b 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
vpcola 0:a1734fe1ec4b 5 * of this software and associated documentation files (the "Software"), to deal
vpcola 0:a1734fe1ec4b 6 * in the Software without restriction, including without limitation the rights
vpcola 0:a1734fe1ec4b 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
vpcola 0:a1734fe1ec4b 8 * copies of the Software, and to permit persons to whom the Software is
vpcola 0:a1734fe1ec4b 9 * furnished to do so, subject to the following conditions:
vpcola 0:a1734fe1ec4b 10 *
vpcola 0:a1734fe1ec4b 11 * The above copyright notice and this permission notice shall be included in
vpcola 0:a1734fe1ec4b 12 * all copies or substantial portions of the Software.
vpcola 0:a1734fe1ec4b 13 *
vpcola 0:a1734fe1ec4b 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
vpcola 0:a1734fe1ec4b 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
vpcola 0:a1734fe1ec4b 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
vpcola 0:a1734fe1ec4b 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
vpcola 0:a1734fe1ec4b 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
vpcola 0:a1734fe1ec4b 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
vpcola 0:a1734fe1ec4b 20 * SOFTWARE.
vpcola 0:a1734fe1ec4b 21 */
vpcola 0:a1734fe1ec4b 22 /* Introduction
vpcola 0:a1734fe1ec4b 23 * ------------
vpcola 0:a1734fe1ec4b 24 * SD and MMC cards support a number of interfaces, but common to them all
vpcola 0:a1734fe1ec4b 25 * is one based on SPI. This is the one I'm implmenting because it means
vpcola 0:a1734fe1ec4b 26 * it is much more portable even though not so performant, and we already
vpcola 0:a1734fe1ec4b 27 * have the mbed SPI Interface!
vpcola 0:a1734fe1ec4b 28 *
vpcola 0:a1734fe1ec4b 29 * The main reference I'm using is Chapter 7, "SPI Mode" of:
vpcola 0:a1734fe1ec4b 30 * http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
vpcola 0:a1734fe1ec4b 31 *
vpcola 0:a1734fe1ec4b 32 * SPI Startup
vpcola 0:a1734fe1ec4b 33 * -----------
vpcola 0:a1734fe1ec4b 34 * The SD card powers up in SD mode. The SPI interface mode is selected by
vpcola 0:a1734fe1ec4b 35 * asserting CS low and sending the reset command (CMD0). The card will
vpcola 0:a1734fe1ec4b 36 * respond with a (R1) response.
vpcola 0:a1734fe1ec4b 37 *
vpcola 0:a1734fe1ec4b 38 * CMD8 is optionally sent to determine the voltage range supported, and
vpcola 0:a1734fe1ec4b 39 * indirectly determine whether it is a version 1.x SD/non-SD card or
vpcola 0:a1734fe1ec4b 40 * version 2.x. I'll just ignore this for now.
vpcola 0:a1734fe1ec4b 41 *
vpcola 0:a1734fe1ec4b 42 * ACMD41 is repeatedly issued to initialise the card, until "in idle"
vpcola 0:a1734fe1ec4b 43 * (bit 0) of the R1 response goes to '0', indicating it is initialised.
vpcola 0:a1734fe1ec4b 44 *
vpcola 0:a1734fe1ec4b 45 * You should also indicate whether the host supports High Capicity cards,
vpcola 0:a1734fe1ec4b 46 * and check whether the card is high capacity - i'll also ignore this
vpcola 0:a1734fe1ec4b 47 *
vpcola 0:a1734fe1ec4b 48 * SPI Protocol
vpcola 0:a1734fe1ec4b 49 * ------------
vpcola 0:a1734fe1ec4b 50 * The SD SPI protocol is based on transactions made up of 8-bit words, with
vpcola 0:a1734fe1ec4b 51 * the host starting every bus transaction by asserting the CS signal low. The
vpcola 0:a1734fe1ec4b 52 * card always responds to commands, data blocks and errors.
vpcola 0:a1734fe1ec4b 53 *
vpcola 0:a1734fe1ec4b 54 * The protocol supports a CRC, but by default it is off (except for the
vpcola 0:a1734fe1ec4b 55 * first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
vpcola 0:a1734fe1ec4b 56 * I'll leave the CRC off I think!
vpcola 0:a1734fe1ec4b 57 *
vpcola 0:a1734fe1ec4b 58 * Standard capacity cards have variable data block sizes, whereas High
vpcola 0:a1734fe1ec4b 59 * Capacity cards fix the size of data block to 512 bytes. I'll therefore
vpcola 0:a1734fe1ec4b 60 * just always use the Standard Capacity cards with a block size of 512 bytes.
vpcola 0:a1734fe1ec4b 61 * This is set with CMD16.
vpcola 0:a1734fe1ec4b 62 *
vpcola 0:a1734fe1ec4b 63 * You can read and write single blocks (CMD17, CMD25) or multiple blocks
vpcola 0:a1734fe1ec4b 64 * (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
vpcola 0:a1734fe1ec4b 65 * the card gets a read command, it responds with a response token, and then
vpcola 0:a1734fe1ec4b 66 * a data token or an error.
vpcola 0:a1734fe1ec4b 67 *
vpcola 0:a1734fe1ec4b 68 * SPI Command Format
vpcola 0:a1734fe1ec4b 69 * ------------------
vpcola 0:a1734fe1ec4b 70 * Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
vpcola 0:a1734fe1ec4b 71 *
vpcola 0:a1734fe1ec4b 72 * +---------------+------------+------------+-----------+----------+--------------+
vpcola 0:a1734fe1ec4b 73 * | 01 | cmd[5:0] | arg[31:24] | arg[23:16] | arg[15:8] | arg[7:0] | crc[6:0] | 1 |
vpcola 0:a1734fe1ec4b 74 * +---------------+------------+------------+-----------+----------+--------------+
vpcola 0:a1734fe1ec4b 75 *
vpcola 0:a1734fe1ec4b 76 * As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
vpcola 0:a1734fe1ec4b 77 *
vpcola 0:a1734fe1ec4b 78 * All Application Specific commands shall be preceded with APP_CMD (CMD55).
vpcola 0:a1734fe1ec4b 79 *
vpcola 0:a1734fe1ec4b 80 * SPI Response Format
vpcola 0:a1734fe1ec4b 81 * -------------------
vpcola 0:a1734fe1ec4b 82 * The main response format (R1) is a status byte (normally zero). Key flags:
vpcola 0:a1734fe1ec4b 83 * idle - 1 if the card is in an idle state/initialising
vpcola 0:a1734fe1ec4b 84 * cmd - 1 if an illegal command code was detected
vpcola 0:a1734fe1ec4b 85 *
vpcola 0:a1734fe1ec4b 86 * +-------------------------------------------------+
vpcola 0:a1734fe1ec4b 87 * R1 | 0 | arg | addr | seq | crc | cmd | erase | idle |
vpcola 0:a1734fe1ec4b 88 * +-------------------------------------------------+
vpcola 0:a1734fe1ec4b 89 *
vpcola 0:a1734fe1ec4b 90 * R1b is the same, except it is followed by a busy signal (zeros) until
vpcola 0:a1734fe1ec4b 91 * the first non-zero byte when it is ready again.
vpcola 0:a1734fe1ec4b 92 *
vpcola 0:a1734fe1ec4b 93 * Data Response Token
vpcola 0:a1734fe1ec4b 94 * -------------------
vpcola 0:a1734fe1ec4b 95 * Every data block written to the card is acknowledged by a byte
vpcola 0:a1734fe1ec4b 96 * response token
vpcola 0:a1734fe1ec4b 97 *
vpcola 0:a1734fe1ec4b 98 * +----------------------+
vpcola 0:a1734fe1ec4b 99 * | xxx | 0 | status | 1 |
vpcola 0:a1734fe1ec4b 100 * +----------------------+
vpcola 0:a1734fe1ec4b 101 * 010 - OK!
vpcola 0:a1734fe1ec4b 102 * 101 - CRC Error
vpcola 0:a1734fe1ec4b 103 * 110 - Write Error
vpcola 0:a1734fe1ec4b 104 *
vpcola 0:a1734fe1ec4b 105 * Single Block Read and Write
vpcola 0:a1734fe1ec4b 106 * ---------------------------
vpcola 0:a1734fe1ec4b 107 *
vpcola 0:a1734fe1ec4b 108 * Block transfers have a byte header, followed by the data, followed
vpcola 0:a1734fe1ec4b 109 * by a 16-bit CRC. In our case, the data will always be 512 bytes.
vpcola 0:a1734fe1ec4b 110 *
vpcola 0:a1734fe1ec4b 111 * +------+---------+---------+- - - -+---------+-----------+----------+
vpcola 0:a1734fe1ec4b 112 * | 0xFE | data[0] | data[1] | | data[n] | crc[15:8] | crc[7:0] |
vpcola 0:a1734fe1ec4b 113 * +------+---------+---------+- - - -+---------+-----------+----------+
vpcola 0:a1734fe1ec4b 114 */
vpcola 0:a1734fe1ec4b 115
vpcola 0:a1734fe1ec4b 116 /* If the target has no SPI support then SDCard is not supported */
vpcola 0:a1734fe1ec4b 117 #ifdef DEVICE_SPI
vpcola 0:a1734fe1ec4b 118
vpcola 0:a1734fe1ec4b 119 #include "SDBlockDevice.h"
vpcola 0:a1734fe1ec4b 120 #include "mbed_debug.h"
vpcola 0:a1734fe1ec4b 121
vpcola 0:a1734fe1ec4b 122 #define SD_COMMAND_TIMEOUT 5000
vpcola 0:a1734fe1ec4b 123
vpcola 0:a1734fe1ec4b 124 #define SD_DBG 0
vpcola 0:a1734fe1ec4b 125
vpcola 0:a1734fe1ec4b 126 #define SD_BLOCK_DEVICE_ERROR_WOULD_BLOCK -5001 /*!< operation would block */
vpcola 0:a1734fe1ec4b 127 #define SD_BLOCK_DEVICE_ERROR_UNSUPPORTED -5002 /*!< unsupported operation */
vpcola 0:a1734fe1ec4b 128 #define SD_BLOCK_DEVICE_ERROR_PARAMETER -5003 /*!< invalid parameter */
vpcola 0:a1734fe1ec4b 129 #define SD_BLOCK_DEVICE_ERROR_NO_INIT -5004 /*!< uninitialized */
vpcola 0:a1734fe1ec4b 130 #define SD_BLOCK_DEVICE_ERROR_NO_DEVICE -5005 /*!< device is missing or not connected */
vpcola 0:a1734fe1ec4b 131 #define SD_BLOCK_DEVICE_ERROR_WRITE_PROTECTED -5006 /*!< write protected */
vpcola 0:a1734fe1ec4b 132
vpcola 0:a1734fe1ec4b 133 SDBlockDevice::SDBlockDevice(PinName mosi, PinName miso, PinName sclk, PinName cs)
vpcola 0:a1734fe1ec4b 134 : _spi(mosi, miso, sclk), _cs(cs), _is_initialized(0)
vpcola 0:a1734fe1ec4b 135 {
vpcola 0:a1734fe1ec4b 136 _cs = 1;
vpcola 0:a1734fe1ec4b 137
vpcola 0:a1734fe1ec4b 138 // Set default to 100kHz for initialisation and 1MHz for data transfer
vpcola 0:a1734fe1ec4b 139 _init_sck = 100000;
vpcola 0:a1734fe1ec4b 140 _transfer_sck = 1000000;
vpcola 0:a1734fe1ec4b 141 }
vpcola 0:a1734fe1ec4b 142
vpcola 0:a1734fe1ec4b 143 SDBlockDevice::~SDBlockDevice()
vpcola 0:a1734fe1ec4b 144 {
vpcola 0:a1734fe1ec4b 145 if (_is_initialized) {
vpcola 0:a1734fe1ec4b 146 deinit();
vpcola 0:a1734fe1ec4b 147 }
vpcola 0:a1734fe1ec4b 148 }
vpcola 0:a1734fe1ec4b 149
vpcola 0:a1734fe1ec4b 150 #define R1_IDLE_STATE (1 << 0)
vpcola 0:a1734fe1ec4b 151 #define R1_ERASE_RESET (1 << 1)
vpcola 0:a1734fe1ec4b 152 #define R1_ILLEGAL_COMMAND (1 << 2)
vpcola 0:a1734fe1ec4b 153 #define R1_COM_CRC_ERROR (1 << 3)
vpcola 0:a1734fe1ec4b 154 #define R1_ERASE_SEQUENCE_ERROR (1 << 4)
vpcola 0:a1734fe1ec4b 155 #define R1_ADDRESS_ERROR (1 << 5)
vpcola 0:a1734fe1ec4b 156 #define R1_PARAMETER_ERROR (1 << 6)
vpcola 0:a1734fe1ec4b 157
vpcola 0:a1734fe1ec4b 158 // Types
vpcola 0:a1734fe1ec4b 159 // - v1.x Standard Capacity
vpcola 0:a1734fe1ec4b 160 // - v2.x Standard Capacity
vpcola 0:a1734fe1ec4b 161 // - v2.x High Capacity
vpcola 0:a1734fe1ec4b 162 // - Not recognised as an SD Card
vpcola 0:a1734fe1ec4b 163 #define SDCARD_FAIL 0
vpcola 0:a1734fe1ec4b 164 #define SDCARD_V1 1
vpcola 0:a1734fe1ec4b 165 #define SDCARD_V2 2
vpcola 0:a1734fe1ec4b 166 #define SDCARD_V2HC 3
vpcola 0:a1734fe1ec4b 167
vpcola 0:a1734fe1ec4b 168 int SDBlockDevice::_initialise_card()
vpcola 0:a1734fe1ec4b 169 {
vpcola 0:a1734fe1ec4b 170 _dbg = SD_DBG;
vpcola 0:a1734fe1ec4b 171 // Set to SCK for initialisation, and clock card with cs = 1
vpcola 0:a1734fe1ec4b 172 _spi.lock();
vpcola 0:a1734fe1ec4b 173 _spi.frequency(_init_sck);
vpcola 0:a1734fe1ec4b 174 _cs = 1;
vpcola 0:a1734fe1ec4b 175 for (int i = 0; i < 16; i++) {
vpcola 0:a1734fe1ec4b 176 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 177 }
vpcola 0:a1734fe1ec4b 178 _spi.unlock();
vpcola 0:a1734fe1ec4b 179
vpcola 0:a1734fe1ec4b 180 // send CMD0, should return with all zeros except IDLE STATE set (bit 0)
vpcola 0:a1734fe1ec4b 181 if (_cmd(0, 0) != R1_IDLE_STATE) {
vpcola 0:a1734fe1ec4b 182 debug_if(_dbg, "No disk, or could not put SD card in to SPI idle state\n");
vpcola 0:a1734fe1ec4b 183 return SD_BLOCK_DEVICE_ERROR_NO_DEVICE;
vpcola 0:a1734fe1ec4b 184 }
vpcola 0:a1734fe1ec4b 185
vpcola 0:a1734fe1ec4b 186 // send CMD8 to determine whther it is ver 2.x
vpcola 0:a1734fe1ec4b 187 int r = _cmd8();
vpcola 0:a1734fe1ec4b 188 if (r == R1_IDLE_STATE) {
vpcola 0:a1734fe1ec4b 189 return _initialise_card_v2();
vpcola 0:a1734fe1ec4b 190 } else if (r == (R1_IDLE_STATE | R1_ILLEGAL_COMMAND)) {
vpcola 0:a1734fe1ec4b 191 return _initialise_card_v1();
vpcola 0:a1734fe1ec4b 192 } else {
vpcola 0:a1734fe1ec4b 193 debug_if(_dbg, "Not in idle state after sending CMD8 (not an SD card?)\n");
vpcola 0:a1734fe1ec4b 194 return BD_ERROR_DEVICE_ERROR;
vpcola 0:a1734fe1ec4b 195 }
vpcola 0:a1734fe1ec4b 196 }
vpcola 0:a1734fe1ec4b 197
vpcola 0:a1734fe1ec4b 198 int SDBlockDevice::_initialise_card_v1()
vpcola 0:a1734fe1ec4b 199 {
vpcola 0:a1734fe1ec4b 200 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
vpcola 0:a1734fe1ec4b 201 _cmd(55, 0);
vpcola 0:a1734fe1ec4b 202 if (_cmd(41, 0) == 0) {
vpcola 0:a1734fe1ec4b 203 _block_size = 512;
vpcola 0:a1734fe1ec4b 204 debug_if(_dbg, "\n\rInit: SEDCARD_V1\n\r");
vpcola 0:a1734fe1ec4b 205 return BD_ERROR_OK;
vpcola 0:a1734fe1ec4b 206 }
vpcola 0:a1734fe1ec4b 207 }
vpcola 0:a1734fe1ec4b 208
vpcola 0:a1734fe1ec4b 209 debug_if(_dbg, "Timeout waiting for v1.x card\n");
vpcola 0:a1734fe1ec4b 210 return BD_ERROR_DEVICE_ERROR;
vpcola 0:a1734fe1ec4b 211 }
vpcola 0:a1734fe1ec4b 212
vpcola 0:a1734fe1ec4b 213 int SDBlockDevice::_initialise_card_v2()
vpcola 0:a1734fe1ec4b 214 {
vpcola 0:a1734fe1ec4b 215 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
vpcola 0:a1734fe1ec4b 216 wait_ms(50);
vpcola 0:a1734fe1ec4b 217 _cmd58();
vpcola 0:a1734fe1ec4b 218 _cmd(55, 0);
vpcola 0:a1734fe1ec4b 219 if (_cmd(41, 0x40000000) == 0) {
vpcola 0:a1734fe1ec4b 220 _cmd58();
vpcola 0:a1734fe1ec4b 221 debug_if(_dbg, "\n\rInit: SDCARD_V2\n\r");
vpcola 0:a1734fe1ec4b 222 _block_size = 1;
vpcola 0:a1734fe1ec4b 223 return BD_ERROR_OK;
vpcola 0:a1734fe1ec4b 224 }
vpcola 0:a1734fe1ec4b 225 }
vpcola 0:a1734fe1ec4b 226
vpcola 0:a1734fe1ec4b 227 debug_if(_dbg, "Timeout waiting for v2.x card\n");
vpcola 0:a1734fe1ec4b 228 return BD_ERROR_DEVICE_ERROR;
vpcola 0:a1734fe1ec4b 229 }
vpcola 0:a1734fe1ec4b 230
vpcola 0:a1734fe1ec4b 231 int SDBlockDevice::init()
vpcola 0:a1734fe1ec4b 232 {
vpcola 0:a1734fe1ec4b 233 _lock.lock();
vpcola 0:a1734fe1ec4b 234 int err = _initialise_card();
vpcola 0:a1734fe1ec4b 235 _is_initialized = (err == BD_ERROR_OK);
vpcola 0:a1734fe1ec4b 236 if (!_is_initialized) {
vpcola 0:a1734fe1ec4b 237 debug_if(_dbg, "Fail to initialize card\n");
vpcola 0:a1734fe1ec4b 238 _lock.unlock();
vpcola 0:a1734fe1ec4b 239 return err;
vpcola 0:a1734fe1ec4b 240 }
vpcola 0:a1734fe1ec4b 241 debug_if(_dbg, "init card = %d\n", _is_initialized);
vpcola 0:a1734fe1ec4b 242 _sectors = _sd_sectors();
vpcola 0:a1734fe1ec4b 243
vpcola 0:a1734fe1ec4b 244 // Set block length to 512 (CMD16)
vpcola 0:a1734fe1ec4b 245 if (_cmd(16, 512) != 0) {
vpcola 0:a1734fe1ec4b 246 debug_if(_dbg, "Set 512-byte block timed out\n");
vpcola 0:a1734fe1ec4b 247 _lock.unlock();
vpcola 0:a1734fe1ec4b 248 return BD_ERROR_DEVICE_ERROR;
vpcola 0:a1734fe1ec4b 249 }
vpcola 0:a1734fe1ec4b 250
vpcola 0:a1734fe1ec4b 251 // Set SCK for data transfer
vpcola 0:a1734fe1ec4b 252 _spi.frequency(_transfer_sck);
vpcola 0:a1734fe1ec4b 253 _lock.unlock();
vpcola 0:a1734fe1ec4b 254 return BD_ERROR_OK;
vpcola 0:a1734fe1ec4b 255 }
vpcola 0:a1734fe1ec4b 256
vpcola 0:a1734fe1ec4b 257 int SDBlockDevice::deinit()
vpcola 0:a1734fe1ec4b 258 {
vpcola 0:a1734fe1ec4b 259 return 0;
vpcola 0:a1734fe1ec4b 260 }
vpcola 0:a1734fe1ec4b 261
vpcola 0:a1734fe1ec4b 262 int SDBlockDevice::program(const void *b, bd_addr_t addr, bd_size_t size)
vpcola 0:a1734fe1ec4b 263 {
vpcola 0:a1734fe1ec4b 264 if (!is_valid_program(addr, size)) {
vpcola 0:a1734fe1ec4b 265 return SD_BLOCK_DEVICE_ERROR_PARAMETER;
vpcola 0:a1734fe1ec4b 266 }
vpcola 0:a1734fe1ec4b 267
vpcola 0:a1734fe1ec4b 268 _lock.lock();
vpcola 0:a1734fe1ec4b 269 if (!_is_initialized) {
vpcola 0:a1734fe1ec4b 270 _lock.unlock();
vpcola 0:a1734fe1ec4b 271 return SD_BLOCK_DEVICE_ERROR_NO_INIT;
vpcola 0:a1734fe1ec4b 272 }
vpcola 0:a1734fe1ec4b 273
vpcola 0:a1734fe1ec4b 274 const uint8_t *buffer = static_cast<const uint8_t*>(b);
vpcola 0:a1734fe1ec4b 275 while (size > 0) {
vpcola 0:a1734fe1ec4b 276 bd_addr_t block = addr / 512;
vpcola 0:a1734fe1ec4b 277 // set write address for single block (CMD24)
vpcola 0:a1734fe1ec4b 278 if (_cmd(24, block * _block_size) != 0) {
vpcola 0:a1734fe1ec4b 279 _lock.unlock();
vpcola 0:a1734fe1ec4b 280 return BD_ERROR_DEVICE_ERROR;
vpcola 0:a1734fe1ec4b 281 }
vpcola 0:a1734fe1ec4b 282
vpcola 0:a1734fe1ec4b 283 // send the data block
vpcola 0:a1734fe1ec4b 284 _write(buffer, 512);
vpcola 0:a1734fe1ec4b 285 buffer += 512;
vpcola 0:a1734fe1ec4b 286 addr += 512;
vpcola 0:a1734fe1ec4b 287 size -= 512;
vpcola 0:a1734fe1ec4b 288 }
vpcola 0:a1734fe1ec4b 289 _lock.unlock();
vpcola 0:a1734fe1ec4b 290 return 0;
vpcola 0:a1734fe1ec4b 291 }
vpcola 0:a1734fe1ec4b 292
vpcola 0:a1734fe1ec4b 293 int SDBlockDevice::read(void *b, bd_addr_t addr, bd_size_t size)
vpcola 0:a1734fe1ec4b 294 {
vpcola 0:a1734fe1ec4b 295 if (!is_valid_read(addr, size)) {
vpcola 0:a1734fe1ec4b 296 return SD_BLOCK_DEVICE_ERROR_PARAMETER;
vpcola 0:a1734fe1ec4b 297 }
vpcola 0:a1734fe1ec4b 298
vpcola 0:a1734fe1ec4b 299 _lock.lock();
vpcola 0:a1734fe1ec4b 300 if (!_is_initialized) {
vpcola 0:a1734fe1ec4b 301 _lock.unlock();
vpcola 0:a1734fe1ec4b 302 return SD_BLOCK_DEVICE_ERROR_PARAMETER;
vpcola 0:a1734fe1ec4b 303 }
vpcola 0:a1734fe1ec4b 304
vpcola 0:a1734fe1ec4b 305 uint8_t *buffer = static_cast<uint8_t *>(b);
vpcola 0:a1734fe1ec4b 306 while (size > 0) {
vpcola 0:a1734fe1ec4b 307 bd_addr_t block = addr / 512;
vpcola 0:a1734fe1ec4b 308 // set read address for single block (CMD17)
vpcola 0:a1734fe1ec4b 309 if (_cmd(17, block * _block_size) != 0) {
vpcola 0:a1734fe1ec4b 310 _lock.unlock();
vpcola 0:a1734fe1ec4b 311 return BD_ERROR_DEVICE_ERROR;
vpcola 0:a1734fe1ec4b 312 }
vpcola 0:a1734fe1ec4b 313
vpcola 0:a1734fe1ec4b 314 // receive the data
vpcola 0:a1734fe1ec4b 315 _read(buffer, 512);
vpcola 0:a1734fe1ec4b 316 buffer += 512;
vpcola 0:a1734fe1ec4b 317 addr += 512;
vpcola 0:a1734fe1ec4b 318 size -= 512;
vpcola 0:a1734fe1ec4b 319 }
vpcola 0:a1734fe1ec4b 320 _lock.unlock();
vpcola 0:a1734fe1ec4b 321 return 0;
vpcola 0:a1734fe1ec4b 322 }
vpcola 0:a1734fe1ec4b 323
vpcola 0:a1734fe1ec4b 324 int SDBlockDevice::erase(bd_addr_t addr, bd_size_t size)
vpcola 0:a1734fe1ec4b 325 {
vpcola 0:a1734fe1ec4b 326 return 0;
vpcola 0:a1734fe1ec4b 327 }
vpcola 0:a1734fe1ec4b 328
vpcola 0:a1734fe1ec4b 329 bd_size_t SDBlockDevice::get_read_size() const
vpcola 0:a1734fe1ec4b 330 {
vpcola 0:a1734fe1ec4b 331 return 512;
vpcola 0:a1734fe1ec4b 332 }
vpcola 0:a1734fe1ec4b 333
vpcola 0:a1734fe1ec4b 334 bd_size_t SDBlockDevice::get_program_size() const
vpcola 0:a1734fe1ec4b 335 {
vpcola 0:a1734fe1ec4b 336 return 512;
vpcola 0:a1734fe1ec4b 337 }
vpcola 0:a1734fe1ec4b 338
vpcola 0:a1734fe1ec4b 339 bd_size_t SDBlockDevice::get_erase_size() const
vpcola 0:a1734fe1ec4b 340 {
vpcola 0:a1734fe1ec4b 341 return 512;
vpcola 0:a1734fe1ec4b 342 }
vpcola 0:a1734fe1ec4b 343
vpcola 0:a1734fe1ec4b 344 bd_size_t SDBlockDevice::size() const
vpcola 0:a1734fe1ec4b 345 {
vpcola 0:a1734fe1ec4b 346 bd_size_t sectors = 0;
vpcola 0:a1734fe1ec4b 347 if(_is_initialized) {
vpcola 0:a1734fe1ec4b 348 sectors = _sectors;
vpcola 0:a1734fe1ec4b 349 }
vpcola 0:a1734fe1ec4b 350 return 512*sectors;
vpcola 0:a1734fe1ec4b 351 }
vpcola 0:a1734fe1ec4b 352
vpcola 0:a1734fe1ec4b 353 void SDBlockDevice::debug(bool dbg)
vpcola 0:a1734fe1ec4b 354 {
vpcola 0:a1734fe1ec4b 355 _dbg = dbg;
vpcola 0:a1734fe1ec4b 356 }
vpcola 0:a1734fe1ec4b 357
vpcola 0:a1734fe1ec4b 358
vpcola 0:a1734fe1ec4b 359 // PRIVATE FUNCTIONS
vpcola 0:a1734fe1ec4b 360 int SDBlockDevice::_cmd(int cmd, int arg) {
vpcola 0:a1734fe1ec4b 361 _spi.lock();
vpcola 0:a1734fe1ec4b 362 _cs = 0;
vpcola 0:a1734fe1ec4b 363
vpcola 0:a1734fe1ec4b 364 // send a command
vpcola 0:a1734fe1ec4b 365 _spi.write(0x40 | cmd);
vpcola 0:a1734fe1ec4b 366 _spi.write(arg >> 24);
vpcola 0:a1734fe1ec4b 367 _spi.write(arg >> 16);
vpcola 0:a1734fe1ec4b 368 _spi.write(arg >> 8);
vpcola 0:a1734fe1ec4b 369 _spi.write(arg >> 0);
vpcola 0:a1734fe1ec4b 370 _spi.write(0x95);
vpcola 0:a1734fe1ec4b 371
vpcola 0:a1734fe1ec4b 372 // wait for the repsonse (response[7] == 0)
vpcola 0:a1734fe1ec4b 373 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
vpcola 0:a1734fe1ec4b 374 int response = _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 375 if (!(response & 0x80)) {
vpcola 0:a1734fe1ec4b 376 _cs = 1;
vpcola 0:a1734fe1ec4b 377 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 378 _spi.unlock();
vpcola 0:a1734fe1ec4b 379 return response;
vpcola 0:a1734fe1ec4b 380 }
vpcola 0:a1734fe1ec4b 381 }
vpcola 0:a1734fe1ec4b 382 _cs = 1;
vpcola 0:a1734fe1ec4b 383 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 384 _spi.unlock();
vpcola 0:a1734fe1ec4b 385 return -1; // timeout
vpcola 0:a1734fe1ec4b 386 }
vpcola 0:a1734fe1ec4b 387 int SDBlockDevice::_cmdx(int cmd, int arg) {
vpcola 0:a1734fe1ec4b 388 _spi.lock();
vpcola 0:a1734fe1ec4b 389 _cs = 0;
vpcola 0:a1734fe1ec4b 390
vpcola 0:a1734fe1ec4b 391 // send a command
vpcola 0:a1734fe1ec4b 392 _spi.write(0x40 | cmd);
vpcola 0:a1734fe1ec4b 393 _spi.write(arg >> 24);
vpcola 0:a1734fe1ec4b 394 _spi.write(arg >> 16);
vpcola 0:a1734fe1ec4b 395 _spi.write(arg >> 8);
vpcola 0:a1734fe1ec4b 396 _spi.write(arg >> 0);
vpcola 0:a1734fe1ec4b 397 _spi.write(0x95);
vpcola 0:a1734fe1ec4b 398
vpcola 0:a1734fe1ec4b 399 // wait for the repsonse (response[7] == 0)
vpcola 0:a1734fe1ec4b 400 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
vpcola 0:a1734fe1ec4b 401 int response = _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 402 if (!(response & 0x80)) {
vpcola 0:a1734fe1ec4b 403 _cs = 1;
vpcola 0:a1734fe1ec4b 404 _spi.unlock();
vpcola 0:a1734fe1ec4b 405 return response;
vpcola 0:a1734fe1ec4b 406 }
vpcola 0:a1734fe1ec4b 407 }
vpcola 0:a1734fe1ec4b 408 _cs = 1;
vpcola 0:a1734fe1ec4b 409 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 410 _spi.unlock();
vpcola 0:a1734fe1ec4b 411 return -1; // timeout
vpcola 0:a1734fe1ec4b 412 }
vpcola 0:a1734fe1ec4b 413
vpcola 0:a1734fe1ec4b 414
vpcola 0:a1734fe1ec4b 415 int SDBlockDevice::_cmd58() {
vpcola 0:a1734fe1ec4b 416 _spi.lock();
vpcola 0:a1734fe1ec4b 417 _cs = 0;
vpcola 0:a1734fe1ec4b 418 int arg = 0;
vpcola 0:a1734fe1ec4b 419
vpcola 0:a1734fe1ec4b 420 // send a command
vpcola 0:a1734fe1ec4b 421 _spi.write(0x40 | 58);
vpcola 0:a1734fe1ec4b 422 _spi.write(arg >> 24);
vpcola 0:a1734fe1ec4b 423 _spi.write(arg >> 16);
vpcola 0:a1734fe1ec4b 424 _spi.write(arg >> 8);
vpcola 0:a1734fe1ec4b 425 _spi.write(arg >> 0);
vpcola 0:a1734fe1ec4b 426 _spi.write(0x95);
vpcola 0:a1734fe1ec4b 427
vpcola 0:a1734fe1ec4b 428 // wait for the repsonse (response[7] == 0)
vpcola 0:a1734fe1ec4b 429 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
vpcola 0:a1734fe1ec4b 430 int response = _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 431 if (!(response & 0x80)) {
vpcola 0:a1734fe1ec4b 432 int ocr = _spi.write(0xFF) << 24;
vpcola 0:a1734fe1ec4b 433 ocr |= _spi.write(0xFF) << 16;
vpcola 0:a1734fe1ec4b 434 ocr |= _spi.write(0xFF) << 8;
vpcola 0:a1734fe1ec4b 435 ocr |= _spi.write(0xFF) << 0;
vpcola 0:a1734fe1ec4b 436 _cs = 1;
vpcola 0:a1734fe1ec4b 437 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 438 _spi.unlock();
vpcola 0:a1734fe1ec4b 439 return response;
vpcola 0:a1734fe1ec4b 440 }
vpcola 0:a1734fe1ec4b 441 }
vpcola 0:a1734fe1ec4b 442 _cs = 1;
vpcola 0:a1734fe1ec4b 443 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 444 _spi.unlock();
vpcola 0:a1734fe1ec4b 445 return -1; // timeout
vpcola 0:a1734fe1ec4b 446 }
vpcola 0:a1734fe1ec4b 447
vpcola 0:a1734fe1ec4b 448 int SDBlockDevice::_cmd8() {
vpcola 0:a1734fe1ec4b 449 _spi.lock();
vpcola 0:a1734fe1ec4b 450 _cs = 0;
vpcola 0:a1734fe1ec4b 451
vpcola 0:a1734fe1ec4b 452 // send a command
vpcola 0:a1734fe1ec4b 453 _spi.write(0x40 | 8); // CMD8
vpcola 0:a1734fe1ec4b 454 _spi.write(0x00); // reserved
vpcola 0:a1734fe1ec4b 455 _spi.write(0x00); // reserved
vpcola 0:a1734fe1ec4b 456 _spi.write(0x01); // 3.3v
vpcola 0:a1734fe1ec4b 457 _spi.write(0xAA); // check pattern
vpcola 0:a1734fe1ec4b 458 _spi.write(0x87); // crc
vpcola 0:a1734fe1ec4b 459
vpcola 0:a1734fe1ec4b 460 // wait for the repsonse (response[7] == 0)
vpcola 0:a1734fe1ec4b 461 for (int i = 0; i < SD_COMMAND_TIMEOUT * 1000; i++) {
vpcola 0:a1734fe1ec4b 462 char response[5];
vpcola 0:a1734fe1ec4b 463 response[0] = _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 464 if (!(response[0] & 0x80)) {
vpcola 0:a1734fe1ec4b 465 for (int j = 1; j < 5; j++) {
vpcola 0:a1734fe1ec4b 466 response[i] = _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 467 }
vpcola 0:a1734fe1ec4b 468 _cs = 1;
vpcola 0:a1734fe1ec4b 469 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 470 _spi.unlock();
vpcola 0:a1734fe1ec4b 471 return response[0];
vpcola 0:a1734fe1ec4b 472 }
vpcola 0:a1734fe1ec4b 473 }
vpcola 0:a1734fe1ec4b 474 _cs = 1;
vpcola 0:a1734fe1ec4b 475 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 476 _spi.unlock();
vpcola 0:a1734fe1ec4b 477 return -1; // timeout
vpcola 0:a1734fe1ec4b 478 }
vpcola 0:a1734fe1ec4b 479
vpcola 0:a1734fe1ec4b 480 int SDBlockDevice::_read(uint8_t *buffer, uint32_t length) {
vpcola 0:a1734fe1ec4b 481 _spi.lock();
vpcola 0:a1734fe1ec4b 482 _cs = 0;
vpcola 0:a1734fe1ec4b 483
vpcola 0:a1734fe1ec4b 484 // read until start byte (0xFF)
vpcola 0:a1734fe1ec4b 485 while (_spi.write(0xFF) != 0xFE);
vpcola 0:a1734fe1ec4b 486
vpcola 0:a1734fe1ec4b 487 // read data
vpcola 0:a1734fe1ec4b 488 for (uint32_t i = 0; i < length; i++) {
vpcola 0:a1734fe1ec4b 489 buffer[i] = _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 490 }
vpcola 0:a1734fe1ec4b 491 _spi.write(0xFF); // checksum
vpcola 0:a1734fe1ec4b 492 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 493
vpcola 0:a1734fe1ec4b 494 _cs = 1;
vpcola 0:a1734fe1ec4b 495 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 496 _spi.unlock();
vpcola 0:a1734fe1ec4b 497 return 0;
vpcola 0:a1734fe1ec4b 498 }
vpcola 0:a1734fe1ec4b 499
vpcola 0:a1734fe1ec4b 500 int SDBlockDevice::_write(const uint8_t*buffer, uint32_t length) {
vpcola 0:a1734fe1ec4b 501 _spi.lock();
vpcola 0:a1734fe1ec4b 502 _cs = 0;
vpcola 0:a1734fe1ec4b 503
vpcola 0:a1734fe1ec4b 504 // indicate start of block
vpcola 0:a1734fe1ec4b 505 _spi.write(0xFE);
vpcola 0:a1734fe1ec4b 506
vpcola 0:a1734fe1ec4b 507 // write the data
vpcola 0:a1734fe1ec4b 508 for (uint32_t i = 0; i < length; i++) {
vpcola 0:a1734fe1ec4b 509 _spi.write(buffer[i]);
vpcola 0:a1734fe1ec4b 510 }
vpcola 0:a1734fe1ec4b 511
vpcola 0:a1734fe1ec4b 512 // write the checksum
vpcola 0:a1734fe1ec4b 513 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 514 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 515
vpcola 0:a1734fe1ec4b 516 // check the response token
vpcola 0:a1734fe1ec4b 517 if ((_spi.write(0xFF) & 0x1F) != 0x05) {
vpcola 0:a1734fe1ec4b 518 _cs = 1;
vpcola 0:a1734fe1ec4b 519 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 520 _spi.unlock();
vpcola 0:a1734fe1ec4b 521 return 1;
vpcola 0:a1734fe1ec4b 522 }
vpcola 0:a1734fe1ec4b 523
vpcola 0:a1734fe1ec4b 524 // wait for write to finish
vpcola 0:a1734fe1ec4b 525 while (_spi.write(0xFF) == 0);
vpcola 0:a1734fe1ec4b 526
vpcola 0:a1734fe1ec4b 527 _cs = 1;
vpcola 0:a1734fe1ec4b 528 _spi.write(0xFF);
vpcola 0:a1734fe1ec4b 529 _spi.unlock();
vpcola 0:a1734fe1ec4b 530 return 0;
vpcola 0:a1734fe1ec4b 531 }
vpcola 0:a1734fe1ec4b 532
vpcola 0:a1734fe1ec4b 533 static uint32_t ext_bits(unsigned char *data, int msb, int lsb) {
vpcola 0:a1734fe1ec4b 534 uint32_t bits = 0;
vpcola 0:a1734fe1ec4b 535 uint32_t size = 1 + msb - lsb;
vpcola 0:a1734fe1ec4b 536 for (uint32_t i = 0; i < size; i++) {
vpcola 0:a1734fe1ec4b 537 uint32_t position = lsb + i;
vpcola 0:a1734fe1ec4b 538 uint32_t byte = 15 - (position >> 3);
vpcola 0:a1734fe1ec4b 539 uint32_t bit = position & 0x7;
vpcola 0:a1734fe1ec4b 540 uint32_t value = (data[byte] >> bit) & 1;
vpcola 0:a1734fe1ec4b 541 bits |= value << i;
vpcola 0:a1734fe1ec4b 542 }
vpcola 0:a1734fe1ec4b 543 return bits;
vpcola 0:a1734fe1ec4b 544 }
vpcola 0:a1734fe1ec4b 545
vpcola 0:a1734fe1ec4b 546 uint32_t SDBlockDevice::_sd_sectors() {
vpcola 0:a1734fe1ec4b 547 uint32_t c_size, c_size_mult, read_bl_len;
vpcola 0:a1734fe1ec4b 548 uint32_t block_len, mult, blocknr, capacity;
vpcola 0:a1734fe1ec4b 549 uint32_t hc_c_size;
vpcola 0:a1734fe1ec4b 550 uint32_t blocks;
vpcola 0:a1734fe1ec4b 551
vpcola 0:a1734fe1ec4b 552 // CMD9, Response R2 (R1 byte + 16-byte block read)
vpcola 0:a1734fe1ec4b 553 if (_cmdx(9, 0) != 0) {
vpcola 0:a1734fe1ec4b 554 debug_if(_dbg, "Didn't get a response from the disk\n");
vpcola 0:a1734fe1ec4b 555 return 0;
vpcola 0:a1734fe1ec4b 556 }
vpcola 0:a1734fe1ec4b 557
vpcola 0:a1734fe1ec4b 558 uint8_t csd[16];
vpcola 0:a1734fe1ec4b 559 if (_read(csd, 16) != 0) {
vpcola 0:a1734fe1ec4b 560 debug_if(_dbg, "Couldn't read csd response from disk\n");
vpcola 0:a1734fe1ec4b 561 return 0;
vpcola 0:a1734fe1ec4b 562 }
vpcola 0:a1734fe1ec4b 563
vpcola 0:a1734fe1ec4b 564 // csd_structure : csd[127:126]
vpcola 0:a1734fe1ec4b 565 // c_size : csd[73:62]
vpcola 0:a1734fe1ec4b 566 // c_size_mult : csd[49:47]
vpcola 0:a1734fe1ec4b 567 // read_bl_len : csd[83:80] - the *maximum* read block length
vpcola 0:a1734fe1ec4b 568
vpcola 0:a1734fe1ec4b 569 int csd_structure = ext_bits(csd, 127, 126);
vpcola 0:a1734fe1ec4b 570
vpcola 0:a1734fe1ec4b 571 switch (csd_structure) {
vpcola 0:a1734fe1ec4b 572 case 0:
vpcola 0:a1734fe1ec4b 573 _block_size = 512;
vpcola 0:a1734fe1ec4b 574 c_size = ext_bits(csd, 73, 62);
vpcola 0:a1734fe1ec4b 575 c_size_mult = ext_bits(csd, 49, 47);
vpcola 0:a1734fe1ec4b 576 read_bl_len = ext_bits(csd, 83, 80);
vpcola 0:a1734fe1ec4b 577
vpcola 0:a1734fe1ec4b 578 block_len = 1 << read_bl_len;
vpcola 0:a1734fe1ec4b 579 mult = 1 << (c_size_mult + 2);
vpcola 0:a1734fe1ec4b 580 blocknr = (c_size + 1) * mult;
vpcola 0:a1734fe1ec4b 581 capacity = blocknr * block_len;
vpcola 0:a1734fe1ec4b 582 blocks = capacity / 512;
vpcola 0:a1734fe1ec4b 583 debug_if(_dbg, "\n\rSDBlockDevice\n\rc_size: %d \n\rcapacity: %ld \n\rsectors: %lld\n\r", c_size, capacity, blocks);
vpcola 0:a1734fe1ec4b 584 break;
vpcola 0:a1734fe1ec4b 585
vpcola 0:a1734fe1ec4b 586 case 1:
vpcola 0:a1734fe1ec4b 587 _block_size = 1;
vpcola 0:a1734fe1ec4b 588 hc_c_size = ext_bits(csd, 63, 48);
vpcola 0:a1734fe1ec4b 589 blocks = (hc_c_size+1)*1024;
vpcola 0:a1734fe1ec4b 590 debug_if(_dbg, "\n\rSDHC Card \n\rhc_c_size: %d\n\rcapacity: %lld \n\rsectors: %lld\n\r", hc_c_size, blocks*512, blocks);
vpcola 0:a1734fe1ec4b 591 break;
vpcola 0:a1734fe1ec4b 592
vpcola 0:a1734fe1ec4b 593 default:
vpcola 0:a1734fe1ec4b 594 debug_if(_dbg, "CSD struct unsupported\r\n");
vpcola 0:a1734fe1ec4b 595 return 0;
vpcola 0:a1734fe1ec4b 596 };
vpcola 0:a1734fe1ec4b 597 return blocks;
vpcola 0:a1734fe1ec4b 598 }
vpcola 0:a1734fe1ec4b 599
vpcola 0:a1734fe1ec4b 600 #endif /* DEVICE_SPI */