Vergil Cola / Mbed OS MQTTGateway2

Fork of my original MQTTGateway

Dependencies:   mbed-http

easy-connect/mcr20a-rf-driver/source/MCR20Drv.c@0:a1734fe1ec4b, 2017-04-08 (annotated)

Committer:
vpcola
Date:
Sat Apr 08 14:43:14 2017 +0000
Revision:
0:a1734fe1ec4b
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vpcola 0:a1734fe1ec4b 1 /*!
vpcola 0:a1734fe1ec4b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
vpcola 0:a1734fe1ec4b 3 * All rights reserved.
vpcola 0:a1734fe1ec4b 4 *
vpcola 0:a1734fe1ec4b 5 * \file MCR20Drv.c
vpcola 0:a1734fe1ec4b 6 *
vpcola 0:a1734fe1ec4b 7 * Redistribution and use in source and binary forms, with or without modification,
vpcola 0:a1734fe1ec4b 8 * are permitted provided that the following conditions are met:
vpcola 0:a1734fe1ec4b 9 *
vpcola 0:a1734fe1ec4b 10 * o Redistributions of source code must retain the above copyright notice, this list
vpcola 0:a1734fe1ec4b 11 * of conditions and the following disclaimer.
vpcola 0:a1734fe1ec4b 12 *
vpcola 0:a1734fe1ec4b 13 * o Redistributions in binary form must reproduce the above copyright notice, this
vpcola 0:a1734fe1ec4b 14 * list of conditions and the following disclaimer in the documentation and/or
vpcola 0:a1734fe1ec4b 15 * other materials provided with the distribution.
vpcola 0:a1734fe1ec4b 16 *
vpcola 0:a1734fe1ec4b 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
vpcola 0:a1734fe1ec4b 18 * contributors may be used to endorse or promote products derived from this
vpcola 0:a1734fe1ec4b 19 * software without specific prior written permission.
vpcola 0:a1734fe1ec4b 20 *
vpcola 0:a1734fe1ec4b 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
vpcola 0:a1734fe1ec4b 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
vpcola 0:a1734fe1ec4b 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vpcola 0:a1734fe1ec4b 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
vpcola 0:a1734fe1ec4b 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
vpcola 0:a1734fe1ec4b 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
vpcola 0:a1734fe1ec4b 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
vpcola 0:a1734fe1ec4b 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
vpcola 0:a1734fe1ec4b 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
vpcola 0:a1734fe1ec4b 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vpcola 0:a1734fe1ec4b 31 */
vpcola 0:a1734fe1ec4b 32
vpcola 0:a1734fe1ec4b 33
vpcola 0:a1734fe1ec4b 34 /*****************************************************************************
vpcola 0:a1734fe1ec4b 35 * INCLUDED HEADERS *
vpcola 0:a1734fe1ec4b 36 *---------------------------------------------------------------------------*
vpcola 0:a1734fe1ec4b 37 * Add to this section all the headers that this module needs to include. *
vpcola 0:a1734fe1ec4b 38 *---------------------------------------------------------------------------*
vpcola 0:a1734fe1ec4b 39 *****************************************************************************/
vpcola 0:a1734fe1ec4b 40
vpcola 0:a1734fe1ec4b 41 #include "platform/arm_hal_interrupt.h"
vpcola 0:a1734fe1ec4b 42 #include "MCR20Drv.h"
vpcola 0:a1734fe1ec4b 43 #include "MCR20Reg.h"
vpcola 0:a1734fe1ec4b 44 #include "XcvrSpi.h"
vpcola 0:a1734fe1ec4b 45
vpcola 0:a1734fe1ec4b 46
vpcola 0:a1734fe1ec4b 47 /*****************************************************************************
vpcola 0:a1734fe1ec4b 48 * PRIVATE VARIABLES *
vpcola 0:a1734fe1ec4b 49 *---------------------------------------------------------------------------*
vpcola 0:a1734fe1ec4b 50 * Add to this section all the variables and constants that have local *
vpcola 0:a1734fe1ec4b 51 * (file) scope. *
vpcola 0:a1734fe1ec4b 52 * Each of this declarations shall be preceded by the 'static' keyword. *
vpcola 0:a1734fe1ec4b 53 * These variables / constants cannot be accessed outside this module. *
vpcola 0:a1734fe1ec4b 54 *---------------------------------------------------------------------------*
vpcola 0:a1734fe1ec4b 55 *****************************************************************************/
vpcola 0:a1734fe1ec4b 56 uint32_t mPhyIrqDisableCnt = 1;
vpcola 0:a1734fe1ec4b 57
vpcola 0:a1734fe1ec4b 58 /*****************************************************************************
vpcola 0:a1734fe1ec4b 59 * PUBLIC VARIABLES *
vpcola 0:a1734fe1ec4b 60 *---------------------------------------------------------------------------*
vpcola 0:a1734fe1ec4b 61 * Add to this section all the variables and constants that have global *
vpcola 0:a1734fe1ec4b 62 * (project) scope. *
vpcola 0:a1734fe1ec4b 63 * These variables / constants can be accessed outside this module. *
vpcola 0:a1734fe1ec4b 64 * These variables / constants shall be preceded by the 'extern' keyword in *
vpcola 0:a1734fe1ec4b 65 * the interface header. *
vpcola 0:a1734fe1ec4b 66 *---------------------------------------------------------------------------*
vpcola 0:a1734fe1ec4b 67 *****************************************************************************/
vpcola 0:a1734fe1ec4b 68
vpcola 0:a1734fe1ec4b 69 /*****************************************************************************
vpcola 0:a1734fe1ec4b 70 * PRIVATE FUNCTIONS PROTOTYPES *
vpcola 0:a1734fe1ec4b 71 *---------------------------------------------------------------------------*
vpcola 0:a1734fe1ec4b 72 * Add to this section all the functions prototypes that have local (file) *
vpcola 0:a1734fe1ec4b 73 * scope. *
vpcola 0:a1734fe1ec4b 74 * These functions cannot be accessed outside this module. *
vpcola 0:a1734fe1ec4b 75 * These declarations shall be preceded by the 'static' keyword. *
vpcola 0:a1734fe1ec4b 76 *---------------------------------------------------------------------------*
vpcola 0:a1734fe1ec4b 77 *****************************************************************************/
vpcola 0:a1734fe1ec4b 78
vpcola 0:a1734fe1ec4b 79 /*****************************************************************************
vpcola 0:a1734fe1ec4b 80 * PRIVATE FUNCTIONS *
vpcola 0:a1734fe1ec4b 81 *---------------------------------------------------------------------------*
vpcola 0:a1734fe1ec4b 82 * Add to this section all the functions that have local (file) scope. *
vpcola 0:a1734fe1ec4b 83 * These functions cannot be accessed outside this module. *
vpcola 0:a1734fe1ec4b 84 * These definitions shall be preceded by the 'static' keyword. *
vpcola 0:a1734fe1ec4b 85 *---------------------------------------------------------------------------*
vpcola 0:a1734fe1ec4b 86 *****************************************************************************/
vpcola 0:a1734fe1ec4b 87
vpcola 0:a1734fe1ec4b 88
vpcola 0:a1734fe1ec4b 89 /*****************************************************************************
vpcola 0:a1734fe1ec4b 90 * PUBLIC FUNCTIONS *
vpcola 0:a1734fe1ec4b 91 *---------------------------------------------------------------------------*
vpcola 0:a1734fe1ec4b 92 * Add to this section all the functions that have global (project) scope. *
vpcola 0:a1734fe1ec4b 93 * These functions can be accessed outside this module. *
vpcola 0:a1734fe1ec4b 94 * These functions shall have their declarations (prototypes) within the *
vpcola 0:a1734fe1ec4b 95 * interface header file and shall be preceded by the 'extern' keyword. *
vpcola 0:a1734fe1ec4b 96 *---------------------------------------------------------------------------*
vpcola 0:a1734fe1ec4b 97 *****************************************************************************/
vpcola 0:a1734fe1ec4b 98
vpcola 0:a1734fe1ec4b 99 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 100 * Name: MCR20Drv_Init
vpcola 0:a1734fe1ec4b 101 * Description: -
vpcola 0:a1734fe1ec4b 102 * Parameters: -
vpcola 0:a1734fe1ec4b 103 * Return: -
vpcola 0:a1734fe1ec4b 104 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 105 void MCR20Drv_Init
vpcola 0:a1734fe1ec4b 106 (
vpcola 0:a1734fe1ec4b 107 void
vpcola 0:a1734fe1ec4b 108 )
vpcola 0:a1734fe1ec4b 109 {
vpcola 0:a1734fe1ec4b 110 xcvr_spi_init(gXcvrSpiInstance_c);
vpcola 0:a1734fe1ec4b 111 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
vpcola 0:a1734fe1ec4b 112
vpcola 0:a1734fe1ec4b 113 gXcvrDeassertCS_d();
vpcola 0:a1734fe1ec4b 114 MCR20Drv_RST_B_Deassert();
vpcola 0:a1734fe1ec4b 115 RF_IRQ_Init();
vpcola 0:a1734fe1ec4b 116 RF_IRQ_Disable();
vpcola 0:a1734fe1ec4b 117 mPhyIrqDisableCnt = 1;
vpcola 0:a1734fe1ec4b 118 }
vpcola 0:a1734fe1ec4b 119
vpcola 0:a1734fe1ec4b 120 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 121 * Name: MCR20Drv_DirectAccessSPIWrite
vpcola 0:a1734fe1ec4b 122 * Description: -
vpcola 0:a1734fe1ec4b 123 * Parameters: -
vpcola 0:a1734fe1ec4b 124 * Return: -
vpcola 0:a1734fe1ec4b 125 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 126 void MCR20Drv_DirectAccessSPIWrite
vpcola 0:a1734fe1ec4b 127 (
vpcola 0:a1734fe1ec4b 128 uint8_t address,
vpcola 0:a1734fe1ec4b 129 uint8_t value
vpcola 0:a1734fe1ec4b 130 )
vpcola 0:a1734fe1ec4b 131 {
vpcola 0:a1734fe1ec4b 132 uint16_t txData;
vpcola 0:a1734fe1ec4b 133
vpcola 0:a1734fe1ec4b 134 ProtectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 135
vpcola 0:a1734fe1ec4b 136 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
vpcola 0:a1734fe1ec4b 137
vpcola 0:a1734fe1ec4b 138 gXcvrAssertCS_d();
vpcola 0:a1734fe1ec4b 139
vpcola 0:a1734fe1ec4b 140 txData = (address & TransceiverSPI_DirectRegisterAddressMask);
vpcola 0:a1734fe1ec4b 141 txData |= value << 8;
vpcola 0:a1734fe1ec4b 142
vpcola 0:a1734fe1ec4b 143 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, sizeof(txData));
vpcola 0:a1734fe1ec4b 144
vpcola 0:a1734fe1ec4b 145 gXcvrDeassertCS_d();
vpcola 0:a1734fe1ec4b 146 UnprotectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 147 }
vpcola 0:a1734fe1ec4b 148
vpcola 0:a1734fe1ec4b 149 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 150 * Name: MCR20Drv_DirectAccessSPIMultiByteWrite
vpcola 0:a1734fe1ec4b 151 * Description: -
vpcola 0:a1734fe1ec4b 152 * Parameters: -
vpcola 0:a1734fe1ec4b 153 * Return: -
vpcola 0:a1734fe1ec4b 154 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 155 void MCR20Drv_DirectAccessSPIMultiByteWrite
vpcola 0:a1734fe1ec4b 156 (
vpcola 0:a1734fe1ec4b 157 uint8_t startAddress,
vpcola 0:a1734fe1ec4b 158 uint8_t * byteArray,
vpcola 0:a1734fe1ec4b 159 uint8_t numOfBytes
vpcola 0:a1734fe1ec4b 160 )
vpcola 0:a1734fe1ec4b 161 {
vpcola 0:a1734fe1ec4b 162 uint8_t txData;
vpcola 0:a1734fe1ec4b 163
vpcola 0:a1734fe1ec4b 164 if( (numOfBytes == 0) || (byteArray == 0) )
vpcola 0:a1734fe1ec4b 165 {
vpcola 0:a1734fe1ec4b 166 return;
vpcola 0:a1734fe1ec4b 167 }
vpcola 0:a1734fe1ec4b 168
vpcola 0:a1734fe1ec4b 169 ProtectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 170
vpcola 0:a1734fe1ec4b 171 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
vpcola 0:a1734fe1ec4b 172
vpcola 0:a1734fe1ec4b 173 gXcvrAssertCS_d();
vpcola 0:a1734fe1ec4b 174
vpcola 0:a1734fe1ec4b 175 txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask);
vpcola 0:a1734fe1ec4b 176
vpcola 0:a1734fe1ec4b 177 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, sizeof(txData));
vpcola 0:a1734fe1ec4b 178 xcvr_spi_transfer(gXcvrSpiInstance_c, byteArray, 0, numOfBytes);
vpcola 0:a1734fe1ec4b 179
vpcola 0:a1734fe1ec4b 180 gXcvrDeassertCS_d();
vpcola 0:a1734fe1ec4b 181 UnprotectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 182 }
vpcola 0:a1734fe1ec4b 183
vpcola 0:a1734fe1ec4b 184 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 185 * Name: MCR20Drv_PB_SPIByteWrite
vpcola 0:a1734fe1ec4b 186 * Description: -
vpcola 0:a1734fe1ec4b 187 * Parameters: -
vpcola 0:a1734fe1ec4b 188 * Return: -
vpcola 0:a1734fe1ec4b 189 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 190 void MCR20Drv_PB_SPIByteWrite
vpcola 0:a1734fe1ec4b 191 (
vpcola 0:a1734fe1ec4b 192 uint8_t address,
vpcola 0:a1734fe1ec4b 193 uint8_t value
vpcola 0:a1734fe1ec4b 194 )
vpcola 0:a1734fe1ec4b 195 {
vpcola 0:a1734fe1ec4b 196 uint32_t txData;
vpcola 0:a1734fe1ec4b 197
vpcola 0:a1734fe1ec4b 198 ProtectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 199
vpcola 0:a1734fe1ec4b 200 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
vpcola 0:a1734fe1ec4b 201
vpcola 0:a1734fe1ec4b 202 gXcvrAssertCS_d();
vpcola 0:a1734fe1ec4b 203
vpcola 0:a1734fe1ec4b 204 txData = TransceiverSPI_WriteSelect |
vpcola 0:a1734fe1ec4b 205 TransceiverSPI_PacketBuffAccessSelect |
vpcola 0:a1734fe1ec4b 206 TransceiverSPI_PacketBuffByteModeSelect;
vpcola 0:a1734fe1ec4b 207 txData |= (address) << 8;
vpcola 0:a1734fe1ec4b 208 txData |= (value) << 16;
vpcola 0:a1734fe1ec4b 209
vpcola 0:a1734fe1ec4b 210 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3);
vpcola 0:a1734fe1ec4b 211
vpcola 0:a1734fe1ec4b 212 gXcvrDeassertCS_d();
vpcola 0:a1734fe1ec4b 213 UnprotectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 214 }
vpcola 0:a1734fe1ec4b 215
vpcola 0:a1734fe1ec4b 216 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 217 * Name: MCR20Drv_PB_SPIBurstWrite
vpcola 0:a1734fe1ec4b 218 * Description: -
vpcola 0:a1734fe1ec4b 219 * Parameters: -
vpcola 0:a1734fe1ec4b 220 * Return: -
vpcola 0:a1734fe1ec4b 221 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 222 void MCR20Drv_PB_SPIBurstWrite
vpcola 0:a1734fe1ec4b 223 (
vpcola 0:a1734fe1ec4b 224 uint8_t * byteArray,
vpcola 0:a1734fe1ec4b 225 uint8_t numOfBytes
vpcola 0:a1734fe1ec4b 226 )
vpcola 0:a1734fe1ec4b 227 {
vpcola 0:a1734fe1ec4b 228 uint8_t txData;
vpcola 0:a1734fe1ec4b 229
vpcola 0:a1734fe1ec4b 230 if( (numOfBytes == 0) || (byteArray == 0) )
vpcola 0:a1734fe1ec4b 231 {
vpcola 0:a1734fe1ec4b 232 return;
vpcola 0:a1734fe1ec4b 233 }
vpcola 0:a1734fe1ec4b 234
vpcola 0:a1734fe1ec4b 235 ProtectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 236
vpcola 0:a1734fe1ec4b 237 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
vpcola 0:a1734fe1ec4b 238
vpcola 0:a1734fe1ec4b 239 gXcvrAssertCS_d();
vpcola 0:a1734fe1ec4b 240
vpcola 0:a1734fe1ec4b 241 txData = TransceiverSPI_WriteSelect |
vpcola 0:a1734fe1ec4b 242 TransceiverSPI_PacketBuffAccessSelect |
vpcola 0:a1734fe1ec4b 243 TransceiverSPI_PacketBuffBurstModeSelect;
vpcola 0:a1734fe1ec4b 244
vpcola 0:a1734fe1ec4b 245 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, 1);
vpcola 0:a1734fe1ec4b 246 xcvr_spi_transfer(gXcvrSpiInstance_c, byteArray, 0, numOfBytes);
vpcola 0:a1734fe1ec4b 247
vpcola 0:a1734fe1ec4b 248 gXcvrDeassertCS_d();
vpcola 0:a1734fe1ec4b 249 UnprotectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 250 }
vpcola 0:a1734fe1ec4b 251
vpcola 0:a1734fe1ec4b 252 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 253 * Name: MCR20Drv_DirectAccessSPIRead
vpcola 0:a1734fe1ec4b 254 * Description: -
vpcola 0:a1734fe1ec4b 255 * Parameters: -
vpcola 0:a1734fe1ec4b 256 * Return: -
vpcola 0:a1734fe1ec4b 257 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 258
vpcola 0:a1734fe1ec4b 259 uint8_t MCR20Drv_DirectAccessSPIRead
vpcola 0:a1734fe1ec4b 260 (
vpcola 0:a1734fe1ec4b 261 uint8_t address
vpcola 0:a1734fe1ec4b 262 )
vpcola 0:a1734fe1ec4b 263 {
vpcola 0:a1734fe1ec4b 264 uint8_t txData;
vpcola 0:a1734fe1ec4b 265 uint8_t rxData;
vpcola 0:a1734fe1ec4b 266
vpcola 0:a1734fe1ec4b 267 ProtectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 268
vpcola 0:a1734fe1ec4b 269 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
vpcola 0:a1734fe1ec4b 270
vpcola 0:a1734fe1ec4b 271 gXcvrAssertCS_d();
vpcola 0:a1734fe1ec4b 272
vpcola 0:a1734fe1ec4b 273 txData = (address & TransceiverSPI_DirectRegisterAddressMask) |
vpcola 0:a1734fe1ec4b 274 TransceiverSPI_ReadSelect;
vpcola 0:a1734fe1ec4b 275
vpcola 0:a1734fe1ec4b 276 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, sizeof(txData));
vpcola 0:a1734fe1ec4b 277 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData));
vpcola 0:a1734fe1ec4b 278
vpcola 0:a1734fe1ec4b 279 gXcvrDeassertCS_d();
vpcola 0:a1734fe1ec4b 280 UnprotectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 281
vpcola 0:a1734fe1ec4b 282 return rxData;
vpcola 0:a1734fe1ec4b 283
vpcola 0:a1734fe1ec4b 284 }
vpcola 0:a1734fe1ec4b 285
vpcola 0:a1734fe1ec4b 286 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 287 * Name: MCR20Drv_DirectAccessSPIMultyByteRead
vpcola 0:a1734fe1ec4b 288 * Description: -
vpcola 0:a1734fe1ec4b 289 * Parameters: -
vpcola 0:a1734fe1ec4b 290 * Return: -
vpcola 0:a1734fe1ec4b 291 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 292 uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
vpcola 0:a1734fe1ec4b 293 (
vpcola 0:a1734fe1ec4b 294 uint8_t startAddress,
vpcola 0:a1734fe1ec4b 295 uint8_t * byteArray,
vpcola 0:a1734fe1ec4b 296 uint8_t numOfBytes
vpcola 0:a1734fe1ec4b 297 )
vpcola 0:a1734fe1ec4b 298 {
vpcola 0:a1734fe1ec4b 299 uint8_t txData;
vpcola 0:a1734fe1ec4b 300 uint8_t phyIRQSTS1;
vpcola 0:a1734fe1ec4b 301
vpcola 0:a1734fe1ec4b 302 if( (numOfBytes == 0) || (byteArray == 0) )
vpcola 0:a1734fe1ec4b 303 {
vpcola 0:a1734fe1ec4b 304 return 0;
vpcola 0:a1734fe1ec4b 305 }
vpcola 0:a1734fe1ec4b 306
vpcola 0:a1734fe1ec4b 307 ProtectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 308
vpcola 0:a1734fe1ec4b 309 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
vpcola 0:a1734fe1ec4b 310
vpcola 0:a1734fe1ec4b 311 gXcvrAssertCS_d();
vpcola 0:a1734fe1ec4b 312
vpcola 0:a1734fe1ec4b 313 txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask) |
vpcola 0:a1734fe1ec4b 314 TransceiverSPI_ReadSelect;
vpcola 0:a1734fe1ec4b 315
vpcola 0:a1734fe1ec4b 316 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
vpcola 0:a1734fe1ec4b 317 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
vpcola 0:a1734fe1ec4b 318
vpcola 0:a1734fe1ec4b 319 gXcvrDeassertCS_d();
vpcola 0:a1734fe1ec4b 320 UnprotectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 321
vpcola 0:a1734fe1ec4b 322 return phyIRQSTS1;
vpcola 0:a1734fe1ec4b 323 }
vpcola 0:a1734fe1ec4b 324
vpcola 0:a1734fe1ec4b 325 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 326 * Name: MCR20Drv_PB_SPIBurstRead
vpcola 0:a1734fe1ec4b 327 * Description: -
vpcola 0:a1734fe1ec4b 328 * Parameters: -
vpcola 0:a1734fe1ec4b 329 * Return: -
vpcola 0:a1734fe1ec4b 330 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 331 uint8_t MCR20Drv_PB_SPIBurstRead
vpcola 0:a1734fe1ec4b 332 (
vpcola 0:a1734fe1ec4b 333 uint8_t * byteArray,
vpcola 0:a1734fe1ec4b 334 uint8_t numOfBytes
vpcola 0:a1734fe1ec4b 335 )
vpcola 0:a1734fe1ec4b 336 {
vpcola 0:a1734fe1ec4b 337 uint8_t txData;
vpcola 0:a1734fe1ec4b 338 uint8_t phyIRQSTS1;
vpcola 0:a1734fe1ec4b 339
vpcola 0:a1734fe1ec4b 340 if( (numOfBytes == 0) || (byteArray == 0) )
vpcola 0:a1734fe1ec4b 341 {
vpcola 0:a1734fe1ec4b 342 return 0;
vpcola 0:a1734fe1ec4b 343 }
vpcola 0:a1734fe1ec4b 344
vpcola 0:a1734fe1ec4b 345 ProtectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 346
vpcola 0:a1734fe1ec4b 347 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
vpcola 0:a1734fe1ec4b 348
vpcola 0:a1734fe1ec4b 349 gXcvrAssertCS_d();
vpcola 0:a1734fe1ec4b 350
vpcola 0:a1734fe1ec4b 351 txData = TransceiverSPI_ReadSelect |
vpcola 0:a1734fe1ec4b 352 TransceiverSPI_PacketBuffAccessSelect |
vpcola 0:a1734fe1ec4b 353 TransceiverSPI_PacketBuffBurstModeSelect;
vpcola 0:a1734fe1ec4b 354
vpcola 0:a1734fe1ec4b 355 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
vpcola 0:a1734fe1ec4b 356 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
vpcola 0:a1734fe1ec4b 357
vpcola 0:a1734fe1ec4b 358 gXcvrDeassertCS_d();
vpcola 0:a1734fe1ec4b 359 UnprotectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 360
vpcola 0:a1734fe1ec4b 361 return phyIRQSTS1;
vpcola 0:a1734fe1ec4b 362 }
vpcola 0:a1734fe1ec4b 363
vpcola 0:a1734fe1ec4b 364 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 365 * Name: MCR20Drv_IndirectAccessSPIWrite
vpcola 0:a1734fe1ec4b 366 * Description: -
vpcola 0:a1734fe1ec4b 367 * Parameters: -
vpcola 0:a1734fe1ec4b 368 * Return: -
vpcola 0:a1734fe1ec4b 369 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 370 void MCR20Drv_IndirectAccessSPIWrite
vpcola 0:a1734fe1ec4b 371 (
vpcola 0:a1734fe1ec4b 372 uint8_t address,
vpcola 0:a1734fe1ec4b 373 uint8_t value
vpcola 0:a1734fe1ec4b 374 )
vpcola 0:a1734fe1ec4b 375 {
vpcola 0:a1734fe1ec4b 376 uint32_t txData;
vpcola 0:a1734fe1ec4b 377
vpcola 0:a1734fe1ec4b 378 ProtectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 379
vpcola 0:a1734fe1ec4b 380 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
vpcola 0:a1734fe1ec4b 381
vpcola 0:a1734fe1ec4b 382 gXcvrAssertCS_d();
vpcola 0:a1734fe1ec4b 383
vpcola 0:a1734fe1ec4b 384 txData = TransceiverSPI_IARIndexReg;
vpcola 0:a1734fe1ec4b 385 txData |= (address) << 8;
vpcola 0:a1734fe1ec4b 386 txData |= (value) << 16;
vpcola 0:a1734fe1ec4b 387
vpcola 0:a1734fe1ec4b 388 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3);
vpcola 0:a1734fe1ec4b 389
vpcola 0:a1734fe1ec4b 390 gXcvrDeassertCS_d();
vpcola 0:a1734fe1ec4b 391 UnprotectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 392 }
vpcola 0:a1734fe1ec4b 393
vpcola 0:a1734fe1ec4b 394 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 395 * Name: MCR20Drv_IndirectAccessSPIMultiByteWrite
vpcola 0:a1734fe1ec4b 396 * Description: -
vpcola 0:a1734fe1ec4b 397 * Parameters: -
vpcola 0:a1734fe1ec4b 398 * Return: -
vpcola 0:a1734fe1ec4b 399 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 400 void MCR20Drv_IndirectAccessSPIMultiByteWrite
vpcola 0:a1734fe1ec4b 401 (
vpcola 0:a1734fe1ec4b 402 uint8_t startAddress,
vpcola 0:a1734fe1ec4b 403 uint8_t * byteArray,
vpcola 0:a1734fe1ec4b 404 uint8_t numOfBytes
vpcola 0:a1734fe1ec4b 405 )
vpcola 0:a1734fe1ec4b 406 {
vpcola 0:a1734fe1ec4b 407 uint16_t txData;
vpcola 0:a1734fe1ec4b 408
vpcola 0:a1734fe1ec4b 409 if( (numOfBytes == 0) || (byteArray == 0) )
vpcola 0:a1734fe1ec4b 410 {
vpcola 0:a1734fe1ec4b 411 return;
vpcola 0:a1734fe1ec4b 412 }
vpcola 0:a1734fe1ec4b 413
vpcola 0:a1734fe1ec4b 414 ProtectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 415
vpcola 0:a1734fe1ec4b 416 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
vpcola 0:a1734fe1ec4b 417
vpcola 0:a1734fe1ec4b 418 gXcvrAssertCS_d();
vpcola 0:a1734fe1ec4b 419
vpcola 0:a1734fe1ec4b 420 txData = TransceiverSPI_IARIndexReg;
vpcola 0:a1734fe1ec4b 421 txData |= (startAddress) << 8;
vpcola 0:a1734fe1ec4b 422
vpcola 0:a1734fe1ec4b 423 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
vpcola 0:a1734fe1ec4b 424 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)byteArray, 0, numOfBytes);
vpcola 0:a1734fe1ec4b 425
vpcola 0:a1734fe1ec4b 426 gXcvrDeassertCS_d();
vpcola 0:a1734fe1ec4b 427 UnprotectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 428 }
vpcola 0:a1734fe1ec4b 429
vpcola 0:a1734fe1ec4b 430 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 431 * Name: MCR20Drv_IndirectAccessSPIRead
vpcola 0:a1734fe1ec4b 432 * Description: -
vpcola 0:a1734fe1ec4b 433 * Parameters: -
vpcola 0:a1734fe1ec4b 434 * Return: -
vpcola 0:a1734fe1ec4b 435 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 436 uint8_t MCR20Drv_IndirectAccessSPIRead
vpcola 0:a1734fe1ec4b 437 (
vpcola 0:a1734fe1ec4b 438 uint8_t address
vpcola 0:a1734fe1ec4b 439 )
vpcola 0:a1734fe1ec4b 440 {
vpcola 0:a1734fe1ec4b 441 uint16_t txData;
vpcola 0:a1734fe1ec4b 442 uint8_t rxData;
vpcola 0:a1734fe1ec4b 443
vpcola 0:a1734fe1ec4b 444 ProtectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 445
vpcola 0:a1734fe1ec4b 446 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
vpcola 0:a1734fe1ec4b 447
vpcola 0:a1734fe1ec4b 448 gXcvrAssertCS_d();
vpcola 0:a1734fe1ec4b 449
vpcola 0:a1734fe1ec4b 450 txData = TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect;
vpcola 0:a1734fe1ec4b 451 txData |= (address) << 8;
vpcola 0:a1734fe1ec4b 452
vpcola 0:a1734fe1ec4b 453 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
vpcola 0:a1734fe1ec4b 454 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData));
vpcola 0:a1734fe1ec4b 455
vpcola 0:a1734fe1ec4b 456 gXcvrDeassertCS_d();
vpcola 0:a1734fe1ec4b 457 UnprotectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 458
vpcola 0:a1734fe1ec4b 459 return rxData;
vpcola 0:a1734fe1ec4b 460 }
vpcola 0:a1734fe1ec4b 461
vpcola 0:a1734fe1ec4b 462 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 463 * Name: MCR20Drv_IndirectAccessSPIMultiByteRead
vpcola 0:a1734fe1ec4b 464 * Description: -
vpcola 0:a1734fe1ec4b 465 * Parameters: -
vpcola 0:a1734fe1ec4b 466 * Return: -
vpcola 0:a1734fe1ec4b 467 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 468 void MCR20Drv_IndirectAccessSPIMultiByteRead
vpcola 0:a1734fe1ec4b 469 (
vpcola 0:a1734fe1ec4b 470 uint8_t startAddress,
vpcola 0:a1734fe1ec4b 471 uint8_t * byteArray,
vpcola 0:a1734fe1ec4b 472 uint8_t numOfBytes
vpcola 0:a1734fe1ec4b 473 )
vpcola 0:a1734fe1ec4b 474 {
vpcola 0:a1734fe1ec4b 475 uint16_t txData;
vpcola 0:a1734fe1ec4b 476
vpcola 0:a1734fe1ec4b 477 if( (numOfBytes == 0) || (byteArray == 0) )
vpcola 0:a1734fe1ec4b 478 {
vpcola 0:a1734fe1ec4b 479 return;
vpcola 0:a1734fe1ec4b 480 }
vpcola 0:a1734fe1ec4b 481
vpcola 0:a1734fe1ec4b 482 ProtectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 483
vpcola 0:a1734fe1ec4b 484 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
vpcola 0:a1734fe1ec4b 485
vpcola 0:a1734fe1ec4b 486 gXcvrAssertCS_d();
vpcola 0:a1734fe1ec4b 487
vpcola 0:a1734fe1ec4b 488 txData = (TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect);
vpcola 0:a1734fe1ec4b 489 txData |= (startAddress) << 8;
vpcola 0:a1734fe1ec4b 490
vpcola 0:a1734fe1ec4b 491 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
vpcola 0:a1734fe1ec4b 492 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
vpcola 0:a1734fe1ec4b 493
vpcola 0:a1734fe1ec4b 494 gXcvrDeassertCS_d();
vpcola 0:a1734fe1ec4b 495 UnprotectFromMCR20Interrupt();
vpcola 0:a1734fe1ec4b 496 }
vpcola 0:a1734fe1ec4b 497
vpcola 0:a1734fe1ec4b 498 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 499 * Name: MCR20Drv_IsIrqPending
vpcola 0:a1734fe1ec4b 500 * Description: -
vpcola 0:a1734fe1ec4b 501 * Parameters: -
vpcola 0:a1734fe1ec4b 502 * Return: -
vpcola 0:a1734fe1ec4b 503 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 504 uint32_t MCR20Drv_IsIrqPending
vpcola 0:a1734fe1ec4b 505 (
vpcola 0:a1734fe1ec4b 506 void
vpcola 0:a1734fe1ec4b 507 )
vpcola 0:a1734fe1ec4b 508 {
vpcola 0:a1734fe1ec4b 509 return RF_isIRQ_Pending();
vpcola 0:a1734fe1ec4b 510 }
vpcola 0:a1734fe1ec4b 511
vpcola 0:a1734fe1ec4b 512 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 513 * Name: MCR20Drv_IRQ_Disable
vpcola 0:a1734fe1ec4b 514 * Description: -
vpcola 0:a1734fe1ec4b 515 * Parameters: -
vpcola 0:a1734fe1ec4b 516 * Return: -
vpcola 0:a1734fe1ec4b 517 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 518 void MCR20Drv_IRQ_Disable
vpcola 0:a1734fe1ec4b 519 (
vpcola 0:a1734fe1ec4b 520 void
vpcola 0:a1734fe1ec4b 521 )
vpcola 0:a1734fe1ec4b 522 {
vpcola 0:a1734fe1ec4b 523 platform_enter_critical();
vpcola 0:a1734fe1ec4b 524
vpcola 0:a1734fe1ec4b 525 if( mPhyIrqDisableCnt == 0 )
vpcola 0:a1734fe1ec4b 526 {
vpcola 0:a1734fe1ec4b 527 RF_IRQ_Disable();
vpcola 0:a1734fe1ec4b 528 }
vpcola 0:a1734fe1ec4b 529
vpcola 0:a1734fe1ec4b 530 mPhyIrqDisableCnt++;
vpcola 0:a1734fe1ec4b 531
vpcola 0:a1734fe1ec4b 532 platform_exit_critical();
vpcola 0:a1734fe1ec4b 533 }
vpcola 0:a1734fe1ec4b 534
vpcola 0:a1734fe1ec4b 535 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 536 * Name: MCR20Drv_IRQ_Enable
vpcola 0:a1734fe1ec4b 537 * Description: -
vpcola 0:a1734fe1ec4b 538 * Parameters: -
vpcola 0:a1734fe1ec4b 539 * Return: -
vpcola 0:a1734fe1ec4b 540 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 541 void MCR20Drv_IRQ_Enable
vpcola 0:a1734fe1ec4b 542 (
vpcola 0:a1734fe1ec4b 543 void
vpcola 0:a1734fe1ec4b 544 )
vpcola 0:a1734fe1ec4b 545 {
vpcola 0:a1734fe1ec4b 546 platform_enter_critical();
vpcola 0:a1734fe1ec4b 547
vpcola 0:a1734fe1ec4b 548 if( mPhyIrqDisableCnt )
vpcola 0:a1734fe1ec4b 549 {
vpcola 0:a1734fe1ec4b 550 mPhyIrqDisableCnt--;
vpcola 0:a1734fe1ec4b 551
vpcola 0:a1734fe1ec4b 552 if( mPhyIrqDisableCnt == 0 )
vpcola 0:a1734fe1ec4b 553 {
vpcola 0:a1734fe1ec4b 554 RF_IRQ_Enable();
vpcola 0:a1734fe1ec4b 555 }
vpcola 0:a1734fe1ec4b 556 }
vpcola 0:a1734fe1ec4b 557
vpcola 0:a1734fe1ec4b 558 platform_exit_critical();
vpcola 0:a1734fe1ec4b 559 }
vpcola 0:a1734fe1ec4b 560
vpcola 0:a1734fe1ec4b 561 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 562 * Name: MCR20Drv_RST_Assert
vpcola 0:a1734fe1ec4b 563 * Description: -
vpcola 0:a1734fe1ec4b 564 * Parameters: -
vpcola 0:a1734fe1ec4b 565 * Return: -
vpcola 0:a1734fe1ec4b 566 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 567 void MCR20Drv_RST_B_Assert
vpcola 0:a1734fe1ec4b 568 (
vpcola 0:a1734fe1ec4b 569 void
vpcola 0:a1734fe1ec4b 570 )
vpcola 0:a1734fe1ec4b 571 {
vpcola 0:a1734fe1ec4b 572 RF_RST_Set(0);
vpcola 0:a1734fe1ec4b 573 }
vpcola 0:a1734fe1ec4b 574
vpcola 0:a1734fe1ec4b 575 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 576 * Name: MCR20Drv_RST_Deassert
vpcola 0:a1734fe1ec4b 577 * Description: -
vpcola 0:a1734fe1ec4b 578 * Parameters: -
vpcola 0:a1734fe1ec4b 579 * Return: -
vpcola 0:a1734fe1ec4b 580 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 581 void MCR20Drv_RST_B_Deassert
vpcola 0:a1734fe1ec4b 582 (
vpcola 0:a1734fe1ec4b 583 void
vpcola 0:a1734fe1ec4b 584 )
vpcola 0:a1734fe1ec4b 585 {
vpcola 0:a1734fe1ec4b 586 RF_RST_Set(1);
vpcola 0:a1734fe1ec4b 587 }
vpcola 0:a1734fe1ec4b 588
vpcola 0:a1734fe1ec4b 589 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 590 * Name: MCR20Drv_SoftRST_Assert
vpcola 0:a1734fe1ec4b 591 * Description: -
vpcola 0:a1734fe1ec4b 592 * Parameters: -
vpcola 0:a1734fe1ec4b 593 * Return: -
vpcola 0:a1734fe1ec4b 594 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 595 void MCR20Drv_SoftRST_Assert
vpcola 0:a1734fe1ec4b 596 (
vpcola 0:a1734fe1ec4b 597 void
vpcola 0:a1734fe1ec4b 598 )
vpcola 0:a1734fe1ec4b 599 {
vpcola 0:a1734fe1ec4b 600 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
vpcola 0:a1734fe1ec4b 601 }
vpcola 0:a1734fe1ec4b 602
vpcola 0:a1734fe1ec4b 603 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 604 * Name: MCR20Drv_SoftRST_Deassert
vpcola 0:a1734fe1ec4b 605 * Description: -
vpcola 0:a1734fe1ec4b 606 * Parameters: -
vpcola 0:a1734fe1ec4b 607 * Return: -
vpcola 0:a1734fe1ec4b 608 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 609 void MCR20Drv_SoftRST_Deassert
vpcola 0:a1734fe1ec4b 610 (
vpcola 0:a1734fe1ec4b 611 void
vpcola 0:a1734fe1ec4b 612 )
vpcola 0:a1734fe1ec4b 613 {
vpcola 0:a1734fe1ec4b 614 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
vpcola 0:a1734fe1ec4b 615 }
vpcola 0:a1734fe1ec4b 616
vpcola 0:a1734fe1ec4b 617 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 618 * Name: MCR20Drv_Soft_RESET
vpcola 0:a1734fe1ec4b 619 * Description: -
vpcola 0:a1734fe1ec4b 620 * Parameters: -
vpcola 0:a1734fe1ec4b 621 * Return: -
vpcola 0:a1734fe1ec4b 622 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 623 void MCR20Drv_Soft_RESET
vpcola 0:a1734fe1ec4b 624 (
vpcola 0:a1734fe1ec4b 625 void
vpcola 0:a1734fe1ec4b 626 )
vpcola 0:a1734fe1ec4b 627 {
vpcola 0:a1734fe1ec4b 628 //assert SOG_RST
vpcola 0:a1734fe1ec4b 629 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
vpcola 0:a1734fe1ec4b 630
vpcola 0:a1734fe1ec4b 631 //deassert SOG_RST
vpcola 0:a1734fe1ec4b 632 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
vpcola 0:a1734fe1ec4b 633 }
vpcola 0:a1734fe1ec4b 634
vpcola 0:a1734fe1ec4b 635 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 636 * Name: MCR20Drv_RESET
vpcola 0:a1734fe1ec4b 637 * Description: -
vpcola 0:a1734fe1ec4b 638 * Parameters: -
vpcola 0:a1734fe1ec4b 639 * Return: -
vpcola 0:a1734fe1ec4b 640 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 641 void MCR20Drv_RESET
vpcola 0:a1734fe1ec4b 642 (
vpcola 0:a1734fe1ec4b 643 void
vpcola 0:a1734fe1ec4b 644 )
vpcola 0:a1734fe1ec4b 645 {
vpcola 0:a1734fe1ec4b 646 volatile uint32_t delay = 1000;
vpcola 0:a1734fe1ec4b 647 //assert RST_B
vpcola 0:a1734fe1ec4b 648 MCR20Drv_RST_B_Assert();
vpcola 0:a1734fe1ec4b 649
vpcola 0:a1734fe1ec4b 650 while(delay--);
vpcola 0:a1734fe1ec4b 651
vpcola 0:a1734fe1ec4b 652 //deassert RST_B
vpcola 0:a1734fe1ec4b 653 MCR20Drv_RST_B_Deassert();
vpcola 0:a1734fe1ec4b 654 }
vpcola 0:a1734fe1ec4b 655
vpcola 0:a1734fe1ec4b 656 /*---------------------------------------------------------------------------
vpcola 0:a1734fe1ec4b 657 * Name: MCR20Drv_Set_CLK_OUT_Freq
vpcola 0:a1734fe1ec4b 658 * Description: -
vpcola 0:a1734fe1ec4b 659 * Parameters: -
vpcola 0:a1734fe1ec4b 660 * Return: -
vpcola 0:a1734fe1ec4b 661 *---------------------------------------------------------------------------*/
vpcola 0:a1734fe1ec4b 662 void MCR20Drv_Set_CLK_OUT_Freq
vpcola 0:a1734fe1ec4b 663 (
vpcola 0:a1734fe1ec4b 664 uint8_t freqDiv
vpcola 0:a1734fe1ec4b 665 )
vpcola 0:a1734fe1ec4b 666 {
vpcola 0:a1734fe1ec4b 667 uint8_t clkOutCtrlReg = (freqDiv & cCLK_OUT_DIV_Mask) | cCLK_OUT_EN | cCLK_OUT_EXTEND;
vpcola 0:a1734fe1ec4b 668
vpcola 0:a1734fe1ec4b 669 if(freqDiv == gCLK_OUT_FREQ_DISABLE)
vpcola 0:a1734fe1ec4b 670 {
vpcola 0:a1734fe1ec4b 671 clkOutCtrlReg = (cCLK_OUT_EXTEND | gCLK_OUT_FREQ_4_MHz); //reset value with clock out disabled
vpcola 0:a1734fe1ec4b 672 }
vpcola 0:a1734fe1ec4b 673
vpcola 0:a1734fe1ec4b 674 MCR20Drv_DirectAccessSPIWrite((uint8_t) CLK_OUT_CTRL, clkOutCtrlReg);
vpcola 0:a1734fe1ec4b 675 }