Vishal Bharam / MMA8451Q8

Fork of MMA8451Q8b by Stanley Cohen

Committer:
vbharam
Date:
Mon Feb 09 04:41:57 2015 +0000
Revision:
9:acccb8faf90c
Parent:
8:993bb9e96a4b
Single Tap

Who changed what in which revision?

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samux 1:d2630136d51e 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
samux 1:d2630136d51e 2 *
samux 1:d2630136d51e 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
samux 1:d2630136d51e 4 * and associated documentation files (the "Software"), to deal in the Software without
samux 1:d2630136d51e 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
samux 1:d2630136d51e 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
samux 1:d2630136d51e 7 * Software is furnished to do so, subject to the following conditions:
samux 1:d2630136d51e 8 *
samux 1:d2630136d51e 9 * The above copyright notice and this permission notice shall be included in all copies or
samux 1:d2630136d51e 10 * substantial portions of the Software.
samux 1:d2630136d51e 11 *
samux 1:d2630136d51e 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
samux 1:d2630136d51e 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
samux 1:d2630136d51e 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
samux 1:d2630136d51e 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
samux 1:d2630136d51e 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
samux 1:d2630136d51e 17 */
scohennm 5:5a7293378401 18 // Modify to change full scale gravity range 141207 sc
samux 1:d2630136d51e 19
scohennm 5:5a7293378401 20
scohennm 5:5a7293378401 21 #include "MMA8451Q8.h"
emilmont 0:6149091f755d 22
samux 1:d2630136d51e 23 #define REG_WHO_AM_I 0x0D
samux 1:d2630136d51e 24 #define REG_CTRL_REG_1 0x2A
emilmont 0:6149091f755d 25 #define REG_OUT_X_MSB 0x01
emilmont 0:6149091f755d 26 #define REG_OUT_Y_MSB 0x03
emilmont 0:6149091f755d 27 #define REG_OUT_Z_MSB 0x05
scohennm 5:5a7293378401 28 #define XYZ_DATA_CFG 0x0E
scohennm 8:993bb9e96a4b 29 // adding tap config register adderesses
scohennm 8:993bb9e96a4b 30 #define REG_PULSE_SRC 0x22
scohennm 8:993bb9e96a4b 31 #define REG_PULSE_CFG 0x21
emilmont 0:6149091f755d 32
samux 1:d2630136d51e 33 #define UINT14_MAX 16383
emilmont 0:6149091f755d 34
scohennm 5:5a7293378401 35 #define MAX_2G 0x00
scohennm 5:5a7293378401 36 #define MAX_4G 0x01
scohennm 5:5a7293378401 37 #define MAX_8G 0x02
scohennm 5:5a7293378401 38
scohennm 5:5a7293378401 39 #define NUM_DATA 2
scohennm 5:5a7293378401 40 #define GSCALING 1024.0
scohennm 5:5a7293378401 41 #define ADDRESS_INDEX 0
scohennm 5:5a7293378401 42 #define DATA_INDEX 1
scohennm 5:5a7293378401 43
scohennm 5:5a7293378401 44 float gScaling[3] = {4095.0,2048.0,1024.0}; //scaling for acceleration of gravity values
scohennm 5:5a7293378401 45
emilmont 0:6149091f755d 46 MMA8451Q::MMA8451Q(PinName sda, PinName scl, int addr) : m_i2c(sda, scl), m_addr(addr) {
emilmont 0:6149091f755d 47 // activate the peripheral
emilmont 0:6149091f755d 48 uint8_t data[2] = {REG_CTRL_REG_1, 0x01};
samux 1:d2630136d51e 49 writeRegs(data, 2);
emilmont 0:6149091f755d 50 }
emilmont 0:6149091f755d 51
emilmont 0:6149091f755d 52 MMA8451Q::~MMA8451Q() { }
emilmont 0:6149091f755d 53
emilmont 0:6149091f755d 54 uint8_t MMA8451Q::getWhoAmI() {
emilmont 0:6149091f755d 55 uint8_t who_am_i = 0;
samux 1:d2630136d51e 56 readRegs(REG_WHO_AM_I, &who_am_i, 1);
emilmont 0:6149091f755d 57 return who_am_i;
emilmont 0:6149091f755d 58 }
scohennm 5:5a7293378401 59 void MMA8451Q::setGLimit(int gSelect) {
scohennm 5:5a7293378401 60 uint8_t data[NUM_DATA] = {REG_CTRL_REG_1, 0x00};
scohennm 5:5a7293378401 61 gChosen = gSelect;
scohennm 5:5a7293378401 62 writeRegs(data, NUM_DATA); // put in standby
scohennm 5:5a7293378401 63 data[ADDRESS_INDEX ] = XYZ_DATA_CFG;
scohennm 5:5a7293378401 64 data[DATA_INDEX] = gChosen;
scohennm 5:5a7293378401 65 writeRegs(data, 2);// change g limit
scohennm 5:5a7293378401 66 data[ADDRESS_INDEX ] = REG_CTRL_REG_1;
scohennm 5:5a7293378401 67 data[DATA_INDEX] = 0x01;
scohennm 5:5a7293378401 68 writeRegs(data, 2); // make active
scohennm 5:5a7293378401 69 }
vbharam 9:acccb8faf90c 70
scohennm 8:993bb9e96a4b 71 // add Puse configuratioin register access
scohennm 8:993bb9e96a4b 72 // Also add function prototype to .h file
scohennm 8:993bb9e96a4b 73 void MMA8451Q::setPulseConfiguration(uint8_t latch,uint8_t axisSet) {
scohennm 8:993bb9e96a4b 74 uint8_t configBits;
scohennm 8:993bb9e96a4b 75 uint8_t data[NUM_DATA] = {REG_CTRL_REG_1, 0x00}; // put in standby mode
scohennm 8:993bb9e96a4b 76 // set up configuration bits.
scohennm 8:993bb9e96a4b 77 configBits = latch | axisSet;
scohennm 8:993bb9e96a4b 78 writeRegs(data, NUM_DATA); // put in standby
scohennm 8:993bb9e96a4b 79 data[ADDRESS_INDEX ] = REG_PULSE_CFG;
scohennm 8:993bb9e96a4b 80 data[DATA_INDEX] = configBits;
scohennm 8:993bb9e96a4b 81 writeRegs(data, NUM_DATA);
scohennm 8:993bb9e96a4b 82 data[ADDRESS_INDEX ] = REG_CTRL_REG_1; // put back in active mode
scohennm 8:993bb9e96a4b 83 data[DATA_INDEX] = 0x01;
scohennm 8:993bb9e96a4b 84 writeRegs(data, 2); // make active
scohennm 8:993bb9e96a4b 85 }
vbharam 9:acccb8faf90c 86
vbharam 9:acccb8faf90c 87 //Generic register set mode for those needing to be put in standby to update
vbharam 9:acccb8faf90c 88 void MMA8451Q::setRegisterInStandby(uint8_t regAddress, uint8_t regData) {
vbharam 9:acccb8faf90c 89 uint8_t data[NUM_DATA] = {REG_CTRL_REG_1, 0x00};
vbharam 9:acccb8faf90c 90 writeRegs(data, NUM_DATA); // put in standby
vbharam 9:acccb8faf90c 91 data[ADDRESS_INDEX ] = regAddress;
vbharam 9:acccb8faf90c 92 data[DATA_INDEX] = regData;
vbharam 9:acccb8faf90c 93 writeRegs(data, NUM_DATA);
vbharam 9:acccb8faf90c 94 data[ADDRESS_INDEX] = REG_CTRL_REG_1; // put back in active mode
vbharam 9:acccb8faf90c 95 data[DATA_INDEX] = 0x01;
vbharam 9:acccb8faf90c 96 writeRegs(data, 2); // make active
vbharam 9:acccb8faf90c 97 }
vbharam 9:acccb8faf90c 98
chris 3:db7126dbd63f 99 float MMA8451Q::getAccX() {
scohennm 5:5a7293378401 100 return (float(getAccAxis(REG_OUT_X_MSB))/gScaling[gChosen]);
emilmont 0:6149091f755d 101 }
emilmont 0:6149091f755d 102
scohennm 7:ed7e11d269f8 103
chris 3:db7126dbd63f 104 float MMA8451Q::getAccY() {
scohennm 5:5a7293378401 105 return (float(getAccAxis(REG_OUT_Y_MSB))/gScaling[gChosen]);
emilmont 0:6149091f755d 106 }
emilmont 0:6149091f755d 107
chris 3:db7126dbd63f 108 float MMA8451Q::getAccZ() {
scohennm 5:5a7293378401 109 return (float(getAccAxis(REG_OUT_Z_MSB))/gScaling[gChosen]);
emilmont 0:6149091f755d 110 }
emilmont 0:6149091f755d 111
chris 3:db7126dbd63f 112 void MMA8451Q::getAccAllAxis(float * res) {
emilmont 0:6149091f755d 113 res[0] = getAccX();
emilmont 0:6149091f755d 114 res[1] = getAccY();
emilmont 0:6149091f755d 115 res[2] = getAccZ();
emilmont 0:6149091f755d 116 }
emilmont 0:6149091f755d 117
emilmont 0:6149091f755d 118 int16_t MMA8451Q::getAccAxis(uint8_t addr) {
emilmont 0:6149091f755d 119 int16_t acc;
emilmont 0:6149091f755d 120 uint8_t res[2];
samux 1:d2630136d51e 121 readRegs(addr, res, 2);
emilmont 0:6149091f755d 122
emilmont 0:6149091f755d 123 acc = (res[0] << 6) | (res[1] >> 2);
emilmont 0:6149091f755d 124 if (acc > UINT14_MAX/2)
emilmont 0:6149091f755d 125 acc -= UINT14_MAX;
emilmont 0:6149091f755d 126
emilmont 0:6149091f755d 127 return acc;
emilmont 0:6149091f755d 128 }
emilmont 0:6149091f755d 129
samux 1:d2630136d51e 130 void MMA8451Q::readRegs(int addr, uint8_t * data, int len) {
emilmont 0:6149091f755d 131 char t[1] = {addr};
emilmont 0:6149091f755d 132 m_i2c.write(m_addr, t, 1, true);
emilmont 0:6149091f755d 133 m_i2c.read(m_addr, (char *)data, len);
emilmont 0:6149091f755d 134 }
emilmont 0:6149091f755d 135
samux 1:d2630136d51e 136 void MMA8451Q::writeRegs(uint8_t * data, int len) {
emilmont 0:6149091f755d 137 m_i2c.write(m_addr, (char *)data, len);
emilmont 0:6149091f755d 138 }