Denislam Valeev / Mbed OS Nucleo_rtos_basic

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mbed-os/targets/TARGET_NXP/TARGET_LPC176X/gpio_irq_api.c@0:e056ac8fecf8, 2018-03-13 (annotated)

Committer:
valeyev
Date:
Tue Mar 13 07:17:50 2018 +0000
Revision:
0:e056ac8fecf8
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Who changed what in which revision?

UserRevisionLine numberNew contents of line
valeyev 0:e056ac8fecf8 1 /* mbed Microcontroller Library
valeyev 0:e056ac8fecf8 2 * Copyright (c) 2006-2013 ARM Limited
valeyev 0:e056ac8fecf8 3 *
valeyev 0:e056ac8fecf8 4 * Licensed under the Apache License, Version 2.0 (the "License");
valeyev 0:e056ac8fecf8 5 * you may not use this file except in compliance with the License.
valeyev 0:e056ac8fecf8 6 * You may obtain a copy of the License at
valeyev 0:e056ac8fecf8 7 *
valeyev 0:e056ac8fecf8 8 * http://www.apache.org/licenses/LICENSE-2.0
valeyev 0:e056ac8fecf8 9 *
valeyev 0:e056ac8fecf8 10 * Unless required by applicable law or agreed to in writing, software
valeyev 0:e056ac8fecf8 11 * distributed under the License is distributed on an "AS IS" BASIS,
valeyev 0:e056ac8fecf8 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
valeyev 0:e056ac8fecf8 13 * See the License for the specific language governing permissions and
valeyev 0:e056ac8fecf8 14 * limitations under the License.
valeyev 0:e056ac8fecf8 15 */
valeyev 0:e056ac8fecf8 16 #include <stddef.h>
valeyev 0:e056ac8fecf8 17
valeyev 0:e056ac8fecf8 18 #include "gpio_irq_api.h"
valeyev 0:e056ac8fecf8 19 #include "mbed_error.h"
valeyev 0:e056ac8fecf8 20 #include "cmsis.h"
valeyev 0:e056ac8fecf8 21
valeyev 0:e056ac8fecf8 22 #define CHANNEL_NUM 48
valeyev 0:e056ac8fecf8 23
valeyev 0:e056ac8fecf8 24 static uint32_t channel_ids[CHANNEL_NUM] = {0};
valeyev 0:e056ac8fecf8 25 static gpio_irq_handler irq_handler;
valeyev 0:e056ac8fecf8 26
valeyev 0:e056ac8fecf8 27 static void handle_interrupt_in(void) {
valeyev 0:e056ac8fecf8 28 // Read in all current interrupt registers. We do this once as the
valeyev 0:e056ac8fecf8 29 // GPIO interrupt registers are on the APB bus, and this is slow.
valeyev 0:e056ac8fecf8 30 uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
valeyev 0:e056ac8fecf8 31 uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
valeyev 0:e056ac8fecf8 32 uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
valeyev 0:e056ac8fecf8 33 uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
valeyev 0:e056ac8fecf8 34 uint8_t bitloc;
valeyev 0:e056ac8fecf8 35
valeyev 0:e056ac8fecf8 36 while(rise0 > 0) { //Continue as long as there are interrupts pending
valeyev 0:e056ac8fecf8 37 bitloc = 31 - __CLZ(rise0); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
valeyev 0:e056ac8fecf8 38 if (channel_ids[bitloc] != 0)
valeyev 0:e056ac8fecf8 39 irq_handler(channel_ids[bitloc], IRQ_RISE); //Run that interrupt
valeyev 0:e056ac8fecf8 40
valeyev 0:e056ac8fecf8 41 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
valeyev 0:e056ac8fecf8 42 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
valeyev 0:e056ac8fecf8 43 rise0 -= 1<<bitloc;
valeyev 0:e056ac8fecf8 44 }
valeyev 0:e056ac8fecf8 45
valeyev 0:e056ac8fecf8 46 while(fall0 > 0) { //Continue as long as there are interrupts pending
valeyev 0:e056ac8fecf8 47 bitloc = 31 - __CLZ(fall0); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
valeyev 0:e056ac8fecf8 48 if (channel_ids[bitloc] != 0)
valeyev 0:e056ac8fecf8 49 irq_handler(channel_ids[bitloc], IRQ_FALL); //Run that interrupt
valeyev 0:e056ac8fecf8 50
valeyev 0:e056ac8fecf8 51 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
valeyev 0:e056ac8fecf8 52 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
valeyev 0:e056ac8fecf8 53 fall0 -= 1<<bitloc;
valeyev 0:e056ac8fecf8 54 }
valeyev 0:e056ac8fecf8 55
valeyev 0:e056ac8fecf8 56 //Same for port 2, only we need to watch the channel_index
valeyev 0:e056ac8fecf8 57 while(rise2 > 0) { //Continue as long as there are interrupts pending
valeyev 0:e056ac8fecf8 58 bitloc = 31 - __CLZ(rise2); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
valeyev 0:e056ac8fecf8 59
valeyev 0:e056ac8fecf8 60 if (bitloc < 16) //Not sure if this is actually needed
valeyev 0:e056ac8fecf8 61 if (channel_ids[bitloc+32] != 0)
valeyev 0:e056ac8fecf8 62 irq_handler(channel_ids[bitloc+32], IRQ_RISE); //Run that interrupt
valeyev 0:e056ac8fecf8 63
valeyev 0:e056ac8fecf8 64 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
valeyev 0:e056ac8fecf8 65 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
valeyev 0:e056ac8fecf8 66 rise2 -= 1<<bitloc;
valeyev 0:e056ac8fecf8 67 }
valeyev 0:e056ac8fecf8 68
valeyev 0:e056ac8fecf8 69 while(fall2 > 0) { //Continue as long as there are interrupts pending
valeyev 0:e056ac8fecf8 70 bitloc = 31 - __CLZ(fall2); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
valeyev 0:e056ac8fecf8 71
valeyev 0:e056ac8fecf8 72 if (bitloc < 16) //Not sure if this is actually needed
valeyev 0:e056ac8fecf8 73 if (channel_ids[bitloc+32] != 0)
valeyev 0:e056ac8fecf8 74 irq_handler(channel_ids[bitloc+32], IRQ_FALL); //Run that interrupt
valeyev 0:e056ac8fecf8 75
valeyev 0:e056ac8fecf8 76 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
valeyev 0:e056ac8fecf8 77 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
valeyev 0:e056ac8fecf8 78 fall2 -= 1<<bitloc;
valeyev 0:e056ac8fecf8 79 }
valeyev 0:e056ac8fecf8 80 }
valeyev 0:e056ac8fecf8 81
valeyev 0:e056ac8fecf8 82 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
valeyev 0:e056ac8fecf8 83 if (pin == NC) return -1;
valeyev 0:e056ac8fecf8 84
valeyev 0:e056ac8fecf8 85 irq_handler = handler;
valeyev 0:e056ac8fecf8 86
valeyev 0:e056ac8fecf8 87 obj->port = (int)pin & ~0x1F;
valeyev 0:e056ac8fecf8 88 obj->pin = (int)pin & 0x1F;
valeyev 0:e056ac8fecf8 89
valeyev 0:e056ac8fecf8 90 // Interrupts available only on GPIO0 and GPIO2
valeyev 0:e056ac8fecf8 91 if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
valeyev 0:e056ac8fecf8 92 error("pins on this port cannot generate interrupts");
valeyev 0:e056ac8fecf8 93 }
valeyev 0:e056ac8fecf8 94
valeyev 0:e056ac8fecf8 95 // put us in the interrupt table
valeyev 0:e056ac8fecf8 96 int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
valeyev 0:e056ac8fecf8 97 channel_ids[index] = id;
valeyev 0:e056ac8fecf8 98 obj->ch = index;
valeyev 0:e056ac8fecf8 99
valeyev 0:e056ac8fecf8 100 NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
valeyev 0:e056ac8fecf8 101 NVIC_EnableIRQ(EINT3_IRQn);
valeyev 0:e056ac8fecf8 102 return 0;
valeyev 0:e056ac8fecf8 103 }
valeyev 0:e056ac8fecf8 104
valeyev 0:e056ac8fecf8 105 void gpio_irq_free(gpio_irq_t *obj) {
valeyev 0:e056ac8fecf8 106 channel_ids[obj->ch] = 0;
valeyev 0:e056ac8fecf8 107 }
valeyev 0:e056ac8fecf8 108
valeyev 0:e056ac8fecf8 109 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
valeyev 0:e056ac8fecf8 110 // ensure nothing is pending
valeyev 0:e056ac8fecf8 111 switch (obj->port) {
valeyev 0:e056ac8fecf8 112 case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
valeyev 0:e056ac8fecf8 113 case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
valeyev 0:e056ac8fecf8 114 }
valeyev 0:e056ac8fecf8 115
valeyev 0:e056ac8fecf8 116 // enable the pin interrupt
valeyev 0:e056ac8fecf8 117 if (event == IRQ_RISE) {
valeyev 0:e056ac8fecf8 118 switch (obj->port) {
valeyev 0:e056ac8fecf8 119 case LPC_GPIO0_BASE:
valeyev 0:e056ac8fecf8 120 if (enable) {
valeyev 0:e056ac8fecf8 121 LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
valeyev 0:e056ac8fecf8 122 } else {
valeyev 0:e056ac8fecf8 123 LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
valeyev 0:e056ac8fecf8 124 }
valeyev 0:e056ac8fecf8 125 break;
valeyev 0:e056ac8fecf8 126 case LPC_GPIO2_BASE:
valeyev 0:e056ac8fecf8 127 if (enable) {
valeyev 0:e056ac8fecf8 128 LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
valeyev 0:e056ac8fecf8 129 } else {
valeyev 0:e056ac8fecf8 130 LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
valeyev 0:e056ac8fecf8 131 }
valeyev 0:e056ac8fecf8 132 break;
valeyev 0:e056ac8fecf8 133 }
valeyev 0:e056ac8fecf8 134 } else {
valeyev 0:e056ac8fecf8 135 switch (obj->port) {
valeyev 0:e056ac8fecf8 136 case LPC_GPIO0_BASE:
valeyev 0:e056ac8fecf8 137 if (enable) {
valeyev 0:e056ac8fecf8 138 LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
valeyev 0:e056ac8fecf8 139 } else {
valeyev 0:e056ac8fecf8 140 LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
valeyev 0:e056ac8fecf8 141 }
valeyev 0:e056ac8fecf8 142 break;
valeyev 0:e056ac8fecf8 143 case LPC_GPIO2_BASE:
valeyev 0:e056ac8fecf8 144 if (enable) {
valeyev 0:e056ac8fecf8 145 LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
valeyev 0:e056ac8fecf8 146 } else {
valeyev 0:e056ac8fecf8 147 LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
valeyev 0:e056ac8fecf8 148 }
valeyev 0:e056ac8fecf8 149 break;
valeyev 0:e056ac8fecf8 150 }
valeyev 0:e056ac8fecf8 151 }
valeyev 0:e056ac8fecf8 152 }
valeyev 0:e056ac8fecf8 153
valeyev 0:e056ac8fecf8 154 void gpio_irq_enable(gpio_irq_t *obj) {
valeyev 0:e056ac8fecf8 155 NVIC_EnableIRQ(EINT3_IRQn);
valeyev 0:e056ac8fecf8 156 }
valeyev 0:e056ac8fecf8 157
valeyev 0:e056ac8fecf8 158 void gpio_irq_disable(gpio_irq_t *obj) {
valeyev 0:e056ac8fecf8 159 NVIC_DisableIRQ(EINT3_IRQn);
valeyev 0:e056ac8fecf8 160 }
valeyev 0:e056ac8fecf8 161