A V
UARTs.c@0:49f07865b3e4, 2009-11-27 (annotated)
- Committer:
- valesek
- Date:
- Fri Nov 27 16:05:35 2009 +0000
- Revision:
- 0:49f07865b3e4
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| valesek | 0:49f07865b3e4 | 1 | #include <LPC17xx.h> |
| valesek | 0:49f07865b3e4 | 2 | #include "typedefs.h" |
| valesek | 0:49f07865b3e4 | 3 | #include "UARTs.h" |
| valesek | 0:49f07865b3e4 | 4 | |
| valesek | 0:49f07865b3e4 | 5 | void |
| valesek | 0:49f07865b3e4 | 6 | init_UARTs( UI_8 number_of_UART /* number of interface 0=UART0, 1=UART1, 2=UART2, 3=UART3 */ |
| valesek | 0:49f07865b3e4 | 7 | ,UI_8 data_bits_count /* count of data bits 5,6,7,8 */ |
| valesek | 0:49f07865b3e4 | 8 | ,UI_8 stop_bits_count /* count of stop bits 1=1, 2=2 (if data_bits==5 then stopbits=1and1/2) */ |
| valesek | 0:49f07865b3e4 | 9 | ,UI_8 type_of_parity /* type of parity 0=fixed "0", 1=fixed "1", 2=odd , 3=even, 4=none (without parity bit) */ |
| valesek | 0:49f07865b3e4 | 10 | ,UI_8 break_control /* 0=disable 1=enable */ |
| valesek | 0:49f07865b3e4 | 11 | |
| valesek | 0:49f07865b3e4 | 12 | ) |
| valesek | 0:49f07865b3e4 | 13 | { |
| valesek | 0:49f07865b3e4 | 14 | LPC_UART_TypeDef *uart; |
| valesek | 0:49f07865b3e4 | 15 | |
| valesek | 0:49f07865b3e4 | 16 | switch(number_of_UART) |
| valesek | 0:49f07865b3e4 | 17 | { |
| valesek | 0:49f07865b3e4 | 18 | case UART0: uart=(LPC_UART_TypeDef *) LPC_UART0; break; |
| valesek | 0:49f07865b3e4 | 19 | case UART1: uart=(LPC_UART_TypeDef *) LPC_UART1; break; |
| valesek | 0:49f07865b3e4 | 20 | case UART2: uart=(LPC_UART_TypeDef *) LPC_UART2; break; |
| valesek | 0:49f07865b3e4 | 21 | case UART3: uart=(LPC_UART_TypeDef *) LPC_UART3; break; |
| valesek | 0:49f07865b3e4 | 22 | } |
| valesek | 0:49f07865b3e4 | 23 | uart->LCR=(data_bits_count-(UI_8) 5)|((stop_bits_count-(UI_8) 1)<<2)|(type_of_parity<<3)|(break_control<<6); |
| valesek | 0:49f07865b3e4 | 24 | uart->LCR|=MASK_DIVISOR_LATCH_ACCESS_BIT; |
| valesek | 0:49f07865b3e4 | 25 | uart->DLL= |
| valesek | 0:49f07865b3e4 | 26 | uart->DLM= |
| valesek | 0:49f07865b3e4 | 27 | uart->LCR&=~MASK_DIVISOR_LATCH_ACCESS_BIT; |
| valesek | 0:49f07865b3e4 | 28 | |
| valesek | 0:49f07865b3e4 | 29 | |
| valesek | 0:49f07865b3e4 | 30 | // /* Initialize the serial interface */ |
| valesek | 0:49f07865b3e4 | 31 | // rbuf.in = 0; |
| valesek | 0:49f07865b3e4 | 32 | // rbuf.out = 0; |
| valesek | 0:49f07865b3e4 | 33 | // tbuf.in = 0; |
| valesek | 0:49f07865b3e4 | 34 | // tbuf.out = 0; |
| valesek | 0:49f07865b3e4 | 35 | // tx_active = __FALSE; |
| valesek | 0:49f07865b3e4 | 36 | // |
| valesek | 0:49f07865b3e4 | 37 | // /* Enable RxD1 and TxD1 pins. */ |
| valesek | 0:49f07865b3e4 | 38 | // PINSEL0 = 0x00050000; |
| valesek | 0:49f07865b3e4 | 39 | // /* 8-bits, no parity, 1 stop bit */ |
| valesek | 0:49f07865b3e4 | 40 | // U1LCR = 0x83; |
| valesek | 0:49f07865b3e4 | 41 | // /* 19200 Baud Rate @ 15MHz VPB Clock */ |
| valesek | 0:49f07865b3e4 | 42 | // U1DLL = 49; |
| valesek | 0:49f07865b3e4 | 43 | // U1DLM = 0; |
| valesek | 0:49f07865b3e4 | 44 | // U1LCR = 0x03; |
| valesek | 0:49f07865b3e4 | 45 | // /* Enable RDA and THRE interrupts. */ |
| valesek | 0:49f07865b3e4 | 46 | // U1IER = 0x03; |
| valesek | 0:49f07865b3e4 | 47 | // /* Enable UART1 interrupts. */ |
| valesek | 0:49f07865b3e4 | 48 | // VICVectAddr14 = (U32)handler_UART1; |
| valesek | 0:49f07865b3e4 | 49 | // VICVectCntl14 = 0x27; |
| valesek | 0:49f07865b3e4 | 50 | // VICIntEnable |= 1 << 7; |
| valesek | 0:49f07865b3e4 | 51 | } |