Revision 550:42c5b5cfc728, committed 2015-06-27

Comitter:

va009039

Date:

Sat Jun 27 01:57:17 2015 +0000

Parent:

549:379291b4cc1b

Commit message:

USBclk48MHz.

Changed in this revision

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c	Tue May 26 07:54:31 2015 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c	Sat Jun 27 01:57:17 2015 +0000
@@ -27,15 +27,15 @@
   *                                    | 2- PLL_HSE_XTAL        |
   *                                    | (external 8 MHz xtal)  |
   *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 24                     | 32
+  * SYSCLK(MHz)                        | 32                     | 32
   *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 24                     | 32
+  * AHBCLK (MHz)                       | 32                     | 32
   *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 24                     | 32
+  * APB1CLK (MHz)                      | 32                     | 32
   *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 24                     | 32
+  * APB2CLK (MHz)                      | 32                     | 32
   *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | NO
+  * USB capable (48 MHz precise clock) | YES                    | YES
   *-----------------------------------------------------------------------------
   ******************************************************************************
   * @attention
@@ -81,6 +81,7 @@
 
 #include "stm32l1xx.h"
 #include "hal_tick.h"
+#include "toolchain.h"
 
 /**
   * @}
@@ -449,7 +450,7 @@
   * @param  None
   * @retval None
   */
-void SetSysClock(void)
+WEAK void SetSysClock(void)
 {
   /* 1- Try to start with HSE and external clock */
 #if USE_PLL_HSE_EXTC != 0
@@ -508,12 +509,12 @@
     RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
   }
   RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-  // SYSCLK = 24 MHz ((8 MHz * 6) / 2)
-  // USBCLK = 48 MHz (8 MHz * 6) --> USB OK
+  // SYSCLK = 32 MHz ((8 MHz * 12) / 3)
+  // USBCLK = 48 MHz ((8 MHz * 12) / 2) --> USB OK
   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
+  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL12;
+  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
   {
     return 0; // FAIL
@@ -521,10 +522,10 @@
  
   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
   {
     return 0; // FAIL
@@ -558,12 +559,12 @@
   RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
   RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
-  // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
+  // SYSCLK = 32 MHz ((16 MHz * 6) / 3)
+  // USBCLK = 48 MHz ((16 MHz * 6) / 2) --> USB OK
   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
+  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
+  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
   {
     return 0; // FAIL