FRDM_K64F_LCD - A simple 128x32 graphical LCD program to quicksta…

Users » tushki7 » Code » FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies: C12832

mbed/TARGET_TEENSY3_1/MK20DX256.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:: tushki7
Date:: Sun Apr 12 15:45:52 2015 +0000
Revision:: 1:eb68c94a8ee5
Parent:: 0:60d829a0353a

A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

User	Revision	Line number	New contents of line
tushki7	0:60d829a0353a	1	/*
tushki7	0:60d829a0353a	2	** ###################################################################
tushki7	0:60d829a0353a	3	** Processors: MK20DX64VLH7
tushki7	0:60d829a0353a	4	** MK20DX128VLH7
tushki7	0:60d829a0353a	5	** MK20DX256VLH7
tushki7	0:60d829a0353a	6	** MK20DX64VLK7
tushki7	0:60d829a0353a	7	** MK20DX128VLK7
tushki7	0:60d829a0353a	8	** MK20DX256VLK7
tushki7	0:60d829a0353a	9	** MK20DX128VLL7
tushki7	0:60d829a0353a	10	** MK20DX256VLL7
tushki7	0:60d829a0353a	11	** MK20DX64VMB7
tushki7	0:60d829a0353a	12	** MK20DX128VMB7
tushki7	0:60d829a0353a	13	** MK20DX256VMB7
tushki7	0:60d829a0353a	14	** MK20DX128VML7
tushki7	0:60d829a0353a	15	** MK20DX256VML7
tushki7	0:60d829a0353a	16	**
tushki7	0:60d829a0353a	17	** Compilers: ARM Compiler
tushki7	0:60d829a0353a	18	** Freescale C/C++ for Embedded ARM
tushki7	0:60d829a0353a	19	** GNU C Compiler
tushki7	0:60d829a0353a	20	** IAR ANSI C/C++ Compiler for ARM
tushki7	0:60d829a0353a	21	**
tushki7	0:60d829a0353a	22	** Reference manual: Kxx (P1 silicon) Sub-Family Reference Manual Rev. 0, draft A Oct 2011
tushki7	0:60d829a0353a	23	** Version: rev. 1.0, 2012-01-15
tushki7	0:60d829a0353a	24	**
tushki7	0:60d829a0353a	25	** Abstract:
tushki7	0:60d829a0353a	26	** Provides a system configuration function and a global variable that
tushki7	0:60d829a0353a	27	** contains the system frequency. It configures the device and initializes
tushki7	0:60d829a0353a	28	** the oscillator (PLL) that is part of the microcontroller device.
tushki7	0:60d829a0353a	29	**
tushki7	0:60d829a0353a	30	** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
tushki7	0:60d829a0353a	31	**
tushki7	0:60d829a0353a	32	** http: www.freescale.com
tushki7	0:60d829a0353a	33	** mail: support@freescale.com
tushki7	0:60d829a0353a	34	**
tushki7	0:60d829a0353a	35	** Revisions:
tushki7	0:60d829a0353a	36	** - rev. 1.0 (2012-01-15)
tushki7	0:60d829a0353a	37	** Initial public version.
tushki7	0:60d829a0353a	38	**
tushki7	0:60d829a0353a	39	** ###################################################################
tushki7	0:60d829a0353a	40	*/
tushki7	0:60d829a0353a	41
tushki7	0:60d829a0353a	42	/**
tushki7	0:60d829a0353a	43	* @file MK20DX256.h
tushki7	0:60d829a0353a	44	* @version 2.0
tushki7	0:60d829a0353a	45	* @date 2012-03-19
tushki7	0:60d829a0353a	46	* @brief CMSIS Peripheral Access Layer for MK20DX256
tushki7	0:60d829a0353a	47	*
tushki7	0:60d829a0353a	48	* CMSIS Peripheral Access Layer for MK20DX256
tushki7	0:60d829a0353a	49	*/
tushki7	0:60d829a0353a	50
tushki7	0:60d829a0353a	51	#if !defined(MK20DX256_H_)
tushki7	0:60d829a0353a	52	#define MK20DX256_H_ /*< Symbol preventing repeated inclusion /
tushki7	0:60d829a0353a	53	#define MCU_MK20DX256
tushki7	0:60d829a0353a	54	/** Memory map major version (memory maps with equal major version number are
tushki7	0:60d829a0353a	55	* compatible) */
tushki7	0:60d829a0353a	56	#define MCU_MEM_MAP_VERSION 0x0200u
tushki7	0:60d829a0353a	57	/** Memory map minor version */
tushki7	0:60d829a0353a	58	#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
tushki7	0:60d829a0353a	59
tushki7	0:60d829a0353a	60	/**
tushki7	0:60d829a0353a	61	* @brief Macro to access a single bit of a peripheral register (bit band region
tushki7	0:60d829a0353a	62	* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
tushki7	0:60d829a0353a	63	* @param Reg Register to access.
tushki7	0:60d829a0353a	64	* @param Bit Bit number to access.
tushki7	0:60d829a0353a	65	* @return Value of the targeted bit in the bit band region.
tushki7	0:60d829a0353a	66	*/
tushki7	0:60d829a0353a	67	#define BITBAND_REG(Reg,Bit) (((uint32_t volatile)(0x42000000u + (32u((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u((uint32_t)(Bit))))))
tushki7	0:60d829a0353a	68
tushki7	0:60d829a0353a	69	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	70	-- Interrupt vector numbers
tushki7	0:60d829a0353a	71	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	72
tushki7	0:60d829a0353a	73	/**
tushki7	0:60d829a0353a	74	* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
tushki7	0:60d829a0353a	75	* @{
tushki7	0:60d829a0353a	76	*/
tushki7	0:60d829a0353a	77
tushki7	0:60d829a0353a	78	/** Interrupt Number Definitions */
tushki7	0:60d829a0353a	79	typedef enum IRQn {
tushki7	0:60d829a0353a	80	/* Core interrupts */
tushki7	0:60d829a0353a	81	NonMaskableInt_IRQn = -14, /*< Non Maskable Interrupt /
tushki7	0:60d829a0353a	82	MemoryManagement_IRQn = -12, /*< Cortex-M4 Memory Management Interrupt /
tushki7	0:60d829a0353a	83	BusFault_IRQn = -11, /*< Cortex-M4 Bus Fault Interrupt /
tushki7	0:60d829a0353a	84	UsageFault_IRQn = -10, /*< Cortex-M4 Usage Fault Interrupt /
tushki7	0:60d829a0353a	85	SVCall_IRQn = -5, /*< Cortex-M4 SV Call Interrupt /
tushki7	0:60d829a0353a	86	DebugMonitor_IRQn = -4, /*< Cortex-M4 Debug Monitor Interrupt /
tushki7	0:60d829a0353a	87	PendSV_IRQn = -2, /*< Cortex-M4 Pend SV Interrupt /
tushki7	0:60d829a0353a	88	SysTick_IRQn = -1, /*< Cortex-M4 System Tick Interrupt /
tushki7	0:60d829a0353a	89
tushki7	0:60d829a0353a	90	/* Device specific interrupts */
tushki7	0:60d829a0353a	91
tushki7	0:60d829a0353a	92	DMA0_IRQn = 0, /*< DMA channel 0 transfer complete interrupt /
tushki7	0:60d829a0353a	93	DMA1_IRQn = 1, /*< DMA channel 1 transfer complete interrupt /
tushki7	0:60d829a0353a	94	DMA2_IRQn = 2, /*< DMA channel 2 transfer complete interrupt /
tushki7	0:60d829a0353a	95	DMA3_IRQn = 3, /*< DMA channel 3 transfer complete interrupt /
tushki7	0:60d829a0353a	96	DMA4_IRQn = 4,
tushki7	0:60d829a0353a	97	DMA5_IRQn = 5,
tushki7	0:60d829a0353a	98	DMA6_IRQn = 6,
tushki7	0:60d829a0353a	99	DMA7_IRQn = 7,
tushki7	0:60d829a0353a	100	DMA8_IRQn = 8,
tushki7	0:60d829a0353a	101	DMA9_IRQn = 9,
tushki7	0:60d829a0353a	102	DMA10_IRQn = 10,
tushki7	0:60d829a0353a	103	DMA11_IRQn = 11,
tushki7	0:60d829a0353a	104	DMA12_IRQn = 12,
tushki7	0:60d829a0353a	105	DMA13_IRQn = 13,
tushki7	0:60d829a0353a	106	DMA14_IRQn = 14,
tushki7	0:60d829a0353a	107	DMA15_IRQn = 15,
tushki7	0:60d829a0353a	108	DMA_Error_IRQn = 16, /*< DMA error interrupt /
tushki7	0:60d829a0353a	109	Reserved33_IRQn = 17,
tushki7	0:60d829a0353a	110	FTFL_IRQn = 18, /*< FTFL interrupt /
tushki7	0:60d829a0353a	111	Read_Collision_IRQn = 19, /*< Read collision interrupt /
tushki7	0:60d829a0353a	112	LVD_LVW_IRQn = 20, /*< Low Voltage Detect, Low Voltage Warning /
tushki7	0:60d829a0353a	113	LLW_IRQn = 21, /*< Low Leakage Wakeup /
tushki7	0:60d829a0353a	114	Watchdog_IRQn = 22, /*< WDOG interrupt /
tushki7	0:60d829a0353a	115	Reserved39_IRQn = 23,
tushki7	0:60d829a0353a	116	I2C0_IRQn = 24, /*< I2C0 interrupt /
tushki7	0:60d829a0353a	117	I2C1_IRQn = 25,
tushki7	0:60d829a0353a	118	SPI0_IRQn = 26, /*< SPI0 interrupt /
tushki7	0:60d829a0353a	119	SPI1_IRQn = 27,
tushki7	0:60d829a0353a	120	Reserved44_IRQn = 28,
tushki7	0:60d829a0353a	121	CAN0_ORed_Message_buffer_IRQn = 29, /*< CAN0 OR'd message buffers interrupt /
tushki7	0:60d829a0353a	122	CAN0_Bus_Off_IRQn = 30, /*< CAN0 bus off interrupt /
tushki7	0:60d829a0353a	123	CAN0_Error_IRQn = 31, /*< CAN0 error interrupt /
tushki7	0:60d829a0353a	124	CAN0_Tx_Warning_IRQn = 32, /*< CAN0 Tx warning interrupt /
tushki7	0:60d829a0353a	125	CAN0_Rx_Warning_IRQn = 33, /*< CAN0 Rx warning interrupt /
tushki7	0:60d829a0353a	126	CAN0_Wake_Up_IRQn = 34, /*< CAN0 wake up interrupt /
tushki7	0:60d829a0353a	127	I2S0_Tx_IRQn = 35, /*< I2S0 transmit interrupt /
tushki7	0:60d829a0353a	128	I2S0_Rx_IRQn = 36, /*< I2S0 receive interrupt /
tushki7	0:60d829a0353a	129	Reserved53_IRQn = 37,
tushki7	0:60d829a0353a	130	Reserved54_IRQn = 38,
tushki7	0:60d829a0353a	131	Reserved55_IRQn = 39,
tushki7	0:60d829a0353a	132	Reserved56_IRQn = 40,
tushki7	0:60d829a0353a	133	Reserved57_IRQn = 41,
tushki7	0:60d829a0353a	134	Reserved58_IRQn = 42,
tushki7	0:60d829a0353a	135	Reserved59_IRQn = 43,
tushki7	0:60d829a0353a	136	UART0_LON_IRQn = 44, /*< UART0 LON interrupt /
tushki7	0:60d829a0353a	137	UART0_RX_TX_IRQn = 45, /*< UART0 receive/transmit interrupt /
tushki7	0:60d829a0353a	138	UART0_ERR_IRQn = 46, /*< UART0 error interrupt /
tushki7	0:60d829a0353a	139	UART1_RX_TX_IRQn = 47, /*< UART1 receive/transmit interrupt /
tushki7	0:60d829a0353a	140	UART1_ERR_IRQn = 48, /*< UART1 error interrupt /
tushki7	0:60d829a0353a	141	UART2_RX_TX_IRQn = 49, /*< UART2 receive/transmit interrupt /
tushki7	0:60d829a0353a	142	UART2_ERR_IRQn = 50, /*< UART2 error interrupt /
tushki7	0:60d829a0353a	143	Reserved67_IRQn = 51,
tushki7	0:60d829a0353a	144	Reserved68_IRQn = 52,
tushki7	0:60d829a0353a	145	Reserved69_IRQn = 53,
tushki7	0:60d829a0353a	146	Reserved70_IRQn = 54,
tushki7	0:60d829a0353a	147	Reserved71_IRQn = 55,
tushki7	0:60d829a0353a	148	Reserved72_IRQn = 56,
tushki7	0:60d829a0353a	149	ADC0_IRQn = 57, /*< ADC0 interrupt /
tushki7	0:60d829a0353a	150	ADC1_IRQn = 58,
tushki7	0:60d829a0353a	151	CMP0_IRQn = 59, /*< CMP0 interrupt /
tushki7	0:60d829a0353a	152	CMP1_IRQn = 60, /*< CMP1 interrupt /
tushki7	0:60d829a0353a	153	CMP2_IRQn = 61,
tushki7	0:60d829a0353a	154	FTM0_IRQn = 62, /*< FTM0 fault, overflow and channels interrupt /
tushki7	0:60d829a0353a	155	FTM1_IRQn = 63, /*< FTM1 fault, overflow and channels interrupt /
tushki7	0:60d829a0353a	156	FTM2_IRQn = 64,
tushki7	0:60d829a0353a	157	CMT_IRQn = 65, /*< CMT interrupt /
tushki7	0:60d829a0353a	158	RTC_IRQn = 66, /*< RTC interrupt /
tushki7	0:60d829a0353a	159	RTC_Seconds_IRQn = 67, /*< RTC seconds interrupt /
tushki7	0:60d829a0353a	160	PIT0_IRQn = 68, /*< PIT timer channel 0 interrupt /
tushki7	0:60d829a0353a	161	PIT1_IRQn = 69, /*< PIT timer channel 1 interrupt /
tushki7	0:60d829a0353a	162	PIT2_IRQn = 70, /*< PIT timer channel 2 interrupt /
tushki7	0:60d829a0353a	163	PIT3_IRQn = 71, /*< PIT timer channel 3 interrupt /
tushki7	0:60d829a0353a	164	PDB0_IRQn = 72, /*< PDB0 interrupt /
tushki7	0:60d829a0353a	165	USB0_IRQn = 73, /*< USB0 interrupt /
tushki7	0:60d829a0353a	166	USBDCD_IRQn = 74, /*< USBDCD interrupt /
tushki7	0:60d829a0353a	167	Reserved91_IRQn = 75,
tushki7	0:60d829a0353a	168	Reserved92_IRQn = 76,
tushki7	0:60d829a0353a	169	Reserved93_IRQn = 77,
tushki7	0:60d829a0353a	170	Reserved94_IRQn = 78,
tushki7	0:60d829a0353a	171	Reserved95_IRQn = 79,
tushki7	0:60d829a0353a	172	Reserved96_IRQn = 80,
tushki7	0:60d829a0353a	173	DAC0_IRQn = 81,
tushki7	0:60d829a0353a	174	Reserved98_IRQn = 82,
tushki7	0:60d829a0353a	175	TSI0_IRQn = 83, /*< TSI0 interrupt /
tushki7	0:60d829a0353a	176	MCG_IRQn = 84, /*< MCG interrupt /
tushki7	0:60d829a0353a	177	LPTimer_IRQn = 85, /*< LPTimer interrupt /
tushki7	0:60d829a0353a	178	Reserved102_IRQn = 86,
tushki7	0:60d829a0353a	179	PORTA_IRQn = 87, /*< Port A interrupt /
tushki7	0:60d829a0353a	180	PORTB_IRQn = 88, /*< Port B interrupt /
tushki7	0:60d829a0353a	181	PORTC_IRQn = 89, /*< Port C interrupt /
tushki7	0:60d829a0353a	182	PORTD_IRQn = 90, /*< Port D interrupt /
tushki7	0:60d829a0353a	183	PORTE_IRQn = 91, /*< Port E interrupt /
tushki7	0:60d829a0353a	184	Reserved108_IRQn = 92,
tushki7	0:60d829a0353a	185	Reserved109_IRQn = 93,
tushki7	0:60d829a0353a	186	SWI_IRQn = 94 /*< Software interrupt /
tushki7	0:60d829a0353a	187
tushki7	0:60d829a0353a	188	} IRQn_Type;
tushki7	0:60d829a0353a	189
tushki7	0:60d829a0353a	190	/**
tushki7	0:60d829a0353a	191	* @}
tushki7	0:60d829a0353a	192	/ / end of group Interrupt_vector_numbers */
tushki7	0:60d829a0353a	193
tushki7	0:60d829a0353a	194
tushki7	0:60d829a0353a	195	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	196	-- Cortex M4 Core Configuration
tushki7	0:60d829a0353a	197	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	198
tushki7	0:60d829a0353a	199	/**
tushki7	0:60d829a0353a	200	* @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
tushki7	0:60d829a0353a	201	* @{
tushki7	0:60d829a0353a	202	*/
tushki7	0:60d829a0353a	203
tushki7	0:60d829a0353a	204	#define __MPU_PRESENT 0 /*< Defines if an MPU is present or not /
tushki7	0:60d829a0353a	205	#define __NVIC_PRIO_BITS 4 /*< Number of priority bits implemented in the NVIC /
tushki7	0:60d829a0353a	206	#define __Vendor_SysTickConfig 0 /*< Vendor specific implementation of SysTickConfig is defined /
tushki7	0:60d829a0353a	207
tushki7	0:60d829a0353a	208	#include "core_cm4.h" /* Core Peripheral Access Layer */
tushki7	0:60d829a0353a	209	#include "system_MK20DX256.h" /* Device specific configuration file */
tushki7	0:60d829a0353a	210
tushki7	0:60d829a0353a	211	/**
tushki7	0:60d829a0353a	212	* @}
tushki7	0:60d829a0353a	213	/ / end of group Cortex_Core_Configuration */
tushki7	0:60d829a0353a	214
tushki7	0:60d829a0353a	215
tushki7	0:60d829a0353a	216	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	217	-- Device Peripheral Access Layer
tushki7	0:60d829a0353a	218	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	219
tushki7	0:60d829a0353a	220	/**
tushki7	0:60d829a0353a	221	* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
tushki7	0:60d829a0353a	222	* @{
tushki7	0:60d829a0353a	223	*/
tushki7	0:60d829a0353a	224
tushki7	0:60d829a0353a	225
tushki7	0:60d829a0353a	226	/*
tushki7	0:60d829a0353a	227	** Start of section using anonymous unions
tushki7	0:60d829a0353a	228	*/
tushki7	0:60d829a0353a	229
tushki7	0:60d829a0353a	230	#if defined(__ARMCC_VERSION)
tushki7	0:60d829a0353a	231	#pragma push
tushki7	0:60d829a0353a	232	#pragma anon_unions
tushki7	0:60d829a0353a	233	#elif defined(__CWCC__)
tushki7	0:60d829a0353a	234	#pragma push
tushki7	0:60d829a0353a	235	#pragma cpp_extensions on
tushki7	0:60d829a0353a	236	#elif defined(__GNUC__)
tushki7	0:60d829a0353a	237	/* anonymous unions are enabled by default */
tushki7	0:60d829a0353a	238	#elif defined(__IAR_SYSTEMS_ICC__)
tushki7	0:60d829a0353a	239	#pragma language=extended
tushki7	0:60d829a0353a	240	#else
tushki7	0:60d829a0353a	241	#error Not supported compiler type
tushki7	0:60d829a0353a	242	#endif
tushki7	0:60d829a0353a	243
tushki7	0:60d829a0353a	244	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	245	-- ADC Peripheral Access Layer
tushki7	0:60d829a0353a	246	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	247
tushki7	0:60d829a0353a	248	/**
tushki7	0:60d829a0353a	249	* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
tushki7	0:60d829a0353a	250	* @{
tushki7	0:60d829a0353a	251	*/
tushki7	0:60d829a0353a	252
tushki7	0:60d829a0353a	253	/** ADC - Register Layout Typedef */
tushki7	0:60d829a0353a	254	typedef struct {
tushki7	0:60d829a0353a	255	__IO uint32_t SC1[2]; /*< ADC status and control registers 1, array offset: 0x0, array step: 0x4 /
tushki7	0:60d829a0353a	256	__IO uint32_t CFG1; /*< ADC configuration register 1, offset: 0x8 /
tushki7	0:60d829a0353a	257	__IO uint32_t CFG2; /*< Configuration register 2, offset: 0xC /
tushki7	0:60d829a0353a	258	__I uint32_t R[2]; /*< ADC data result register, array offset: 0x10, array step: 0x4 /
tushki7	0:60d829a0353a	259	__IO uint32_t CV1; /*< Compare value registers, offset: 0x18 /
tushki7	0:60d829a0353a	260	__IO uint32_t CV2; /*< Compare value registers, offset: 0x1C /
tushki7	0:60d829a0353a	261	__IO uint32_t SC2; /*< Status and control register 2, offset: 0x20 /
tushki7	0:60d829a0353a	262	__IO uint32_t SC3; /*< Status and control register 3, offset: 0x24 /
tushki7	0:60d829a0353a	263	__IO uint32_t OFS; /*< ADC offset correction register, offset: 0x28 /
tushki7	0:60d829a0353a	264	__IO uint32_t PG; /*< ADC plus-side gain register, offset: 0x2C /
tushki7	0:60d829a0353a	265	__IO uint32_t MG; /*< ADC minus-side gain register, offset: 0x30 /
tushki7	0:60d829a0353a	266	__IO uint32_t CLPD; /*< ADC plus-side general calibration value register, offset: 0x34 /
tushki7	0:60d829a0353a	267	__IO uint32_t CLPS; /*< ADC plus-side general calibration value register, offset: 0x38 /
tushki7	0:60d829a0353a	268	__IO uint32_t CLP4; /*< ADC plus-side general calibration value register, offset: 0x3C /
tushki7	0:60d829a0353a	269	__IO uint32_t CLP3; /*< ADC plus-side general calibration value register, offset: 0x40 /
tushki7	0:60d829a0353a	270	__IO uint32_t CLP2; /*< ADC plus-side general calibration value register, offset: 0x44 /
tushki7	0:60d829a0353a	271	__IO uint32_t CLP1; /*< ADC plus-side general calibration value register, offset: 0x48 /
tushki7	0:60d829a0353a	272	__IO uint32_t CLP0; /*< ADC plus-side general calibration value register, offset: 0x4C /
tushki7	0:60d829a0353a	273	uint8_t RESERVED_0[4];
tushki7	0:60d829a0353a	274	__IO uint32_t CLMD; /*< ADC minus-side general calibration value register, offset: 0x54 /
tushki7	0:60d829a0353a	275	__IO uint32_t CLMS; /*< ADC minus-side general calibration value register, offset: 0x58 /
tushki7	0:60d829a0353a	276	__IO uint32_t CLM4; /*< ADC minus-side general calibration value register, offset: 0x5C /
tushki7	0:60d829a0353a	277	__IO uint32_t CLM3; /*< ADC minus-side general calibration value register, offset: 0x60 /
tushki7	0:60d829a0353a	278	__IO uint32_t CLM2; /*< ADC minus-side general calibration value register, offset: 0x64 /
tushki7	0:60d829a0353a	279	__IO uint32_t CLM1; /*< ADC minus-side general calibration value register, offset: 0x68 /
tushki7	0:60d829a0353a	280	__IO uint32_t CLM0; /*< ADC minus-side general calibration value register, offset: 0x6C /
tushki7	0:60d829a0353a	281	} ADC_Type;
tushki7	0:60d829a0353a	282
tushki7	0:60d829a0353a	283	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	284	-- ADC Register Masks
tushki7	0:60d829a0353a	285	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	286
tushki7	0:60d829a0353a	287	/**
tushki7	0:60d829a0353a	288	* @addtogroup ADC_Register_Masks ADC Register Masks
tushki7	0:60d829a0353a	289	* @{
tushki7	0:60d829a0353a	290	*/
tushki7	0:60d829a0353a	291
tushki7	0:60d829a0353a	292	/* SC1 Bit Fields */
tushki7	0:60d829a0353a	293	#define ADC_SC1_ADCH_MASK 0x1Fu
tushki7	0:60d829a0353a	294	#define ADC_SC1_ADCH_SHIFT 0
tushki7	0:60d829a0353a	295	#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
tushki7	0:60d829a0353a	296	#define ADC_SC1_DIFF_MASK 0x20u
tushki7	0:60d829a0353a	297	#define ADC_SC1_DIFF_SHIFT 5
tushki7	0:60d829a0353a	298	#define ADC_SC1_AIEN_MASK 0x40u
tushki7	0:60d829a0353a	299	#define ADC_SC1_AIEN_SHIFT 6
tushki7	0:60d829a0353a	300	#define ADC_SC1_COCO_MASK 0x80u
tushki7	0:60d829a0353a	301	#define ADC_SC1_COCO_SHIFT 7
tushki7	0:60d829a0353a	302	/* CFG1 Bit Fields */
tushki7	0:60d829a0353a	303	#define ADC_CFG1_ADICLK_MASK 0x3u
tushki7	0:60d829a0353a	304	#define ADC_CFG1_ADICLK_SHIFT 0
tushki7	0:60d829a0353a	305	#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
tushki7	0:60d829a0353a	306	#define ADC_CFG1_MODE_MASK 0xCu
tushki7	0:60d829a0353a	307	#define ADC_CFG1_MODE_SHIFT 2
tushki7	0:60d829a0353a	308	#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
tushki7	0:60d829a0353a	309	#define ADC_CFG1_ADLSMP_MASK 0x10u
tushki7	0:60d829a0353a	310	#define ADC_CFG1_ADLSMP_SHIFT 4
tushki7	0:60d829a0353a	311	#define ADC_CFG1_ADIV_MASK 0x60u
tushki7	0:60d829a0353a	312	#define ADC_CFG1_ADIV_SHIFT 5
tushki7	0:60d829a0353a	313	#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
tushki7	0:60d829a0353a	314	#define ADC_CFG1_ADLPC_MASK 0x80u
tushki7	0:60d829a0353a	315	#define ADC_CFG1_ADLPC_SHIFT 7
tushki7	0:60d829a0353a	316	/* CFG2 Bit Fields */
tushki7	0:60d829a0353a	317	#define ADC_CFG2_ADLSTS_MASK 0x3u
tushki7	0:60d829a0353a	318	#define ADC_CFG2_ADLSTS_SHIFT 0
tushki7	0:60d829a0353a	319	#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
tushki7	0:60d829a0353a	320	#define ADC_CFG2_ADHSC_MASK 0x4u
tushki7	0:60d829a0353a	321	#define ADC_CFG2_ADHSC_SHIFT 2
tushki7	0:60d829a0353a	322	#define ADC_CFG2_ADACKEN_MASK 0x8u
tushki7	0:60d829a0353a	323	#define ADC_CFG2_ADACKEN_SHIFT 3
tushki7	0:60d829a0353a	324	#define ADC_CFG2_MUXSEL_MASK 0x10u
tushki7	0:60d829a0353a	325	#define ADC_CFG2_MUXSEL_SHIFT 4
tushki7	0:60d829a0353a	326	/* R Bit Fields */
tushki7	0:60d829a0353a	327	#define ADC_R_D_MASK 0xFFFFu
tushki7	0:60d829a0353a	328	#define ADC_R_D_SHIFT 0
tushki7	0:60d829a0353a	329	#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
tushki7	0:60d829a0353a	330	/* CV1 Bit Fields */
tushki7	0:60d829a0353a	331	#define ADC_CV1_CV_MASK 0xFFFFu
tushki7	0:60d829a0353a	332	#define ADC_CV1_CV_SHIFT 0
tushki7	0:60d829a0353a	333	#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
tushki7	0:60d829a0353a	334	/* CV2 Bit Fields */
tushki7	0:60d829a0353a	335	#define ADC_CV2_CV_MASK 0xFFFFu
tushki7	0:60d829a0353a	336	#define ADC_CV2_CV_SHIFT 0
tushki7	0:60d829a0353a	337	#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
tushki7	0:60d829a0353a	338	/* SC2 Bit Fields */
tushki7	0:60d829a0353a	339	#define ADC_SC2_REFSEL_MASK 0x3u
tushki7	0:60d829a0353a	340	#define ADC_SC2_REFSEL_SHIFT 0
tushki7	0:60d829a0353a	341	#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
tushki7	0:60d829a0353a	342	#define ADC_SC2_DMAEN_MASK 0x4u
tushki7	0:60d829a0353a	343	#define ADC_SC2_DMAEN_SHIFT 2
tushki7	0:60d829a0353a	344	#define ADC_SC2_ACREN_MASK 0x8u
tushki7	0:60d829a0353a	345	#define ADC_SC2_ACREN_SHIFT 3
tushki7	0:60d829a0353a	346	#define ADC_SC2_ACFGT_MASK 0x10u
tushki7	0:60d829a0353a	347	#define ADC_SC2_ACFGT_SHIFT 4
tushki7	0:60d829a0353a	348	#define ADC_SC2_ACFE_MASK 0x20u
tushki7	0:60d829a0353a	349	#define ADC_SC2_ACFE_SHIFT 5
tushki7	0:60d829a0353a	350	#define ADC_SC2_ADTRG_MASK 0x40u
tushki7	0:60d829a0353a	351	#define ADC_SC2_ADTRG_SHIFT 6
tushki7	0:60d829a0353a	352	#define ADC_SC2_ADACT_MASK 0x80u
tushki7	0:60d829a0353a	353	#define ADC_SC2_ADACT_SHIFT 7
tushki7	0:60d829a0353a	354	/* SC3 Bit Fields */
tushki7	0:60d829a0353a	355	#define ADC_SC3_AVGS_MASK 0x3u
tushki7	0:60d829a0353a	356	#define ADC_SC3_AVGS_SHIFT 0
tushki7	0:60d829a0353a	357	#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
tushki7	0:60d829a0353a	358	#define ADC_SC3_AVGE_MASK 0x4u
tushki7	0:60d829a0353a	359	#define ADC_SC3_AVGE_SHIFT 2
tushki7	0:60d829a0353a	360	#define ADC_SC3_ADCO_MASK 0x8u
tushki7	0:60d829a0353a	361	#define ADC_SC3_ADCO_SHIFT 3
tushki7	0:60d829a0353a	362	#define ADC_SC3_CALF_MASK 0x40u
tushki7	0:60d829a0353a	363	#define ADC_SC3_CALF_SHIFT 6
tushki7	0:60d829a0353a	364	#define ADC_SC3_CAL_MASK 0x80u
tushki7	0:60d829a0353a	365	#define ADC_SC3_CAL_SHIFT 7
tushki7	0:60d829a0353a	366	/* OFS Bit Fields */
tushki7	0:60d829a0353a	367	#define ADC_OFS_OFS_MASK 0xFFFFu
tushki7	0:60d829a0353a	368	#define ADC_OFS_OFS_SHIFT 0
tushki7	0:60d829a0353a	369	#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
tushki7	0:60d829a0353a	370	/* PG Bit Fields */
tushki7	0:60d829a0353a	371	#define ADC_PG_PG_MASK 0xFFFFu
tushki7	0:60d829a0353a	372	#define ADC_PG_PG_SHIFT 0
tushki7	0:60d829a0353a	373	#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
tushki7	0:60d829a0353a	374	/* MG Bit Fields */
tushki7	0:60d829a0353a	375	#define ADC_MG_MG_MASK 0xFFFFu
tushki7	0:60d829a0353a	376	#define ADC_MG_MG_SHIFT 0
tushki7	0:60d829a0353a	377	#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
tushki7	0:60d829a0353a	378	/* CLPD Bit Fields */
tushki7	0:60d829a0353a	379	#define ADC_CLPD_CLPD_MASK 0x3Fu
tushki7	0:60d829a0353a	380	#define ADC_CLPD_CLPD_SHIFT 0
tushki7	0:60d829a0353a	381	#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
tushki7	0:60d829a0353a	382	/* CLPS Bit Fields */
tushki7	0:60d829a0353a	383	#define ADC_CLPS_CLPS_MASK 0x3Fu
tushki7	0:60d829a0353a	384	#define ADC_CLPS_CLPS_SHIFT 0
tushki7	0:60d829a0353a	385	#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
tushki7	0:60d829a0353a	386	/* CLP4 Bit Fields */
tushki7	0:60d829a0353a	387	#define ADC_CLP4_CLP4_MASK 0x3FFu
tushki7	0:60d829a0353a	388	#define ADC_CLP4_CLP4_SHIFT 0
tushki7	0:60d829a0353a	389	#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
tushki7	0:60d829a0353a	390	/* CLP3 Bit Fields */
tushki7	0:60d829a0353a	391	#define ADC_CLP3_CLP3_MASK 0x1FFu
tushki7	0:60d829a0353a	392	#define ADC_CLP3_CLP3_SHIFT 0
tushki7	0:60d829a0353a	393	#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
tushki7	0:60d829a0353a	394	/* CLP2 Bit Fields */
tushki7	0:60d829a0353a	395	#define ADC_CLP2_CLP2_MASK 0xFFu
tushki7	0:60d829a0353a	396	#define ADC_CLP2_CLP2_SHIFT 0
tushki7	0:60d829a0353a	397	#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
tushki7	0:60d829a0353a	398	/* CLP1 Bit Fields */
tushki7	0:60d829a0353a	399	#define ADC_CLP1_CLP1_MASK 0x7Fu
tushki7	0:60d829a0353a	400	#define ADC_CLP1_CLP1_SHIFT 0
tushki7	0:60d829a0353a	401	#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
tushki7	0:60d829a0353a	402	/* CLP0 Bit Fields */
tushki7	0:60d829a0353a	403	#define ADC_CLP0_CLP0_MASK 0x3Fu
tushki7	0:60d829a0353a	404	#define ADC_CLP0_CLP0_SHIFT 0
tushki7	0:60d829a0353a	405	#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
tushki7	0:60d829a0353a	406	/* CLMD Bit Fields */
tushki7	0:60d829a0353a	407	#define ADC_CLMD_CLMD_MASK 0x3Fu
tushki7	0:60d829a0353a	408	#define ADC_CLMD_CLMD_SHIFT 0
tushki7	0:60d829a0353a	409	#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
tushki7	0:60d829a0353a	410	/* CLMS Bit Fields */
tushki7	0:60d829a0353a	411	#define ADC_CLMS_CLMS_MASK 0x3Fu
tushki7	0:60d829a0353a	412	#define ADC_CLMS_CLMS_SHIFT 0
tushki7	0:60d829a0353a	413	#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
tushki7	0:60d829a0353a	414	/* CLM4 Bit Fields */
tushki7	0:60d829a0353a	415	#define ADC_CLM4_CLM4_MASK 0x3FFu
tushki7	0:60d829a0353a	416	#define ADC_CLM4_CLM4_SHIFT 0
tushki7	0:60d829a0353a	417	#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
tushki7	0:60d829a0353a	418	/* CLM3 Bit Fields */
tushki7	0:60d829a0353a	419	#define ADC_CLM3_CLM3_MASK 0x1FFu
tushki7	0:60d829a0353a	420	#define ADC_CLM3_CLM3_SHIFT 0
tushki7	0:60d829a0353a	421	#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
tushki7	0:60d829a0353a	422	/* CLM2 Bit Fields */
tushki7	0:60d829a0353a	423	#define ADC_CLM2_CLM2_MASK 0xFFu
tushki7	0:60d829a0353a	424	#define ADC_CLM2_CLM2_SHIFT 0
tushki7	0:60d829a0353a	425	#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
tushki7	0:60d829a0353a	426	/* CLM1 Bit Fields */
tushki7	0:60d829a0353a	427	#define ADC_CLM1_CLM1_MASK 0x7Fu
tushki7	0:60d829a0353a	428	#define ADC_CLM1_CLM1_SHIFT 0
tushki7	0:60d829a0353a	429	#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
tushki7	0:60d829a0353a	430	/* CLM0 Bit Fields */
tushki7	0:60d829a0353a	431	#define ADC_CLM0_CLM0_MASK 0x3Fu
tushki7	0:60d829a0353a	432	#define ADC_CLM0_CLM0_SHIFT 0
tushki7	0:60d829a0353a	433	#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
tushki7	0:60d829a0353a	434
tushki7	0:60d829a0353a	435	/**
tushki7	0:60d829a0353a	436	* @}
tushki7	0:60d829a0353a	437	/ / end of group ADC_Register_Masks */
tushki7	0:60d829a0353a	438
tushki7	0:60d829a0353a	439
tushki7	0:60d829a0353a	440	/* ADC - Peripheral instance base addresses */
tushki7	0:60d829a0353a	441	/** Peripheral ADC0 base address */
tushki7	0:60d829a0353a	442	#define ADC0_BASE (0x4003B000u)
tushki7	0:60d829a0353a	443	/** Peripheral ADC0 base pointer */
tushki7	0:60d829a0353a	444	#define ADC0 ((ADC_Type *)ADC0_BASE)
tushki7	0:60d829a0353a	445
tushki7	0:60d829a0353a	446	/**
tushki7	0:60d829a0353a	447	* @}
tushki7	0:60d829a0353a	448	/ / end of group ADC_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	449
tushki7	0:60d829a0353a	450
tushki7	0:60d829a0353a	451	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	452	-- CMP Peripheral Access Layer
tushki7	0:60d829a0353a	453	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	454
tushki7	0:60d829a0353a	455	/**
tushki7	0:60d829a0353a	456	* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
tushki7	0:60d829a0353a	457	* @{
tushki7	0:60d829a0353a	458	*/
tushki7	0:60d829a0353a	459
tushki7	0:60d829a0353a	460	/** CMP - Register Layout Typedef */
tushki7	0:60d829a0353a	461	typedef struct {
tushki7	0:60d829a0353a	462	__IO uint8_t CR0; /*< CMP Control Register 0, offset: 0x0 /
tushki7	0:60d829a0353a	463	__IO uint8_t CR1; /*< CMP Control Register 1, offset: 0x1 /
tushki7	0:60d829a0353a	464	__IO uint8_t FPR; /*< CMP Filter Period Register, offset: 0x2 /
tushki7	0:60d829a0353a	465	__IO uint8_t SCR; /*< CMP Status and Control Register, offset: 0x3 /
tushki7	0:60d829a0353a	466	__IO uint8_t DACCR; /*< DAC Control Register, offset: 0x4 /
tushki7	0:60d829a0353a	467	__IO uint8_t MUXCR; /*< MUX Control Register, offset: 0x5 /
tushki7	0:60d829a0353a	468	} CMP_Type;
tushki7	0:60d829a0353a	469
tushki7	0:60d829a0353a	470	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	471	-- CMP Register Masks
tushki7	0:60d829a0353a	472	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	473
tushki7	0:60d829a0353a	474	/**
tushki7	0:60d829a0353a	475	* @addtogroup CMP_Register_Masks CMP Register Masks
tushki7	0:60d829a0353a	476	* @{
tushki7	0:60d829a0353a	477	*/
tushki7	0:60d829a0353a	478
tushki7	0:60d829a0353a	479	/* CR0 Bit Fields */
tushki7	0:60d829a0353a	480	#define CMP_CR0_HYSTCTR_MASK 0x3u
tushki7	0:60d829a0353a	481	#define CMP_CR0_HYSTCTR_SHIFT 0
tushki7	0:60d829a0353a	482	#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
tushki7	0:60d829a0353a	483	#define CMP_CR0_FILTER_CNT_MASK 0x70u
tushki7	0:60d829a0353a	484	#define CMP_CR0_FILTER_CNT_SHIFT 4
tushki7	0:60d829a0353a	485	#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
tushki7	0:60d829a0353a	486	/* CR1 Bit Fields */
tushki7	0:60d829a0353a	487	#define CMP_CR1_EN_MASK 0x1u
tushki7	0:60d829a0353a	488	#define CMP_CR1_EN_SHIFT 0
tushki7	0:60d829a0353a	489	#define CMP_CR1_OPE_MASK 0x2u
tushki7	0:60d829a0353a	490	#define CMP_CR1_OPE_SHIFT 1
tushki7	0:60d829a0353a	491	#define CMP_CR1_COS_MASK 0x4u
tushki7	0:60d829a0353a	492	#define CMP_CR1_COS_SHIFT 2
tushki7	0:60d829a0353a	493	#define CMP_CR1_INV_MASK 0x8u
tushki7	0:60d829a0353a	494	#define CMP_CR1_INV_SHIFT 3
tushki7	0:60d829a0353a	495	#define CMP_CR1_PMODE_MASK 0x10u
tushki7	0:60d829a0353a	496	#define CMP_CR1_PMODE_SHIFT 4
tushki7	0:60d829a0353a	497	#define CMP_CR1_WE_MASK 0x40u
tushki7	0:60d829a0353a	498	#define CMP_CR1_WE_SHIFT 6
tushki7	0:60d829a0353a	499	#define CMP_CR1_SE_MASK 0x80u
tushki7	0:60d829a0353a	500	#define CMP_CR1_SE_SHIFT 7
tushki7	0:60d829a0353a	501	/* FPR Bit Fields */
tushki7	0:60d829a0353a	502	#define CMP_FPR_FILT_PER_MASK 0xFFu
tushki7	0:60d829a0353a	503	#define CMP_FPR_FILT_PER_SHIFT 0
tushki7	0:60d829a0353a	504	#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
tushki7	0:60d829a0353a	505	/* SCR Bit Fields */
tushki7	0:60d829a0353a	506	#define CMP_SCR_COUT_MASK 0x1u
tushki7	0:60d829a0353a	507	#define CMP_SCR_COUT_SHIFT 0
tushki7	0:60d829a0353a	508	#define CMP_SCR_CFF_MASK 0x2u
tushki7	0:60d829a0353a	509	#define CMP_SCR_CFF_SHIFT 1
tushki7	0:60d829a0353a	510	#define CMP_SCR_CFR_MASK 0x4u
tushki7	0:60d829a0353a	511	#define CMP_SCR_CFR_SHIFT 2
tushki7	0:60d829a0353a	512	#define CMP_SCR_IEF_MASK 0x8u
tushki7	0:60d829a0353a	513	#define CMP_SCR_IEF_SHIFT 3
tushki7	0:60d829a0353a	514	#define CMP_SCR_IER_MASK 0x10u
tushki7	0:60d829a0353a	515	#define CMP_SCR_IER_SHIFT 4
tushki7	0:60d829a0353a	516	#define CMP_SCR_DMAEN_MASK 0x40u
tushki7	0:60d829a0353a	517	#define CMP_SCR_DMAEN_SHIFT 6
tushki7	0:60d829a0353a	518	/* DACCR Bit Fields */
tushki7	0:60d829a0353a	519	#define CMP_DACCR_VOSEL_MASK 0x3Fu
tushki7	0:60d829a0353a	520	#define CMP_DACCR_VOSEL_SHIFT 0
tushki7	0:60d829a0353a	521	#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
tushki7	0:60d829a0353a	522	#define CMP_DACCR_VRSEL_MASK 0x40u
tushki7	0:60d829a0353a	523	#define CMP_DACCR_VRSEL_SHIFT 6
tushki7	0:60d829a0353a	524	#define CMP_DACCR_DACEN_MASK 0x80u
tushki7	0:60d829a0353a	525	#define CMP_DACCR_DACEN_SHIFT 7
tushki7	0:60d829a0353a	526	/* MUXCR Bit Fields */
tushki7	0:60d829a0353a	527	#define CMP_MUXCR_MSEL_MASK 0x7u
tushki7	0:60d829a0353a	528	#define CMP_MUXCR_MSEL_SHIFT 0
tushki7	0:60d829a0353a	529	#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
tushki7	0:60d829a0353a	530	#define CMP_MUXCR_PSEL_MASK 0x38u
tushki7	0:60d829a0353a	531	#define CMP_MUXCR_PSEL_SHIFT 3
tushki7	0:60d829a0353a	532	#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
tushki7	0:60d829a0353a	533
tushki7	0:60d829a0353a	534	/**
tushki7	0:60d829a0353a	535	* @}
tushki7	0:60d829a0353a	536	/ / end of group CMP_Register_Masks */
tushki7	0:60d829a0353a	537
tushki7	0:60d829a0353a	538
tushki7	0:60d829a0353a	539	/* CMP - Peripheral instance base addresses */
tushki7	0:60d829a0353a	540	/** Peripheral CMP0 base address */
tushki7	0:60d829a0353a	541	#define CMP0_BASE (0x40073000u)
tushki7	0:60d829a0353a	542	/** Peripheral CMP0 base pointer */
tushki7	0:60d829a0353a	543	#define CMP0 ((CMP_Type *)CMP0_BASE)
tushki7	0:60d829a0353a	544	/** Peripheral CMP1 base address */
tushki7	0:60d829a0353a	545	#define CMP1_BASE (0x40073008u)
tushki7	0:60d829a0353a	546	/** Peripheral CMP1 base pointer */
tushki7	0:60d829a0353a	547	#define CMP1 ((CMP_Type *)CMP1_BASE)
tushki7	0:60d829a0353a	548
tushki7	0:60d829a0353a	549	/**
tushki7	0:60d829a0353a	550	* @}
tushki7	0:60d829a0353a	551	/ / end of group CMP_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	552
tushki7	0:60d829a0353a	553
tushki7	0:60d829a0353a	554	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	555	-- CMT Peripheral Access Layer
tushki7	0:60d829a0353a	556	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	557
tushki7	0:60d829a0353a	558	/**
tushki7	0:60d829a0353a	559	* @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
tushki7	0:60d829a0353a	560	* @{
tushki7	0:60d829a0353a	561	*/
tushki7	0:60d829a0353a	562
tushki7	0:60d829a0353a	563	/** CMT - Register Layout Typedef */
tushki7	0:60d829a0353a	564	typedef struct {
tushki7	0:60d829a0353a	565	__IO uint8_t CGH1; /*< CMT Carrier Generator High Data Register 1, offset: 0x0 /
tushki7	0:60d829a0353a	566	__IO uint8_t CGL1; /*< CMT Carrier Generator Low Data Register 1, offset: 0x1 /
tushki7	0:60d829a0353a	567	__IO uint8_t CGH2; /*< CMT Carrier Generator High Data Register 2, offset: 0x2 /
tushki7	0:60d829a0353a	568	__IO uint8_t CGL2; /*< CMT Carrier Generator Low Data Register 2, offset: 0x3 /
tushki7	0:60d829a0353a	569	__IO uint8_t OC; /*< CMT Output Control Register, offset: 0x4 /
tushki7	0:60d829a0353a	570	__IO uint8_t MSC; /*< CMT Modulator Status and Control Register, offset: 0x5 /
tushki7	0:60d829a0353a	571	__IO uint8_t CMD1; /*< CMT Modulator Data Register Mark High, offset: 0x6 /
tushki7	0:60d829a0353a	572	__IO uint8_t CMD2; /*< CMT Modulator Data Register Mark Low, offset: 0x7 /
tushki7	0:60d829a0353a	573	__IO uint8_t CMD3; /*< CMT Modulator Data Register Space High, offset: 0x8 /
tushki7	0:60d829a0353a	574	__IO uint8_t CMD4; /*< CMT Modulator Data Register Space Low, offset: 0x9 /
tushki7	0:60d829a0353a	575	__IO uint8_t PPS; /*< CMT Primary Prescaler Register, offset: 0xA /
tushki7	0:60d829a0353a	576	__IO uint8_t DMA; /*< CMT Direct Memory Access, offset: 0xB /
tushki7	0:60d829a0353a	577	} CMT_Type;
tushki7	0:60d829a0353a	578
tushki7	0:60d829a0353a	579	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	580	-- CMT Register Masks
tushki7	0:60d829a0353a	581	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	582
tushki7	0:60d829a0353a	583	/**
tushki7	0:60d829a0353a	584	* @addtogroup CMT_Register_Masks CMT Register Masks
tushki7	0:60d829a0353a	585	* @{
tushki7	0:60d829a0353a	586	*/
tushki7	0:60d829a0353a	587
tushki7	0:60d829a0353a	588	/* CGH1 Bit Fields */
tushki7	0:60d829a0353a	589	#define CMT_CGH1_PH_MASK 0xFFu
tushki7	0:60d829a0353a	590	#define CMT_CGH1_PH_SHIFT 0
tushki7	0:60d829a0353a	591	#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
tushki7	0:60d829a0353a	592	/* CGL1 Bit Fields */
tushki7	0:60d829a0353a	593	#define CMT_CGL1_PL_MASK 0xFFu
tushki7	0:60d829a0353a	594	#define CMT_CGL1_PL_SHIFT 0
tushki7	0:60d829a0353a	595	#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
tushki7	0:60d829a0353a	596	/* CGH2 Bit Fields */
tushki7	0:60d829a0353a	597	#define CMT_CGH2_SH_MASK 0xFFu
tushki7	0:60d829a0353a	598	#define CMT_CGH2_SH_SHIFT 0
tushki7	0:60d829a0353a	599	#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
tushki7	0:60d829a0353a	600	/* CGL2 Bit Fields */
tushki7	0:60d829a0353a	601	#define CMT_CGL2_SL_MASK 0xFFu
tushki7	0:60d829a0353a	602	#define CMT_CGL2_SL_SHIFT 0
tushki7	0:60d829a0353a	603	#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
tushki7	0:60d829a0353a	604	/* OC Bit Fields */
tushki7	0:60d829a0353a	605	#define CMT_OC_IROPEN_MASK 0x20u
tushki7	0:60d829a0353a	606	#define CMT_OC_IROPEN_SHIFT 5
tushki7	0:60d829a0353a	607	#define CMT_OC_CMTPOL_MASK 0x40u
tushki7	0:60d829a0353a	608	#define CMT_OC_CMTPOL_SHIFT 6
tushki7	0:60d829a0353a	609	#define CMT_OC_IROL_MASK 0x80u
tushki7	0:60d829a0353a	610	#define CMT_OC_IROL_SHIFT 7
tushki7	0:60d829a0353a	611	/* MSC Bit Fields */
tushki7	0:60d829a0353a	612	#define CMT_MSC_MCGEN_MASK 0x1u
tushki7	0:60d829a0353a	613	#define CMT_MSC_MCGEN_SHIFT 0
tushki7	0:60d829a0353a	614	#define CMT_MSC_EOCIE_MASK 0x2u
tushki7	0:60d829a0353a	615	#define CMT_MSC_EOCIE_SHIFT 1
tushki7	0:60d829a0353a	616	#define CMT_MSC_FSK_MASK 0x4u
tushki7	0:60d829a0353a	617	#define CMT_MSC_FSK_SHIFT 2
tushki7	0:60d829a0353a	618	#define CMT_MSC_BASE_MASK 0x8u
tushki7	0:60d829a0353a	619	#define CMT_MSC_BASE_SHIFT 3
tushki7	0:60d829a0353a	620	#define CMT_MSC_EXSPC_MASK 0x10u
tushki7	0:60d829a0353a	621	#define CMT_MSC_EXSPC_SHIFT 4
tushki7	0:60d829a0353a	622	#define CMT_MSC_CMTDIV_MASK 0x60u
tushki7	0:60d829a0353a	623	#define CMT_MSC_CMTDIV_SHIFT 5
tushki7	0:60d829a0353a	624	#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
tushki7	0:60d829a0353a	625	#define CMT_MSC_EOCF_MASK 0x80u
tushki7	0:60d829a0353a	626	#define CMT_MSC_EOCF_SHIFT 7
tushki7	0:60d829a0353a	627	/* CMD1 Bit Fields */
tushki7	0:60d829a0353a	628	#define CMT_CMD1_MB_MASK 0xFFu
tushki7	0:60d829a0353a	629	#define CMT_CMD1_MB_SHIFT 0
tushki7	0:60d829a0353a	630	#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
tushki7	0:60d829a0353a	631	/* CMD2 Bit Fields */
tushki7	0:60d829a0353a	632	#define CMT_CMD2_MB_MASK 0xFFu
tushki7	0:60d829a0353a	633	#define CMT_CMD2_MB_SHIFT 0
tushki7	0:60d829a0353a	634	#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
tushki7	0:60d829a0353a	635	/* CMD3 Bit Fields */
tushki7	0:60d829a0353a	636	#define CMT_CMD3_SB_MASK 0xFFu
tushki7	0:60d829a0353a	637	#define CMT_CMD3_SB_SHIFT 0
tushki7	0:60d829a0353a	638	#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
tushki7	0:60d829a0353a	639	/* CMD4 Bit Fields */
tushki7	0:60d829a0353a	640	#define CMT_CMD4_SB_MASK 0xFFu
tushki7	0:60d829a0353a	641	#define CMT_CMD4_SB_SHIFT 0
tushki7	0:60d829a0353a	642	#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
tushki7	0:60d829a0353a	643	/* PPS Bit Fields */
tushki7	0:60d829a0353a	644	#define CMT_PPS_PPSDIV_MASK 0xFu
tushki7	0:60d829a0353a	645	#define CMT_PPS_PPSDIV_SHIFT 0
tushki7	0:60d829a0353a	646	#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
tushki7	0:60d829a0353a	647	/* DMA Bit Fields */
tushki7	0:60d829a0353a	648	#define CMT_DMA_DMA_MASK 0x1u
tushki7	0:60d829a0353a	649	#define CMT_DMA_DMA_SHIFT 0
tushki7	0:60d829a0353a	650
tushki7	0:60d829a0353a	651	/**
tushki7	0:60d829a0353a	652	* @}
tushki7	0:60d829a0353a	653	/ / end of group CMT_Register_Masks */
tushki7	0:60d829a0353a	654
tushki7	0:60d829a0353a	655
tushki7	0:60d829a0353a	656	/* CMT - Peripheral instance base addresses */
tushki7	0:60d829a0353a	657	/** Peripheral CMT base address */
tushki7	0:60d829a0353a	658	#define CMT_BASE (0x40062000u)
tushki7	0:60d829a0353a	659	/** Peripheral CMT base pointer */
tushki7	0:60d829a0353a	660	#define CMT ((CMT_Type *)CMT_BASE)
tushki7	0:60d829a0353a	661
tushki7	0:60d829a0353a	662	/**
tushki7	0:60d829a0353a	663	* @}
tushki7	0:60d829a0353a	664	/ / end of group CMT_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	665
tushki7	0:60d829a0353a	666
tushki7	0:60d829a0353a	667	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	668	-- CRC Peripheral Access Layer
tushki7	0:60d829a0353a	669	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	670
tushki7	0:60d829a0353a	671	/**
tushki7	0:60d829a0353a	672	* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
tushki7	0:60d829a0353a	673	* @{
tushki7	0:60d829a0353a	674	*/
tushki7	0:60d829a0353a	675
tushki7	0:60d829a0353a	676	/** CRC - Register Layout Typedef */
tushki7	0:60d829a0353a	677	typedef struct {
tushki7	0:60d829a0353a	678	union { /* offset: 0x0 */
tushki7	0:60d829a0353a	679	struct { /* offset: 0x0 */
tushki7	0:60d829a0353a	680	__IO uint16_t CRCL; /*< CRC_CRCL register., offset: 0x0 /
tushki7	0:60d829a0353a	681	__IO uint16_t CRCH; /*< CRC_CRCH register., offset: 0x2 /
tushki7	0:60d829a0353a	682	} ACCESS16BIT;
tushki7	0:60d829a0353a	683	__IO uint32_t CRC; /*< CRC Data Register, offset: 0x0 /
tushki7	0:60d829a0353a	684	struct { /* offset: 0x0 */
tushki7	0:60d829a0353a	685	__IO uint8_t CRCLL; /*< CRC_CRCLL register., offset: 0x0 /
tushki7	0:60d829a0353a	686	__IO uint8_t CRCLU; /*< CRC_CRCLU register., offset: 0x1 /
tushki7	0:60d829a0353a	687	__IO uint8_t CRCHL; /*< CRC_CRCHL register., offset: 0x2 /
tushki7	0:60d829a0353a	688	__IO uint8_t CRCHU; /*< CRC_CRCHU register., offset: 0x3 /
tushki7	0:60d829a0353a	689	} ACCESS8BIT;
tushki7	0:60d829a0353a	690	};
tushki7	0:60d829a0353a	691	union { /* offset: 0x4 */
tushki7	0:60d829a0353a	692	struct { /* offset: 0x4 */
tushki7	0:60d829a0353a	693	__IO uint16_t GPOLYL; /*< CRC_GPOLYL register., offset: 0x4 /
tushki7	0:60d829a0353a	694	__IO uint16_t GPOLYH; /*< CRC_GPOLYH register., offset: 0x6 /
tushki7	0:60d829a0353a	695	} GPOLY_ACCESS16BIT;
tushki7	0:60d829a0353a	696	__IO uint32_t GPOLY; /*< CRC Polynomial Register, offset: 0x4 /
tushki7	0:60d829a0353a	697	struct { /* offset: 0x4 */
tushki7	0:60d829a0353a	698	__IO uint8_t GPOLYLL; /*< CRC_GPOLYLL register., offset: 0x4 /
tushki7	0:60d829a0353a	699	__IO uint8_t GPOLYLU; /*< CRC_GPOLYLU register., offset: 0x5 /
tushki7	0:60d829a0353a	700	__IO uint8_t GPOLYHL; /*< CRC_GPOLYHL register., offset: 0x6 /
tushki7	0:60d829a0353a	701	__IO uint8_t GPOLYHU; /*< CRC_GPOLYHU register., offset: 0x7 /
tushki7	0:60d829a0353a	702	} GPOLY_ACCESS8BIT;
tushki7	0:60d829a0353a	703	};
tushki7	0:60d829a0353a	704	union { /* offset: 0x8 */
tushki7	0:60d829a0353a	705	__IO uint32_t CTRL; /*< CRC Control Register, offset: 0x8 /
tushki7	0:60d829a0353a	706	struct { /* offset: 0x8 */
tushki7	0:60d829a0353a	707	uint8_t RESERVED_0[3];
tushki7	0:60d829a0353a	708	__IO uint8_t CTRLHU; /*< CRC_CTRLHU register., offset: 0xB /
tushki7	0:60d829a0353a	709	} CTRL_ACCESS8BIT;
tushki7	0:60d829a0353a	710	};
tushki7	0:60d829a0353a	711	} CRC_Type;
tushki7	0:60d829a0353a	712
tushki7	0:60d829a0353a	713	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	714	-- CRC Register Masks
tushki7	0:60d829a0353a	715	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	716
tushki7	0:60d829a0353a	717	/**
tushki7	0:60d829a0353a	718	* @addtogroup CRC_Register_Masks CRC Register Masks
tushki7	0:60d829a0353a	719	* @{
tushki7	0:60d829a0353a	720	*/
tushki7	0:60d829a0353a	721
tushki7	0:60d829a0353a	722	/* CRCL Bit Fields */
tushki7	0:60d829a0353a	723	#define CRC_CRCL_CRCL_MASK 0xFFFFu
tushki7	0:60d829a0353a	724	#define CRC_CRCL_CRCL_SHIFT 0
tushki7	0:60d829a0353a	725	#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
tushki7	0:60d829a0353a	726	/* CRCH Bit Fields */
tushki7	0:60d829a0353a	727	#define CRC_CRCH_CRCH_MASK 0xFFFFu
tushki7	0:60d829a0353a	728	#define CRC_CRCH_CRCH_SHIFT 0
tushki7	0:60d829a0353a	729	#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
tushki7	0:60d829a0353a	730	/* CRC Bit Fields */
tushki7	0:60d829a0353a	731	#define CRC_CRC_LL_MASK 0xFFu
tushki7	0:60d829a0353a	732	#define CRC_CRC_LL_SHIFT 0
tushki7	0:60d829a0353a	733	#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
tushki7	0:60d829a0353a	734	#define CRC_CRC_LU_MASK 0xFF00u
tushki7	0:60d829a0353a	735	#define CRC_CRC_LU_SHIFT 8
tushki7	0:60d829a0353a	736	#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
tushki7	0:60d829a0353a	737	#define CRC_CRC_HL_MASK 0xFF0000u
tushki7	0:60d829a0353a	738	#define CRC_CRC_HL_SHIFT 16
tushki7	0:60d829a0353a	739	#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
tushki7	0:60d829a0353a	740	#define CRC_CRC_HU_MASK 0xFF000000u
tushki7	0:60d829a0353a	741	#define CRC_CRC_HU_SHIFT 24
tushki7	0:60d829a0353a	742	#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
tushki7	0:60d829a0353a	743	/* CRCLL Bit Fields */
tushki7	0:60d829a0353a	744	#define CRC_CRCLL_CRCLL_MASK 0xFFu
tushki7	0:60d829a0353a	745	#define CRC_CRCLL_CRCLL_SHIFT 0
tushki7	0:60d829a0353a	746	#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
tushki7	0:60d829a0353a	747	/* CRCLU Bit Fields */
tushki7	0:60d829a0353a	748	#define CRC_CRCLU_CRCLU_MASK 0xFFu
tushki7	0:60d829a0353a	749	#define CRC_CRCLU_CRCLU_SHIFT 0
tushki7	0:60d829a0353a	750	#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
tushki7	0:60d829a0353a	751	/* CRCHL Bit Fields */
tushki7	0:60d829a0353a	752	#define CRC_CRCHL_CRCHL_MASK 0xFFu
tushki7	0:60d829a0353a	753	#define CRC_CRCHL_CRCHL_SHIFT 0
tushki7	0:60d829a0353a	754	#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
tushki7	0:60d829a0353a	755	/* CRCHU Bit Fields */
tushki7	0:60d829a0353a	756	#define CRC_CRCHU_CRCHU_MASK 0xFFu
tushki7	0:60d829a0353a	757	#define CRC_CRCHU_CRCHU_SHIFT 0
tushki7	0:60d829a0353a	758	#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
tushki7	0:60d829a0353a	759	/* GPOLYL Bit Fields */
tushki7	0:60d829a0353a	760	#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
tushki7	0:60d829a0353a	761	#define CRC_GPOLYL_GPOLYL_SHIFT 0
tushki7	0:60d829a0353a	762	#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
tushki7	0:60d829a0353a	763	/* GPOLYH Bit Fields */
tushki7	0:60d829a0353a	764	#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
tushki7	0:60d829a0353a	765	#define CRC_GPOLYH_GPOLYH_SHIFT 0
tushki7	0:60d829a0353a	766	#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
tushki7	0:60d829a0353a	767	/* GPOLY Bit Fields */
tushki7	0:60d829a0353a	768	#define CRC_GPOLY_LOW_MASK 0xFFFFu
tushki7	0:60d829a0353a	769	#define CRC_GPOLY_LOW_SHIFT 0
tushki7	0:60d829a0353a	770	#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
tushki7	0:60d829a0353a	771	#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	772	#define CRC_GPOLY_HIGH_SHIFT 16
tushki7	0:60d829a0353a	773	#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
tushki7	0:60d829a0353a	774	/* GPOLYLL Bit Fields */
tushki7	0:60d829a0353a	775	#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
tushki7	0:60d829a0353a	776	#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
tushki7	0:60d829a0353a	777	#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
tushki7	0:60d829a0353a	778	/* GPOLYLU Bit Fields */
tushki7	0:60d829a0353a	779	#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
tushki7	0:60d829a0353a	780	#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
tushki7	0:60d829a0353a	781	#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
tushki7	0:60d829a0353a	782	/* GPOLYHL Bit Fields */
tushki7	0:60d829a0353a	783	#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
tushki7	0:60d829a0353a	784	#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
tushki7	0:60d829a0353a	785	#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
tushki7	0:60d829a0353a	786	/* GPOLYHU Bit Fields */
tushki7	0:60d829a0353a	787	#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
tushki7	0:60d829a0353a	788	#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
tushki7	0:60d829a0353a	789	#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
tushki7	0:60d829a0353a	790	/* CTRL Bit Fields */
tushki7	0:60d829a0353a	791	#define CRC_CTRL_TCRC_MASK 0x1000000u
tushki7	0:60d829a0353a	792	#define CRC_CTRL_TCRC_SHIFT 24
tushki7	0:60d829a0353a	793	#define CRC_CTRL_WAS_MASK 0x2000000u
tushki7	0:60d829a0353a	794	#define CRC_CTRL_WAS_SHIFT 25
tushki7	0:60d829a0353a	795	#define CRC_CTRL_FXOR_MASK 0x4000000u
tushki7	0:60d829a0353a	796	#define CRC_CTRL_FXOR_SHIFT 26
tushki7	0:60d829a0353a	797	#define CRC_CTRL_TOTR_MASK 0x30000000u
tushki7	0:60d829a0353a	798	#define CRC_CTRL_TOTR_SHIFT 28
tushki7	0:60d829a0353a	799	#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
tushki7	0:60d829a0353a	800	#define CRC_CTRL_TOT_MASK 0xC0000000u
tushki7	0:60d829a0353a	801	#define CRC_CTRL_TOT_SHIFT 30
tushki7	0:60d829a0353a	802	#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
tushki7	0:60d829a0353a	803	/* CTRLHU Bit Fields */
tushki7	0:60d829a0353a	804	#define CRC_CTRLHU_TCRC_MASK 0x1u
tushki7	0:60d829a0353a	805	#define CRC_CTRLHU_TCRC_SHIFT 0
tushki7	0:60d829a0353a	806	#define CRC_CTRLHU_WAS_MASK 0x2u
tushki7	0:60d829a0353a	807	#define CRC_CTRLHU_WAS_SHIFT 1
tushki7	0:60d829a0353a	808	#define CRC_CTRLHU_FXOR_MASK 0x4u
tushki7	0:60d829a0353a	809	#define CRC_CTRLHU_FXOR_SHIFT 2
tushki7	0:60d829a0353a	810	#define CRC_CTRLHU_TOTR_MASK 0x30u
tushki7	0:60d829a0353a	811	#define CRC_CTRLHU_TOTR_SHIFT 4
tushki7	0:60d829a0353a	812	#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
tushki7	0:60d829a0353a	813	#define CRC_CTRLHU_TOT_MASK 0xC0u
tushki7	0:60d829a0353a	814	#define CRC_CTRLHU_TOT_SHIFT 6
tushki7	0:60d829a0353a	815	#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
tushki7	0:60d829a0353a	816
tushki7	0:60d829a0353a	817	/**
tushki7	0:60d829a0353a	818	* @}
tushki7	0:60d829a0353a	819	/ / end of group CRC_Register_Masks */
tushki7	0:60d829a0353a	820
tushki7	0:60d829a0353a	821
tushki7	0:60d829a0353a	822	/* CRC - Peripheral instance base addresses */
tushki7	0:60d829a0353a	823	/** Peripheral CRC base address */
tushki7	0:60d829a0353a	824	#define CRC_BASE (0x40032000u)
tushki7	0:60d829a0353a	825	/** Peripheral CRC base pointer */
tushki7	0:60d829a0353a	826	#define CRC0 ((CRC_Type *)CRC_BASE)
tushki7	0:60d829a0353a	827
tushki7	0:60d829a0353a	828	/**
tushki7	0:60d829a0353a	829	* @}
tushki7	0:60d829a0353a	830	/ / end of group CRC_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	831
tushki7	0:60d829a0353a	832
tushki7	0:60d829a0353a	833	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	834	-- DAC Peripheral Access Layer
tushki7	0:60d829a0353a	835	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	836
tushki7	0:60d829a0353a	837	/**
tushki7	0:60d829a0353a	838	* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
tushki7	0:60d829a0353a	839	* @{
tushki7	0:60d829a0353a	840	*/
tushki7	0:60d829a0353a	841
tushki7	0:60d829a0353a	842	/** DAC - Register Layout Typedef */
tushki7	0:60d829a0353a	843	typedef struct {
tushki7	0:60d829a0353a	844	struct { /* offset: 0x0, array step: 0x2 */
tushki7	0:60d829a0353a	845	__IO uint8_t DATL; /*< DAC Data Low Register, array offset: 0x0, array step: 0x2 /
tushki7	0:60d829a0353a	846	__IO uint8_t DATH; /*< DAC Data High Register, array offset: 0x1, array step: 0x2 /
tushki7	0:60d829a0353a	847	} DAT[16];
tushki7	0:60d829a0353a	848	__IO uint8_t SR; /*< DAC Status Register, offset: 0x20 /
tushki7	0:60d829a0353a	849	__IO uint8_t C0; /*< DAC Control Register, offset: 0x21 /
tushki7	0:60d829a0353a	850	__IO uint8_t C1; /*< DAC Control Register 1, offset: 0x22 /
tushki7	0:60d829a0353a	851	__IO uint8_t C2; /*< DAC Control Register 2, offset: 0x23 /
tushki7	0:60d829a0353a	852	} DAC_Type, *DAC_MemMapPtr;
tushki7	0:60d829a0353a	853
tushki7	0:60d829a0353a	854	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	855	-- DAC Register Masks
tushki7	0:60d829a0353a	856	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	857
tushki7	0:60d829a0353a	858	/**
tushki7	0:60d829a0353a	859	* @addtogroup DAC_Register_Masks DAC Register Masks
tushki7	0:60d829a0353a	860	* @{
tushki7	0:60d829a0353a	861	*/
tushki7	0:60d829a0353a	862
tushki7	0:60d829a0353a	863	/* DATL Bit Fields */
tushki7	0:60d829a0353a	864	#define DAC_DATL_DATA0_MASK 0xFFu
tushki7	0:60d829a0353a	865	#define DAC_DATL_DATA0_SHIFT 0
tushki7	0:60d829a0353a	866	#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
tushki7	0:60d829a0353a	867	/* DATH Bit Fields */
tushki7	0:60d829a0353a	868	#define DAC_DATH_DATA1_MASK 0xFu
tushki7	0:60d829a0353a	869	#define DAC_DATH_DATA1_SHIFT 0
tushki7	0:60d829a0353a	870	#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
tushki7	0:60d829a0353a	871	/* SR Bit Fields */
tushki7	0:60d829a0353a	872	#define DAC_SR_DACBFRPBF_MASK 0x1u
tushki7	0:60d829a0353a	873	#define DAC_SR_DACBFRPBF_SHIFT 0
tushki7	0:60d829a0353a	874	#define DAC_SR_DACBFRPTF_MASK 0x2u
tushki7	0:60d829a0353a	875	#define DAC_SR_DACBFRPTF_SHIFT 1
tushki7	0:60d829a0353a	876	#define DAC_SR_DACBFWMF_MASK 0x4u
tushki7	0:60d829a0353a	877	#define DAC_SR_DACBFWMF_SHIFT 2
tushki7	0:60d829a0353a	878	/* C0 Bit Fields */
tushki7	0:60d829a0353a	879	#define DAC_C0_DACBBIEN_MASK 0x1u
tushki7	0:60d829a0353a	880	#define DAC_C0_DACBBIEN_SHIFT 0
tushki7	0:60d829a0353a	881	#define DAC_C0_DACBTIEN_MASK 0x2u
tushki7	0:60d829a0353a	882	#define DAC_C0_DACBTIEN_SHIFT 1
tushki7	0:60d829a0353a	883	#define DAC_C0_DACBWIEN_MASK 0x4u
tushki7	0:60d829a0353a	884	#define DAC_C0_DACBWIEN_SHIFT 2
tushki7	0:60d829a0353a	885	#define DAC_C0_LPEN_MASK 0x8u
tushki7	0:60d829a0353a	886	#define DAC_C0_LPEN_SHIFT 3
tushki7	0:60d829a0353a	887	#define DAC_C0_DACSWTRG_MASK 0x10u
tushki7	0:60d829a0353a	888	#define DAC_C0_DACSWTRG_SHIFT 4
tushki7	0:60d829a0353a	889	#define DAC_C0_DACTRGSEL_MASK 0x20u
tushki7	0:60d829a0353a	890	#define DAC_C0_DACTRGSEL_SHIFT 5
tushki7	0:60d829a0353a	891	#define DAC_C0_DACRFS_MASK 0x40u
tushki7	0:60d829a0353a	892	#define DAC_C0_DACRFS_SHIFT 6
tushki7	0:60d829a0353a	893	#define DAC_C0_DACEN_MASK 0x80u
tushki7	0:60d829a0353a	894	#define DAC_C0_DACEN_SHIFT 7
tushki7	0:60d829a0353a	895	/* C1 Bit Fields */
tushki7	0:60d829a0353a	896	#define DAC_C1_DACBFEN_MASK 0x1u
tushki7	0:60d829a0353a	897	#define DAC_C1_DACBFEN_SHIFT 0
tushki7	0:60d829a0353a	898	#define DAC_C1_DACBFMD_MASK 0x6u
tushki7	0:60d829a0353a	899	#define DAC_C1_DACBFMD_SHIFT 1
tushki7	0:60d829a0353a	900	#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
tushki7	0:60d829a0353a	901	#define DAC_C1_DACBFWM_MASK 0x18u
tushki7	0:60d829a0353a	902	#define DAC_C1_DACBFWM_SHIFT 3
tushki7	0:60d829a0353a	903	#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
tushki7	0:60d829a0353a	904	#define DAC_C1_DMAEN_MASK 0x80u
tushki7	0:60d829a0353a	905	#define DAC_C1_DMAEN_SHIFT 7
tushki7	0:60d829a0353a	906	/* C2 Bit Fields */
tushki7	0:60d829a0353a	907	#define DAC_C2_DACBFUP_MASK 0xFu
tushki7	0:60d829a0353a	908	#define DAC_C2_DACBFUP_SHIFT 0
tushki7	0:60d829a0353a	909	#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
tushki7	0:60d829a0353a	910	#define DAC_C2_DACBFRP_MASK 0xF0u
tushki7	0:60d829a0353a	911	#define DAC_C2_DACBFRP_SHIFT 4
tushki7	0:60d829a0353a	912	#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
tushki7	0:60d829a0353a	913
tushki7	0:60d829a0353a	914	/**
tushki7	0:60d829a0353a	915	* @}
tushki7	0:60d829a0353a	916	/ / end of group DAC_Register_Masks */
tushki7	0:60d829a0353a	917
tushki7	0:60d829a0353a	918
tushki7	0:60d829a0353a	919	/* DAC - Peripheral instance base addresses */
tushki7	0:60d829a0353a	920	/** Peripheral DAC0 base address */
tushki7	0:60d829a0353a	921	#define DAC0_BASE (0x400CC000u)
tushki7	0:60d829a0353a	922	/** Peripheral DAC0 base pointer */
tushki7	0:60d829a0353a	923	#define DAC0 ((DAC_Type *)DAC0_BASE)
tushki7	0:60d829a0353a	924	/** Array initializer of DAC peripheral base pointers */
tushki7	0:60d829a0353a	925	#define DAC_BASES { DAC0 }
tushki7	0:60d829a0353a	926
tushki7	0:60d829a0353a	927	/**
tushki7	0:60d829a0353a	928	* @}
tushki7	0:60d829a0353a	929	/ / end of group DAC_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	930
tushki7	0:60d829a0353a	931
tushki7	0:60d829a0353a	932	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	933	-- DMA Peripheral Access Layer
tushki7	0:60d829a0353a	934	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	935
tushki7	0:60d829a0353a	936	/**
tushki7	0:60d829a0353a	937	* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
tushki7	0:60d829a0353a	938	* @{
tushki7	0:60d829a0353a	939	*/
tushki7	0:60d829a0353a	940
tushki7	0:60d829a0353a	941	/** DMA - Register Layout Typedef */
tushki7	0:60d829a0353a	942	typedef struct {
tushki7	0:60d829a0353a	943	__IO uint32_t CR; /*< Control Register, offset: 0x0 /
tushki7	0:60d829a0353a	944	__I uint32_t ES; /*< Error Status Register, offset: 0x4 /
tushki7	0:60d829a0353a	945	uint8_t RESERVED_0[4];
tushki7	0:60d829a0353a	946	__IO uint32_t ERQ; /*< Enable Request Register, offset: 0xC /
tushki7	0:60d829a0353a	947	uint8_t RESERVED_1[4];
tushki7	0:60d829a0353a	948	__IO uint32_t EEI; /*< Enable Error Interrupt Register, offset: 0x14 /
tushki7	0:60d829a0353a	949	__O uint8_t CEEI; /*< Clear Enable Error Interrupt Register, offset: 0x18 /
tushki7	0:60d829a0353a	950	__O uint8_t SEEI; /*< Set Enable Error Interrupt Register, offset: 0x19 /
tushki7	0:60d829a0353a	951	__O uint8_t CERQ; /*< Clear Enable Request Register, offset: 0x1A /
tushki7	0:60d829a0353a	952	__O uint8_t SERQ; /*< Set Enable Request Register, offset: 0x1B /
tushki7	0:60d829a0353a	953	__O uint8_t CDNE; /*< Clear DONE Status Bit Register, offset: 0x1C /
tushki7	0:60d829a0353a	954	__O uint8_t SSRT; /*< Set START Bit Register, offset: 0x1D /
tushki7	0:60d829a0353a	955	__O uint8_t CERR; /*< Clear Error Register, offset: 0x1E /
tushki7	0:60d829a0353a	956	__O uint8_t CINT; /*< Clear Interrupt Request Register, offset: 0x1F /
tushki7	0:60d829a0353a	957	uint8_t RESERVED_2[4];
tushki7	0:60d829a0353a	958	__IO uint32_t INT; /*< Interrupt Request Register, offset: 0x24 /
tushki7	0:60d829a0353a	959	uint8_t RESERVED_3[4];
tushki7	0:60d829a0353a	960	__IO uint32_t ERR; /*< Error Register, offset: 0x2C /
tushki7	0:60d829a0353a	961	uint8_t RESERVED_4[4];
tushki7	0:60d829a0353a	962	__IO uint32_t HRS; /*< Hardware Request Status Register, offset: 0x34 /
tushki7	0:60d829a0353a	963	uint8_t RESERVED_5[200];
tushki7	0:60d829a0353a	964	__IO uint8_t DCHPRI3; /*< Channel n Priority Register, offset: 0x100 /
tushki7	0:60d829a0353a	965	__IO uint8_t DCHPRI2; /*< Channel n Priority Register, offset: 0x101 /
tushki7	0:60d829a0353a	966	__IO uint8_t DCHPRI1; /*< Channel n Priority Register, offset: 0x102 /
tushki7	0:60d829a0353a	967	__IO uint8_t DCHPRI0; /*< Channel n Priority Register, offset: 0x103 /
tushki7	0:60d829a0353a	968	uint8_t RESERVED_6[3836];
tushki7	0:60d829a0353a	969	struct { /* offset: 0x1000, array step: 0x20 */
tushki7	0:60d829a0353a	970	__IO uint32_t SADDR; /*< TCD Source Address, array offset: 0x1000, array step: 0x20 /
tushki7	0:60d829a0353a	971	__IO uint16_t SOFF; /*< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 /
tushki7	0:60d829a0353a	972	__IO uint16_t ATTR; /*< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 /
tushki7	0:60d829a0353a	973	union { /* offset: 0x1008, array step: 0x20 */
tushki7	0:60d829a0353a	974	__IO uint32_t NBYTES_MLNO; /*< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 /
tushki7	0:60d829a0353a	975	__IO uint32_t NBYTES_MLOFFNO; /*< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 /
tushki7	0:60d829a0353a	976	__IO uint32_t NBYTES_MLOFFYES; /*< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 /
tushki7	0:60d829a0353a	977	};
tushki7	0:60d829a0353a	978	__IO uint32_t SLAST; /*< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 /
tushki7	0:60d829a0353a	979	__IO uint32_t DADDR; /*< TCD Destination Address, array offset: 0x1010, array step: 0x20 /
tushki7	0:60d829a0353a	980	__IO uint16_t DOFF; /*< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 /
tushki7	0:60d829a0353a	981	union { /* offset: 0x1016, array step: 0x20 */
tushki7	0:60d829a0353a	982	__IO uint16_t CITER_ELINKNO; /*< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 /
tushki7	0:60d829a0353a	983	__IO uint16_t CITER_ELINKYES; /*< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 /
tushki7	0:60d829a0353a	984	};
tushki7	0:60d829a0353a	985	__IO uint32_t DLAST_SGA; /*< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 /
tushki7	0:60d829a0353a	986	__IO uint16_t CSR; /*< TCD Control and Status, array offset: 0x101C, array step: 0x20 /
tushki7	0:60d829a0353a	987	union { /* offset: 0x101E, array step: 0x20 */
tushki7	0:60d829a0353a	988	__IO uint16_t BITER_ELINKNO; /*< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 /
tushki7	0:60d829a0353a	989	__IO uint16_t BITER_ELINKYES; /*< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 /
tushki7	0:60d829a0353a	990	};
tushki7	0:60d829a0353a	991	} TCD[4];
tushki7	0:60d829a0353a	992	} DMA_Type;
tushki7	0:60d829a0353a	993
tushki7	0:60d829a0353a	994	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	995	-- DMA Register Masks
tushki7	0:60d829a0353a	996	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	997
tushki7	0:60d829a0353a	998	/**
tushki7	0:60d829a0353a	999	* @addtogroup DMA_Register_Masks DMA Register Masks
tushki7	0:60d829a0353a	1000	* @{
tushki7	0:60d829a0353a	1001	*/
tushki7	0:60d829a0353a	1002
tushki7	0:60d829a0353a	1003	/* CR Bit Fields */
tushki7	0:60d829a0353a	1004	#define DMA_CR_EDBG_MASK 0x2u
tushki7	0:60d829a0353a	1005	#define DMA_CR_EDBG_SHIFT 1
tushki7	0:60d829a0353a	1006	#define DMA_CR_ERCA_MASK 0x4u
tushki7	0:60d829a0353a	1007	#define DMA_CR_ERCA_SHIFT 2
tushki7	0:60d829a0353a	1008	#define DMA_CR_HOE_MASK 0x10u
tushki7	0:60d829a0353a	1009	#define DMA_CR_HOE_SHIFT 4
tushki7	0:60d829a0353a	1010	#define DMA_CR_HALT_MASK 0x20u
tushki7	0:60d829a0353a	1011	#define DMA_CR_HALT_SHIFT 5
tushki7	0:60d829a0353a	1012	#define DMA_CR_CLM_MASK 0x40u
tushki7	0:60d829a0353a	1013	#define DMA_CR_CLM_SHIFT 6
tushki7	0:60d829a0353a	1014	#define DMA_CR_EMLM_MASK 0x80u
tushki7	0:60d829a0353a	1015	#define DMA_CR_EMLM_SHIFT 7
tushki7	0:60d829a0353a	1016	#define DMA_CR_ECX_MASK 0x10000u
tushki7	0:60d829a0353a	1017	#define DMA_CR_ECX_SHIFT 16
tushki7	0:60d829a0353a	1018	#define DMA_CR_CX_MASK 0x20000u
tushki7	0:60d829a0353a	1019	#define DMA_CR_CX_SHIFT 17
tushki7	0:60d829a0353a	1020	/* ES Bit Fields */
tushki7	0:60d829a0353a	1021	#define DMA_ES_DBE_MASK 0x1u
tushki7	0:60d829a0353a	1022	#define DMA_ES_DBE_SHIFT 0
tushki7	0:60d829a0353a	1023	#define DMA_ES_SBE_MASK 0x2u
tushki7	0:60d829a0353a	1024	#define DMA_ES_SBE_SHIFT 1
tushki7	0:60d829a0353a	1025	#define DMA_ES_SGE_MASK 0x4u
tushki7	0:60d829a0353a	1026	#define DMA_ES_SGE_SHIFT 2
tushki7	0:60d829a0353a	1027	#define DMA_ES_NCE_MASK 0x8u
tushki7	0:60d829a0353a	1028	#define DMA_ES_NCE_SHIFT 3
tushki7	0:60d829a0353a	1029	#define DMA_ES_DOE_MASK 0x10u
tushki7	0:60d829a0353a	1030	#define DMA_ES_DOE_SHIFT 4
tushki7	0:60d829a0353a	1031	#define DMA_ES_DAE_MASK 0x20u
tushki7	0:60d829a0353a	1032	#define DMA_ES_DAE_SHIFT 5
tushki7	0:60d829a0353a	1033	#define DMA_ES_SOE_MASK 0x40u
tushki7	0:60d829a0353a	1034	#define DMA_ES_SOE_SHIFT 6
tushki7	0:60d829a0353a	1035	#define DMA_ES_SAE_MASK 0x80u
tushki7	0:60d829a0353a	1036	#define DMA_ES_SAE_SHIFT 7
tushki7	0:60d829a0353a	1037	#define DMA_ES_ERRCHN_MASK 0xF00u
tushki7	0:60d829a0353a	1038	#define DMA_ES_ERRCHN_SHIFT 8
tushki7	0:60d829a0353a	1039	#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
tushki7	0:60d829a0353a	1040	#define DMA_ES_CPE_MASK 0x4000u
tushki7	0:60d829a0353a	1041	#define DMA_ES_CPE_SHIFT 14
tushki7	0:60d829a0353a	1042	#define DMA_ES_ECX_MASK 0x10000u
tushki7	0:60d829a0353a	1043	#define DMA_ES_ECX_SHIFT 16
tushki7	0:60d829a0353a	1044	#define DMA_ES_VLD_MASK 0x80000000u
tushki7	0:60d829a0353a	1045	#define DMA_ES_VLD_SHIFT 31
tushki7	0:60d829a0353a	1046	/* ERQ Bit Fields */
tushki7	0:60d829a0353a	1047	#define DMA_ERQ_ERQ0_MASK 0x1u
tushki7	0:60d829a0353a	1048	#define DMA_ERQ_ERQ0_SHIFT 0
tushki7	0:60d829a0353a	1049	#define DMA_ERQ_ERQ1_MASK 0x2u
tushki7	0:60d829a0353a	1050	#define DMA_ERQ_ERQ1_SHIFT 1
tushki7	0:60d829a0353a	1051	#define DMA_ERQ_ERQ2_MASK 0x4u
tushki7	0:60d829a0353a	1052	#define DMA_ERQ_ERQ2_SHIFT 2
tushki7	0:60d829a0353a	1053	#define DMA_ERQ_ERQ3_MASK 0x8u
tushki7	0:60d829a0353a	1054	#define DMA_ERQ_ERQ3_SHIFT 3
tushki7	0:60d829a0353a	1055	/* EEI Bit Fields */
tushki7	0:60d829a0353a	1056	#define DMA_EEI_EEI0_MASK 0x1u
tushki7	0:60d829a0353a	1057	#define DMA_EEI_EEI0_SHIFT 0
tushki7	0:60d829a0353a	1058	#define DMA_EEI_EEI1_MASK 0x2u
tushki7	0:60d829a0353a	1059	#define DMA_EEI_EEI1_SHIFT 1
tushki7	0:60d829a0353a	1060	#define DMA_EEI_EEI2_MASK 0x4u
tushki7	0:60d829a0353a	1061	#define DMA_EEI_EEI2_SHIFT 2
tushki7	0:60d829a0353a	1062	#define DMA_EEI_EEI3_MASK 0x8u
tushki7	0:60d829a0353a	1063	#define DMA_EEI_EEI3_SHIFT 3
tushki7	0:60d829a0353a	1064	/* CEEI Bit Fields */
tushki7	0:60d829a0353a	1065	#define DMA_CEEI_CEEI_MASK 0xFu
tushki7	0:60d829a0353a	1066	#define DMA_CEEI_CEEI_SHIFT 0
tushki7	0:60d829a0353a	1067	#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
tushki7	0:60d829a0353a	1068	#define DMA_CEEI_CAEE_MASK 0x40u
tushki7	0:60d829a0353a	1069	#define DMA_CEEI_CAEE_SHIFT 6
tushki7	0:60d829a0353a	1070	#define DMA_CEEI_NOP_MASK 0x80u
tushki7	0:60d829a0353a	1071	#define DMA_CEEI_NOP_SHIFT 7
tushki7	0:60d829a0353a	1072	/* SEEI Bit Fields */
tushki7	0:60d829a0353a	1073	#define DMA_SEEI_SEEI_MASK 0xFu
tushki7	0:60d829a0353a	1074	#define DMA_SEEI_SEEI_SHIFT 0
tushki7	0:60d829a0353a	1075	#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
tushki7	0:60d829a0353a	1076	#define DMA_SEEI_SAEE_MASK 0x40u
tushki7	0:60d829a0353a	1077	#define DMA_SEEI_SAEE_SHIFT 6
tushki7	0:60d829a0353a	1078	#define DMA_SEEI_NOP_MASK 0x80u
tushki7	0:60d829a0353a	1079	#define DMA_SEEI_NOP_SHIFT 7
tushki7	0:60d829a0353a	1080	/* CERQ Bit Fields */
tushki7	0:60d829a0353a	1081	#define DMA_CERQ_CERQ_MASK 0xFu
tushki7	0:60d829a0353a	1082	#define DMA_CERQ_CERQ_SHIFT 0
tushki7	0:60d829a0353a	1083	#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
tushki7	0:60d829a0353a	1084	#define DMA_CERQ_CAER_MASK 0x40u
tushki7	0:60d829a0353a	1085	#define DMA_CERQ_CAER_SHIFT 6
tushki7	0:60d829a0353a	1086	#define DMA_CERQ_NOP_MASK 0x80u
tushki7	0:60d829a0353a	1087	#define DMA_CERQ_NOP_SHIFT 7
tushki7	0:60d829a0353a	1088	/* SERQ Bit Fields */
tushki7	0:60d829a0353a	1089	#define DMA_SERQ_SERQ_MASK 0xFu
tushki7	0:60d829a0353a	1090	#define DMA_SERQ_SERQ_SHIFT 0
tushki7	0:60d829a0353a	1091	#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
tushki7	0:60d829a0353a	1092	#define DMA_SERQ_SAER_MASK 0x40u
tushki7	0:60d829a0353a	1093	#define DMA_SERQ_SAER_SHIFT 6
tushki7	0:60d829a0353a	1094	#define DMA_SERQ_NOP_MASK 0x80u
tushki7	0:60d829a0353a	1095	#define DMA_SERQ_NOP_SHIFT 7
tushki7	0:60d829a0353a	1096	/* CDNE Bit Fields */
tushki7	0:60d829a0353a	1097	#define DMA_CDNE_CDNE_MASK 0xFu
tushki7	0:60d829a0353a	1098	#define DMA_CDNE_CDNE_SHIFT 0
tushki7	0:60d829a0353a	1099	#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
tushki7	0:60d829a0353a	1100	#define DMA_CDNE_CADN_MASK 0x40u
tushki7	0:60d829a0353a	1101	#define DMA_CDNE_CADN_SHIFT 6
tushki7	0:60d829a0353a	1102	#define DMA_CDNE_NOP_MASK 0x80u
tushki7	0:60d829a0353a	1103	#define DMA_CDNE_NOP_SHIFT 7
tushki7	0:60d829a0353a	1104	/* SSRT Bit Fields */
tushki7	0:60d829a0353a	1105	#define DMA_SSRT_SSRT_MASK 0xFu
tushki7	0:60d829a0353a	1106	#define DMA_SSRT_SSRT_SHIFT 0
tushki7	0:60d829a0353a	1107	#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
tushki7	0:60d829a0353a	1108	#define DMA_SSRT_SAST_MASK 0x40u
tushki7	0:60d829a0353a	1109	#define DMA_SSRT_SAST_SHIFT 6
tushki7	0:60d829a0353a	1110	#define DMA_SSRT_NOP_MASK 0x80u
tushki7	0:60d829a0353a	1111	#define DMA_SSRT_NOP_SHIFT 7
tushki7	0:60d829a0353a	1112	/* CERR Bit Fields */
tushki7	0:60d829a0353a	1113	#define DMA_CERR_CERR_MASK 0xFu
tushki7	0:60d829a0353a	1114	#define DMA_CERR_CERR_SHIFT 0
tushki7	0:60d829a0353a	1115	#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
tushki7	0:60d829a0353a	1116	#define DMA_CERR_CAEI_MASK 0x40u
tushki7	0:60d829a0353a	1117	#define DMA_CERR_CAEI_SHIFT 6
tushki7	0:60d829a0353a	1118	#define DMA_CERR_NOP_MASK 0x80u
tushki7	0:60d829a0353a	1119	#define DMA_CERR_NOP_SHIFT 7
tushki7	0:60d829a0353a	1120	/* CINT Bit Fields */
tushki7	0:60d829a0353a	1121	#define DMA_CINT_CINT_MASK 0xFu
tushki7	0:60d829a0353a	1122	#define DMA_CINT_CINT_SHIFT 0
tushki7	0:60d829a0353a	1123	#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
tushki7	0:60d829a0353a	1124	#define DMA_CINT_CAIR_MASK 0x40u
tushki7	0:60d829a0353a	1125	#define DMA_CINT_CAIR_SHIFT 6
tushki7	0:60d829a0353a	1126	#define DMA_CINT_NOP_MASK 0x80u
tushki7	0:60d829a0353a	1127	#define DMA_CINT_NOP_SHIFT 7
tushki7	0:60d829a0353a	1128	/* INT Bit Fields */
tushki7	0:60d829a0353a	1129	#define DMA_INT_INT0_MASK 0x1u
tushki7	0:60d829a0353a	1130	#define DMA_INT_INT0_SHIFT 0
tushki7	0:60d829a0353a	1131	#define DMA_INT_INT1_MASK 0x2u
tushki7	0:60d829a0353a	1132	#define DMA_INT_INT1_SHIFT 1
tushki7	0:60d829a0353a	1133	#define DMA_INT_INT2_MASK 0x4u
tushki7	0:60d829a0353a	1134	#define DMA_INT_INT2_SHIFT 2
tushki7	0:60d829a0353a	1135	#define DMA_INT_INT3_MASK 0x8u
tushki7	0:60d829a0353a	1136	#define DMA_INT_INT3_SHIFT 3
tushki7	0:60d829a0353a	1137	/* ERR Bit Fields */
tushki7	0:60d829a0353a	1138	#define DMA_ERR_ERR0_MASK 0x1u
tushki7	0:60d829a0353a	1139	#define DMA_ERR_ERR0_SHIFT 0
tushki7	0:60d829a0353a	1140	#define DMA_ERR_ERR1_MASK 0x2u
tushki7	0:60d829a0353a	1141	#define DMA_ERR_ERR1_SHIFT 1
tushki7	0:60d829a0353a	1142	#define DMA_ERR_ERR2_MASK 0x4u
tushki7	0:60d829a0353a	1143	#define DMA_ERR_ERR2_SHIFT 2
tushki7	0:60d829a0353a	1144	#define DMA_ERR_ERR3_MASK 0x8u
tushki7	0:60d829a0353a	1145	#define DMA_ERR_ERR3_SHIFT 3
tushki7	0:60d829a0353a	1146	/* HRS Bit Fields */
tushki7	0:60d829a0353a	1147	#define DMA_HRS_HRS0_MASK 0x1u
tushki7	0:60d829a0353a	1148	#define DMA_HRS_HRS0_SHIFT 0
tushki7	0:60d829a0353a	1149	#define DMA_HRS_HRS1_MASK 0x2u
tushki7	0:60d829a0353a	1150	#define DMA_HRS_HRS1_SHIFT 1
tushki7	0:60d829a0353a	1151	#define DMA_HRS_HRS2_MASK 0x4u
tushki7	0:60d829a0353a	1152	#define DMA_HRS_HRS2_SHIFT 2
tushki7	0:60d829a0353a	1153	#define DMA_HRS_HRS3_MASK 0x8u
tushki7	0:60d829a0353a	1154	#define DMA_HRS_HRS3_SHIFT 3
tushki7	0:60d829a0353a	1155	/* DCHPRI3 Bit Fields */
tushki7	0:60d829a0353a	1156	#define DMA_DCHPRI3_CHPRI_MASK 0xFu
tushki7	0:60d829a0353a	1157	#define DMA_DCHPRI3_CHPRI_SHIFT 0
tushki7	0:60d829a0353a	1158	#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
tushki7	0:60d829a0353a	1159	#define DMA_DCHPRI3_DPA_MASK 0x40u
tushki7	0:60d829a0353a	1160	#define DMA_DCHPRI3_DPA_SHIFT 6
tushki7	0:60d829a0353a	1161	#define DMA_DCHPRI3_ECP_MASK 0x80u
tushki7	0:60d829a0353a	1162	#define DMA_DCHPRI3_ECP_SHIFT 7
tushki7	0:60d829a0353a	1163	/* DCHPRI2 Bit Fields */
tushki7	0:60d829a0353a	1164	#define DMA_DCHPRI2_CHPRI_MASK 0xFu
tushki7	0:60d829a0353a	1165	#define DMA_DCHPRI2_CHPRI_SHIFT 0
tushki7	0:60d829a0353a	1166	#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
tushki7	0:60d829a0353a	1167	#define DMA_DCHPRI2_DPA_MASK 0x40u
tushki7	0:60d829a0353a	1168	#define DMA_DCHPRI2_DPA_SHIFT 6
tushki7	0:60d829a0353a	1169	#define DMA_DCHPRI2_ECP_MASK 0x80u
tushki7	0:60d829a0353a	1170	#define DMA_DCHPRI2_ECP_SHIFT 7
tushki7	0:60d829a0353a	1171	/* DCHPRI1 Bit Fields */
tushki7	0:60d829a0353a	1172	#define DMA_DCHPRI1_CHPRI_MASK 0xFu
tushki7	0:60d829a0353a	1173	#define DMA_DCHPRI1_CHPRI_SHIFT 0
tushki7	0:60d829a0353a	1174	#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
tushki7	0:60d829a0353a	1175	#define DMA_DCHPRI1_DPA_MASK 0x40u
tushki7	0:60d829a0353a	1176	#define DMA_DCHPRI1_DPA_SHIFT 6
tushki7	0:60d829a0353a	1177	#define DMA_DCHPRI1_ECP_MASK 0x80u
tushki7	0:60d829a0353a	1178	#define DMA_DCHPRI1_ECP_SHIFT 7
tushki7	0:60d829a0353a	1179	/* DCHPRI0 Bit Fields */
tushki7	0:60d829a0353a	1180	#define DMA_DCHPRI0_CHPRI_MASK 0xFu
tushki7	0:60d829a0353a	1181	#define DMA_DCHPRI0_CHPRI_SHIFT 0
tushki7	0:60d829a0353a	1182	#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
tushki7	0:60d829a0353a	1183	#define DMA_DCHPRI0_DPA_MASK 0x40u
tushki7	0:60d829a0353a	1184	#define DMA_DCHPRI0_DPA_SHIFT 6
tushki7	0:60d829a0353a	1185	#define DMA_DCHPRI0_ECP_MASK 0x80u
tushki7	0:60d829a0353a	1186	#define DMA_DCHPRI0_ECP_SHIFT 7
tushki7	0:60d829a0353a	1187	/* SADDR Bit Fields */
tushki7	0:60d829a0353a	1188	#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	1189	#define DMA_SADDR_SADDR_SHIFT 0
tushki7	0:60d829a0353a	1190	#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
tushki7	0:60d829a0353a	1191	/* SOFF Bit Fields */
tushki7	0:60d829a0353a	1192	#define DMA_SOFF_SOFF_MASK 0xFFFFu
tushki7	0:60d829a0353a	1193	#define DMA_SOFF_SOFF_SHIFT 0
tushki7	0:60d829a0353a	1194	#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
tushki7	0:60d829a0353a	1195	/* ATTR Bit Fields */
tushki7	0:60d829a0353a	1196	#define DMA_ATTR_DSIZE_MASK 0x7u
tushki7	0:60d829a0353a	1197	#define DMA_ATTR_DSIZE_SHIFT 0
tushki7	0:60d829a0353a	1198	#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
tushki7	0:60d829a0353a	1199	#define DMA_ATTR_DMOD_MASK 0xF8u
tushki7	0:60d829a0353a	1200	#define DMA_ATTR_DMOD_SHIFT 3
tushki7	0:60d829a0353a	1201	#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
tushki7	0:60d829a0353a	1202	#define DMA_ATTR_SSIZE_MASK 0x700u
tushki7	0:60d829a0353a	1203	#define DMA_ATTR_SSIZE_SHIFT 8
tushki7	0:60d829a0353a	1204	#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
tushki7	0:60d829a0353a	1205	#define DMA_ATTR_SMOD_MASK 0xF800u
tushki7	0:60d829a0353a	1206	#define DMA_ATTR_SMOD_SHIFT 11
tushki7	0:60d829a0353a	1207	#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
tushki7	0:60d829a0353a	1208	/* NBYTES_MLNO Bit Fields */
tushki7	0:60d829a0353a	1209	#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	1210	#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
tushki7	0:60d829a0353a	1211	#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
tushki7	0:60d829a0353a	1212	/* NBYTES_MLOFFNO Bit Fields */
tushki7	0:60d829a0353a	1213	#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
tushki7	0:60d829a0353a	1214	#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
tushki7	0:60d829a0353a	1215	#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
tushki7	0:60d829a0353a	1216	#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
tushki7	0:60d829a0353a	1217	#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
tushki7	0:60d829a0353a	1218	#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
tushki7	0:60d829a0353a	1219	#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
tushki7	0:60d829a0353a	1220	/* NBYTES_MLOFFYES Bit Fields */
tushki7	0:60d829a0353a	1221	#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
tushki7	0:60d829a0353a	1222	#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
tushki7	0:60d829a0353a	1223	#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
tushki7	0:60d829a0353a	1224	#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
tushki7	0:60d829a0353a	1225	#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
tushki7	0:60d829a0353a	1226	#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
tushki7	0:60d829a0353a	1227	#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
tushki7	0:60d829a0353a	1228	#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
tushki7	0:60d829a0353a	1229	#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
tushki7	0:60d829a0353a	1230	#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
tushki7	0:60d829a0353a	1231	/* SLAST Bit Fields */
tushki7	0:60d829a0353a	1232	#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	1233	#define DMA_SLAST_SLAST_SHIFT 0
tushki7	0:60d829a0353a	1234	#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
tushki7	0:60d829a0353a	1235	/* DADDR Bit Fields */
tushki7	0:60d829a0353a	1236	#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	1237	#define DMA_DADDR_DADDR_SHIFT 0
tushki7	0:60d829a0353a	1238	#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
tushki7	0:60d829a0353a	1239	/* DOFF Bit Fields */
tushki7	0:60d829a0353a	1240	#define DMA_DOFF_DOFF_MASK 0xFFFFu
tushki7	0:60d829a0353a	1241	#define DMA_DOFF_DOFF_SHIFT 0
tushki7	0:60d829a0353a	1242	#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
tushki7	0:60d829a0353a	1243	/* CITER_ELINKNO Bit Fields */
tushki7	0:60d829a0353a	1244	#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
tushki7	0:60d829a0353a	1245	#define DMA_CITER_ELINKNO_CITER_SHIFT 0
tushki7	0:60d829a0353a	1246	#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
tushki7	0:60d829a0353a	1247	#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
tushki7	0:60d829a0353a	1248	#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
tushki7	0:60d829a0353a	1249	/* CITER_ELINKYES Bit Fields */
tushki7	0:60d829a0353a	1250	#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
tushki7	0:60d829a0353a	1251	#define DMA_CITER_ELINKYES_CITER_SHIFT 0
tushki7	0:60d829a0353a	1252	#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
tushki7	0:60d829a0353a	1253	#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
tushki7	0:60d829a0353a	1254	#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
tushki7	0:60d829a0353a	1255	#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
tushki7	0:60d829a0353a	1256	#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
tushki7	0:60d829a0353a	1257	#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
tushki7	0:60d829a0353a	1258	/* DLAST_SGA Bit Fields */
tushki7	0:60d829a0353a	1259	#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	1260	#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
tushki7	0:60d829a0353a	1261	#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
tushki7	0:60d829a0353a	1262	/* CSR Bit Fields */
tushki7	0:60d829a0353a	1263	#define DMA_CSR_START_MASK 0x1u
tushki7	0:60d829a0353a	1264	#define DMA_CSR_START_SHIFT 0
tushki7	0:60d829a0353a	1265	#define DMA_CSR_INTMAJOR_MASK 0x2u
tushki7	0:60d829a0353a	1266	#define DMA_CSR_INTMAJOR_SHIFT 1
tushki7	0:60d829a0353a	1267	#define DMA_CSR_INTHALF_MASK 0x4u
tushki7	0:60d829a0353a	1268	#define DMA_CSR_INTHALF_SHIFT 2
tushki7	0:60d829a0353a	1269	#define DMA_CSR_DREQ_MASK 0x8u
tushki7	0:60d829a0353a	1270	#define DMA_CSR_DREQ_SHIFT 3
tushki7	0:60d829a0353a	1271	#define DMA_CSR_ESG_MASK 0x10u
tushki7	0:60d829a0353a	1272	#define DMA_CSR_ESG_SHIFT 4
tushki7	0:60d829a0353a	1273	#define DMA_CSR_MAJORELINK_MASK 0x20u
tushki7	0:60d829a0353a	1274	#define DMA_CSR_MAJORELINK_SHIFT 5
tushki7	0:60d829a0353a	1275	#define DMA_CSR_ACTIVE_MASK 0x40u
tushki7	0:60d829a0353a	1276	#define DMA_CSR_ACTIVE_SHIFT 6
tushki7	0:60d829a0353a	1277	#define DMA_CSR_DONE_MASK 0x80u
tushki7	0:60d829a0353a	1278	#define DMA_CSR_DONE_SHIFT 7
tushki7	0:60d829a0353a	1279	#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
tushki7	0:60d829a0353a	1280	#define DMA_CSR_MAJORLINKCH_SHIFT 8
tushki7	0:60d829a0353a	1281	#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
tushki7	0:60d829a0353a	1282	#define DMA_CSR_BWC_MASK 0xC000u
tushki7	0:60d829a0353a	1283	#define DMA_CSR_BWC_SHIFT 14
tushki7	0:60d829a0353a	1284	#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
tushki7	0:60d829a0353a	1285	/* BITER_ELINKNO Bit Fields */
tushki7	0:60d829a0353a	1286	#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
tushki7	0:60d829a0353a	1287	#define DMA_BITER_ELINKNO_BITER_SHIFT 0
tushki7	0:60d829a0353a	1288	#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
tushki7	0:60d829a0353a	1289	#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
tushki7	0:60d829a0353a	1290	#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
tushki7	0:60d829a0353a	1291	/* BITER_ELINKYES Bit Fields */
tushki7	0:60d829a0353a	1292	#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
tushki7	0:60d829a0353a	1293	#define DMA_BITER_ELINKYES_BITER_SHIFT 0
tushki7	0:60d829a0353a	1294	#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
tushki7	0:60d829a0353a	1295	#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
tushki7	0:60d829a0353a	1296	#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
tushki7	0:60d829a0353a	1297	#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
tushki7	0:60d829a0353a	1298	#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
tushki7	0:60d829a0353a	1299	#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
tushki7	0:60d829a0353a	1300
tushki7	0:60d829a0353a	1301	/**
tushki7	0:60d829a0353a	1302	* @}
tushki7	0:60d829a0353a	1303	/ / end of group DMA_Register_Masks */
tushki7	0:60d829a0353a	1304
tushki7	0:60d829a0353a	1305
tushki7	0:60d829a0353a	1306	/* DMA - Peripheral instance base addresses */
tushki7	0:60d829a0353a	1307	/** Peripheral DMA base address */
tushki7	0:60d829a0353a	1308	#define DMA_BASE (0x40008000u)
tushki7	0:60d829a0353a	1309	/** Peripheral DMA base pointer */
tushki7	0:60d829a0353a	1310	#define DMA0 ((DMA_Type *)DMA_BASE)
tushki7	0:60d829a0353a	1311
tushki7	0:60d829a0353a	1312	/**
tushki7	0:60d829a0353a	1313	* @}
tushki7	0:60d829a0353a	1314	/ / end of group DMA_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	1315
tushki7	0:60d829a0353a	1316
tushki7	0:60d829a0353a	1317	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	1318	-- DMAMUX Peripheral Access Layer
tushki7	0:60d829a0353a	1319	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	1320
tushki7	0:60d829a0353a	1321	/**
tushki7	0:60d829a0353a	1322	* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
tushki7	0:60d829a0353a	1323	* @{
tushki7	0:60d829a0353a	1324	*/
tushki7	0:60d829a0353a	1325
tushki7	0:60d829a0353a	1326	/** DMAMUX - Register Layout Typedef */
tushki7	0:60d829a0353a	1327	typedef struct {
tushki7	0:60d829a0353a	1328	__IO uint8_t CHCFG[16]; /*< Channel Configuration Register, array offset: 0x0, array step: 0x1 /
tushki7	0:60d829a0353a	1329	} DMAMUX_Type;
tushki7	0:60d829a0353a	1330
tushki7	0:60d829a0353a	1331	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	1332	-- DMAMUX Register Masks
tushki7	0:60d829a0353a	1333	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	1334
tushki7	0:60d829a0353a	1335	/**
tushki7	0:60d829a0353a	1336	* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
tushki7	0:60d829a0353a	1337	* @{
tushki7	0:60d829a0353a	1338	*/
tushki7	0:60d829a0353a	1339
tushki7	0:60d829a0353a	1340	/* CHCFG Bit Fields */
tushki7	0:60d829a0353a	1341	#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
tushki7	0:60d829a0353a	1342	#define DMAMUX_CHCFG_SOURCE_SHIFT 0
tushki7	0:60d829a0353a	1343	#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
tushki7	0:60d829a0353a	1344	#define DMAMUX_CHCFG_TRIG_MASK 0x40u
tushki7	0:60d829a0353a	1345	#define DMAMUX_CHCFG_TRIG_SHIFT 6
tushki7	0:60d829a0353a	1346	#define DMAMUX_CHCFG_ENBL_MASK 0x80u
tushki7	0:60d829a0353a	1347	#define DMAMUX_CHCFG_ENBL_SHIFT 7
tushki7	0:60d829a0353a	1348
tushki7	0:60d829a0353a	1349	/**
tushki7	0:60d829a0353a	1350	* @}
tushki7	0:60d829a0353a	1351	/ / end of group DMAMUX_Register_Masks */
tushki7	0:60d829a0353a	1352
tushki7	0:60d829a0353a	1353
tushki7	0:60d829a0353a	1354	/* DMAMUX - Peripheral instance base addresses */
tushki7	0:60d829a0353a	1355	/** Peripheral DMAMUX base address */
tushki7	0:60d829a0353a	1356	#define DMAMUX_BASE (0x40021000u)
tushki7	0:60d829a0353a	1357	/** Peripheral DMAMUX base pointer */
tushki7	0:60d829a0353a	1358	#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
tushki7	0:60d829a0353a	1359
tushki7	0:60d829a0353a	1360	/**
tushki7	0:60d829a0353a	1361	* @}
tushki7	0:60d829a0353a	1362	/ / end of group DMAMUX_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	1363
tushki7	0:60d829a0353a	1364
tushki7	0:60d829a0353a	1365	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	1366	-- EWM Peripheral Access Layer
tushki7	0:60d829a0353a	1367	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	1368
tushki7	0:60d829a0353a	1369	/**
tushki7	0:60d829a0353a	1370	* @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
tushki7	0:60d829a0353a	1371	* @{
tushki7	0:60d829a0353a	1372	*/
tushki7	0:60d829a0353a	1373
tushki7	0:60d829a0353a	1374	/** EWM - Register Layout Typedef */
tushki7	0:60d829a0353a	1375	typedef struct {
tushki7	0:60d829a0353a	1376	__IO uint8_t CTRL; /*< Control Register, offset: 0x0 /
tushki7	0:60d829a0353a	1377	__O uint8_t SERV; /*< Service Register, offset: 0x1 /
tushki7	0:60d829a0353a	1378	__IO uint8_t CMPL; /*< Compare Low Register, offset: 0x2 /
tushki7	0:60d829a0353a	1379	__IO uint8_t CMPH; /*< Compare High Register, offset: 0x3 /
tushki7	0:60d829a0353a	1380	} EWM_Type;
tushki7	0:60d829a0353a	1381
tushki7	0:60d829a0353a	1382	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	1383	-- EWM Register Masks
tushki7	0:60d829a0353a	1384	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	1385
tushki7	0:60d829a0353a	1386	/**
tushki7	0:60d829a0353a	1387	* @addtogroup EWM_Register_Masks EWM Register Masks
tushki7	0:60d829a0353a	1388	* @{
tushki7	0:60d829a0353a	1389	*/
tushki7	0:60d829a0353a	1390
tushki7	0:60d829a0353a	1391	/* CTRL Bit Fields */
tushki7	0:60d829a0353a	1392	#define EWM_CTRL_EWMEN_MASK 0x1u
tushki7	0:60d829a0353a	1393	#define EWM_CTRL_EWMEN_SHIFT 0
tushki7	0:60d829a0353a	1394	#define EWM_CTRL_ASSIN_MASK 0x2u
tushki7	0:60d829a0353a	1395	#define EWM_CTRL_ASSIN_SHIFT 1
tushki7	0:60d829a0353a	1396	#define EWM_CTRL_INEN_MASK 0x4u
tushki7	0:60d829a0353a	1397	#define EWM_CTRL_INEN_SHIFT 2
tushki7	0:60d829a0353a	1398	#define EWM_CTRL_INTEN_MASK 0x8u
tushki7	0:60d829a0353a	1399	#define EWM_CTRL_INTEN_SHIFT 3
tushki7	0:60d829a0353a	1400	/* SERV Bit Fields */
tushki7	0:60d829a0353a	1401	#define EWM_SERV_SERVICE_MASK 0xFFu
tushki7	0:60d829a0353a	1402	#define EWM_SERV_SERVICE_SHIFT 0
tushki7	0:60d829a0353a	1403	#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
tushki7	0:60d829a0353a	1404	/* CMPL Bit Fields */
tushki7	0:60d829a0353a	1405	#define EWM_CMPL_COMPAREL_MASK 0xFFu
tushki7	0:60d829a0353a	1406	#define EWM_CMPL_COMPAREL_SHIFT 0
tushki7	0:60d829a0353a	1407	#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
tushki7	0:60d829a0353a	1408	/* CMPH Bit Fields */
tushki7	0:60d829a0353a	1409	#define EWM_CMPH_COMPAREH_MASK 0xFFu
tushki7	0:60d829a0353a	1410	#define EWM_CMPH_COMPAREH_SHIFT 0
tushki7	0:60d829a0353a	1411	#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
tushki7	0:60d829a0353a	1412
tushki7	0:60d829a0353a	1413	/**
tushki7	0:60d829a0353a	1414	* @}
tushki7	0:60d829a0353a	1415	/ / end of group EWM_Register_Masks */
tushki7	0:60d829a0353a	1416
tushki7	0:60d829a0353a	1417
tushki7	0:60d829a0353a	1418	/* EWM - Peripheral instance base addresses */
tushki7	0:60d829a0353a	1419	/** Peripheral EWM base address */
tushki7	0:60d829a0353a	1420	#define EWM_BASE (0x40061000u)
tushki7	0:60d829a0353a	1421	/** Peripheral EWM base pointer */
tushki7	0:60d829a0353a	1422	#define EWM ((EWM_Type *)EWM_BASE)
tushki7	0:60d829a0353a	1423
tushki7	0:60d829a0353a	1424	/**
tushki7	0:60d829a0353a	1425	* @}
tushki7	0:60d829a0353a	1426	/ / end of group EWM_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	1427
tushki7	0:60d829a0353a	1428
tushki7	0:60d829a0353a	1429	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	1430	-- FMC Peripheral Access Layer
tushki7	0:60d829a0353a	1431	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	1432
tushki7	0:60d829a0353a	1433	/**
tushki7	0:60d829a0353a	1434	* @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
tushki7	0:60d829a0353a	1435	* @{
tushki7	0:60d829a0353a	1436	*/
tushki7	0:60d829a0353a	1437
tushki7	0:60d829a0353a	1438	/** FMC - Register Layout Typedef */
tushki7	0:60d829a0353a	1439	typedef struct {
tushki7	0:60d829a0353a	1440	__IO uint32_t PFAPR; /*< Flash Access Protection Register, offset: 0x0 /
tushki7	0:60d829a0353a	1441	__IO uint32_t PFB0CR; /*< Flash Control Register, offset: 0x4 /
tushki7	0:60d829a0353a	1442	uint8_t RESERVED_0[248];
tushki7	0:60d829a0353a	1443	struct { /* offset: 0x100, array step: 0x20 */
tushki7	0:60d829a0353a	1444	__IO uint32_t TAGVD[2]; /*< Cache Tag Storage, array offset: 0x100, array step: index0x20, index20x4 /
tushki7	0:60d829a0353a	1445	uint8_t RESERVED_0[24];
tushki7	0:60d829a0353a	1446	} TAG_WAY[4];
tushki7	0:60d829a0353a	1447	uint8_t RESERVED_1[132];
tushki7	0:60d829a0353a	1448	struct { /* offset: 0x204, array step: 0x8 */
tushki7	0:60d829a0353a	1449	__IO uint32_t DATAW0S; /*< Cache Data Storage, array offset: 0x204, array step: 0x8 /
tushki7	0:60d829a0353a	1450	uint8_t RESERVED_0[4];
tushki7	0:60d829a0353a	1451	} DATAW0S[2];
tushki7	0:60d829a0353a	1452	uint8_t RESERVED_2[48];
tushki7	0:60d829a0353a	1453	struct { /* offset: 0x244, array step: 0x8 */
tushki7	0:60d829a0353a	1454	__IO uint32_t DATAW1S; /*< Cache Data Storage, array offset: 0x244, array step: 0x8 /
tushki7	0:60d829a0353a	1455	uint8_t RESERVED_0[4];
tushki7	0:60d829a0353a	1456	} DATAW1S[2];
tushki7	0:60d829a0353a	1457	uint8_t RESERVED_3[48];
tushki7	0:60d829a0353a	1458	struct { /* offset: 0x284, array step: 0x8 */
tushki7	0:60d829a0353a	1459	__IO uint32_t DATAW2S; /*< Cache Data Storage, array offset: 0x284, array step: 0x8 /
tushki7	0:60d829a0353a	1460	uint8_t RESERVED_0[4];
tushki7	0:60d829a0353a	1461	} DATAW2S[2];
tushki7	0:60d829a0353a	1462	uint8_t RESERVED_4[48];
tushki7	0:60d829a0353a	1463	struct { /* offset: 0x2C4, array step: 0x8 */
tushki7	0:60d829a0353a	1464	__IO uint32_t DATAW3S; /*< Cache Data Storage, array offset: 0x2C4, array step: 0x8 /
tushki7	0:60d829a0353a	1465	uint8_t RESERVED_0[4];
tushki7	0:60d829a0353a	1466	} DATAW3S[2];
tushki7	0:60d829a0353a	1467	} FMC_Type;
tushki7	0:60d829a0353a	1468
tushki7	0:60d829a0353a	1469	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	1470	-- FMC Register Masks
tushki7	0:60d829a0353a	1471	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	1472
tushki7	0:60d829a0353a	1473	/**
tushki7	0:60d829a0353a	1474	* @addtogroup FMC_Register_Masks FMC Register Masks
tushki7	0:60d829a0353a	1475	* @{
tushki7	0:60d829a0353a	1476	*/
tushki7	0:60d829a0353a	1477
tushki7	0:60d829a0353a	1478	/* PFAPR Bit Fields */
tushki7	0:60d829a0353a	1479	#define FMC_PFAPR_M0AP_MASK 0x3u
tushki7	0:60d829a0353a	1480	#define FMC_PFAPR_M0AP_SHIFT 0
tushki7	0:60d829a0353a	1481	#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
tushki7	0:60d829a0353a	1482	#define FMC_PFAPR_M1AP_MASK 0xCu
tushki7	0:60d829a0353a	1483	#define FMC_PFAPR_M1AP_SHIFT 2
tushki7	0:60d829a0353a	1484	#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
tushki7	0:60d829a0353a	1485	#define FMC_PFAPR_M2AP_MASK 0x30u
tushki7	0:60d829a0353a	1486	#define FMC_PFAPR_M2AP_SHIFT 4
tushki7	0:60d829a0353a	1487	#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
tushki7	0:60d829a0353a	1488	#define FMC_PFAPR_M3AP_MASK 0xC0u
tushki7	0:60d829a0353a	1489	#define FMC_PFAPR_M3AP_SHIFT 6
tushki7	0:60d829a0353a	1490	#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
tushki7	0:60d829a0353a	1491	#define FMC_PFAPR_M0PFD_MASK 0x10000u
tushki7	0:60d829a0353a	1492	#define FMC_PFAPR_M0PFD_SHIFT 16
tushki7	0:60d829a0353a	1493	#define FMC_PFAPR_M1PFD_MASK 0x20000u
tushki7	0:60d829a0353a	1494	#define FMC_PFAPR_M1PFD_SHIFT 17
tushki7	0:60d829a0353a	1495	#define FMC_PFAPR_M2PFD_MASK 0x40000u
tushki7	0:60d829a0353a	1496	#define FMC_PFAPR_M2PFD_SHIFT 18
tushki7	0:60d829a0353a	1497	#define FMC_PFAPR_M3PFD_MASK 0x80000u
tushki7	0:60d829a0353a	1498	#define FMC_PFAPR_M3PFD_SHIFT 19
tushki7	0:60d829a0353a	1499	/* PFB0CR Bit Fields */
tushki7	0:60d829a0353a	1500	#define FMC_PFB0CR_B0SEBE_MASK 0x1u
tushki7	0:60d829a0353a	1501	#define FMC_PFB0CR_B0SEBE_SHIFT 0
tushki7	0:60d829a0353a	1502	#define FMC_PFB0CR_B0IPE_MASK 0x2u
tushki7	0:60d829a0353a	1503	#define FMC_PFB0CR_B0IPE_SHIFT 1
tushki7	0:60d829a0353a	1504	#define FMC_PFB0CR_B0DPE_MASK 0x4u
tushki7	0:60d829a0353a	1505	#define FMC_PFB0CR_B0DPE_SHIFT 2
tushki7	0:60d829a0353a	1506	#define FMC_PFB0CR_B0ICE_MASK 0x8u
tushki7	0:60d829a0353a	1507	#define FMC_PFB0CR_B0ICE_SHIFT 3
tushki7	0:60d829a0353a	1508	#define FMC_PFB0CR_B0DCE_MASK 0x10u
tushki7	0:60d829a0353a	1509	#define FMC_PFB0CR_B0DCE_SHIFT 4
tushki7	0:60d829a0353a	1510	#define FMC_PFB0CR_CRC_MASK 0xE0u
tushki7	0:60d829a0353a	1511	#define FMC_PFB0CR_CRC_SHIFT 5
tushki7	0:60d829a0353a	1512	#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
tushki7	0:60d829a0353a	1513	#define FMC_PFB0CR_B0MW_MASK 0x60000u
tushki7	0:60d829a0353a	1514	#define FMC_PFB0CR_B0MW_SHIFT 17
tushki7	0:60d829a0353a	1515	#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
tushki7	0:60d829a0353a	1516	#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
tushki7	0:60d829a0353a	1517	#define FMC_PFB0CR_S_B_INV_SHIFT 19
tushki7	0:60d829a0353a	1518	#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
tushki7	0:60d829a0353a	1519	#define FMC_PFB0CR_CINV_WAY_SHIFT 20
tushki7	0:60d829a0353a	1520	#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
tushki7	0:60d829a0353a	1521	#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
tushki7	0:60d829a0353a	1522	#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
tushki7	0:60d829a0353a	1523	#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
tushki7	0:60d829a0353a	1524	#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
tushki7	0:60d829a0353a	1525	#define FMC_PFB0CR_B0RWSC_SHIFT 28
tushki7	0:60d829a0353a	1526	#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
tushki7	0:60d829a0353a	1527	/* TAGVD Bit Fields */
tushki7	0:60d829a0353a	1528	#define FMC_TAGVD_valid_MASK 0x1u
tushki7	0:60d829a0353a	1529	#define FMC_TAGVD_valid_SHIFT 0
tushki7	0:60d829a0353a	1530	#define FMC_TAGVD_tag_MASK 0x7FFC0u
tushki7	0:60d829a0353a	1531	#define FMC_TAGVD_tag_SHIFT 6
tushki7	0:60d829a0353a	1532	#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
tushki7	0:60d829a0353a	1533	/* DATAW0S Bit Fields */
tushki7	0:60d829a0353a	1534	#define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	1535	#define FMC_DATAW0S_data_SHIFT 0
tushki7	0:60d829a0353a	1536	#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
tushki7	0:60d829a0353a	1537	/* DATAW1S Bit Fields */
tushki7	0:60d829a0353a	1538	#define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	1539	#define FMC_DATAW1S_data_SHIFT 0
tushki7	0:60d829a0353a	1540	#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
tushki7	0:60d829a0353a	1541	/* DATAW2S Bit Fields */
tushki7	0:60d829a0353a	1542	#define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	1543	#define FMC_DATAW2S_data_SHIFT 0
tushki7	0:60d829a0353a	1544	#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
tushki7	0:60d829a0353a	1545	/* DATAW3S Bit Fields */
tushki7	0:60d829a0353a	1546	#define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	1547	#define FMC_DATAW3S_data_SHIFT 0
tushki7	0:60d829a0353a	1548	#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
tushki7	0:60d829a0353a	1549
tushki7	0:60d829a0353a	1550	/**
tushki7	0:60d829a0353a	1551	* @}
tushki7	0:60d829a0353a	1552	/ / end of group FMC_Register_Masks */
tushki7	0:60d829a0353a	1553
tushki7	0:60d829a0353a	1554
tushki7	0:60d829a0353a	1555	/* FMC - Peripheral instance base addresses */
tushki7	0:60d829a0353a	1556	/** Peripheral FMC base address */
tushki7	0:60d829a0353a	1557	#define FMC_BASE (0x4001F000u)
tushki7	0:60d829a0353a	1558	/** Peripheral FMC base pointer */
tushki7	0:60d829a0353a	1559	#define FMC ((FMC_Type *)FMC_BASE)
tushki7	0:60d829a0353a	1560
tushki7	0:60d829a0353a	1561	/**
tushki7	0:60d829a0353a	1562	* @}
tushki7	0:60d829a0353a	1563	/ / end of group FMC_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	1564
tushki7	0:60d829a0353a	1565
tushki7	0:60d829a0353a	1566	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	1567	-- FTFL Peripheral Access Layer
tushki7	0:60d829a0353a	1568	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	1569
tushki7	0:60d829a0353a	1570	/**
tushki7	0:60d829a0353a	1571	* @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
tushki7	0:60d829a0353a	1572	* @{
tushki7	0:60d829a0353a	1573	*/
tushki7	0:60d829a0353a	1574
tushki7	0:60d829a0353a	1575	/** FTFL - Register Layout Typedef */
tushki7	0:60d829a0353a	1576	typedef struct {
tushki7	0:60d829a0353a	1577	__IO uint8_t FSTAT; /*< Flash Status Register, offset: 0x0 /
tushki7	0:60d829a0353a	1578	__IO uint8_t FCNFG; /*< Flash Configuration Register, offset: 0x1 /
tushki7	0:60d829a0353a	1579	__I uint8_t FSEC; /*< Flash Security Register, offset: 0x2 /
tushki7	0:60d829a0353a	1580	__I uint8_t FOPT; /*< Flash Option Register, offset: 0x3 /
tushki7	0:60d829a0353a	1581	__IO uint8_t FCCOB3; /*< Flash Common Command Object Registers, offset: 0x4 /
tushki7	0:60d829a0353a	1582	__IO uint8_t FCCOB2; /*< Flash Common Command Object Registers, offset: 0x5 /
tushki7	0:60d829a0353a	1583	__IO uint8_t FCCOB1; /*< Flash Common Command Object Registers, offset: 0x6 /
tushki7	0:60d829a0353a	1584	__IO uint8_t FCCOB0; /*< Flash Common Command Object Registers, offset: 0x7 /
tushki7	0:60d829a0353a	1585	__IO uint8_t FCCOB7; /*< Flash Common Command Object Registers, offset: 0x8 /
tushki7	0:60d829a0353a	1586	__IO uint8_t FCCOB6; /*< Flash Common Command Object Registers, offset: 0x9 /
tushki7	0:60d829a0353a	1587	__IO uint8_t FCCOB5; /*< Flash Common Command Object Registers, offset: 0xA /
tushki7	0:60d829a0353a	1588	__IO uint8_t FCCOB4; /*< Flash Common Command Object Registers, offset: 0xB /
tushki7	0:60d829a0353a	1589	__IO uint8_t FCCOBB; /*< Flash Common Command Object Registers, offset: 0xC /
tushki7	0:60d829a0353a	1590	__IO uint8_t FCCOBA; /*< Flash Common Command Object Registers, offset: 0xD /
tushki7	0:60d829a0353a	1591	__IO uint8_t FCCOB9; /*< Flash Common Command Object Registers, offset: 0xE /
tushki7	0:60d829a0353a	1592	__IO uint8_t FCCOB8; /*< Flash Common Command Object Registers, offset: 0xF /
tushki7	0:60d829a0353a	1593	__IO uint8_t FPROT3; /*< Program Flash Protection Registers, offset: 0x10 /
tushki7	0:60d829a0353a	1594	__IO uint8_t FPROT2; /*< Program Flash Protection Registers, offset: 0x11 /
tushki7	0:60d829a0353a	1595	__IO uint8_t FPROT1; /*< Program Flash Protection Registers, offset: 0x12 /
tushki7	0:60d829a0353a	1596	__IO uint8_t FPROT0; /*< Program Flash Protection Registers, offset: 0x13 /
tushki7	0:60d829a0353a	1597	uint8_t RESERVED_0[2];
tushki7	0:60d829a0353a	1598	__IO uint8_t FEPROT; /*< EEPROM Protection Register, offset: 0x16 /
tushki7	0:60d829a0353a	1599	__IO uint8_t FDPROT; /*< Data Flash Protection Register, offset: 0x17 /
tushki7	0:60d829a0353a	1600	} FTFL_Type;
tushki7	0:60d829a0353a	1601
tushki7	0:60d829a0353a	1602	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	1603	-- FTFL Register Masks
tushki7	0:60d829a0353a	1604	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	1605
tushki7	0:60d829a0353a	1606	/**
tushki7	0:60d829a0353a	1607	* @addtogroup FTFL_Register_Masks FTFL Register Masks
tushki7	0:60d829a0353a	1608	* @{
tushki7	0:60d829a0353a	1609	*/
tushki7	0:60d829a0353a	1610
tushki7	0:60d829a0353a	1611	/* FSTAT Bit Fields */
tushki7	0:60d829a0353a	1612	#define FTFL_FSTAT_MGSTAT0_MASK 0x1u
tushki7	0:60d829a0353a	1613	#define FTFL_FSTAT_MGSTAT0_SHIFT 0
tushki7	0:60d829a0353a	1614	#define FTFL_FSTAT_FPVIOL_MASK 0x10u
tushki7	0:60d829a0353a	1615	#define FTFL_FSTAT_FPVIOL_SHIFT 4
tushki7	0:60d829a0353a	1616	#define FTFL_FSTAT_ACCERR_MASK 0x20u
tushki7	0:60d829a0353a	1617	#define FTFL_FSTAT_ACCERR_SHIFT 5
tushki7	0:60d829a0353a	1618	#define FTFL_FSTAT_RDCOLERR_MASK 0x40u
tushki7	0:60d829a0353a	1619	#define FTFL_FSTAT_RDCOLERR_SHIFT 6
tushki7	0:60d829a0353a	1620	#define FTFL_FSTAT_CCIF_MASK 0x80u
tushki7	0:60d829a0353a	1621	#define FTFL_FSTAT_CCIF_SHIFT 7
tushki7	0:60d829a0353a	1622	/* FCNFG Bit Fields */
tushki7	0:60d829a0353a	1623	#define FTFL_FCNFG_EEERDY_MASK 0x1u
tushki7	0:60d829a0353a	1624	#define FTFL_FCNFG_EEERDY_SHIFT 0
tushki7	0:60d829a0353a	1625	#define FTFL_FCNFG_RAMRDY_MASK 0x2u
tushki7	0:60d829a0353a	1626	#define FTFL_FCNFG_RAMRDY_SHIFT 1
tushki7	0:60d829a0353a	1627	#define FTFL_FCNFG_PFLSH_MASK 0x4u
tushki7	0:60d829a0353a	1628	#define FTFL_FCNFG_PFLSH_SHIFT 2
tushki7	0:60d829a0353a	1629	#define FTFL_FCNFG_ERSSUSP_MASK 0x10u
tushki7	0:60d829a0353a	1630	#define FTFL_FCNFG_ERSSUSP_SHIFT 4
tushki7	0:60d829a0353a	1631	#define FTFL_FCNFG_ERSAREQ_MASK 0x20u
tushki7	0:60d829a0353a	1632	#define FTFL_FCNFG_ERSAREQ_SHIFT 5
tushki7	0:60d829a0353a	1633	#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
tushki7	0:60d829a0353a	1634	#define FTFL_FCNFG_RDCOLLIE_SHIFT 6
tushki7	0:60d829a0353a	1635	#define FTFL_FCNFG_CCIE_MASK 0x80u
tushki7	0:60d829a0353a	1636	#define FTFL_FCNFG_CCIE_SHIFT 7
tushki7	0:60d829a0353a	1637	/* FSEC Bit Fields */
tushki7	0:60d829a0353a	1638	#define FTFL_FSEC_SEC_MASK 0x3u
tushki7	0:60d829a0353a	1639	#define FTFL_FSEC_SEC_SHIFT 0
tushki7	0:60d829a0353a	1640	#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
tushki7	0:60d829a0353a	1641	#define FTFL_FSEC_FSLACC_MASK 0xCu
tushki7	0:60d829a0353a	1642	#define FTFL_FSEC_FSLACC_SHIFT 2
tushki7	0:60d829a0353a	1643	#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
tushki7	0:60d829a0353a	1644	#define FTFL_FSEC_MEEN_MASK 0x30u
tushki7	0:60d829a0353a	1645	#define FTFL_FSEC_MEEN_SHIFT 4
tushki7	0:60d829a0353a	1646	#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
tushki7	0:60d829a0353a	1647	#define FTFL_FSEC_KEYEN_MASK 0xC0u
tushki7	0:60d829a0353a	1648	#define FTFL_FSEC_KEYEN_SHIFT 6
tushki7	0:60d829a0353a	1649	#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
tushki7	0:60d829a0353a	1650	/* FOPT Bit Fields */
tushki7	0:60d829a0353a	1651	#define FTFL_FOPT_OPT_MASK 0xFFu
tushki7	0:60d829a0353a	1652	#define FTFL_FOPT_OPT_SHIFT 0
tushki7	0:60d829a0353a	1653	#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
tushki7	0:60d829a0353a	1654	/* FCCOB3 Bit Fields */
tushki7	0:60d829a0353a	1655	#define FTFL_FCCOB3_CCOBn_MASK 0xFFu
tushki7	0:60d829a0353a	1656	#define FTFL_FCCOB3_CCOBn_SHIFT 0
tushki7	0:60d829a0353a	1657	#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
tushki7	0:60d829a0353a	1658	/* FCCOB2 Bit Fields */
tushki7	0:60d829a0353a	1659	#define FTFL_FCCOB2_CCOBn_MASK 0xFFu
tushki7	0:60d829a0353a	1660	#define FTFL_FCCOB2_CCOBn_SHIFT 0
tushki7	0:60d829a0353a	1661	#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
tushki7	0:60d829a0353a	1662	/* FCCOB1 Bit Fields */
tushki7	0:60d829a0353a	1663	#define FTFL_FCCOB1_CCOBn_MASK 0xFFu
tushki7	0:60d829a0353a	1664	#define FTFL_FCCOB1_CCOBn_SHIFT 0
tushki7	0:60d829a0353a	1665	#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
tushki7	0:60d829a0353a	1666	/* FCCOB0 Bit Fields */
tushki7	0:60d829a0353a	1667	#define FTFL_FCCOB0_CCOBn_MASK 0xFFu
tushki7	0:60d829a0353a	1668	#define FTFL_FCCOB0_CCOBn_SHIFT 0
tushki7	0:60d829a0353a	1669	#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
tushki7	0:60d829a0353a	1670	/* FCCOB7 Bit Fields */
tushki7	0:60d829a0353a	1671	#define FTFL_FCCOB7_CCOBn_MASK 0xFFu
tushki7	0:60d829a0353a	1672	#define FTFL_FCCOB7_CCOBn_SHIFT 0
tushki7	0:60d829a0353a	1673	#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
tushki7	0:60d829a0353a	1674	/* FCCOB6 Bit Fields */
tushki7	0:60d829a0353a	1675	#define FTFL_FCCOB6_CCOBn_MASK 0xFFu
tushki7	0:60d829a0353a	1676	#define FTFL_FCCOB6_CCOBn_SHIFT 0
tushki7	0:60d829a0353a	1677	#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
tushki7	0:60d829a0353a	1678	/* FCCOB5 Bit Fields */
tushki7	0:60d829a0353a	1679	#define FTFL_FCCOB5_CCOBn_MASK 0xFFu
tushki7	0:60d829a0353a	1680	#define FTFL_FCCOB5_CCOBn_SHIFT 0
tushki7	0:60d829a0353a	1681	#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
tushki7	0:60d829a0353a	1682	/* FCCOB4 Bit Fields */
tushki7	0:60d829a0353a	1683	#define FTFL_FCCOB4_CCOBn_MASK 0xFFu
tushki7	0:60d829a0353a	1684	#define FTFL_FCCOB4_CCOBn_SHIFT 0
tushki7	0:60d829a0353a	1685	#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
tushki7	0:60d829a0353a	1686	/* FCCOBB Bit Fields */
tushki7	0:60d829a0353a	1687	#define FTFL_FCCOBB_CCOBn_MASK 0xFFu
tushki7	0:60d829a0353a	1688	#define FTFL_FCCOBB_CCOBn_SHIFT 0
tushki7	0:60d829a0353a	1689	#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
tushki7	0:60d829a0353a	1690	/* FCCOBA Bit Fields */
tushki7	0:60d829a0353a	1691	#define FTFL_FCCOBA_CCOBn_MASK 0xFFu
tushki7	0:60d829a0353a	1692	#define FTFL_FCCOBA_CCOBn_SHIFT 0
tushki7	0:60d829a0353a	1693	#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
tushki7	0:60d829a0353a	1694	/* FCCOB9 Bit Fields */
tushki7	0:60d829a0353a	1695	#define FTFL_FCCOB9_CCOBn_MASK 0xFFu
tushki7	0:60d829a0353a	1696	#define FTFL_FCCOB9_CCOBn_SHIFT 0
tushki7	0:60d829a0353a	1697	#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
tushki7	0:60d829a0353a	1698	/* FCCOB8 Bit Fields */
tushki7	0:60d829a0353a	1699	#define FTFL_FCCOB8_CCOBn_MASK 0xFFu
tushki7	0:60d829a0353a	1700	#define FTFL_FCCOB8_CCOBn_SHIFT 0
tushki7	0:60d829a0353a	1701	#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
tushki7	0:60d829a0353a	1702	/* FPROT3 Bit Fields */
tushki7	0:60d829a0353a	1703	#define FTFL_FPROT3_PROT_MASK 0xFFu
tushki7	0:60d829a0353a	1704	#define FTFL_FPROT3_PROT_SHIFT 0
tushki7	0:60d829a0353a	1705	#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
tushki7	0:60d829a0353a	1706	/* FPROT2 Bit Fields */
tushki7	0:60d829a0353a	1707	#define FTFL_FPROT2_PROT_MASK 0xFFu
tushki7	0:60d829a0353a	1708	#define FTFL_FPROT2_PROT_SHIFT 0
tushki7	0:60d829a0353a	1709	#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
tushki7	0:60d829a0353a	1710	/* FPROT1 Bit Fields */
tushki7	0:60d829a0353a	1711	#define FTFL_FPROT1_PROT_MASK 0xFFu
tushki7	0:60d829a0353a	1712	#define FTFL_FPROT1_PROT_SHIFT 0
tushki7	0:60d829a0353a	1713	#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
tushki7	0:60d829a0353a	1714	/* FPROT0 Bit Fields */
tushki7	0:60d829a0353a	1715	#define FTFL_FPROT0_PROT_MASK 0xFFu
tushki7	0:60d829a0353a	1716	#define FTFL_FPROT0_PROT_SHIFT 0
tushki7	0:60d829a0353a	1717	#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
tushki7	0:60d829a0353a	1718	/* FEPROT Bit Fields */
tushki7	0:60d829a0353a	1719	#define FTFL_FEPROT_EPROT_MASK 0xFFu
tushki7	0:60d829a0353a	1720	#define FTFL_FEPROT_EPROT_SHIFT 0
tushki7	0:60d829a0353a	1721	#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
tushki7	0:60d829a0353a	1722	/* FDPROT Bit Fields */
tushki7	0:60d829a0353a	1723	#define FTFL_FDPROT_DPROT_MASK 0xFFu
tushki7	0:60d829a0353a	1724	#define FTFL_FDPROT_DPROT_SHIFT 0
tushki7	0:60d829a0353a	1725	#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
tushki7	0:60d829a0353a	1726
tushki7	0:60d829a0353a	1727	/**
tushki7	0:60d829a0353a	1728	* @}
tushki7	0:60d829a0353a	1729	/ / end of group FTFL_Register_Masks */
tushki7	0:60d829a0353a	1730
tushki7	0:60d829a0353a	1731
tushki7	0:60d829a0353a	1732	/* FTFL - Peripheral instance base addresses */
tushki7	0:60d829a0353a	1733	/** Peripheral FTFL base address */
tushki7	0:60d829a0353a	1734	#define FTFL_BASE (0x40020000u)
tushki7	0:60d829a0353a	1735	/** Peripheral FTFL base pointer */
tushki7	0:60d829a0353a	1736	#define FTFL ((FTFL_Type *)FTFL_BASE)
tushki7	0:60d829a0353a	1737
tushki7	0:60d829a0353a	1738	/**
tushki7	0:60d829a0353a	1739	* @}
tushki7	0:60d829a0353a	1740	/ / end of group FTFL_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	1741
tushki7	0:60d829a0353a	1742
tushki7	0:60d829a0353a	1743	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	1744	-- FTM Peripheral Access Layer
tushki7	0:60d829a0353a	1745	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	1746
tushki7	0:60d829a0353a	1747	/**
tushki7	0:60d829a0353a	1748	* @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
tushki7	0:60d829a0353a	1749	* @{
tushki7	0:60d829a0353a	1750	*/
tushki7	0:60d829a0353a	1751
tushki7	0:60d829a0353a	1752	/** FTM - Register Layout Typedef */
tushki7	0:60d829a0353a	1753	typedef struct {
tushki7	0:60d829a0353a	1754	__IO uint32_t SC; /*< Status and Control, offset: 0x0 /
tushki7	0:60d829a0353a	1755	__IO uint32_t CNT; /*< Counter, offset: 0x4 /
tushki7	0:60d829a0353a	1756	__IO uint32_t MOD; /*< Modulo, offset: 0x8 /
tushki7	0:60d829a0353a	1757	struct { /* offset: 0xC, array step: 0x8 */
tushki7	0:60d829a0353a	1758	__IO uint32_t CnSC; /*< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 /
tushki7	0:60d829a0353a	1759	__IO uint32_t CnV; /*< Channel (n) Value, array offset: 0x10, array step: 0x8 /
tushki7	0:60d829a0353a	1760	} CONTROLS[8];
tushki7	0:60d829a0353a	1761	__IO uint32_t CNTIN; /*< Counter Initial Value, offset: 0x4C /
tushki7	0:60d829a0353a	1762	__I uint32_t STATUS; /*< Capture and Compare Status, offset: 0x50 /
tushki7	0:60d829a0353a	1763	__IO uint32_t MODE; /*< Features Mode Selection, offset: 0x54 /
tushki7	0:60d829a0353a	1764	__IO uint32_t SYNC; /*< Synchronization, offset: 0x58 /
tushki7	0:60d829a0353a	1765	__IO uint32_t OUTINIT; /*< Initial State for Channels Output, offset: 0x5C /
tushki7	0:60d829a0353a	1766	__IO uint32_t OUTMASK; /*< Output Mask, offset: 0x60 /
tushki7	0:60d829a0353a	1767	__IO uint32_t COMBINE; /*< Function for Linked Channels, offset: 0x64 /
tushki7	0:60d829a0353a	1768	__IO uint32_t DEADTIME; /*< Deadtime Insertion Control, offset: 0x68 /
tushki7	0:60d829a0353a	1769	__IO uint32_t EXTTRIG; /*< FTM External Trigger, offset: 0x6C /
tushki7	0:60d829a0353a	1770	__IO uint32_t POL; /*< Channels Polarity, offset: 0x70 /
tushki7	0:60d829a0353a	1771	__IO uint32_t FMS; /*< Fault Mode Status, offset: 0x74 /
tushki7	0:60d829a0353a	1772	__IO uint32_t FILTER; /*< Input Capture Filter Control, offset: 0x78 /
tushki7	0:60d829a0353a	1773	__IO uint32_t FLTCTRL; /*< Fault Control, offset: 0x7C /
tushki7	0:60d829a0353a	1774	__IO uint32_t QDCTRL; /*< Quadrature Decoder Control and Status, offset: 0x80 /
tushki7	0:60d829a0353a	1775	__IO uint32_t CONF; /*< Configuration, offset: 0x84 /
tushki7	0:60d829a0353a	1776	__IO uint32_t FLTPOL; /*< FTM Fault Input Polarity, offset: 0x88 /
tushki7	0:60d829a0353a	1777	__IO uint32_t SYNCONF; /*< Synchronization Configuration, offset: 0x8C /
tushki7	0:60d829a0353a	1778	__IO uint32_t INVCTRL; /*< FTM Inverting Control, offset: 0x90 /
tushki7	0:60d829a0353a	1779	__IO uint32_t SWOCTRL; /*< FTM Software Output Control, offset: 0x94 /
tushki7	0:60d829a0353a	1780	__IO uint32_t PWMLOAD; /*< FTM PWM Load, offset: 0x98 /
tushki7	0:60d829a0353a	1781	} FTM_Type;
tushki7	0:60d829a0353a	1782
tushki7	0:60d829a0353a	1783	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	1784	-- FTM Register Masks
tushki7	0:60d829a0353a	1785	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	1786
tushki7	0:60d829a0353a	1787	/**
tushki7	0:60d829a0353a	1788	* @addtogroup FTM_Register_Masks FTM Register Masks
tushki7	0:60d829a0353a	1789	* @{
tushki7	0:60d829a0353a	1790	*/
tushki7	0:60d829a0353a	1791
tushki7	0:60d829a0353a	1792	/* SC Bit Fields */
tushki7	0:60d829a0353a	1793	#define FTM_SC_PS_MASK 0x7u
tushki7	0:60d829a0353a	1794	#define FTM_SC_PS_SHIFT 0
tushki7	0:60d829a0353a	1795	#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
tushki7	0:60d829a0353a	1796	#define FTM_SC_CLKS_MASK 0x18u
tushki7	0:60d829a0353a	1797	#define FTM_SC_CLKS_SHIFT 3
tushki7	0:60d829a0353a	1798	#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
tushki7	0:60d829a0353a	1799	#define FTM_SC_CPWMS_MASK 0x20u
tushki7	0:60d829a0353a	1800	#define FTM_SC_CPWMS_SHIFT 5
tushki7	0:60d829a0353a	1801	#define FTM_SC_TOIE_MASK 0x40u
tushki7	0:60d829a0353a	1802	#define FTM_SC_TOIE_SHIFT 6
tushki7	0:60d829a0353a	1803	#define FTM_SC_TOF_MASK 0x80u
tushki7	0:60d829a0353a	1804	#define FTM_SC_TOF_SHIFT 7
tushki7	0:60d829a0353a	1805	/* CNT Bit Fields */
tushki7	0:60d829a0353a	1806	#define FTM_CNT_COUNT_MASK 0xFFFFu
tushki7	0:60d829a0353a	1807	#define FTM_CNT_COUNT_SHIFT 0
tushki7	0:60d829a0353a	1808	#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
tushki7	0:60d829a0353a	1809	/* MOD Bit Fields */
tushki7	0:60d829a0353a	1810	#define FTM_MOD_MOD_MASK 0xFFFFu
tushki7	0:60d829a0353a	1811	#define FTM_MOD_MOD_SHIFT 0
tushki7	0:60d829a0353a	1812	#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
tushki7	0:60d829a0353a	1813	/* CnSC Bit Fields */
tushki7	0:60d829a0353a	1814	#define FTM_CnSC_DMA_MASK 0x1u
tushki7	0:60d829a0353a	1815	#define FTM_CnSC_DMA_SHIFT 0
tushki7	0:60d829a0353a	1816	#define FTM_CnSC_ELSA_MASK 0x4u
tushki7	0:60d829a0353a	1817	#define FTM_CnSC_ELSA_SHIFT 2
tushki7	0:60d829a0353a	1818	#define FTM_CnSC_ELSB_MASK 0x8u
tushki7	0:60d829a0353a	1819	#define FTM_CnSC_ELSB_SHIFT 3
tushki7	0:60d829a0353a	1820	#define FTM_CnSC_MSA_MASK 0x10u
tushki7	0:60d829a0353a	1821	#define FTM_CnSC_MSA_SHIFT 4
tushki7	0:60d829a0353a	1822	#define FTM_CnSC_MSB_MASK 0x20u
tushki7	0:60d829a0353a	1823	#define FTM_CnSC_MSB_SHIFT 5
tushki7	0:60d829a0353a	1824	#define FTM_CnSC_CHIE_MASK 0x40u
tushki7	0:60d829a0353a	1825	#define FTM_CnSC_CHIE_SHIFT 6
tushki7	0:60d829a0353a	1826	#define FTM_CnSC_CHF_MASK 0x80u
tushki7	0:60d829a0353a	1827	#define FTM_CnSC_CHF_SHIFT 7
tushki7	0:60d829a0353a	1828	/* CnV Bit Fields */
tushki7	0:60d829a0353a	1829	#define FTM_CnV_VAL_MASK 0xFFFFu
tushki7	0:60d829a0353a	1830	#define FTM_CnV_VAL_SHIFT 0
tushki7	0:60d829a0353a	1831	#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
tushki7	0:60d829a0353a	1832	/* CNTIN Bit Fields */
tushki7	0:60d829a0353a	1833	#define FTM_CNTIN_INIT_MASK 0xFFFFu
tushki7	0:60d829a0353a	1834	#define FTM_CNTIN_INIT_SHIFT 0
tushki7	0:60d829a0353a	1835	#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
tushki7	0:60d829a0353a	1836	/* STATUS Bit Fields */
tushki7	0:60d829a0353a	1837	#define FTM_STATUS_CH0F_MASK 0x1u
tushki7	0:60d829a0353a	1838	#define FTM_STATUS_CH0F_SHIFT 0
tushki7	0:60d829a0353a	1839	#define FTM_STATUS_CH1F_MASK 0x2u
tushki7	0:60d829a0353a	1840	#define FTM_STATUS_CH1F_SHIFT 1
tushki7	0:60d829a0353a	1841	#define FTM_STATUS_CH2F_MASK 0x4u
tushki7	0:60d829a0353a	1842	#define FTM_STATUS_CH2F_SHIFT 2
tushki7	0:60d829a0353a	1843	#define FTM_STATUS_CH3F_MASK 0x8u
tushki7	0:60d829a0353a	1844	#define FTM_STATUS_CH3F_SHIFT 3
tushki7	0:60d829a0353a	1845	#define FTM_STATUS_CH4F_MASK 0x10u
tushki7	0:60d829a0353a	1846	#define FTM_STATUS_CH4F_SHIFT 4
tushki7	0:60d829a0353a	1847	#define FTM_STATUS_CH5F_MASK 0x20u
tushki7	0:60d829a0353a	1848	#define FTM_STATUS_CH5F_SHIFT 5
tushki7	0:60d829a0353a	1849	#define FTM_STATUS_CH6F_MASK 0x40u
tushki7	0:60d829a0353a	1850	#define FTM_STATUS_CH6F_SHIFT 6
tushki7	0:60d829a0353a	1851	#define FTM_STATUS_CH7F_MASK 0x80u
tushki7	0:60d829a0353a	1852	#define FTM_STATUS_CH7F_SHIFT 7
tushki7	0:60d829a0353a	1853	/* MODE Bit Fields */
tushki7	0:60d829a0353a	1854	#define FTM_MODE_FTMEN_MASK 0x1u
tushki7	0:60d829a0353a	1855	#define FTM_MODE_FTMEN_SHIFT 0
tushki7	0:60d829a0353a	1856	#define FTM_MODE_INIT_MASK 0x2u
tushki7	0:60d829a0353a	1857	#define FTM_MODE_INIT_SHIFT 1
tushki7	0:60d829a0353a	1858	#define FTM_MODE_WPDIS_MASK 0x4u
tushki7	0:60d829a0353a	1859	#define FTM_MODE_WPDIS_SHIFT 2
tushki7	0:60d829a0353a	1860	#define FTM_MODE_PWMSYNC_MASK 0x8u
tushki7	0:60d829a0353a	1861	#define FTM_MODE_PWMSYNC_SHIFT 3
tushki7	0:60d829a0353a	1862	#define FTM_MODE_CAPTEST_MASK 0x10u
tushki7	0:60d829a0353a	1863	#define FTM_MODE_CAPTEST_SHIFT 4
tushki7	0:60d829a0353a	1864	#define FTM_MODE_FAULTM_MASK 0x60u
tushki7	0:60d829a0353a	1865	#define FTM_MODE_FAULTM_SHIFT 5
tushki7	0:60d829a0353a	1866	#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
tushki7	0:60d829a0353a	1867	#define FTM_MODE_FAULTIE_MASK 0x80u
tushki7	0:60d829a0353a	1868	#define FTM_MODE_FAULTIE_SHIFT 7
tushki7	0:60d829a0353a	1869	/* SYNC Bit Fields */
tushki7	0:60d829a0353a	1870	#define FTM_SYNC_CNTMIN_MASK 0x1u
tushki7	0:60d829a0353a	1871	#define FTM_SYNC_CNTMIN_SHIFT 0
tushki7	0:60d829a0353a	1872	#define FTM_SYNC_CNTMAX_MASK 0x2u
tushki7	0:60d829a0353a	1873	#define FTM_SYNC_CNTMAX_SHIFT 1
tushki7	0:60d829a0353a	1874	#define FTM_SYNC_REINIT_MASK 0x4u
tushki7	0:60d829a0353a	1875	#define FTM_SYNC_REINIT_SHIFT 2
tushki7	0:60d829a0353a	1876	#define FTM_SYNC_SYNCHOM_MASK 0x8u
tushki7	0:60d829a0353a	1877	#define FTM_SYNC_SYNCHOM_SHIFT 3
tushki7	0:60d829a0353a	1878	#define FTM_SYNC_TRIG0_MASK 0x10u
tushki7	0:60d829a0353a	1879	#define FTM_SYNC_TRIG0_SHIFT 4
tushki7	0:60d829a0353a	1880	#define FTM_SYNC_TRIG1_MASK 0x20u
tushki7	0:60d829a0353a	1881	#define FTM_SYNC_TRIG1_SHIFT 5
tushki7	0:60d829a0353a	1882	#define FTM_SYNC_TRIG2_MASK 0x40u
tushki7	0:60d829a0353a	1883	#define FTM_SYNC_TRIG2_SHIFT 6
tushki7	0:60d829a0353a	1884	#define FTM_SYNC_SWSYNC_MASK 0x80u
tushki7	0:60d829a0353a	1885	#define FTM_SYNC_SWSYNC_SHIFT 7
tushki7	0:60d829a0353a	1886	/* OUTINIT Bit Fields */
tushki7	0:60d829a0353a	1887	#define FTM_OUTINIT_CH0OI_MASK 0x1u
tushki7	0:60d829a0353a	1888	#define FTM_OUTINIT_CH0OI_SHIFT 0
tushki7	0:60d829a0353a	1889	#define FTM_OUTINIT_CH1OI_MASK 0x2u
tushki7	0:60d829a0353a	1890	#define FTM_OUTINIT_CH1OI_SHIFT 1
tushki7	0:60d829a0353a	1891	#define FTM_OUTINIT_CH2OI_MASK 0x4u
tushki7	0:60d829a0353a	1892	#define FTM_OUTINIT_CH2OI_SHIFT 2
tushki7	0:60d829a0353a	1893	#define FTM_OUTINIT_CH3OI_MASK 0x8u
tushki7	0:60d829a0353a	1894	#define FTM_OUTINIT_CH3OI_SHIFT 3
tushki7	0:60d829a0353a	1895	#define FTM_OUTINIT_CH4OI_MASK 0x10u
tushki7	0:60d829a0353a	1896	#define FTM_OUTINIT_CH4OI_SHIFT 4
tushki7	0:60d829a0353a	1897	#define FTM_OUTINIT_CH5OI_MASK 0x20u
tushki7	0:60d829a0353a	1898	#define FTM_OUTINIT_CH5OI_SHIFT 5
tushki7	0:60d829a0353a	1899	#define FTM_OUTINIT_CH6OI_MASK 0x40u
tushki7	0:60d829a0353a	1900	#define FTM_OUTINIT_CH6OI_SHIFT 6
tushki7	0:60d829a0353a	1901	#define FTM_OUTINIT_CH7OI_MASK 0x80u
tushki7	0:60d829a0353a	1902	#define FTM_OUTINIT_CH7OI_SHIFT 7
tushki7	0:60d829a0353a	1903	/* OUTMASK Bit Fields */
tushki7	0:60d829a0353a	1904	#define FTM_OUTMASK_CH0OM_MASK 0x1u
tushki7	0:60d829a0353a	1905	#define FTM_OUTMASK_CH0OM_SHIFT 0
tushki7	0:60d829a0353a	1906	#define FTM_OUTMASK_CH1OM_MASK 0x2u
tushki7	0:60d829a0353a	1907	#define FTM_OUTMASK_CH1OM_SHIFT 1
tushki7	0:60d829a0353a	1908	#define FTM_OUTMASK_CH2OM_MASK 0x4u
tushki7	0:60d829a0353a	1909	#define FTM_OUTMASK_CH2OM_SHIFT 2
tushki7	0:60d829a0353a	1910	#define FTM_OUTMASK_CH3OM_MASK 0x8u
tushki7	0:60d829a0353a	1911	#define FTM_OUTMASK_CH3OM_SHIFT 3
tushki7	0:60d829a0353a	1912	#define FTM_OUTMASK_CH4OM_MASK 0x10u
tushki7	0:60d829a0353a	1913	#define FTM_OUTMASK_CH4OM_SHIFT 4
tushki7	0:60d829a0353a	1914	#define FTM_OUTMASK_CH5OM_MASK 0x20u
tushki7	0:60d829a0353a	1915	#define FTM_OUTMASK_CH5OM_SHIFT 5
tushki7	0:60d829a0353a	1916	#define FTM_OUTMASK_CH6OM_MASK 0x40u
tushki7	0:60d829a0353a	1917	#define FTM_OUTMASK_CH6OM_SHIFT 6
tushki7	0:60d829a0353a	1918	#define FTM_OUTMASK_CH7OM_MASK 0x80u
tushki7	0:60d829a0353a	1919	#define FTM_OUTMASK_CH7OM_SHIFT 7
tushki7	0:60d829a0353a	1920	/* COMBINE Bit Fields */
tushki7	0:60d829a0353a	1921	#define FTM_COMBINE_COMBINE0_MASK 0x1u
tushki7	0:60d829a0353a	1922	#define FTM_COMBINE_COMBINE0_SHIFT 0
tushki7	0:60d829a0353a	1923	#define FTM_COMBINE_COMP0_MASK 0x2u
tushki7	0:60d829a0353a	1924	#define FTM_COMBINE_COMP0_SHIFT 1
tushki7	0:60d829a0353a	1925	#define FTM_COMBINE_DECAPEN0_MASK 0x4u
tushki7	0:60d829a0353a	1926	#define FTM_COMBINE_DECAPEN0_SHIFT 2
tushki7	0:60d829a0353a	1927	#define FTM_COMBINE_DECAP0_MASK 0x8u
tushki7	0:60d829a0353a	1928	#define FTM_COMBINE_DECAP0_SHIFT 3
tushki7	0:60d829a0353a	1929	#define FTM_COMBINE_DTEN0_MASK 0x10u
tushki7	0:60d829a0353a	1930	#define FTM_COMBINE_DTEN0_SHIFT 4
tushki7	0:60d829a0353a	1931	#define FTM_COMBINE_SYNCEN0_MASK 0x20u
tushki7	0:60d829a0353a	1932	#define FTM_COMBINE_SYNCEN0_SHIFT 5
tushki7	0:60d829a0353a	1933	#define FTM_COMBINE_FAULTEN0_MASK 0x40u
tushki7	0:60d829a0353a	1934	#define FTM_COMBINE_FAULTEN0_SHIFT 6
tushki7	0:60d829a0353a	1935	#define FTM_COMBINE_COMBINE1_MASK 0x100u
tushki7	0:60d829a0353a	1936	#define FTM_COMBINE_COMBINE1_SHIFT 8
tushki7	0:60d829a0353a	1937	#define FTM_COMBINE_COMP1_MASK 0x200u
tushki7	0:60d829a0353a	1938	#define FTM_COMBINE_COMP1_SHIFT 9
tushki7	0:60d829a0353a	1939	#define FTM_COMBINE_DECAPEN1_MASK 0x400u
tushki7	0:60d829a0353a	1940	#define FTM_COMBINE_DECAPEN1_SHIFT 10
tushki7	0:60d829a0353a	1941	#define FTM_COMBINE_DECAP1_MASK 0x800u
tushki7	0:60d829a0353a	1942	#define FTM_COMBINE_DECAP1_SHIFT 11
tushki7	0:60d829a0353a	1943	#define FTM_COMBINE_DTEN1_MASK 0x1000u
tushki7	0:60d829a0353a	1944	#define FTM_COMBINE_DTEN1_SHIFT 12
tushki7	0:60d829a0353a	1945	#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
tushki7	0:60d829a0353a	1946	#define FTM_COMBINE_SYNCEN1_SHIFT 13
tushki7	0:60d829a0353a	1947	#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
tushki7	0:60d829a0353a	1948	#define FTM_COMBINE_FAULTEN1_SHIFT 14
tushki7	0:60d829a0353a	1949	#define FTM_COMBINE_COMBINE2_MASK 0x10000u
tushki7	0:60d829a0353a	1950	#define FTM_COMBINE_COMBINE2_SHIFT 16
tushki7	0:60d829a0353a	1951	#define FTM_COMBINE_COMP2_MASK 0x20000u
tushki7	0:60d829a0353a	1952	#define FTM_COMBINE_COMP2_SHIFT 17
tushki7	0:60d829a0353a	1953	#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
tushki7	0:60d829a0353a	1954	#define FTM_COMBINE_DECAPEN2_SHIFT 18
tushki7	0:60d829a0353a	1955	#define FTM_COMBINE_DECAP2_MASK 0x80000u
tushki7	0:60d829a0353a	1956	#define FTM_COMBINE_DECAP2_SHIFT 19
tushki7	0:60d829a0353a	1957	#define FTM_COMBINE_DTEN2_MASK 0x100000u
tushki7	0:60d829a0353a	1958	#define FTM_COMBINE_DTEN2_SHIFT 20
tushki7	0:60d829a0353a	1959	#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
tushki7	0:60d829a0353a	1960	#define FTM_COMBINE_SYNCEN2_SHIFT 21
tushki7	0:60d829a0353a	1961	#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
tushki7	0:60d829a0353a	1962	#define FTM_COMBINE_FAULTEN2_SHIFT 22
tushki7	0:60d829a0353a	1963	#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
tushki7	0:60d829a0353a	1964	#define FTM_COMBINE_COMBINE3_SHIFT 24
tushki7	0:60d829a0353a	1965	#define FTM_COMBINE_COMP3_MASK 0x2000000u
tushki7	0:60d829a0353a	1966	#define FTM_COMBINE_COMP3_SHIFT 25
tushki7	0:60d829a0353a	1967	#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
tushki7	0:60d829a0353a	1968	#define FTM_COMBINE_DECAPEN3_SHIFT 26
tushki7	0:60d829a0353a	1969	#define FTM_COMBINE_DECAP3_MASK 0x8000000u
tushki7	0:60d829a0353a	1970	#define FTM_COMBINE_DECAP3_SHIFT 27
tushki7	0:60d829a0353a	1971	#define FTM_COMBINE_DTEN3_MASK 0x10000000u
tushki7	0:60d829a0353a	1972	#define FTM_COMBINE_DTEN3_SHIFT 28
tushki7	0:60d829a0353a	1973	#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
tushki7	0:60d829a0353a	1974	#define FTM_COMBINE_SYNCEN3_SHIFT 29
tushki7	0:60d829a0353a	1975	#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
tushki7	0:60d829a0353a	1976	#define FTM_COMBINE_FAULTEN3_SHIFT 30
tushki7	0:60d829a0353a	1977	/* DEADTIME Bit Fields */
tushki7	0:60d829a0353a	1978	#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
tushki7	0:60d829a0353a	1979	#define FTM_DEADTIME_DTVAL_SHIFT 0
tushki7	0:60d829a0353a	1980	#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
tushki7	0:60d829a0353a	1981	#define FTM_DEADTIME_DTPS_MASK 0xC0u
tushki7	0:60d829a0353a	1982	#define FTM_DEADTIME_DTPS_SHIFT 6
tushki7	0:60d829a0353a	1983	#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
tushki7	0:60d829a0353a	1984	/* EXTTRIG Bit Fields */
tushki7	0:60d829a0353a	1985	#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
tushki7	0:60d829a0353a	1986	#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
tushki7	0:60d829a0353a	1987	#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
tushki7	0:60d829a0353a	1988	#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
tushki7	0:60d829a0353a	1989	#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
tushki7	0:60d829a0353a	1990	#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
tushki7	0:60d829a0353a	1991	#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
tushki7	0:60d829a0353a	1992	#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
tushki7	0:60d829a0353a	1993	#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
tushki7	0:60d829a0353a	1994	#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
tushki7	0:60d829a0353a	1995	#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
tushki7	0:60d829a0353a	1996	#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
tushki7	0:60d829a0353a	1997	#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
tushki7	0:60d829a0353a	1998	#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
tushki7	0:60d829a0353a	1999	#define FTM_EXTTRIG_TRIGF_MASK 0x80u
tushki7	0:60d829a0353a	2000	#define FTM_EXTTRIG_TRIGF_SHIFT 7
tushki7	0:60d829a0353a	2001	/* POL Bit Fields */
tushki7	0:60d829a0353a	2002	#define FTM_POL_POL0_MASK 0x1u
tushki7	0:60d829a0353a	2003	#define FTM_POL_POL0_SHIFT 0
tushki7	0:60d829a0353a	2004	#define FTM_POL_POL1_MASK 0x2u
tushki7	0:60d829a0353a	2005	#define FTM_POL_POL1_SHIFT 1
tushki7	0:60d829a0353a	2006	#define FTM_POL_POL2_MASK 0x4u
tushki7	0:60d829a0353a	2007	#define FTM_POL_POL2_SHIFT 2
tushki7	0:60d829a0353a	2008	#define FTM_POL_POL3_MASK 0x8u
tushki7	0:60d829a0353a	2009	#define FTM_POL_POL3_SHIFT 3
tushki7	0:60d829a0353a	2010	#define FTM_POL_POL4_MASK 0x10u
tushki7	0:60d829a0353a	2011	#define FTM_POL_POL4_SHIFT 4
tushki7	0:60d829a0353a	2012	#define FTM_POL_POL5_MASK 0x20u
tushki7	0:60d829a0353a	2013	#define FTM_POL_POL5_SHIFT 5
tushki7	0:60d829a0353a	2014	#define FTM_POL_POL6_MASK 0x40u
tushki7	0:60d829a0353a	2015	#define FTM_POL_POL6_SHIFT 6
tushki7	0:60d829a0353a	2016	#define FTM_POL_POL7_MASK 0x80u
tushki7	0:60d829a0353a	2017	#define FTM_POL_POL7_SHIFT 7
tushki7	0:60d829a0353a	2018	/* FMS Bit Fields */
tushki7	0:60d829a0353a	2019	#define FTM_FMS_FAULTF0_MASK 0x1u
tushki7	0:60d829a0353a	2020	#define FTM_FMS_FAULTF0_SHIFT 0
tushki7	0:60d829a0353a	2021	#define FTM_FMS_FAULTF1_MASK 0x2u
tushki7	0:60d829a0353a	2022	#define FTM_FMS_FAULTF1_SHIFT 1
tushki7	0:60d829a0353a	2023	#define FTM_FMS_FAULTF2_MASK 0x4u
tushki7	0:60d829a0353a	2024	#define FTM_FMS_FAULTF2_SHIFT 2
tushki7	0:60d829a0353a	2025	#define FTM_FMS_FAULTF3_MASK 0x8u
tushki7	0:60d829a0353a	2026	#define FTM_FMS_FAULTF3_SHIFT 3
tushki7	0:60d829a0353a	2027	#define FTM_FMS_FAULTIN_MASK 0x20u
tushki7	0:60d829a0353a	2028	#define FTM_FMS_FAULTIN_SHIFT 5
tushki7	0:60d829a0353a	2029	#define FTM_FMS_WPEN_MASK 0x40u
tushki7	0:60d829a0353a	2030	#define FTM_FMS_WPEN_SHIFT 6
tushki7	0:60d829a0353a	2031	#define FTM_FMS_FAULTF_MASK 0x80u
tushki7	0:60d829a0353a	2032	#define FTM_FMS_FAULTF_SHIFT 7
tushki7	0:60d829a0353a	2033	/* FILTER Bit Fields */
tushki7	0:60d829a0353a	2034	#define FTM_FILTER_CH0FVAL_MASK 0xFu
tushki7	0:60d829a0353a	2035	#define FTM_FILTER_CH0FVAL_SHIFT 0
tushki7	0:60d829a0353a	2036	#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
tushki7	0:60d829a0353a	2037	#define FTM_FILTER_CH1FVAL_MASK 0xF0u
tushki7	0:60d829a0353a	2038	#define FTM_FILTER_CH1FVAL_SHIFT 4
tushki7	0:60d829a0353a	2039	#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
tushki7	0:60d829a0353a	2040	#define FTM_FILTER_CH2FVAL_MASK 0xF00u
tushki7	0:60d829a0353a	2041	#define FTM_FILTER_CH2FVAL_SHIFT 8
tushki7	0:60d829a0353a	2042	#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
tushki7	0:60d829a0353a	2043	#define FTM_FILTER_CH3FVAL_MASK 0xF000u
tushki7	0:60d829a0353a	2044	#define FTM_FILTER_CH3FVAL_SHIFT 12
tushki7	0:60d829a0353a	2045	#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
tushki7	0:60d829a0353a	2046	/* FLTCTRL Bit Fields */
tushki7	0:60d829a0353a	2047	#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
tushki7	0:60d829a0353a	2048	#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
tushki7	0:60d829a0353a	2049	#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
tushki7	0:60d829a0353a	2050	#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
tushki7	0:60d829a0353a	2051	#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
tushki7	0:60d829a0353a	2052	#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
tushki7	0:60d829a0353a	2053	#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
tushki7	0:60d829a0353a	2054	#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
tushki7	0:60d829a0353a	2055	#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
tushki7	0:60d829a0353a	2056	#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
tushki7	0:60d829a0353a	2057	#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
tushki7	0:60d829a0353a	2058	#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
tushki7	0:60d829a0353a	2059	#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
tushki7	0:60d829a0353a	2060	#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
tushki7	0:60d829a0353a	2061	#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
tushki7	0:60d829a0353a	2062	#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
tushki7	0:60d829a0353a	2063	#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
tushki7	0:60d829a0353a	2064	#define FTM_FLTCTRL_FFVAL_SHIFT 8
tushki7	0:60d829a0353a	2065	#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
tushki7	0:60d829a0353a	2066	/* QDCTRL Bit Fields */
tushki7	0:60d829a0353a	2067	#define FTM_QDCTRL_QUADEN_MASK 0x1u
tushki7	0:60d829a0353a	2068	#define FTM_QDCTRL_QUADEN_SHIFT 0
tushki7	0:60d829a0353a	2069	#define FTM_QDCTRL_TOFDIR_MASK 0x2u
tushki7	0:60d829a0353a	2070	#define FTM_QDCTRL_TOFDIR_SHIFT 1
tushki7	0:60d829a0353a	2071	#define FTM_QDCTRL_QUADIR_MASK 0x4u
tushki7	0:60d829a0353a	2072	#define FTM_QDCTRL_QUADIR_SHIFT 2
tushki7	0:60d829a0353a	2073	#define FTM_QDCTRL_QUADMODE_MASK 0x8u
tushki7	0:60d829a0353a	2074	#define FTM_QDCTRL_QUADMODE_SHIFT 3
tushki7	0:60d829a0353a	2075	#define FTM_QDCTRL_PHBPOL_MASK 0x10u
tushki7	0:60d829a0353a	2076	#define FTM_QDCTRL_PHBPOL_SHIFT 4
tushki7	0:60d829a0353a	2077	#define FTM_QDCTRL_PHAPOL_MASK 0x20u
tushki7	0:60d829a0353a	2078	#define FTM_QDCTRL_PHAPOL_SHIFT 5
tushki7	0:60d829a0353a	2079	#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
tushki7	0:60d829a0353a	2080	#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
tushki7	0:60d829a0353a	2081	#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
tushki7	0:60d829a0353a	2082	#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
tushki7	0:60d829a0353a	2083	/* CONF Bit Fields */
tushki7	0:60d829a0353a	2084	#define FTM_CONF_NUMTOF_MASK 0x1Fu
tushki7	0:60d829a0353a	2085	#define FTM_CONF_NUMTOF_SHIFT 0
tushki7	0:60d829a0353a	2086	#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
tushki7	0:60d829a0353a	2087	#define FTM_CONF_BDMMODE_MASK 0xC0u
tushki7	0:60d829a0353a	2088	#define FTM_CONF_BDMMODE_SHIFT 6
tushki7	0:60d829a0353a	2089	#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
tushki7	0:60d829a0353a	2090	#define FTM_CONF_GTBEEN_MASK 0x200u
tushki7	0:60d829a0353a	2091	#define FTM_CONF_GTBEEN_SHIFT 9
tushki7	0:60d829a0353a	2092	#define FTM_CONF_GTBEOUT_MASK 0x400u
tushki7	0:60d829a0353a	2093	#define FTM_CONF_GTBEOUT_SHIFT 10
tushki7	0:60d829a0353a	2094	/* FLTPOL Bit Fields */
tushki7	0:60d829a0353a	2095	#define FTM_FLTPOL_FLT0POL_MASK 0x1u
tushki7	0:60d829a0353a	2096	#define FTM_FLTPOL_FLT0POL_SHIFT 0
tushki7	0:60d829a0353a	2097	#define FTM_FLTPOL_FLT1POL_MASK 0x2u
tushki7	0:60d829a0353a	2098	#define FTM_FLTPOL_FLT1POL_SHIFT 1
tushki7	0:60d829a0353a	2099	#define FTM_FLTPOL_FLT2POL_MASK 0x4u
tushki7	0:60d829a0353a	2100	#define FTM_FLTPOL_FLT2POL_SHIFT 2
tushki7	0:60d829a0353a	2101	#define FTM_FLTPOL_FLT3POL_MASK 0x8u
tushki7	0:60d829a0353a	2102	#define FTM_FLTPOL_FLT3POL_SHIFT 3
tushki7	0:60d829a0353a	2103	/* SYNCONF Bit Fields */
tushki7	0:60d829a0353a	2104	#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
tushki7	0:60d829a0353a	2105	#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
tushki7	0:60d829a0353a	2106	#define FTM_SYNCONF_CNTINC_MASK 0x4u
tushki7	0:60d829a0353a	2107	#define FTM_SYNCONF_CNTINC_SHIFT 2
tushki7	0:60d829a0353a	2108	#define FTM_SYNCONF_INVC_MASK 0x10u
tushki7	0:60d829a0353a	2109	#define FTM_SYNCONF_INVC_SHIFT 4
tushki7	0:60d829a0353a	2110	#define FTM_SYNCONF_SWOC_MASK 0x20u
tushki7	0:60d829a0353a	2111	#define FTM_SYNCONF_SWOC_SHIFT 5
tushki7	0:60d829a0353a	2112	#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
tushki7	0:60d829a0353a	2113	#define FTM_SYNCONF_SYNCMODE_SHIFT 7
tushki7	0:60d829a0353a	2114	#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
tushki7	0:60d829a0353a	2115	#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
tushki7	0:60d829a0353a	2116	#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
tushki7	0:60d829a0353a	2117	#define FTM_SYNCONF_SWWRBUF_SHIFT 9
tushki7	0:60d829a0353a	2118	#define FTM_SYNCONF_SWOM_MASK 0x400u
tushki7	0:60d829a0353a	2119	#define FTM_SYNCONF_SWOM_SHIFT 10
tushki7	0:60d829a0353a	2120	#define FTM_SYNCONF_SWINVC_MASK 0x800u
tushki7	0:60d829a0353a	2121	#define FTM_SYNCONF_SWINVC_SHIFT 11
tushki7	0:60d829a0353a	2122	#define FTM_SYNCONF_SWSOC_MASK 0x1000u
tushki7	0:60d829a0353a	2123	#define FTM_SYNCONF_SWSOC_SHIFT 12
tushki7	0:60d829a0353a	2124	#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
tushki7	0:60d829a0353a	2125	#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
tushki7	0:60d829a0353a	2126	#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
tushki7	0:60d829a0353a	2127	#define FTM_SYNCONF_HWWRBUF_SHIFT 17
tushki7	0:60d829a0353a	2128	#define FTM_SYNCONF_HWOM_MASK 0x40000u
tushki7	0:60d829a0353a	2129	#define FTM_SYNCONF_HWOM_SHIFT 18
tushki7	0:60d829a0353a	2130	#define FTM_SYNCONF_HWINVC_MASK 0x80000u
tushki7	0:60d829a0353a	2131	#define FTM_SYNCONF_HWINVC_SHIFT 19
tushki7	0:60d829a0353a	2132	#define FTM_SYNCONF_HWSOC_MASK 0x100000u
tushki7	0:60d829a0353a	2133	#define FTM_SYNCONF_HWSOC_SHIFT 20
tushki7	0:60d829a0353a	2134	/* INVCTRL Bit Fields */
tushki7	0:60d829a0353a	2135	#define FTM_INVCTRL_INV0EN_MASK 0x1u
tushki7	0:60d829a0353a	2136	#define FTM_INVCTRL_INV0EN_SHIFT 0
tushki7	0:60d829a0353a	2137	#define FTM_INVCTRL_INV1EN_MASK 0x2u
tushki7	0:60d829a0353a	2138	#define FTM_INVCTRL_INV1EN_SHIFT 1
tushki7	0:60d829a0353a	2139	#define FTM_INVCTRL_INV2EN_MASK 0x4u
tushki7	0:60d829a0353a	2140	#define FTM_INVCTRL_INV2EN_SHIFT 2
tushki7	0:60d829a0353a	2141	#define FTM_INVCTRL_INV3EN_MASK 0x8u
tushki7	0:60d829a0353a	2142	#define FTM_INVCTRL_INV3EN_SHIFT 3
tushki7	0:60d829a0353a	2143	/* SWOCTRL Bit Fields */
tushki7	0:60d829a0353a	2144	#define FTM_SWOCTRL_CH0OC_MASK 0x1u
tushki7	0:60d829a0353a	2145	#define FTM_SWOCTRL_CH0OC_SHIFT 0
tushki7	0:60d829a0353a	2146	#define FTM_SWOCTRL_CH1OC_MASK 0x2u
tushki7	0:60d829a0353a	2147	#define FTM_SWOCTRL_CH1OC_SHIFT 1
tushki7	0:60d829a0353a	2148	#define FTM_SWOCTRL_CH2OC_MASK 0x4u
tushki7	0:60d829a0353a	2149	#define FTM_SWOCTRL_CH2OC_SHIFT 2
tushki7	0:60d829a0353a	2150	#define FTM_SWOCTRL_CH3OC_MASK 0x8u
tushki7	0:60d829a0353a	2151	#define FTM_SWOCTRL_CH3OC_SHIFT 3
tushki7	0:60d829a0353a	2152	#define FTM_SWOCTRL_CH4OC_MASK 0x10u
tushki7	0:60d829a0353a	2153	#define FTM_SWOCTRL_CH4OC_SHIFT 4
tushki7	0:60d829a0353a	2154	#define FTM_SWOCTRL_CH5OC_MASK 0x20u
tushki7	0:60d829a0353a	2155	#define FTM_SWOCTRL_CH5OC_SHIFT 5
tushki7	0:60d829a0353a	2156	#define FTM_SWOCTRL_CH6OC_MASK 0x40u
tushki7	0:60d829a0353a	2157	#define FTM_SWOCTRL_CH6OC_SHIFT 6
tushki7	0:60d829a0353a	2158	#define FTM_SWOCTRL_CH7OC_MASK 0x80u
tushki7	0:60d829a0353a	2159	#define FTM_SWOCTRL_CH7OC_SHIFT 7
tushki7	0:60d829a0353a	2160	#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
tushki7	0:60d829a0353a	2161	#define FTM_SWOCTRL_CH0OCV_SHIFT 8
tushki7	0:60d829a0353a	2162	#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
tushki7	0:60d829a0353a	2163	#define FTM_SWOCTRL_CH1OCV_SHIFT 9
tushki7	0:60d829a0353a	2164	#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
tushki7	0:60d829a0353a	2165	#define FTM_SWOCTRL_CH2OCV_SHIFT 10
tushki7	0:60d829a0353a	2166	#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
tushki7	0:60d829a0353a	2167	#define FTM_SWOCTRL_CH3OCV_SHIFT 11
tushki7	0:60d829a0353a	2168	#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
tushki7	0:60d829a0353a	2169	#define FTM_SWOCTRL_CH4OCV_SHIFT 12
tushki7	0:60d829a0353a	2170	#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
tushki7	0:60d829a0353a	2171	#define FTM_SWOCTRL_CH5OCV_SHIFT 13
tushki7	0:60d829a0353a	2172	#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
tushki7	0:60d829a0353a	2173	#define FTM_SWOCTRL_CH6OCV_SHIFT 14
tushki7	0:60d829a0353a	2174	#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
tushki7	0:60d829a0353a	2175	#define FTM_SWOCTRL_CH7OCV_SHIFT 15
tushki7	0:60d829a0353a	2176	/* PWMLOAD Bit Fields */
tushki7	0:60d829a0353a	2177	#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
tushki7	0:60d829a0353a	2178	#define FTM_PWMLOAD_CH0SEL_SHIFT 0
tushki7	0:60d829a0353a	2179	#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
tushki7	0:60d829a0353a	2180	#define FTM_PWMLOAD_CH1SEL_SHIFT 1
tushki7	0:60d829a0353a	2181	#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
tushki7	0:60d829a0353a	2182	#define FTM_PWMLOAD_CH2SEL_SHIFT 2
tushki7	0:60d829a0353a	2183	#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
tushki7	0:60d829a0353a	2184	#define FTM_PWMLOAD_CH3SEL_SHIFT 3
tushki7	0:60d829a0353a	2185	#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
tushki7	0:60d829a0353a	2186	#define FTM_PWMLOAD_CH4SEL_SHIFT 4
tushki7	0:60d829a0353a	2187	#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
tushki7	0:60d829a0353a	2188	#define FTM_PWMLOAD_CH5SEL_SHIFT 5
tushki7	0:60d829a0353a	2189	#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
tushki7	0:60d829a0353a	2190	#define FTM_PWMLOAD_CH6SEL_SHIFT 6
tushki7	0:60d829a0353a	2191	#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
tushki7	0:60d829a0353a	2192	#define FTM_PWMLOAD_CH7SEL_SHIFT 7
tushki7	0:60d829a0353a	2193	#define FTM_PWMLOAD_LDOK_MASK 0x200u
tushki7	0:60d829a0353a	2194	#define FTM_PWMLOAD_LDOK_SHIFT 9
tushki7	0:60d829a0353a	2195
tushki7	0:60d829a0353a	2196	/**
tushki7	0:60d829a0353a	2197	* @}
tushki7	0:60d829a0353a	2198	/ / end of group FTM_Register_Masks */
tushki7	0:60d829a0353a	2199
tushki7	0:60d829a0353a	2200
tushki7	0:60d829a0353a	2201	/* FTM - Peripheral instance base addresses */
tushki7	0:60d829a0353a	2202	/** Peripheral FTM0 base address */
tushki7	0:60d829a0353a	2203	#define FTM0_BASE (0x40038000u)
tushki7	0:60d829a0353a	2204	/** Peripheral FTM0 base pointer */
tushki7	0:60d829a0353a	2205	#define FTM0 ((FTM_Type *)FTM0_BASE)
tushki7	0:60d829a0353a	2206	/** Peripheral FTM1 base address */
tushki7	0:60d829a0353a	2207	#define FTM1_BASE (0x40039000u)
tushki7	0:60d829a0353a	2208	/** Peripheral FTM1 base pointer */
tushki7	0:60d829a0353a	2209	#define FTM1 ((FTM_Type *)FTM1_BASE)
tushki7	0:60d829a0353a	2210
tushki7	0:60d829a0353a	2211	/**
tushki7	0:60d829a0353a	2212	* @}
tushki7	0:60d829a0353a	2213	/ / end of group FTM_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	2214
tushki7	0:60d829a0353a	2215
tushki7	0:60d829a0353a	2216	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	2217	-- GPIO Peripheral Access Layer
tushki7	0:60d829a0353a	2218	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	2219
tushki7	0:60d829a0353a	2220	/**
tushki7	0:60d829a0353a	2221	* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
tushki7	0:60d829a0353a	2222	* @{
tushki7	0:60d829a0353a	2223	*/
tushki7	0:60d829a0353a	2224
tushki7	0:60d829a0353a	2225	/** GPIO - Register Layout Typedef */
tushki7	0:60d829a0353a	2226	typedef struct {
tushki7	0:60d829a0353a	2227	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
tushki7	0:60d829a0353a	2228	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
tushki7	0:60d829a0353a	2229	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
tushki7	0:60d829a0353a	2230	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
tushki7	0:60d829a0353a	2231	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
tushki7	0:60d829a0353a	2232	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
tushki7	0:60d829a0353a	2233	} GPIO_Type;
tushki7	0:60d829a0353a	2234
tushki7	0:60d829a0353a	2235	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	2236	-- GPIO Register Masks
tushki7	0:60d829a0353a	2237	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	2238
tushki7	0:60d829a0353a	2239	/**
tushki7	0:60d829a0353a	2240	* @addtogroup GPIO_Register_Masks GPIO Register Masks
tushki7	0:60d829a0353a	2241	* @{
tushki7	0:60d829a0353a	2242	*/
tushki7	0:60d829a0353a	2243
tushki7	0:60d829a0353a	2244	/* PDOR Bit Fields */
tushki7	0:60d829a0353a	2245	#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	2246	#define GPIO_PDOR_PDO_SHIFT 0
tushki7	0:60d829a0353a	2247	#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
tushki7	0:60d829a0353a	2248	/* PSOR Bit Fields */
tushki7	0:60d829a0353a	2249	#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	2250	#define GPIO_PSOR_PTSO_SHIFT 0
tushki7	0:60d829a0353a	2251	#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
tushki7	0:60d829a0353a	2252	/* PCOR Bit Fields */
tushki7	0:60d829a0353a	2253	#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	2254	#define GPIO_PCOR_PTCO_SHIFT 0
tushki7	0:60d829a0353a	2255	#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
tushki7	0:60d829a0353a	2256	/* PTOR Bit Fields */
tushki7	0:60d829a0353a	2257	#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	2258	#define GPIO_PTOR_PTTO_SHIFT 0
tushki7	0:60d829a0353a	2259	#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
tushki7	0:60d829a0353a	2260	/* PDIR Bit Fields */
tushki7	0:60d829a0353a	2261	#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	2262	#define GPIO_PDIR_PDI_SHIFT 0
tushki7	0:60d829a0353a	2263	#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
tushki7	0:60d829a0353a	2264	/* PDDR Bit Fields */
tushki7	0:60d829a0353a	2265	#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	2266	#define GPIO_PDDR_PDD_SHIFT 0
tushki7	0:60d829a0353a	2267	#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
tushki7	0:60d829a0353a	2268
tushki7	0:60d829a0353a	2269	/**
tushki7	0:60d829a0353a	2270	* @}
tushki7	0:60d829a0353a	2271	/ / end of group GPIO_Register_Masks */
tushki7	0:60d829a0353a	2272
tushki7	0:60d829a0353a	2273
tushki7	0:60d829a0353a	2274	/* GPIO - Peripheral instance base addresses */
tushki7	0:60d829a0353a	2275	/** Peripheral PTA base address */
tushki7	0:60d829a0353a	2276	#define PTA_BASE (0x400FF000u)
tushki7	0:60d829a0353a	2277	/** Peripheral PTA base pointer */
tushki7	0:60d829a0353a	2278	#define PTA ((GPIO_Type *)PTA_BASE)
tushki7	0:60d829a0353a	2279	/** Peripheral PTB base address */
tushki7	0:60d829a0353a	2280	#define PTB_BASE (0x400FF040u)
tushki7	0:60d829a0353a	2281	/** Peripheral PTB base pointer */
tushki7	0:60d829a0353a	2282	#define PTB ((GPIO_Type *)PTB_BASE)
tushki7	0:60d829a0353a	2283	/** Peripheral PTC base address */
tushki7	0:60d829a0353a	2284	#define PTC_BASE (0x400FF080u)
tushki7	0:60d829a0353a	2285	/** Peripheral PTC base pointer */
tushki7	0:60d829a0353a	2286	#define PTC ((GPIO_Type *)PTC_BASE)
tushki7	0:60d829a0353a	2287	/** Peripheral PTD base address */
tushki7	0:60d829a0353a	2288	#define PTD_BASE (0x400FF0C0u)
tushki7	0:60d829a0353a	2289	/** Peripheral PTD base pointer */
tushki7	0:60d829a0353a	2290	#define PTD ((GPIO_Type *)PTD_BASE)
tushki7	0:60d829a0353a	2291	/** Peripheral PTE base address */
tushki7	0:60d829a0353a	2292	#define PTE_BASE (0x400FF100u)
tushki7	0:60d829a0353a	2293	/** Peripheral PTE base pointer */
tushki7	0:60d829a0353a	2294	#define PTE ((GPIO_Type *)PTE_BASE)
tushki7	0:60d829a0353a	2295
tushki7	0:60d829a0353a	2296	/**
tushki7	0:60d829a0353a	2297	* @}
tushki7	0:60d829a0353a	2298	/ / end of group GPIO_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	2299
tushki7	0:60d829a0353a	2300
tushki7	0:60d829a0353a	2301	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	2302	-- I2C Peripheral Access Layer
tushki7	0:60d829a0353a	2303	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	2304
tushki7	0:60d829a0353a	2305	/**
tushki7	0:60d829a0353a	2306	* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
tushki7	0:60d829a0353a	2307	* @{
tushki7	0:60d829a0353a	2308	*/
tushki7	0:60d829a0353a	2309
tushki7	0:60d829a0353a	2310	/** I2C - Register Layout Typedef */
tushki7	0:60d829a0353a	2311	typedef struct {
tushki7	0:60d829a0353a	2312	__IO uint8_t A1; /*< I2C Address Register 1, offset: 0x0 /
tushki7	0:60d829a0353a	2313	__IO uint8_t F; /*< I2C Frequency Divider register, offset: 0x1 /
tushki7	0:60d829a0353a	2314	__IO uint8_t C1; /*< I2C Control Register 1, offset: 0x2 /
tushki7	0:60d829a0353a	2315	__IO uint8_t S; /*< I2C Status Register, offset: 0x3 /
tushki7	0:60d829a0353a	2316	__IO uint8_t D; /*< I2C Data I/O register, offset: 0x4 /
tushki7	0:60d829a0353a	2317	__IO uint8_t C2; /*< I2C Control Register 2, offset: 0x5 /
tushki7	0:60d829a0353a	2318	__IO uint8_t FLT; /*< I2C Programmable Input Glitch Filter register, offset: 0x6 /
tushki7	0:60d829a0353a	2319	__IO uint8_t RA; /*< I2C Range Address register, offset: 0x7 /
tushki7	0:60d829a0353a	2320	__IO uint8_t SMB; /*< I2C SMBus Control and Status register, offset: 0x8 /
tushki7	0:60d829a0353a	2321	__IO uint8_t A2; /*< I2C Address Register 2, offset: 0x9 /
tushki7	0:60d829a0353a	2322	__IO uint8_t SLTH; /*< I2C SCL Low Timeout Register High, offset: 0xA /
tushki7	0:60d829a0353a	2323	__IO uint8_t SLTL; /*< I2C SCL Low Timeout Register Low, offset: 0xB /
tushki7	0:60d829a0353a	2324	} I2C_Type;
tushki7	0:60d829a0353a	2325
tushki7	0:60d829a0353a	2326	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	2327	-- I2C Register Masks
tushki7	0:60d829a0353a	2328	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	2329
tushki7	0:60d829a0353a	2330	/**
tushki7	0:60d829a0353a	2331	* @addtogroup I2C_Register_Masks I2C Register Masks
tushki7	0:60d829a0353a	2332	* @{
tushki7	0:60d829a0353a	2333	*/
tushki7	0:60d829a0353a	2334
tushki7	0:60d829a0353a	2335	/* A1 Bit Fields */
tushki7	0:60d829a0353a	2336	#define I2C_A1_AD_MASK 0xFEu
tushki7	0:60d829a0353a	2337	#define I2C_A1_AD_SHIFT 1
tushki7	0:60d829a0353a	2338	#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
tushki7	0:60d829a0353a	2339	/* F Bit Fields */
tushki7	0:60d829a0353a	2340	#define I2C_F_ICR_MASK 0x3Fu
tushki7	0:60d829a0353a	2341	#define I2C_F_ICR_SHIFT 0
tushki7	0:60d829a0353a	2342	#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
tushki7	0:60d829a0353a	2343	#define I2C_F_MULT_MASK 0xC0u
tushki7	0:60d829a0353a	2344	#define I2C_F_MULT_SHIFT 6
tushki7	0:60d829a0353a	2345	#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
tushki7	0:60d829a0353a	2346	/* C1 Bit Fields */
tushki7	0:60d829a0353a	2347	#define I2C_C1_DMAEN_MASK 0x1u
tushki7	0:60d829a0353a	2348	#define I2C_C1_DMAEN_SHIFT 0
tushki7	0:60d829a0353a	2349	#define I2C_C1_WUEN_MASK 0x2u
tushki7	0:60d829a0353a	2350	#define I2C_C1_WUEN_SHIFT 1
tushki7	0:60d829a0353a	2351	#define I2C_C1_RSTA_MASK 0x4u
tushki7	0:60d829a0353a	2352	#define I2C_C1_RSTA_SHIFT 2
tushki7	0:60d829a0353a	2353	#define I2C_C1_TXAK_MASK 0x8u
tushki7	0:60d829a0353a	2354	#define I2C_C1_TXAK_SHIFT 3
tushki7	0:60d829a0353a	2355	#define I2C_C1_TX_MASK 0x10u
tushki7	0:60d829a0353a	2356	#define I2C_C1_TX_SHIFT 4
tushki7	0:60d829a0353a	2357	#define I2C_C1_MST_MASK 0x20u
tushki7	0:60d829a0353a	2358	#define I2C_C1_MST_SHIFT 5
tushki7	0:60d829a0353a	2359	#define I2C_C1_IICIE_MASK 0x40u
tushki7	0:60d829a0353a	2360	#define I2C_C1_IICIE_SHIFT 6
tushki7	0:60d829a0353a	2361	#define I2C_C1_IICEN_MASK 0x80u
tushki7	0:60d829a0353a	2362	#define I2C_C1_IICEN_SHIFT 7
tushki7	0:60d829a0353a	2363	/* S Bit Fields */
tushki7	0:60d829a0353a	2364	#define I2C_S_RXAK_MASK 0x1u
tushki7	0:60d829a0353a	2365	#define I2C_S_RXAK_SHIFT 0
tushki7	0:60d829a0353a	2366	#define I2C_S_IICIF_MASK 0x2u
tushki7	0:60d829a0353a	2367	#define I2C_S_IICIF_SHIFT 1
tushki7	0:60d829a0353a	2368	#define I2C_S_SRW_MASK 0x4u
tushki7	0:60d829a0353a	2369	#define I2C_S_SRW_SHIFT 2
tushki7	0:60d829a0353a	2370	#define I2C_S_RAM_MASK 0x8u
tushki7	0:60d829a0353a	2371	#define I2C_S_RAM_SHIFT 3
tushki7	0:60d829a0353a	2372	#define I2C_S_ARBL_MASK 0x10u
tushki7	0:60d829a0353a	2373	#define I2C_S_ARBL_SHIFT 4
tushki7	0:60d829a0353a	2374	#define I2C_S_BUSY_MASK 0x20u
tushki7	0:60d829a0353a	2375	#define I2C_S_BUSY_SHIFT 5
tushki7	0:60d829a0353a	2376	#define I2C_S_IAAS_MASK 0x40u
tushki7	0:60d829a0353a	2377	#define I2C_S_IAAS_SHIFT 6
tushki7	0:60d829a0353a	2378	#define I2C_S_TCF_MASK 0x80u
tushki7	0:60d829a0353a	2379	#define I2C_S_TCF_SHIFT 7
tushki7	0:60d829a0353a	2380	/* D Bit Fields */
tushki7	0:60d829a0353a	2381	#define I2C_D_DATA_MASK 0xFFu
tushki7	0:60d829a0353a	2382	#define I2C_D_DATA_SHIFT 0
tushki7	0:60d829a0353a	2383	#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
tushki7	0:60d829a0353a	2384	/* C2 Bit Fields */
tushki7	0:60d829a0353a	2385	#define I2C_C2_AD_MASK 0x7u
tushki7	0:60d829a0353a	2386	#define I2C_C2_AD_SHIFT 0
tushki7	0:60d829a0353a	2387	#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
tushki7	0:60d829a0353a	2388	#define I2C_C2_RMEN_MASK 0x8u
tushki7	0:60d829a0353a	2389	#define I2C_C2_RMEN_SHIFT 3
tushki7	0:60d829a0353a	2390	#define I2C_C2_SBRC_MASK 0x10u
tushki7	0:60d829a0353a	2391	#define I2C_C2_SBRC_SHIFT 4
tushki7	0:60d829a0353a	2392	#define I2C_C2_HDRS_MASK 0x20u
tushki7	0:60d829a0353a	2393	#define I2C_C2_HDRS_SHIFT 5
tushki7	0:60d829a0353a	2394	#define I2C_C2_ADEXT_MASK 0x40u
tushki7	0:60d829a0353a	2395	#define I2C_C2_ADEXT_SHIFT 6
tushki7	0:60d829a0353a	2396	#define I2C_C2_GCAEN_MASK 0x80u
tushki7	0:60d829a0353a	2397	#define I2C_C2_GCAEN_SHIFT 7
tushki7	0:60d829a0353a	2398	/* FLT Bit Fields */
tushki7	0:60d829a0353a	2399	#define I2C_FLT_FLT_MASK 0x1Fu
tushki7	0:60d829a0353a	2400	#define I2C_FLT_FLT_SHIFT 0
tushki7	0:60d829a0353a	2401	#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
tushki7	0:60d829a0353a	2402	/* RA Bit Fields */
tushki7	0:60d829a0353a	2403	#define I2C_RA_RAD_MASK 0xFEu
tushki7	0:60d829a0353a	2404	#define I2C_RA_RAD_SHIFT 1
tushki7	0:60d829a0353a	2405	#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
tushki7	0:60d829a0353a	2406	/* SMB Bit Fields */
tushki7	0:60d829a0353a	2407	#define I2C_SMB_SHTF2IE_MASK 0x1u
tushki7	0:60d829a0353a	2408	#define I2C_SMB_SHTF2IE_SHIFT 0
tushki7	0:60d829a0353a	2409	#define I2C_SMB_SHTF2_MASK 0x2u
tushki7	0:60d829a0353a	2410	#define I2C_SMB_SHTF2_SHIFT 1
tushki7	0:60d829a0353a	2411	#define I2C_SMB_SHTF1_MASK 0x4u
tushki7	0:60d829a0353a	2412	#define I2C_SMB_SHTF1_SHIFT 2
tushki7	0:60d829a0353a	2413	#define I2C_SMB_SLTF_MASK 0x8u
tushki7	0:60d829a0353a	2414	#define I2C_SMB_SLTF_SHIFT 3
tushki7	0:60d829a0353a	2415	#define I2C_SMB_TCKSEL_MASK 0x10u
tushki7	0:60d829a0353a	2416	#define I2C_SMB_TCKSEL_SHIFT 4
tushki7	0:60d829a0353a	2417	#define I2C_SMB_SIICAEN_MASK 0x20u
tushki7	0:60d829a0353a	2418	#define I2C_SMB_SIICAEN_SHIFT 5
tushki7	0:60d829a0353a	2419	#define I2C_SMB_ALERTEN_MASK 0x40u
tushki7	0:60d829a0353a	2420	#define I2C_SMB_ALERTEN_SHIFT 6
tushki7	0:60d829a0353a	2421	#define I2C_SMB_FACK_MASK 0x80u
tushki7	0:60d829a0353a	2422	#define I2C_SMB_FACK_SHIFT 7
tushki7	0:60d829a0353a	2423	/* A2 Bit Fields */
tushki7	0:60d829a0353a	2424	#define I2C_A2_SAD_MASK 0xFEu
tushki7	0:60d829a0353a	2425	#define I2C_A2_SAD_SHIFT 1
tushki7	0:60d829a0353a	2426	#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
tushki7	0:60d829a0353a	2427	/* SLTH Bit Fields */
tushki7	0:60d829a0353a	2428	#define I2C_SLTH_SSLT_MASK 0xFFu
tushki7	0:60d829a0353a	2429	#define I2C_SLTH_SSLT_SHIFT 0
tushki7	0:60d829a0353a	2430	#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
tushki7	0:60d829a0353a	2431	/* SLTL Bit Fields */
tushki7	0:60d829a0353a	2432	#define I2C_SLTL_SSLT_MASK 0xFFu
tushki7	0:60d829a0353a	2433	#define I2C_SLTL_SSLT_SHIFT 0
tushki7	0:60d829a0353a	2434	#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
tushki7	0:60d829a0353a	2435
tushki7	0:60d829a0353a	2436	/**
tushki7	0:60d829a0353a	2437	* @}
tushki7	0:60d829a0353a	2438	/ / end of group I2C_Register_Masks */
tushki7	0:60d829a0353a	2439
tushki7	0:60d829a0353a	2440
tushki7	0:60d829a0353a	2441	/* I2C - Peripheral instance base addresses */
tushki7	0:60d829a0353a	2442	/** Peripheral I2C0 base address */
tushki7	0:60d829a0353a	2443	#define I2C0_BASE (0x40066000u)
tushki7	0:60d829a0353a	2444	#define I2C1_BASE (0x40067000u)
tushki7	0:60d829a0353a	2445	/** Peripheral I2C0 base pointer */
tushki7	0:60d829a0353a	2446	#define I2C0 ((I2C_Type *)I2C0_BASE)
tushki7	0:60d829a0353a	2447	#define I2C1 ((I2C_Type *)I2C1_BASE)
tushki7	0:60d829a0353a	2448	/**
tushki7	0:60d829a0353a	2449	* @}
tushki7	0:60d829a0353a	2450	/ / end of group I2C_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	2451
tushki7	0:60d829a0353a	2452
tushki7	0:60d829a0353a	2453	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	2454	-- I2S Peripheral Access Layer
tushki7	0:60d829a0353a	2455	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	2456
tushki7	0:60d829a0353a	2457	/**
tushki7	0:60d829a0353a	2458	* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
tushki7	0:60d829a0353a	2459	* @{
tushki7	0:60d829a0353a	2460	*/
tushki7	0:60d829a0353a	2461
tushki7	0:60d829a0353a	2462	/** I2S - Register Layout Typedef */
tushki7	0:60d829a0353a	2463	typedef struct {
tushki7	0:60d829a0353a	2464	__IO uint32_t TCSR; /*< SAI Transmit Control Register, offset: 0x0 /
tushki7	0:60d829a0353a	2465	__IO uint32_t TCR1; /*< SAI Transmit Configuration 1 Register, offset: 0x4 /
tushki7	0:60d829a0353a	2466	__IO uint32_t TCR2; /*< SAI Transmit Configuration 2 Register, offset: 0x8 /
tushki7	0:60d829a0353a	2467	__IO uint32_t TCR3; /*< SAI Transmit Configuration 3 Register, offset: 0xC /
tushki7	0:60d829a0353a	2468	__IO uint32_t TCR4; /*< SAI Transmit Configuration 4 Register, offset: 0x10 /
tushki7	0:60d829a0353a	2469	__IO uint32_t TCR5; /*< SAI Transmit Configuration 5 Register, offset: 0x14 /
tushki7	0:60d829a0353a	2470	uint8_t RESERVED_0[8];
tushki7	0:60d829a0353a	2471	__O uint32_t TDR[2]; /*< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 /
tushki7	0:60d829a0353a	2472	uint8_t RESERVED_1[24];
tushki7	0:60d829a0353a	2473	__I uint32_t TFR[2]; /*< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 /
tushki7	0:60d829a0353a	2474	uint8_t RESERVED_2[24];
tushki7	0:60d829a0353a	2475	__IO uint32_t TMR; /*< SAI Transmit Mask Register, offset: 0x60 /
tushki7	0:60d829a0353a	2476	uint8_t RESERVED_3[28];
tushki7	0:60d829a0353a	2477	__IO uint32_t RCSR; /*< SAI Receive Control Register, offset: 0x80 /
tushki7	0:60d829a0353a	2478	__IO uint32_t RCR1; /*< SAI Receive Configuration 1 Register, offset: 0x84 /
tushki7	0:60d829a0353a	2479	__IO uint32_t RCR2; /*< SAI Receive Configuration 2 Register, offset: 0x88 /
tushki7	0:60d829a0353a	2480	__IO uint32_t RCR3; /*< SAI Receive Configuration 3 Register, offset: 0x8C /
tushki7	0:60d829a0353a	2481	__IO uint32_t RCR4; /*< SAI Receive Configuration 4 Register, offset: 0x90 /
tushki7	0:60d829a0353a	2482	__IO uint32_t RCR5; /*< SAI Receive Configuration 5 Register, offset: 0x94 /
tushki7	0:60d829a0353a	2483	uint8_t RESERVED_4[8];
tushki7	0:60d829a0353a	2484	__I uint32_t RDR[2]; /*< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 /
tushki7	0:60d829a0353a	2485	uint8_t RESERVED_5[24];
tushki7	0:60d829a0353a	2486	__I uint32_t RFR[2]; /*< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 /
tushki7	0:60d829a0353a	2487	uint8_t RESERVED_6[24];
tushki7	0:60d829a0353a	2488	__IO uint32_t RMR; /*< SAI Receive Mask Register, offset: 0xE0 /
tushki7	0:60d829a0353a	2489	uint8_t RESERVED_7[28];
tushki7	0:60d829a0353a	2490	__IO uint32_t MCR; /*< SAI MCLK Control Register, offset: 0x100 /
tushki7	0:60d829a0353a	2491	__IO uint32_t MDR; /*< MCLK Divide Register, offset: 0x104 /
tushki7	0:60d829a0353a	2492	} I2S_Type;
tushki7	0:60d829a0353a	2493
tushki7	0:60d829a0353a	2494	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	2495	-- I2S Register Masks
tushki7	0:60d829a0353a	2496	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	2497
tushki7	0:60d829a0353a	2498	/**
tushki7	0:60d829a0353a	2499	* @addtogroup I2S_Register_Masks I2S Register Masks
tushki7	0:60d829a0353a	2500	* @{
tushki7	0:60d829a0353a	2501	*/
tushki7	0:60d829a0353a	2502
tushki7	0:60d829a0353a	2503	/* TCSR Bit Fields */
tushki7	0:60d829a0353a	2504	#define I2S_TCSR_FRDE_MASK 0x1u
tushki7	0:60d829a0353a	2505	#define I2S_TCSR_FRDE_SHIFT 0
tushki7	0:60d829a0353a	2506	#define I2S_TCSR_FWDE_MASK 0x2u
tushki7	0:60d829a0353a	2507	#define I2S_TCSR_FWDE_SHIFT 1
tushki7	0:60d829a0353a	2508	#define I2S_TCSR_FRIE_MASK 0x100u
tushki7	0:60d829a0353a	2509	#define I2S_TCSR_FRIE_SHIFT 8
tushki7	0:60d829a0353a	2510	#define I2S_TCSR_FWIE_MASK 0x200u
tushki7	0:60d829a0353a	2511	#define I2S_TCSR_FWIE_SHIFT 9
tushki7	0:60d829a0353a	2512	#define I2S_TCSR_FEIE_MASK 0x400u
tushki7	0:60d829a0353a	2513	#define I2S_TCSR_FEIE_SHIFT 10
tushki7	0:60d829a0353a	2514	#define I2S_TCSR_SEIE_MASK 0x800u
tushki7	0:60d829a0353a	2515	#define I2S_TCSR_SEIE_SHIFT 11
tushki7	0:60d829a0353a	2516	#define I2S_TCSR_WSIE_MASK 0x1000u
tushki7	0:60d829a0353a	2517	#define I2S_TCSR_WSIE_SHIFT 12
tushki7	0:60d829a0353a	2518	#define I2S_TCSR_FRF_MASK 0x10000u
tushki7	0:60d829a0353a	2519	#define I2S_TCSR_FRF_SHIFT 16
tushki7	0:60d829a0353a	2520	#define I2S_TCSR_FWF_MASK 0x20000u
tushki7	0:60d829a0353a	2521	#define I2S_TCSR_FWF_SHIFT 17
tushki7	0:60d829a0353a	2522	#define I2S_TCSR_FEF_MASK 0x40000u
tushki7	0:60d829a0353a	2523	#define I2S_TCSR_FEF_SHIFT 18
tushki7	0:60d829a0353a	2524	#define I2S_TCSR_SEF_MASK 0x80000u
tushki7	0:60d829a0353a	2525	#define I2S_TCSR_SEF_SHIFT 19
tushki7	0:60d829a0353a	2526	#define I2S_TCSR_WSF_MASK 0x100000u
tushki7	0:60d829a0353a	2527	#define I2S_TCSR_WSF_SHIFT 20
tushki7	0:60d829a0353a	2528	#define I2S_TCSR_SR_MASK 0x1000000u
tushki7	0:60d829a0353a	2529	#define I2S_TCSR_SR_SHIFT 24
tushki7	0:60d829a0353a	2530	#define I2S_TCSR_FR_MASK 0x2000000u
tushki7	0:60d829a0353a	2531	#define I2S_TCSR_FR_SHIFT 25
tushki7	0:60d829a0353a	2532	#define I2S_TCSR_BCE_MASK 0x10000000u
tushki7	0:60d829a0353a	2533	#define I2S_TCSR_BCE_SHIFT 28
tushki7	0:60d829a0353a	2534	#define I2S_TCSR_DBGE_MASK 0x20000000u
tushki7	0:60d829a0353a	2535	#define I2S_TCSR_DBGE_SHIFT 29
tushki7	0:60d829a0353a	2536	#define I2S_TCSR_STOPE_MASK 0x40000000u
tushki7	0:60d829a0353a	2537	#define I2S_TCSR_STOPE_SHIFT 30
tushki7	0:60d829a0353a	2538	#define I2S_TCSR_TE_MASK 0x80000000u
tushki7	0:60d829a0353a	2539	#define I2S_TCSR_TE_SHIFT 31
tushki7	0:60d829a0353a	2540	/* TCR1 Bit Fields */
tushki7	0:60d829a0353a	2541	#define I2S_TCR1_TFW_MASK 0x7u
tushki7	0:60d829a0353a	2542	#define I2S_TCR1_TFW_SHIFT 0
tushki7	0:60d829a0353a	2543	#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
tushki7	0:60d829a0353a	2544	/* TCR2 Bit Fields */
tushki7	0:60d829a0353a	2545	#define I2S_TCR2_DIV_MASK 0xFFu
tushki7	0:60d829a0353a	2546	#define I2S_TCR2_DIV_SHIFT 0
tushki7	0:60d829a0353a	2547	#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
tushki7	0:60d829a0353a	2548	#define I2S_TCR2_BCD_MASK 0x1000000u
tushki7	0:60d829a0353a	2549	#define I2S_TCR2_BCD_SHIFT 24
tushki7	0:60d829a0353a	2550	#define I2S_TCR2_BCP_MASK 0x2000000u
tushki7	0:60d829a0353a	2551	#define I2S_TCR2_BCP_SHIFT 25
tushki7	0:60d829a0353a	2552	#define I2S_TCR2_MSEL_MASK 0xC000000u
tushki7	0:60d829a0353a	2553	#define I2S_TCR2_MSEL_SHIFT 26
tushki7	0:60d829a0353a	2554	#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
tushki7	0:60d829a0353a	2555	#define I2S_TCR2_BCI_MASK 0x10000000u
tushki7	0:60d829a0353a	2556	#define I2S_TCR2_BCI_SHIFT 28
tushki7	0:60d829a0353a	2557	#define I2S_TCR2_BCS_MASK 0x20000000u
tushki7	0:60d829a0353a	2558	#define I2S_TCR2_BCS_SHIFT 29
tushki7	0:60d829a0353a	2559	#define I2S_TCR2_SYNC_MASK 0xC0000000u
tushki7	0:60d829a0353a	2560	#define I2S_TCR2_SYNC_SHIFT 30
tushki7	0:60d829a0353a	2561	#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
tushki7	0:60d829a0353a	2562	/* TCR3 Bit Fields */
tushki7	0:60d829a0353a	2563	#define I2S_TCR3_WDFL_MASK 0x1Fu
tushki7	0:60d829a0353a	2564	#define I2S_TCR3_WDFL_SHIFT 0
tushki7	0:60d829a0353a	2565	#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
tushki7	0:60d829a0353a	2566	#define I2S_TCR3_TCE_MASK 0x30000u
tushki7	0:60d829a0353a	2567	#define I2S_TCR3_TCE_SHIFT 16
tushki7	0:60d829a0353a	2568	#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
tushki7	0:60d829a0353a	2569	/* TCR4 Bit Fields */
tushki7	0:60d829a0353a	2570	#define I2S_TCR4_FSD_MASK 0x1u
tushki7	0:60d829a0353a	2571	#define I2S_TCR4_FSD_SHIFT 0
tushki7	0:60d829a0353a	2572	#define I2S_TCR4_FSP_MASK 0x2u
tushki7	0:60d829a0353a	2573	#define I2S_TCR4_FSP_SHIFT 1
tushki7	0:60d829a0353a	2574	#define I2S_TCR4_FSE_MASK 0x8u
tushki7	0:60d829a0353a	2575	#define I2S_TCR4_FSE_SHIFT 3
tushki7	0:60d829a0353a	2576	#define I2S_TCR4_MF_MASK 0x10u
tushki7	0:60d829a0353a	2577	#define I2S_TCR4_MF_SHIFT 4
tushki7	0:60d829a0353a	2578	#define I2S_TCR4_SYWD_MASK 0x1F00u
tushki7	0:60d829a0353a	2579	#define I2S_TCR4_SYWD_SHIFT 8
tushki7	0:60d829a0353a	2580	#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
tushki7	0:60d829a0353a	2581	#define I2S_TCR4_FRSZ_MASK 0x1F0000u
tushki7	0:60d829a0353a	2582	#define I2S_TCR4_FRSZ_SHIFT 16
tushki7	0:60d829a0353a	2583	#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
tushki7	0:60d829a0353a	2584	/* TCR5 Bit Fields */
tushki7	0:60d829a0353a	2585	#define I2S_TCR5_FBT_MASK 0x1F00u
tushki7	0:60d829a0353a	2586	#define I2S_TCR5_FBT_SHIFT 8
tushki7	0:60d829a0353a	2587	#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
tushki7	0:60d829a0353a	2588	#define I2S_TCR5_W0W_MASK 0x1F0000u
tushki7	0:60d829a0353a	2589	#define I2S_TCR5_W0W_SHIFT 16
tushki7	0:60d829a0353a	2590	#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
tushki7	0:60d829a0353a	2591	#define I2S_TCR5_WNW_MASK 0x1F000000u
tushki7	0:60d829a0353a	2592	#define I2S_TCR5_WNW_SHIFT 24
tushki7	0:60d829a0353a	2593	#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
tushki7	0:60d829a0353a	2594	/* TDR Bit Fields */
tushki7	0:60d829a0353a	2595	#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	2596	#define I2S_TDR_TDR_SHIFT 0
tushki7	0:60d829a0353a	2597	#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
tushki7	0:60d829a0353a	2598	/* TFR Bit Fields */
tushki7	0:60d829a0353a	2599	#define I2S_TFR_RFP_MASK 0xFu
tushki7	0:60d829a0353a	2600	#define I2S_TFR_RFP_SHIFT 0
tushki7	0:60d829a0353a	2601	#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
tushki7	0:60d829a0353a	2602	#define I2S_TFR_WFP_MASK 0xF0000u
tushki7	0:60d829a0353a	2603	#define I2S_TFR_WFP_SHIFT 16
tushki7	0:60d829a0353a	2604	#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
tushki7	0:60d829a0353a	2605	/* TMR Bit Fields */
tushki7	0:60d829a0353a	2606	#define I2S_TMR_TWM_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	2607	#define I2S_TMR_TWM_SHIFT 0
tushki7	0:60d829a0353a	2608	#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
tushki7	0:60d829a0353a	2609	/* RCSR Bit Fields */
tushki7	0:60d829a0353a	2610	#define I2S_RCSR_FRDE_MASK 0x1u
tushki7	0:60d829a0353a	2611	#define I2S_RCSR_FRDE_SHIFT 0
tushki7	0:60d829a0353a	2612	#define I2S_RCSR_FWDE_MASK 0x2u
tushki7	0:60d829a0353a	2613	#define I2S_RCSR_FWDE_SHIFT 1
tushki7	0:60d829a0353a	2614	#define I2S_RCSR_FRIE_MASK 0x100u
tushki7	0:60d829a0353a	2615	#define I2S_RCSR_FRIE_SHIFT 8
tushki7	0:60d829a0353a	2616	#define I2S_RCSR_FWIE_MASK 0x200u
tushki7	0:60d829a0353a	2617	#define I2S_RCSR_FWIE_SHIFT 9
tushki7	0:60d829a0353a	2618	#define I2S_RCSR_FEIE_MASK 0x400u
tushki7	0:60d829a0353a	2619	#define I2S_RCSR_FEIE_SHIFT 10
tushki7	0:60d829a0353a	2620	#define I2S_RCSR_SEIE_MASK 0x800u
tushki7	0:60d829a0353a	2621	#define I2S_RCSR_SEIE_SHIFT 11
tushki7	0:60d829a0353a	2622	#define I2S_RCSR_WSIE_MASK 0x1000u
tushki7	0:60d829a0353a	2623	#define I2S_RCSR_WSIE_SHIFT 12
tushki7	0:60d829a0353a	2624	#define I2S_RCSR_FRF_MASK 0x10000u
tushki7	0:60d829a0353a	2625	#define I2S_RCSR_FRF_SHIFT 16
tushki7	0:60d829a0353a	2626	#define I2S_RCSR_FWF_MASK 0x20000u
tushki7	0:60d829a0353a	2627	#define I2S_RCSR_FWF_SHIFT 17
tushki7	0:60d829a0353a	2628	#define I2S_RCSR_FEF_MASK 0x40000u
tushki7	0:60d829a0353a	2629	#define I2S_RCSR_FEF_SHIFT 18
tushki7	0:60d829a0353a	2630	#define I2S_RCSR_SEF_MASK 0x80000u
tushki7	0:60d829a0353a	2631	#define I2S_RCSR_SEF_SHIFT 19
tushki7	0:60d829a0353a	2632	#define I2S_RCSR_WSF_MASK 0x100000u
tushki7	0:60d829a0353a	2633	#define I2S_RCSR_WSF_SHIFT 20
tushki7	0:60d829a0353a	2634	#define I2S_RCSR_SR_MASK 0x1000000u
tushki7	0:60d829a0353a	2635	#define I2S_RCSR_SR_SHIFT 24
tushki7	0:60d829a0353a	2636	#define I2S_RCSR_FR_MASK 0x2000000u
tushki7	0:60d829a0353a	2637	#define I2S_RCSR_FR_SHIFT 25
tushki7	0:60d829a0353a	2638	#define I2S_RCSR_BCE_MASK 0x10000000u
tushki7	0:60d829a0353a	2639	#define I2S_RCSR_BCE_SHIFT 28
tushki7	0:60d829a0353a	2640	#define I2S_RCSR_DBGE_MASK 0x20000000u
tushki7	0:60d829a0353a	2641	#define I2S_RCSR_DBGE_SHIFT 29
tushki7	0:60d829a0353a	2642	#define I2S_RCSR_STOPE_MASK 0x40000000u
tushki7	0:60d829a0353a	2643	#define I2S_RCSR_STOPE_SHIFT 30
tushki7	0:60d829a0353a	2644	#define I2S_RCSR_RE_MASK 0x80000000u
tushki7	0:60d829a0353a	2645	#define I2S_RCSR_RE_SHIFT 31
tushki7	0:60d829a0353a	2646	/* RCR1 Bit Fields */
tushki7	0:60d829a0353a	2647	#define I2S_RCR1_RFW_MASK 0x7u
tushki7	0:60d829a0353a	2648	#define I2S_RCR1_RFW_SHIFT 0
tushki7	0:60d829a0353a	2649	#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
tushki7	0:60d829a0353a	2650	/* RCR2 Bit Fields */
tushki7	0:60d829a0353a	2651	#define I2S_RCR2_DIV_MASK 0xFFu
tushki7	0:60d829a0353a	2652	#define I2S_RCR2_DIV_SHIFT 0
tushki7	0:60d829a0353a	2653	#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
tushki7	0:60d829a0353a	2654	#define I2S_RCR2_BCD_MASK 0x1000000u
tushki7	0:60d829a0353a	2655	#define I2S_RCR2_BCD_SHIFT 24
tushki7	0:60d829a0353a	2656	#define I2S_RCR2_BCP_MASK 0x2000000u
tushki7	0:60d829a0353a	2657	#define I2S_RCR2_BCP_SHIFT 25
tushki7	0:60d829a0353a	2658	#define I2S_RCR2_MSEL_MASK 0xC000000u
tushki7	0:60d829a0353a	2659	#define I2S_RCR2_MSEL_SHIFT 26
tushki7	0:60d829a0353a	2660	#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
tushki7	0:60d829a0353a	2661	#define I2S_RCR2_BCI_MASK 0x10000000u
tushki7	0:60d829a0353a	2662	#define I2S_RCR2_BCI_SHIFT 28
tushki7	0:60d829a0353a	2663	#define I2S_RCR2_BCS_MASK 0x20000000u
tushki7	0:60d829a0353a	2664	#define I2S_RCR2_BCS_SHIFT 29
tushki7	0:60d829a0353a	2665	#define I2S_RCR2_SYNC_MASK 0xC0000000u
tushki7	0:60d829a0353a	2666	#define I2S_RCR2_SYNC_SHIFT 30
tushki7	0:60d829a0353a	2667	#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
tushki7	0:60d829a0353a	2668	/* RCR3 Bit Fields */
tushki7	0:60d829a0353a	2669	#define I2S_RCR3_WDFL_MASK 0x1Fu
tushki7	0:60d829a0353a	2670	#define I2S_RCR3_WDFL_SHIFT 0
tushki7	0:60d829a0353a	2671	#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
tushki7	0:60d829a0353a	2672	#define I2S_RCR3_RCE_MASK 0x30000u
tushki7	0:60d829a0353a	2673	#define I2S_RCR3_RCE_SHIFT 16
tushki7	0:60d829a0353a	2674	#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
tushki7	0:60d829a0353a	2675	/* RCR4 Bit Fields */
tushki7	0:60d829a0353a	2676	#define I2S_RCR4_FSD_MASK 0x1u
tushki7	0:60d829a0353a	2677	#define I2S_RCR4_FSD_SHIFT 0
tushki7	0:60d829a0353a	2678	#define I2S_RCR4_FSP_MASK 0x2u
tushki7	0:60d829a0353a	2679	#define I2S_RCR4_FSP_SHIFT 1
tushki7	0:60d829a0353a	2680	#define I2S_RCR4_FSE_MASK 0x8u
tushki7	0:60d829a0353a	2681	#define I2S_RCR4_FSE_SHIFT 3
tushki7	0:60d829a0353a	2682	#define I2S_RCR4_MF_MASK 0x10u
tushki7	0:60d829a0353a	2683	#define I2S_RCR4_MF_SHIFT 4
tushki7	0:60d829a0353a	2684	#define I2S_RCR4_SYWD_MASK 0x1F00u
tushki7	0:60d829a0353a	2685	#define I2S_RCR4_SYWD_SHIFT 8
tushki7	0:60d829a0353a	2686	#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
tushki7	0:60d829a0353a	2687	#define I2S_RCR4_FRSZ_MASK 0x1F0000u
tushki7	0:60d829a0353a	2688	#define I2S_RCR4_FRSZ_SHIFT 16
tushki7	0:60d829a0353a	2689	#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
tushki7	0:60d829a0353a	2690	/* RCR5 Bit Fields */
tushki7	0:60d829a0353a	2691	#define I2S_RCR5_FBT_MASK 0x1F00u
tushki7	0:60d829a0353a	2692	#define I2S_RCR5_FBT_SHIFT 8
tushki7	0:60d829a0353a	2693	#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
tushki7	0:60d829a0353a	2694	#define I2S_RCR5_W0W_MASK 0x1F0000u
tushki7	0:60d829a0353a	2695	#define I2S_RCR5_W0W_SHIFT 16
tushki7	0:60d829a0353a	2696	#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
tushki7	0:60d829a0353a	2697	#define I2S_RCR5_WNW_MASK 0x1F000000u
tushki7	0:60d829a0353a	2698	#define I2S_RCR5_WNW_SHIFT 24
tushki7	0:60d829a0353a	2699	#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
tushki7	0:60d829a0353a	2700	/* RDR Bit Fields */
tushki7	0:60d829a0353a	2701	#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	2702	#define I2S_RDR_RDR_SHIFT 0
tushki7	0:60d829a0353a	2703	#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
tushki7	0:60d829a0353a	2704	/* RFR Bit Fields */
tushki7	0:60d829a0353a	2705	#define I2S_RFR_RFP_MASK 0xFu
tushki7	0:60d829a0353a	2706	#define I2S_RFR_RFP_SHIFT 0
tushki7	0:60d829a0353a	2707	#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
tushki7	0:60d829a0353a	2708	#define I2S_RFR_WFP_MASK 0xF0000u
tushki7	0:60d829a0353a	2709	#define I2S_RFR_WFP_SHIFT 16
tushki7	0:60d829a0353a	2710	#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
tushki7	0:60d829a0353a	2711	/* RMR Bit Fields */
tushki7	0:60d829a0353a	2712	#define I2S_RMR_RWM_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	2713	#define I2S_RMR_RWM_SHIFT 0
tushki7	0:60d829a0353a	2714	#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
tushki7	0:60d829a0353a	2715	/* MCR Bit Fields */
tushki7	0:60d829a0353a	2716	#define I2S_MCR_MICS_MASK 0x3000000u
tushki7	0:60d829a0353a	2717	#define I2S_MCR_MICS_SHIFT 24
tushki7	0:60d829a0353a	2718	#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
tushki7	0:60d829a0353a	2719	#define I2S_MCR_MOE_MASK 0x40000000u
tushki7	0:60d829a0353a	2720	#define I2S_MCR_MOE_SHIFT 30
tushki7	0:60d829a0353a	2721	#define I2S_MCR_DUF_MASK 0x80000000u
tushki7	0:60d829a0353a	2722	#define I2S_MCR_DUF_SHIFT 31
tushki7	0:60d829a0353a	2723	/* MDR Bit Fields */
tushki7	0:60d829a0353a	2724	#define I2S_MDR_DIVIDE_MASK 0xFFFu
tushki7	0:60d829a0353a	2725	#define I2S_MDR_DIVIDE_SHIFT 0
tushki7	0:60d829a0353a	2726	#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
tushki7	0:60d829a0353a	2727	#define I2S_MDR_FRACT_MASK 0xFF000u
tushki7	0:60d829a0353a	2728	#define I2S_MDR_FRACT_SHIFT 12
tushki7	0:60d829a0353a	2729	#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
tushki7	0:60d829a0353a	2730
tushki7	0:60d829a0353a	2731	/**
tushki7	0:60d829a0353a	2732	* @}
tushki7	0:60d829a0353a	2733	/ / end of group I2S_Register_Masks */
tushki7	0:60d829a0353a	2734
tushki7	0:60d829a0353a	2735
tushki7	0:60d829a0353a	2736	/* I2S - Peripheral instance base addresses */
tushki7	0:60d829a0353a	2737	/** Peripheral I2S0 base address */
tushki7	0:60d829a0353a	2738	#define I2S0_BASE (0x4002F000u)
tushki7	0:60d829a0353a	2739	/** Peripheral I2S0 base pointer */
tushki7	0:60d829a0353a	2740	#define I2S0 ((I2S_Type *)I2S0_BASE)
tushki7	0:60d829a0353a	2741
tushki7	0:60d829a0353a	2742	/**
tushki7	0:60d829a0353a	2743	* @}
tushki7	0:60d829a0353a	2744	/ / end of group I2S_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	2745
tushki7	0:60d829a0353a	2746
tushki7	0:60d829a0353a	2747	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	2748	-- LLWU Peripheral Access Layer
tushki7	0:60d829a0353a	2749	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	2750
tushki7	0:60d829a0353a	2751	/**
tushki7	0:60d829a0353a	2752	* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
tushki7	0:60d829a0353a	2753	* @{
tushki7	0:60d829a0353a	2754	*/
tushki7	0:60d829a0353a	2755
tushki7	0:60d829a0353a	2756	/** LLWU - Register Layout Typedef */
tushki7	0:60d829a0353a	2757	typedef struct {
tushki7	0:60d829a0353a	2758	__IO uint8_t PE1; /*< LLWU Pin Enable 1 Register, offset: 0x0 /
tushki7	0:60d829a0353a	2759	__IO uint8_t PE2; /*< LLWU Pin Enable 2 Register, offset: 0x1 /
tushki7	0:60d829a0353a	2760	__IO uint8_t PE3; /*< LLWU Pin Enable 3 Register, offset: 0x2 /
tushki7	0:60d829a0353a	2761	__IO uint8_t PE4; /*< LLWU Pin Enable 4 Register, offset: 0x3 /
tushki7	0:60d829a0353a	2762	__IO uint8_t ME; /*< LLWU Module Enable Register, offset: 0x4 /
tushki7	0:60d829a0353a	2763	__IO uint8_t F1; /*< LLWU Flag 1 Register, offset: 0x5 /
tushki7	0:60d829a0353a	2764	__IO uint8_t F2; /*< LLWU Flag 2 Register, offset: 0x6 /
tushki7	0:60d829a0353a	2765	__I uint8_t F3; /*< LLWU Flag 3 Register, offset: 0x7 /
tushki7	0:60d829a0353a	2766	__IO uint8_t FILT1; /*< LLWU Pin Filter 1 Register, offset: 0x8 /
tushki7	0:60d829a0353a	2767	__IO uint8_t FILT2; /*< LLWU Pin Filter 2 Register, offset: 0x9 /
tushki7	0:60d829a0353a	2768	__IO uint8_t RST; /*< LLWU Reset Enable Register, offset: 0xA /
tushki7	0:60d829a0353a	2769	} LLWU_Type;
tushki7	0:60d829a0353a	2770
tushki7	0:60d829a0353a	2771	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	2772	-- LLWU Register Masks
tushki7	0:60d829a0353a	2773	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	2774
tushki7	0:60d829a0353a	2775	/**
tushki7	0:60d829a0353a	2776	* @addtogroup LLWU_Register_Masks LLWU Register Masks
tushki7	0:60d829a0353a	2777	* @{
tushki7	0:60d829a0353a	2778	*/
tushki7	0:60d829a0353a	2779
tushki7	0:60d829a0353a	2780	/* PE1 Bit Fields */
tushki7	0:60d829a0353a	2781	#define LLWU_PE1_WUPE0_MASK 0x3u
tushki7	0:60d829a0353a	2782	#define LLWU_PE1_WUPE0_SHIFT 0
tushki7	0:60d829a0353a	2783	#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
tushki7	0:60d829a0353a	2784	#define LLWU_PE1_WUPE1_MASK 0xCu
tushki7	0:60d829a0353a	2785	#define LLWU_PE1_WUPE1_SHIFT 2
tushki7	0:60d829a0353a	2786	#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
tushki7	0:60d829a0353a	2787	#define LLWU_PE1_WUPE2_MASK 0x30u
tushki7	0:60d829a0353a	2788	#define LLWU_PE1_WUPE2_SHIFT 4
tushki7	0:60d829a0353a	2789	#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
tushki7	0:60d829a0353a	2790	#define LLWU_PE1_WUPE3_MASK 0xC0u
tushki7	0:60d829a0353a	2791	#define LLWU_PE1_WUPE3_SHIFT 6
tushki7	0:60d829a0353a	2792	#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
tushki7	0:60d829a0353a	2793	/* PE2 Bit Fields */
tushki7	0:60d829a0353a	2794	#define LLWU_PE2_WUPE4_MASK 0x3u
tushki7	0:60d829a0353a	2795	#define LLWU_PE2_WUPE4_SHIFT 0
tushki7	0:60d829a0353a	2796	#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
tushki7	0:60d829a0353a	2797	#define LLWU_PE2_WUPE5_MASK 0xCu
tushki7	0:60d829a0353a	2798	#define LLWU_PE2_WUPE5_SHIFT 2
tushki7	0:60d829a0353a	2799	#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
tushki7	0:60d829a0353a	2800	#define LLWU_PE2_WUPE6_MASK 0x30u
tushki7	0:60d829a0353a	2801	#define LLWU_PE2_WUPE6_SHIFT 4
tushki7	0:60d829a0353a	2802	#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
tushki7	0:60d829a0353a	2803	#define LLWU_PE2_WUPE7_MASK 0xC0u
tushki7	0:60d829a0353a	2804	#define LLWU_PE2_WUPE7_SHIFT 6
tushki7	0:60d829a0353a	2805	#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
tushki7	0:60d829a0353a	2806	/* PE3 Bit Fields */
tushki7	0:60d829a0353a	2807	#define LLWU_PE3_WUPE8_MASK 0x3u
tushki7	0:60d829a0353a	2808	#define LLWU_PE3_WUPE8_SHIFT 0
tushki7	0:60d829a0353a	2809	#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
tushki7	0:60d829a0353a	2810	#define LLWU_PE3_WUPE9_MASK 0xCu
tushki7	0:60d829a0353a	2811	#define LLWU_PE3_WUPE9_SHIFT 2
tushki7	0:60d829a0353a	2812	#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
tushki7	0:60d829a0353a	2813	#define LLWU_PE3_WUPE10_MASK 0x30u
tushki7	0:60d829a0353a	2814	#define LLWU_PE3_WUPE10_SHIFT 4
tushki7	0:60d829a0353a	2815	#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
tushki7	0:60d829a0353a	2816	#define LLWU_PE3_WUPE11_MASK 0xC0u
tushki7	0:60d829a0353a	2817	#define LLWU_PE3_WUPE11_SHIFT 6
tushki7	0:60d829a0353a	2818	#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
tushki7	0:60d829a0353a	2819	/* PE4 Bit Fields */
tushki7	0:60d829a0353a	2820	#define LLWU_PE4_WUPE12_MASK 0x3u
tushki7	0:60d829a0353a	2821	#define LLWU_PE4_WUPE12_SHIFT 0
tushki7	0:60d829a0353a	2822	#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
tushki7	0:60d829a0353a	2823	#define LLWU_PE4_WUPE13_MASK 0xCu
tushki7	0:60d829a0353a	2824	#define LLWU_PE4_WUPE13_SHIFT 2
tushki7	0:60d829a0353a	2825	#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
tushki7	0:60d829a0353a	2826	#define LLWU_PE4_WUPE14_MASK 0x30u
tushki7	0:60d829a0353a	2827	#define LLWU_PE4_WUPE14_SHIFT 4
tushki7	0:60d829a0353a	2828	#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
tushki7	0:60d829a0353a	2829	#define LLWU_PE4_WUPE15_MASK 0xC0u
tushki7	0:60d829a0353a	2830	#define LLWU_PE4_WUPE15_SHIFT 6
tushki7	0:60d829a0353a	2831	#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
tushki7	0:60d829a0353a	2832	/* ME Bit Fields */
tushki7	0:60d829a0353a	2833	#define LLWU_ME_WUME0_MASK 0x1u
tushki7	0:60d829a0353a	2834	#define LLWU_ME_WUME0_SHIFT 0
tushki7	0:60d829a0353a	2835	#define LLWU_ME_WUME1_MASK 0x2u
tushki7	0:60d829a0353a	2836	#define LLWU_ME_WUME1_SHIFT 1
tushki7	0:60d829a0353a	2837	#define LLWU_ME_WUME2_MASK 0x4u
tushki7	0:60d829a0353a	2838	#define LLWU_ME_WUME2_SHIFT 2
tushki7	0:60d829a0353a	2839	#define LLWU_ME_WUME3_MASK 0x8u
tushki7	0:60d829a0353a	2840	#define LLWU_ME_WUME3_SHIFT 3
tushki7	0:60d829a0353a	2841	#define LLWU_ME_WUME4_MASK 0x10u
tushki7	0:60d829a0353a	2842	#define LLWU_ME_WUME4_SHIFT 4
tushki7	0:60d829a0353a	2843	#define LLWU_ME_WUME5_MASK 0x20u
tushki7	0:60d829a0353a	2844	#define LLWU_ME_WUME5_SHIFT 5
tushki7	0:60d829a0353a	2845	#define LLWU_ME_WUME6_MASK 0x40u
tushki7	0:60d829a0353a	2846	#define LLWU_ME_WUME6_SHIFT 6
tushki7	0:60d829a0353a	2847	#define LLWU_ME_WUME7_MASK 0x80u
tushki7	0:60d829a0353a	2848	#define LLWU_ME_WUME7_SHIFT 7
tushki7	0:60d829a0353a	2849	/* F1 Bit Fields */
tushki7	0:60d829a0353a	2850	#define LLWU_F1_WUF0_MASK 0x1u
tushki7	0:60d829a0353a	2851	#define LLWU_F1_WUF0_SHIFT 0
tushki7	0:60d829a0353a	2852	#define LLWU_F1_WUF1_MASK 0x2u
tushki7	0:60d829a0353a	2853	#define LLWU_F1_WUF1_SHIFT 1
tushki7	0:60d829a0353a	2854	#define LLWU_F1_WUF2_MASK 0x4u
tushki7	0:60d829a0353a	2855	#define LLWU_F1_WUF2_SHIFT 2
tushki7	0:60d829a0353a	2856	#define LLWU_F1_WUF3_MASK 0x8u
tushki7	0:60d829a0353a	2857	#define LLWU_F1_WUF3_SHIFT 3
tushki7	0:60d829a0353a	2858	#define LLWU_F1_WUF4_MASK 0x10u
tushki7	0:60d829a0353a	2859	#define LLWU_F1_WUF4_SHIFT 4
tushki7	0:60d829a0353a	2860	#define LLWU_F1_WUF5_MASK 0x20u
tushki7	0:60d829a0353a	2861	#define LLWU_F1_WUF5_SHIFT 5
tushki7	0:60d829a0353a	2862	#define LLWU_F1_WUF6_MASK 0x40u
tushki7	0:60d829a0353a	2863	#define LLWU_F1_WUF6_SHIFT 6
tushki7	0:60d829a0353a	2864	#define LLWU_F1_WUF7_MASK 0x80u
tushki7	0:60d829a0353a	2865	#define LLWU_F1_WUF7_SHIFT 7
tushki7	0:60d829a0353a	2866	/* F2 Bit Fields */
tushki7	0:60d829a0353a	2867	#define LLWU_F2_WUF8_MASK 0x1u
tushki7	0:60d829a0353a	2868	#define LLWU_F2_WUF8_SHIFT 0
tushki7	0:60d829a0353a	2869	#define LLWU_F2_WUF9_MASK 0x2u
tushki7	0:60d829a0353a	2870	#define LLWU_F2_WUF9_SHIFT 1
tushki7	0:60d829a0353a	2871	#define LLWU_F2_WUF10_MASK 0x4u
tushki7	0:60d829a0353a	2872	#define LLWU_F2_WUF10_SHIFT 2
tushki7	0:60d829a0353a	2873	#define LLWU_F2_WUF11_MASK 0x8u
tushki7	0:60d829a0353a	2874	#define LLWU_F2_WUF11_SHIFT 3
tushki7	0:60d829a0353a	2875	#define LLWU_F2_WUF12_MASK 0x10u
tushki7	0:60d829a0353a	2876	#define LLWU_F2_WUF12_SHIFT 4
tushki7	0:60d829a0353a	2877	#define LLWU_F2_WUF13_MASK 0x20u
tushki7	0:60d829a0353a	2878	#define LLWU_F2_WUF13_SHIFT 5
tushki7	0:60d829a0353a	2879	#define LLWU_F2_WUF14_MASK 0x40u
tushki7	0:60d829a0353a	2880	#define LLWU_F2_WUF14_SHIFT 6
tushki7	0:60d829a0353a	2881	#define LLWU_F2_WUF15_MASK 0x80u
tushki7	0:60d829a0353a	2882	#define LLWU_F2_WUF15_SHIFT 7
tushki7	0:60d829a0353a	2883	/* F3 Bit Fields */
tushki7	0:60d829a0353a	2884	#define LLWU_F3_MWUF0_MASK 0x1u
tushki7	0:60d829a0353a	2885	#define LLWU_F3_MWUF0_SHIFT 0
tushki7	0:60d829a0353a	2886	#define LLWU_F3_MWUF1_MASK 0x2u
tushki7	0:60d829a0353a	2887	#define LLWU_F3_MWUF1_SHIFT 1
tushki7	0:60d829a0353a	2888	#define LLWU_F3_MWUF2_MASK 0x4u
tushki7	0:60d829a0353a	2889	#define LLWU_F3_MWUF2_SHIFT 2
tushki7	0:60d829a0353a	2890	#define LLWU_F3_MWUF3_MASK 0x8u
tushki7	0:60d829a0353a	2891	#define LLWU_F3_MWUF3_SHIFT 3
tushki7	0:60d829a0353a	2892	#define LLWU_F3_MWUF4_MASK 0x10u
tushki7	0:60d829a0353a	2893	#define LLWU_F3_MWUF4_SHIFT 4
tushki7	0:60d829a0353a	2894	#define LLWU_F3_MWUF5_MASK 0x20u
tushki7	0:60d829a0353a	2895	#define LLWU_F3_MWUF5_SHIFT 5
tushki7	0:60d829a0353a	2896	#define LLWU_F3_MWUF6_MASK 0x40u
tushki7	0:60d829a0353a	2897	#define LLWU_F3_MWUF6_SHIFT 6
tushki7	0:60d829a0353a	2898	#define LLWU_F3_MWUF7_MASK 0x80u
tushki7	0:60d829a0353a	2899	#define LLWU_F3_MWUF7_SHIFT 7
tushki7	0:60d829a0353a	2900	/* FILT1 Bit Fields */
tushki7	0:60d829a0353a	2901	#define LLWU_FILT1_FILTSEL_MASK 0xFu
tushki7	0:60d829a0353a	2902	#define LLWU_FILT1_FILTSEL_SHIFT 0
tushki7	0:60d829a0353a	2903	#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
tushki7	0:60d829a0353a	2904	#define LLWU_FILT1_FILTE_MASK 0x60u
tushki7	0:60d829a0353a	2905	#define LLWU_FILT1_FILTE_SHIFT 5
tushki7	0:60d829a0353a	2906	#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
tushki7	0:60d829a0353a	2907	#define LLWU_FILT1_FILTF_MASK 0x80u
tushki7	0:60d829a0353a	2908	#define LLWU_FILT1_FILTF_SHIFT 7
tushki7	0:60d829a0353a	2909	/* FILT2 Bit Fields */
tushki7	0:60d829a0353a	2910	#define LLWU_FILT2_FILTSEL_MASK 0xFu
tushki7	0:60d829a0353a	2911	#define LLWU_FILT2_FILTSEL_SHIFT 0
tushki7	0:60d829a0353a	2912	#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
tushki7	0:60d829a0353a	2913	#define LLWU_FILT2_FILTE_MASK 0x60u
tushki7	0:60d829a0353a	2914	#define LLWU_FILT2_FILTE_SHIFT 5
tushki7	0:60d829a0353a	2915	#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
tushki7	0:60d829a0353a	2916	#define LLWU_FILT2_FILTF_MASK 0x80u
tushki7	0:60d829a0353a	2917	#define LLWU_FILT2_FILTF_SHIFT 7
tushki7	0:60d829a0353a	2918	/* RST Bit Fields */
tushki7	0:60d829a0353a	2919	#define LLWU_RST_RSTFILT_MASK 0x1u
tushki7	0:60d829a0353a	2920	#define LLWU_RST_RSTFILT_SHIFT 0
tushki7	0:60d829a0353a	2921	#define LLWU_RST_LLRSTE_MASK 0x2u
tushki7	0:60d829a0353a	2922	#define LLWU_RST_LLRSTE_SHIFT 1
tushki7	0:60d829a0353a	2923
tushki7	0:60d829a0353a	2924	/**
tushki7	0:60d829a0353a	2925	* @}
tushki7	0:60d829a0353a	2926	/ / end of group LLWU_Register_Masks */
tushki7	0:60d829a0353a	2927
tushki7	0:60d829a0353a	2928
tushki7	0:60d829a0353a	2929	/* LLWU - Peripheral instance base addresses */
tushki7	0:60d829a0353a	2930	/** Peripheral LLWU base address */
tushki7	0:60d829a0353a	2931	#define LLWU_BASE (0x4007C000u)
tushki7	0:60d829a0353a	2932	/** Peripheral LLWU base pointer */
tushki7	0:60d829a0353a	2933	#define LLWU ((LLWU_Type *)LLWU_BASE)
tushki7	0:60d829a0353a	2934
tushki7	0:60d829a0353a	2935	/**
tushki7	0:60d829a0353a	2936	* @}
tushki7	0:60d829a0353a	2937	/ / end of group LLWU_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	2938
tushki7	0:60d829a0353a	2939
tushki7	0:60d829a0353a	2940	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	2941	-- LPTMR Peripheral Access Layer
tushki7	0:60d829a0353a	2942	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	2943
tushki7	0:60d829a0353a	2944	/**
tushki7	0:60d829a0353a	2945	* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
tushki7	0:60d829a0353a	2946	* @{
tushki7	0:60d829a0353a	2947	*/
tushki7	0:60d829a0353a	2948
tushki7	0:60d829a0353a	2949	/** LPTMR - Register Layout Typedef */
tushki7	0:60d829a0353a	2950	typedef struct {
tushki7	0:60d829a0353a	2951	__IO uint32_t CSR; /*< Low Power Timer Control Status Register, offset: 0x0 /
tushki7	0:60d829a0353a	2952	__IO uint32_t PSR; /*< Low Power Timer Prescale Register, offset: 0x4 /
tushki7	0:60d829a0353a	2953	__IO uint32_t CMR; /*< Low Power Timer Compare Register, offset: 0x8 /
tushki7	0:60d829a0353a	2954	__I uint32_t CNR; /*< Low Power Timer Counter Register, offset: 0xC /
tushki7	0:60d829a0353a	2955	} LPTMR_Type;
tushki7	0:60d829a0353a	2956
tushki7	0:60d829a0353a	2957	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	2958	-- LPTMR Register Masks
tushki7	0:60d829a0353a	2959	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	2960
tushki7	0:60d829a0353a	2961	/**
tushki7	0:60d829a0353a	2962	* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
tushki7	0:60d829a0353a	2963	* @{
tushki7	0:60d829a0353a	2964	*/
tushki7	0:60d829a0353a	2965
tushki7	0:60d829a0353a	2966	/* CSR Bit Fields */
tushki7	0:60d829a0353a	2967	#define LPTMR_CSR_TEN_MASK 0x1u
tushki7	0:60d829a0353a	2968	#define LPTMR_CSR_TEN_SHIFT 0
tushki7	0:60d829a0353a	2969	#define LPTMR_CSR_TMS_MASK 0x2u
tushki7	0:60d829a0353a	2970	#define LPTMR_CSR_TMS_SHIFT 1
tushki7	0:60d829a0353a	2971	#define LPTMR_CSR_TFC_MASK 0x4u
tushki7	0:60d829a0353a	2972	#define LPTMR_CSR_TFC_SHIFT 2
tushki7	0:60d829a0353a	2973	#define LPTMR_CSR_TPP_MASK 0x8u
tushki7	0:60d829a0353a	2974	#define LPTMR_CSR_TPP_SHIFT 3
tushki7	0:60d829a0353a	2975	#define LPTMR_CSR_TPS_MASK 0x30u
tushki7	0:60d829a0353a	2976	#define LPTMR_CSR_TPS_SHIFT 4
tushki7	0:60d829a0353a	2977	#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
tushki7	0:60d829a0353a	2978	#define LPTMR_CSR_TIE_MASK 0x40u
tushki7	0:60d829a0353a	2979	#define LPTMR_CSR_TIE_SHIFT 6
tushki7	0:60d829a0353a	2980	#define LPTMR_CSR_TCF_MASK 0x80u
tushki7	0:60d829a0353a	2981	#define LPTMR_CSR_TCF_SHIFT 7
tushki7	0:60d829a0353a	2982	/* PSR Bit Fields */
tushki7	0:60d829a0353a	2983	#define LPTMR_PSR_PCS_MASK 0x3u
tushki7	0:60d829a0353a	2984	#define LPTMR_PSR_PCS_SHIFT 0
tushki7	0:60d829a0353a	2985	#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
tushki7	0:60d829a0353a	2986	#define LPTMR_PSR_PBYP_MASK 0x4u
tushki7	0:60d829a0353a	2987	#define LPTMR_PSR_PBYP_SHIFT 2
tushki7	0:60d829a0353a	2988	#define LPTMR_PSR_PRESCALE_MASK 0x78u
tushki7	0:60d829a0353a	2989	#define LPTMR_PSR_PRESCALE_SHIFT 3
tushki7	0:60d829a0353a	2990	#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
tushki7	0:60d829a0353a	2991	/* CMR Bit Fields */
tushki7	0:60d829a0353a	2992	#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
tushki7	0:60d829a0353a	2993	#define LPTMR_CMR_COMPARE_SHIFT 0
tushki7	0:60d829a0353a	2994	#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
tushki7	0:60d829a0353a	2995	/* CNR Bit Fields */
tushki7	0:60d829a0353a	2996	#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
tushki7	0:60d829a0353a	2997	#define LPTMR_CNR_COUNTER_SHIFT 0
tushki7	0:60d829a0353a	2998	#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
tushki7	0:60d829a0353a	2999
tushki7	0:60d829a0353a	3000	/**
tushki7	0:60d829a0353a	3001	* @}
tushki7	0:60d829a0353a	3002	/ / end of group LPTMR_Register_Masks */
tushki7	0:60d829a0353a	3003
tushki7	0:60d829a0353a	3004
tushki7	0:60d829a0353a	3005	/* LPTMR - Peripheral instance base addresses */
tushki7	0:60d829a0353a	3006	/** Peripheral LPTMR0 base address */
tushki7	0:60d829a0353a	3007	#define LPTMR0_BASE (0x40040000u)
tushki7	0:60d829a0353a	3008	/** Peripheral LPTMR0 base pointer */
tushki7	0:60d829a0353a	3009	#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
tushki7	0:60d829a0353a	3010
tushki7	0:60d829a0353a	3011	/**
tushki7	0:60d829a0353a	3012	* @}
tushki7	0:60d829a0353a	3013	/ / end of group LPTMR_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	3014
tushki7	0:60d829a0353a	3015
tushki7	0:60d829a0353a	3016	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3017	-- MCG Peripheral Access Layer
tushki7	0:60d829a0353a	3018	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3019
tushki7	0:60d829a0353a	3020	/**
tushki7	0:60d829a0353a	3021	* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
tushki7	0:60d829a0353a	3022	* @{
tushki7	0:60d829a0353a	3023	*/
tushki7	0:60d829a0353a	3024
tushki7	0:60d829a0353a	3025	/** MCG - Register Layout Typedef */
tushki7	0:60d829a0353a	3026	typedef struct {
tushki7	0:60d829a0353a	3027	__IO uint8_t C1; /*< MCG Control 1 Register, offset: 0x0 /
tushki7	0:60d829a0353a	3028	__IO uint8_t C2; /*< MCG Control 2 Register, offset: 0x1 /
tushki7	0:60d829a0353a	3029	__IO uint8_t C3; /*< MCG Control 3 Register, offset: 0x2 /
tushki7	0:60d829a0353a	3030	__IO uint8_t C4; /*< MCG Control 4 Register, offset: 0x3 /
tushki7	0:60d829a0353a	3031	__IO uint8_t C5; /*< MCG Control 5 Register, offset: 0x4 /
tushki7	0:60d829a0353a	3032	__IO uint8_t C6; /*< MCG Control 6 Register, offset: 0x5 /
tushki7	0:60d829a0353a	3033	__I uint8_t S; /*< MCG Status Register, offset: 0x6 /
tushki7	0:60d829a0353a	3034	uint8_t RESERVED_0[1];
tushki7	0:60d829a0353a	3035	__IO uint8_t SC; /*< MCG Status and Control Register, offset: 0x8 /
tushki7	0:60d829a0353a	3036	uint8_t RESERVED_1[1];
tushki7	0:60d829a0353a	3037	__IO uint8_t ATCVH; /*< MCG Auto Trim Compare Value High Register, offset: 0xA /
tushki7	0:60d829a0353a	3038	__IO uint8_t ATCVL; /*< MCG Auto Trim Compare Value Low Register, offset: 0xB /
tushki7	0:60d829a0353a	3039	__IO uint8_t C7; /*< MCG Control 7 Register, offset: 0xC /
tushki7	0:60d829a0353a	3040	__IO uint8_t C8; /*< MCG Control 8 Register, offset: 0xD /
tushki7	0:60d829a0353a	3041	} MCG_Type;
tushki7	0:60d829a0353a	3042
tushki7	0:60d829a0353a	3043	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3044	-- MCG Register Masks
tushki7	0:60d829a0353a	3045	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3046
tushki7	0:60d829a0353a	3047	/**
tushki7	0:60d829a0353a	3048	* @addtogroup MCG_Register_Masks MCG Register Masks
tushki7	0:60d829a0353a	3049	* @{
tushki7	0:60d829a0353a	3050	*/
tushki7	0:60d829a0353a	3051
tushki7	0:60d829a0353a	3052	/* C1 Bit Fields */
tushki7	0:60d829a0353a	3053	#define MCG_C1_IREFSTEN_MASK 0x1u
tushki7	0:60d829a0353a	3054	#define MCG_C1_IREFSTEN_SHIFT 0
tushki7	0:60d829a0353a	3055	#define MCG_C1_IRCLKEN_MASK 0x2u
tushki7	0:60d829a0353a	3056	#define MCG_C1_IRCLKEN_SHIFT 1
tushki7	0:60d829a0353a	3057	#define MCG_C1_IREFS_MASK 0x4u
tushki7	0:60d829a0353a	3058	#define MCG_C1_IREFS_SHIFT 2
tushki7	0:60d829a0353a	3059	#define MCG_C1_FRDIV_MASK 0x38u
tushki7	0:60d829a0353a	3060	#define MCG_C1_FRDIV_SHIFT 3
tushki7	0:60d829a0353a	3061	#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
tushki7	0:60d829a0353a	3062	#define MCG_C1_CLKS_MASK 0xC0u
tushki7	0:60d829a0353a	3063	#define MCG_C1_CLKS_SHIFT 6
tushki7	0:60d829a0353a	3064	#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
tushki7	0:60d829a0353a	3065	/* C2 Bit Fields */
tushki7	0:60d829a0353a	3066	#define MCG_C2_IRCS_MASK 0x1u
tushki7	0:60d829a0353a	3067	#define MCG_C2_IRCS_SHIFT 0
tushki7	0:60d829a0353a	3068	#define MCG_C2_LP_MASK 0x2u
tushki7	0:60d829a0353a	3069	#define MCG_C2_LP_SHIFT 1
tushki7	0:60d829a0353a	3070	#define MCG_C2_EREFS0_MASK 0x4u
tushki7	0:60d829a0353a	3071	#define MCG_C2_EREFS0_SHIFT 2
tushki7	0:60d829a0353a	3072	#define MCG_C2_HGO0_MASK 0x8u
tushki7	0:60d829a0353a	3073	#define MCG_C2_HGO0_SHIFT 3
tushki7	0:60d829a0353a	3074	#define MCG_C2_RANGE0_MASK 0x30u
tushki7	0:60d829a0353a	3075	#define MCG_C2_RANGE0_SHIFT 4
tushki7	0:60d829a0353a	3076	#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
tushki7	0:60d829a0353a	3077	#define MCG_C2_LOCRE0_MASK 0x80u
tushki7	0:60d829a0353a	3078	#define MCG_C2_LOCRE0_SHIFT 7
tushki7	0:60d829a0353a	3079	/* C3 Bit Fields */
tushki7	0:60d829a0353a	3080	#define MCG_C3_SCTRIM_MASK 0xFFu
tushki7	0:60d829a0353a	3081	#define MCG_C3_SCTRIM_SHIFT 0
tushki7	0:60d829a0353a	3082	#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
tushki7	0:60d829a0353a	3083	/* C4 Bit Fields */
tushki7	0:60d829a0353a	3084	#define MCG_C4_SCFTRIM_MASK 0x1u
tushki7	0:60d829a0353a	3085	#define MCG_C4_SCFTRIM_SHIFT 0
tushki7	0:60d829a0353a	3086	#define MCG_C4_FCTRIM_MASK 0x1Eu
tushki7	0:60d829a0353a	3087	#define MCG_C4_FCTRIM_SHIFT 1
tushki7	0:60d829a0353a	3088	#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
tushki7	0:60d829a0353a	3089	#define MCG_C4_DRST_DRS_MASK 0x60u
tushki7	0:60d829a0353a	3090	#define MCG_C4_DRST_DRS_SHIFT 5
tushki7	0:60d829a0353a	3091	#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
tushki7	0:60d829a0353a	3092	#define MCG_C4_DMX32_MASK 0x80u
tushki7	0:60d829a0353a	3093	#define MCG_C4_DMX32_SHIFT 7
tushki7	0:60d829a0353a	3094	/* C5 Bit Fields */
tushki7	0:60d829a0353a	3095	#define MCG_C5_PRDIV0_MASK 0x1Fu
tushki7	0:60d829a0353a	3096	#define MCG_C5_PRDIV0_SHIFT 0
tushki7	0:60d829a0353a	3097	#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
tushki7	0:60d829a0353a	3098	#define MCG_C5_PLLSTEN0_MASK 0x20u
tushki7	0:60d829a0353a	3099	#define MCG_C5_PLLSTEN0_SHIFT 5
tushki7	0:60d829a0353a	3100	#define MCG_C5_PLLCLKEN0_MASK 0x40u
tushki7	0:60d829a0353a	3101	#define MCG_C5_PLLCLKEN0_SHIFT 6
tushki7	0:60d829a0353a	3102	/* C6 Bit Fields */
tushki7	0:60d829a0353a	3103	#define MCG_C6_VDIV0_MASK 0x1Fu
tushki7	0:60d829a0353a	3104	#define MCG_C6_VDIV0_SHIFT 0
tushki7	0:60d829a0353a	3105	#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
tushki7	0:60d829a0353a	3106	#define MCG_C6_CME0_MASK 0x20u
tushki7	0:60d829a0353a	3107	#define MCG_C6_CME0_SHIFT 5
tushki7	0:60d829a0353a	3108	#define MCG_C6_PLLS_MASK 0x40u
tushki7	0:60d829a0353a	3109	#define MCG_C6_PLLS_SHIFT 6
tushki7	0:60d829a0353a	3110	#define MCG_C6_LOLIE0_MASK 0x80u
tushki7	0:60d829a0353a	3111	#define MCG_C6_LOLIE0_SHIFT 7
tushki7	0:60d829a0353a	3112	/* S Bit Fields */
tushki7	0:60d829a0353a	3113	#define MCG_S_IRCST_MASK 0x1u
tushki7	0:60d829a0353a	3114	#define MCG_S_IRCST_SHIFT 0
tushki7	0:60d829a0353a	3115	#define MCG_S_OSCINIT0_MASK 0x2u
tushki7	0:60d829a0353a	3116	#define MCG_S_OSCINIT0_SHIFT 1
tushki7	0:60d829a0353a	3117	#define MCG_S_CLKST_MASK 0xCu
tushki7	0:60d829a0353a	3118	#define MCG_S_CLKST_SHIFT 2
tushki7	0:60d829a0353a	3119	#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
tushki7	0:60d829a0353a	3120	#define MCG_S_IREFST_MASK 0x10u
tushki7	0:60d829a0353a	3121	#define MCG_S_IREFST_SHIFT 4
tushki7	0:60d829a0353a	3122	#define MCG_S_PLLST_MASK 0x20u
tushki7	0:60d829a0353a	3123	#define MCG_S_PLLST_SHIFT 5
tushki7	0:60d829a0353a	3124	#define MCG_S_LOCK0_MASK 0x40u
tushki7	0:60d829a0353a	3125	#define MCG_S_LOCK0_SHIFT 6
tushki7	0:60d829a0353a	3126	#define MCG_S_LOLS0_MASK 0x80u
tushki7	0:60d829a0353a	3127	#define MCG_S_LOLS0_SHIFT 7
tushki7	0:60d829a0353a	3128	/* SC Bit Fields */
tushki7	0:60d829a0353a	3129	#define MCG_SC_LOCS0_MASK 0x1u
tushki7	0:60d829a0353a	3130	#define MCG_SC_LOCS0_SHIFT 0
tushki7	0:60d829a0353a	3131	#define MCG_SC_FCRDIV_MASK 0xEu
tushki7	0:60d829a0353a	3132	#define MCG_SC_FCRDIV_SHIFT 1
tushki7	0:60d829a0353a	3133	#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
tushki7	0:60d829a0353a	3134	#define MCG_SC_FLTPRSRV_MASK 0x10u
tushki7	0:60d829a0353a	3135	#define MCG_SC_FLTPRSRV_SHIFT 4
tushki7	0:60d829a0353a	3136	#define MCG_SC_ATMF_MASK 0x20u
tushki7	0:60d829a0353a	3137	#define MCG_SC_ATMF_SHIFT 5
tushki7	0:60d829a0353a	3138	#define MCG_SC_ATMS_MASK 0x40u
tushki7	0:60d829a0353a	3139	#define MCG_SC_ATMS_SHIFT 6
tushki7	0:60d829a0353a	3140	#define MCG_SC_ATME_MASK 0x80u
tushki7	0:60d829a0353a	3141	#define MCG_SC_ATME_SHIFT 7
tushki7	0:60d829a0353a	3142	/* ATCVH Bit Fields */
tushki7	0:60d829a0353a	3143	#define MCG_ATCVH_ATCVH_MASK 0xFFu
tushki7	0:60d829a0353a	3144	#define MCG_ATCVH_ATCVH_SHIFT 0
tushki7	0:60d829a0353a	3145	#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
tushki7	0:60d829a0353a	3146	/* ATCVL Bit Fields */
tushki7	0:60d829a0353a	3147	#define MCG_ATCVL_ATCVL_MASK 0xFFu
tushki7	0:60d829a0353a	3148	#define MCG_ATCVL_ATCVL_SHIFT 0
tushki7	0:60d829a0353a	3149	#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
tushki7	0:60d829a0353a	3150	/* C7 Bit Fields */
tushki7	0:60d829a0353a	3151	#define MCG_C7_OSCSEL_MASK 0x1u
tushki7	0:60d829a0353a	3152	#define MCG_C7_OSCSEL_SHIFT 0
tushki7	0:60d829a0353a	3153	/* C8 Bit Fields */
tushki7	0:60d829a0353a	3154	#define MCG_C8_LOCS1_MASK 0x1u
tushki7	0:60d829a0353a	3155	#define MCG_C8_LOCS1_SHIFT 0
tushki7	0:60d829a0353a	3156	#define MCG_C8_CME1_MASK 0x20u
tushki7	0:60d829a0353a	3157	#define MCG_C8_CME1_SHIFT 5
tushki7	0:60d829a0353a	3158	#define MCG_C8_LOLRE_MASK 0x40u
tushki7	0:60d829a0353a	3159	#define MCG_C8_LOLRE_SHIFT 6
tushki7	0:60d829a0353a	3160	#define MCG_C8_LOCRE1_MASK 0x80u
tushki7	0:60d829a0353a	3161	#define MCG_C8_LOCRE1_SHIFT 7
tushki7	0:60d829a0353a	3162
tushki7	0:60d829a0353a	3163	/**
tushki7	0:60d829a0353a	3164	* @}
tushki7	0:60d829a0353a	3165	/ / end of group MCG_Register_Masks */
tushki7	0:60d829a0353a	3166
tushki7	0:60d829a0353a	3167
tushki7	0:60d829a0353a	3168	/* MCG - Peripheral instance base addresses */
tushki7	0:60d829a0353a	3169	/** Peripheral MCG base address */
tushki7	0:60d829a0353a	3170	#define MCG_BASE (0x40064000u)
tushki7	0:60d829a0353a	3171	/** Peripheral MCG base pointer */
tushki7	0:60d829a0353a	3172	#define MCG ((MCG_Type *)MCG_BASE)
tushki7	0:60d829a0353a	3173
tushki7	0:60d829a0353a	3174	/**
tushki7	0:60d829a0353a	3175	* @}
tushki7	0:60d829a0353a	3176	/ / end of group MCG_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	3177
tushki7	0:60d829a0353a	3178
tushki7	0:60d829a0353a	3179	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3180	-- NV Peripheral Access Layer
tushki7	0:60d829a0353a	3181	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3182
tushki7	0:60d829a0353a	3183	/**
tushki7	0:60d829a0353a	3184	* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
tushki7	0:60d829a0353a	3185	* @{
tushki7	0:60d829a0353a	3186	*/
tushki7	0:60d829a0353a	3187
tushki7	0:60d829a0353a	3188	/** NV - Register Layout Typedef */
tushki7	0:60d829a0353a	3189	typedef struct {
tushki7	0:60d829a0353a	3190	__I uint8_t BACKKEY3; /*< Backdoor Comparison Key 3., offset: 0x0 /
tushki7	0:60d829a0353a	3191	__I uint8_t BACKKEY2; /*< Backdoor Comparison Key 2., offset: 0x1 /
tushki7	0:60d829a0353a	3192	__I uint8_t BACKKEY1; /*< Backdoor Comparison Key 1., offset: 0x2 /
tushki7	0:60d829a0353a	3193	__I uint8_t BACKKEY0; /*< Backdoor Comparison Key 0., offset: 0x3 /
tushki7	0:60d829a0353a	3194	__I uint8_t BACKKEY7; /*< Backdoor Comparison Key 7., offset: 0x4 /
tushki7	0:60d829a0353a	3195	__I uint8_t BACKKEY6; /*< Backdoor Comparison Key 6., offset: 0x5 /
tushki7	0:60d829a0353a	3196	__I uint8_t BACKKEY5; /*< Backdoor Comparison Key 5., offset: 0x6 /
tushki7	0:60d829a0353a	3197	__I uint8_t BACKKEY4; /*< Backdoor Comparison Key 4., offset: 0x7 /
tushki7	0:60d829a0353a	3198	__I uint8_t FPROT3; /*< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 /
tushki7	0:60d829a0353a	3199	__I uint8_t FPROT2; /*< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 /
tushki7	0:60d829a0353a	3200	__I uint8_t FPROT1; /*< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA /
tushki7	0:60d829a0353a	3201	__I uint8_t FPROT0; /*< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB /
tushki7	0:60d829a0353a	3202	__I uint8_t FSEC; /*< Non-volatile Flash Security Register, offset: 0xC /
tushki7	0:60d829a0353a	3203	__I uint8_t FOPT; /*< Non-volatile Flash Option Register, offset: 0xD /
tushki7	0:60d829a0353a	3204	__I uint8_t FEPROT; /*< Non-volatile EERAM Protection Register, offset: 0xE /
tushki7	0:60d829a0353a	3205	__I uint8_t FDPROT; /*< Non-volatile D-Flash Protection Register, offset: 0xF /
tushki7	0:60d829a0353a	3206	} NV_Type;
tushki7	0:60d829a0353a	3207
tushki7	0:60d829a0353a	3208	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3209	-- NV Register Masks
tushki7	0:60d829a0353a	3210	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3211
tushki7	0:60d829a0353a	3212	/**
tushki7	0:60d829a0353a	3213	* @addtogroup NV_Register_Masks NV Register Masks
tushki7	0:60d829a0353a	3214	* @{
tushki7	0:60d829a0353a	3215	*/
tushki7	0:60d829a0353a	3216
tushki7	0:60d829a0353a	3217	/* BACKKEY3 Bit Fields */
tushki7	0:60d829a0353a	3218	#define NV_BACKKEY3_KEY_MASK 0xFFu
tushki7	0:60d829a0353a	3219	#define NV_BACKKEY3_KEY_SHIFT 0
tushki7	0:60d829a0353a	3220	#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
tushki7	0:60d829a0353a	3221	/* BACKKEY2 Bit Fields */
tushki7	0:60d829a0353a	3222	#define NV_BACKKEY2_KEY_MASK 0xFFu
tushki7	0:60d829a0353a	3223	#define NV_BACKKEY2_KEY_SHIFT 0
tushki7	0:60d829a0353a	3224	#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
tushki7	0:60d829a0353a	3225	/* BACKKEY1 Bit Fields */
tushki7	0:60d829a0353a	3226	#define NV_BACKKEY1_KEY_MASK 0xFFu
tushki7	0:60d829a0353a	3227	#define NV_BACKKEY1_KEY_SHIFT 0
tushki7	0:60d829a0353a	3228	#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
tushki7	0:60d829a0353a	3229	/* BACKKEY0 Bit Fields */
tushki7	0:60d829a0353a	3230	#define NV_BACKKEY0_KEY_MASK 0xFFu
tushki7	0:60d829a0353a	3231	#define NV_BACKKEY0_KEY_SHIFT 0
tushki7	0:60d829a0353a	3232	#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
tushki7	0:60d829a0353a	3233	/* BACKKEY7 Bit Fields */
tushki7	0:60d829a0353a	3234	#define NV_BACKKEY7_KEY_MASK 0xFFu
tushki7	0:60d829a0353a	3235	#define NV_BACKKEY7_KEY_SHIFT 0
tushki7	0:60d829a0353a	3236	#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
tushki7	0:60d829a0353a	3237	/* BACKKEY6 Bit Fields */
tushki7	0:60d829a0353a	3238	#define NV_BACKKEY6_KEY_MASK 0xFFu
tushki7	0:60d829a0353a	3239	#define NV_BACKKEY6_KEY_SHIFT 0
tushki7	0:60d829a0353a	3240	#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
tushki7	0:60d829a0353a	3241	/* BACKKEY5 Bit Fields */
tushki7	0:60d829a0353a	3242	#define NV_BACKKEY5_KEY_MASK 0xFFu
tushki7	0:60d829a0353a	3243	#define NV_BACKKEY5_KEY_SHIFT 0
tushki7	0:60d829a0353a	3244	#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
tushki7	0:60d829a0353a	3245	/* BACKKEY4 Bit Fields */
tushki7	0:60d829a0353a	3246	#define NV_BACKKEY4_KEY_MASK 0xFFu
tushki7	0:60d829a0353a	3247	#define NV_BACKKEY4_KEY_SHIFT 0
tushki7	0:60d829a0353a	3248	#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
tushki7	0:60d829a0353a	3249	/* FPROT3 Bit Fields */
tushki7	0:60d829a0353a	3250	#define NV_FPROT3_PROT_MASK 0xFFu
tushki7	0:60d829a0353a	3251	#define NV_FPROT3_PROT_SHIFT 0
tushki7	0:60d829a0353a	3252	#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
tushki7	0:60d829a0353a	3253	/* FPROT2 Bit Fields */
tushki7	0:60d829a0353a	3254	#define NV_FPROT2_PROT_MASK 0xFFu
tushki7	0:60d829a0353a	3255	#define NV_FPROT2_PROT_SHIFT 0
tushki7	0:60d829a0353a	3256	#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
tushki7	0:60d829a0353a	3257	/* FPROT1 Bit Fields */
tushki7	0:60d829a0353a	3258	#define NV_FPROT1_PROT_MASK 0xFFu
tushki7	0:60d829a0353a	3259	#define NV_FPROT1_PROT_SHIFT 0
tushki7	0:60d829a0353a	3260	#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
tushki7	0:60d829a0353a	3261	/* FPROT0 Bit Fields */
tushki7	0:60d829a0353a	3262	#define NV_FPROT0_PROT_MASK 0xFFu
tushki7	0:60d829a0353a	3263	#define NV_FPROT0_PROT_SHIFT 0
tushki7	0:60d829a0353a	3264	#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
tushki7	0:60d829a0353a	3265	/* FSEC Bit Fields */
tushki7	0:60d829a0353a	3266	#define NV_FSEC_SEC_MASK 0x3u
tushki7	0:60d829a0353a	3267	#define NV_FSEC_SEC_SHIFT 0
tushki7	0:60d829a0353a	3268	#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
tushki7	0:60d829a0353a	3269	#define NV_FSEC_FSLACC_MASK 0xCu
tushki7	0:60d829a0353a	3270	#define NV_FSEC_FSLACC_SHIFT 2
tushki7	0:60d829a0353a	3271	#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
tushki7	0:60d829a0353a	3272	#define NV_FSEC_MEEN_MASK 0x30u
tushki7	0:60d829a0353a	3273	#define NV_FSEC_MEEN_SHIFT 4
tushki7	0:60d829a0353a	3274	#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
tushki7	0:60d829a0353a	3275	#define NV_FSEC_KEYEN_MASK 0xC0u
tushki7	0:60d829a0353a	3276	#define NV_FSEC_KEYEN_SHIFT 6
tushki7	0:60d829a0353a	3277	#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
tushki7	0:60d829a0353a	3278	/* FOPT Bit Fields */
tushki7	0:60d829a0353a	3279	#define NV_FOPT_LPBOOT_MASK 0x1u
tushki7	0:60d829a0353a	3280	#define NV_FOPT_LPBOOT_SHIFT 0
tushki7	0:60d829a0353a	3281	#define NV_FOPT_EZPORT_DIS_MASK 0x2u
tushki7	0:60d829a0353a	3282	#define NV_FOPT_EZPORT_DIS_SHIFT 1
tushki7	0:60d829a0353a	3283	/* FEPROT Bit Fields */
tushki7	0:60d829a0353a	3284	#define NV_FEPROT_EPROT_MASK 0xFFu
tushki7	0:60d829a0353a	3285	#define NV_FEPROT_EPROT_SHIFT 0
tushki7	0:60d829a0353a	3286	#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
tushki7	0:60d829a0353a	3287	/* FDPROT Bit Fields */
tushki7	0:60d829a0353a	3288	#define NV_FDPROT_DPROT_MASK 0xFFu
tushki7	0:60d829a0353a	3289	#define NV_FDPROT_DPROT_SHIFT 0
tushki7	0:60d829a0353a	3290	#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
tushki7	0:60d829a0353a	3291
tushki7	0:60d829a0353a	3292	/**
tushki7	0:60d829a0353a	3293	* @}
tushki7	0:60d829a0353a	3294	/ / end of group NV_Register_Masks */
tushki7	0:60d829a0353a	3295
tushki7	0:60d829a0353a	3296
tushki7	0:60d829a0353a	3297	/* NV - Peripheral instance base addresses */
tushki7	0:60d829a0353a	3298	/** Peripheral FTFL_FlashConfig base address */
tushki7	0:60d829a0353a	3299	#define FTFL_FlashConfig_BASE (0x400u)
tushki7	0:60d829a0353a	3300	/** Peripheral FTFL_FlashConfig base pointer */
tushki7	0:60d829a0353a	3301	#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
tushki7	0:60d829a0353a	3302
tushki7	0:60d829a0353a	3303	/**
tushki7	0:60d829a0353a	3304	* @}
tushki7	0:60d829a0353a	3305	/ / end of group NV_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	3306
tushki7	0:60d829a0353a	3307
tushki7	0:60d829a0353a	3308	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3309	-- OSC Peripheral Access Layer
tushki7	0:60d829a0353a	3310	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3311
tushki7	0:60d829a0353a	3312	/**
tushki7	0:60d829a0353a	3313	* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
tushki7	0:60d829a0353a	3314	* @{
tushki7	0:60d829a0353a	3315	*/
tushki7	0:60d829a0353a	3316
tushki7	0:60d829a0353a	3317	/** OSC - Register Layout Typedef */
tushki7	0:60d829a0353a	3318	typedef struct {
tushki7	0:60d829a0353a	3319	__IO uint8_t CR; /*< OSC Control Register, offset: 0x0 /
tushki7	0:60d829a0353a	3320	} OSC_Type;
tushki7	0:60d829a0353a	3321
tushki7	0:60d829a0353a	3322	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3323	-- OSC Register Masks
tushki7	0:60d829a0353a	3324	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3325
tushki7	0:60d829a0353a	3326	/**
tushki7	0:60d829a0353a	3327	* @addtogroup OSC_Register_Masks OSC Register Masks
tushki7	0:60d829a0353a	3328	* @{
tushki7	0:60d829a0353a	3329	*/
tushki7	0:60d829a0353a	3330
tushki7	0:60d829a0353a	3331	/* CR Bit Fields */
tushki7	0:60d829a0353a	3332	#define OSC_CR_SC16P_MASK 0x1u
tushki7	0:60d829a0353a	3333	#define OSC_CR_SC16P_SHIFT 0
tushki7	0:60d829a0353a	3334	#define OSC_CR_SC8P_MASK 0x2u
tushki7	0:60d829a0353a	3335	#define OSC_CR_SC8P_SHIFT 1
tushki7	0:60d829a0353a	3336	#define OSC_CR_SC4P_MASK 0x4u
tushki7	0:60d829a0353a	3337	#define OSC_CR_SC4P_SHIFT 2
tushki7	0:60d829a0353a	3338	#define OSC_CR_SC2P_MASK 0x8u
tushki7	0:60d829a0353a	3339	#define OSC_CR_SC2P_SHIFT 3
tushki7	0:60d829a0353a	3340	#define OSC_CR_EREFSTEN_MASK 0x20u
tushki7	0:60d829a0353a	3341	#define OSC_CR_EREFSTEN_SHIFT 5
tushki7	0:60d829a0353a	3342	#define OSC_CR_ERCLKEN_MASK 0x80u
tushki7	0:60d829a0353a	3343	#define OSC_CR_ERCLKEN_SHIFT 7
tushki7	0:60d829a0353a	3344
tushki7	0:60d829a0353a	3345	/**
tushki7	0:60d829a0353a	3346	* @}
tushki7	0:60d829a0353a	3347	/ / end of group OSC_Register_Masks */
tushki7	0:60d829a0353a	3348
tushki7	0:60d829a0353a	3349
tushki7	0:60d829a0353a	3350	/* OSC - Peripheral instance base addresses */
tushki7	0:60d829a0353a	3351	/** Peripheral OSC0 base address */
tushki7	0:60d829a0353a	3352	#define OSC0_BASE (0x40065000u)
tushki7	0:60d829a0353a	3353	/** Peripheral OSC0 base pointer */
tushki7	0:60d829a0353a	3354	#define OSC0 ((OSC_Type *)OSC0_BASE)
tushki7	0:60d829a0353a	3355
tushki7	0:60d829a0353a	3356	/**
tushki7	0:60d829a0353a	3357	* @}
tushki7	0:60d829a0353a	3358	/ / end of group OSC_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	3359
tushki7	0:60d829a0353a	3360
tushki7	0:60d829a0353a	3361	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3362	-- PDB Peripheral Access Layer
tushki7	0:60d829a0353a	3363	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3364
tushki7	0:60d829a0353a	3365	/**
tushki7	0:60d829a0353a	3366	* @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
tushki7	0:60d829a0353a	3367	* @{
tushki7	0:60d829a0353a	3368	*/
tushki7	0:60d829a0353a	3369
tushki7	0:60d829a0353a	3370	/** PDB - Register Layout Typedef */
tushki7	0:60d829a0353a	3371	typedef struct {
tushki7	0:60d829a0353a	3372	__IO uint32_t SC; /*< Status and Control Register, offset: 0x0 /
tushki7	0:60d829a0353a	3373	__IO uint32_t MOD; /*< Modulus Register, offset: 0x4 /
tushki7	0:60d829a0353a	3374	__I uint32_t CNT; /*< Counter Register, offset: 0x8 /
tushki7	0:60d829a0353a	3375	__IO uint32_t IDLY; /*< Interrupt Delay Register, offset: 0xC /
tushki7	0:60d829a0353a	3376	struct { /* offset: 0x10, array step: 0x10 */
tushki7	0:60d829a0353a	3377	__IO uint32_t C1; /*< Channel n Control Register 1, array offset: 0x10, array step: 0x10 /
tushki7	0:60d829a0353a	3378	__IO uint32_t S; /*< Channel n Status Register, array offset: 0x14, array step: 0x10 /
tushki7	0:60d829a0353a	3379	__IO uint32_t DLY[2]; /*< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index0x10, index20x4 /
tushki7	0:60d829a0353a	3380	} CH[1];
tushki7	0:60d829a0353a	3381	uint8_t RESERVED_0[368];
tushki7	0:60d829a0353a	3382	__IO uint32_t POEN; /*< Pulse-Out n Enable Register, offset: 0x190 /
tushki7	0:60d829a0353a	3383	__IO uint32_t PODLY[2]; /*< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 /
tushki7	0:60d829a0353a	3384	} PDB_Type;
tushki7	0:60d829a0353a	3385
tushki7	0:60d829a0353a	3386	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3387	-- PDB Register Masks
tushki7	0:60d829a0353a	3388	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3389
tushki7	0:60d829a0353a	3390	/**
tushki7	0:60d829a0353a	3391	* @addtogroup PDB_Register_Masks PDB Register Masks
tushki7	0:60d829a0353a	3392	* @{
tushki7	0:60d829a0353a	3393	*/
tushki7	0:60d829a0353a	3394
tushki7	0:60d829a0353a	3395	/* SC Bit Fields */
tushki7	0:60d829a0353a	3396	#define PDB_SC_LDOK_MASK 0x1u
tushki7	0:60d829a0353a	3397	#define PDB_SC_LDOK_SHIFT 0
tushki7	0:60d829a0353a	3398	#define PDB_SC_CONT_MASK 0x2u
tushki7	0:60d829a0353a	3399	#define PDB_SC_CONT_SHIFT 1
tushki7	0:60d829a0353a	3400	#define PDB_SC_MULT_MASK 0xCu
tushki7	0:60d829a0353a	3401	#define PDB_SC_MULT_SHIFT 2
tushki7	0:60d829a0353a	3402	#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
tushki7	0:60d829a0353a	3403	#define PDB_SC_PDBIE_MASK 0x20u
tushki7	0:60d829a0353a	3404	#define PDB_SC_PDBIE_SHIFT 5
tushki7	0:60d829a0353a	3405	#define PDB_SC_PDBIF_MASK 0x40u
tushki7	0:60d829a0353a	3406	#define PDB_SC_PDBIF_SHIFT 6
tushki7	0:60d829a0353a	3407	#define PDB_SC_PDBEN_MASK 0x80u
tushki7	0:60d829a0353a	3408	#define PDB_SC_PDBEN_SHIFT 7
tushki7	0:60d829a0353a	3409	#define PDB_SC_TRGSEL_MASK 0xF00u
tushki7	0:60d829a0353a	3410	#define PDB_SC_TRGSEL_SHIFT 8
tushki7	0:60d829a0353a	3411	#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
tushki7	0:60d829a0353a	3412	#define PDB_SC_PRESCALER_MASK 0x7000u
tushki7	0:60d829a0353a	3413	#define PDB_SC_PRESCALER_SHIFT 12
tushki7	0:60d829a0353a	3414	#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
tushki7	0:60d829a0353a	3415	#define PDB_SC_DMAEN_MASK 0x8000u
tushki7	0:60d829a0353a	3416	#define PDB_SC_DMAEN_SHIFT 15
tushki7	0:60d829a0353a	3417	#define PDB_SC_SWTRIG_MASK 0x10000u
tushki7	0:60d829a0353a	3418	#define PDB_SC_SWTRIG_SHIFT 16
tushki7	0:60d829a0353a	3419	#define PDB_SC_PDBEIE_MASK 0x20000u
tushki7	0:60d829a0353a	3420	#define PDB_SC_PDBEIE_SHIFT 17
tushki7	0:60d829a0353a	3421	#define PDB_SC_LDMOD_MASK 0xC0000u
tushki7	0:60d829a0353a	3422	#define PDB_SC_LDMOD_SHIFT 18
tushki7	0:60d829a0353a	3423	#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
tushki7	0:60d829a0353a	3424	/* MOD Bit Fields */
tushki7	0:60d829a0353a	3425	#define PDB_MOD_MOD_MASK 0xFFFFu
tushki7	0:60d829a0353a	3426	#define PDB_MOD_MOD_SHIFT 0
tushki7	0:60d829a0353a	3427	#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
tushki7	0:60d829a0353a	3428	/* CNT Bit Fields */
tushki7	0:60d829a0353a	3429	#define PDB_CNT_CNT_MASK 0xFFFFu
tushki7	0:60d829a0353a	3430	#define PDB_CNT_CNT_SHIFT 0
tushki7	0:60d829a0353a	3431	#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
tushki7	0:60d829a0353a	3432	/* IDLY Bit Fields */
tushki7	0:60d829a0353a	3433	#define PDB_IDLY_IDLY_MASK 0xFFFFu
tushki7	0:60d829a0353a	3434	#define PDB_IDLY_IDLY_SHIFT 0
tushki7	0:60d829a0353a	3435	#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
tushki7	0:60d829a0353a	3436	/* C1 Bit Fields */
tushki7	0:60d829a0353a	3437	#define PDB_C1_EN_MASK 0xFFu
tushki7	0:60d829a0353a	3438	#define PDB_C1_EN_SHIFT 0
tushki7	0:60d829a0353a	3439	#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
tushki7	0:60d829a0353a	3440	#define PDB_C1_TOS_MASK 0xFF00u
tushki7	0:60d829a0353a	3441	#define PDB_C1_TOS_SHIFT 8
tushki7	0:60d829a0353a	3442	#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
tushki7	0:60d829a0353a	3443	#define PDB_C1_BB_MASK 0xFF0000u
tushki7	0:60d829a0353a	3444	#define PDB_C1_BB_SHIFT 16
tushki7	0:60d829a0353a	3445	#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
tushki7	0:60d829a0353a	3446	/* S Bit Fields */
tushki7	0:60d829a0353a	3447	#define PDB_S_ERR_MASK 0xFFu
tushki7	0:60d829a0353a	3448	#define PDB_S_ERR_SHIFT 0
tushki7	0:60d829a0353a	3449	#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
tushki7	0:60d829a0353a	3450	#define PDB_S_CF_MASK 0xFF0000u
tushki7	0:60d829a0353a	3451	#define PDB_S_CF_SHIFT 16
tushki7	0:60d829a0353a	3452	#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
tushki7	0:60d829a0353a	3453	/* DLY Bit Fields */
tushki7	0:60d829a0353a	3454	#define PDB_DLY_DLY_MASK 0xFFFFu
tushki7	0:60d829a0353a	3455	#define PDB_DLY_DLY_SHIFT 0
tushki7	0:60d829a0353a	3456	#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
tushki7	0:60d829a0353a	3457	/* POEN Bit Fields */
tushki7	0:60d829a0353a	3458	#define PDB_POEN_POEN_MASK 0xFFu
tushki7	0:60d829a0353a	3459	#define PDB_POEN_POEN_SHIFT 0
tushki7	0:60d829a0353a	3460	#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
tushki7	0:60d829a0353a	3461	/* PODLY Bit Fields */
tushki7	0:60d829a0353a	3462	#define PDB_PODLY_DLY2_MASK 0xFFFFu
tushki7	0:60d829a0353a	3463	#define PDB_PODLY_DLY2_SHIFT 0
tushki7	0:60d829a0353a	3464	#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
tushki7	0:60d829a0353a	3465	#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	3466	#define PDB_PODLY_DLY1_SHIFT 16
tushki7	0:60d829a0353a	3467	#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
tushki7	0:60d829a0353a	3468
tushki7	0:60d829a0353a	3469	/**
tushki7	0:60d829a0353a	3470	* @}
tushki7	0:60d829a0353a	3471	/ / end of group PDB_Register_Masks */
tushki7	0:60d829a0353a	3472
tushki7	0:60d829a0353a	3473
tushki7	0:60d829a0353a	3474	/* PDB - Peripheral instance base addresses */
tushki7	0:60d829a0353a	3475	/** Peripheral PDB0 base address */
tushki7	0:60d829a0353a	3476	#define PDB0_BASE (0x40036000u)
tushki7	0:60d829a0353a	3477	/** Peripheral PDB0 base pointer */
tushki7	0:60d829a0353a	3478	#define PDB0 ((PDB_Type *)PDB0_BASE)
tushki7	0:60d829a0353a	3479
tushki7	0:60d829a0353a	3480	/**
tushki7	0:60d829a0353a	3481	* @}
tushki7	0:60d829a0353a	3482	/ / end of group PDB_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	3483
tushki7	0:60d829a0353a	3484
tushki7	0:60d829a0353a	3485	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3486	-- PIT Peripheral Access Layer
tushki7	0:60d829a0353a	3487	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3488
tushki7	0:60d829a0353a	3489	/**
tushki7	0:60d829a0353a	3490	* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
tushki7	0:60d829a0353a	3491	* @{
tushki7	0:60d829a0353a	3492	*/
tushki7	0:60d829a0353a	3493
tushki7	0:60d829a0353a	3494	/** PIT - Register Layout Typedef */
tushki7	0:60d829a0353a	3495	typedef struct {
tushki7	0:60d829a0353a	3496	__IO uint32_t MCR; /*< PIT Module Control Register, offset: 0x0 /
tushki7	0:60d829a0353a	3497	uint8_t RESERVED_0[252];
tushki7	0:60d829a0353a	3498	struct { /* offset: 0x100, array step: 0x10 */
tushki7	0:60d829a0353a	3499	__IO uint32_t LDVAL; /*< Timer Load Value Register, array offset: 0x100, array step: 0x10 /
tushki7	0:60d829a0353a	3500	__I uint32_t CVAL; /*< Current Timer Value Register, array offset: 0x104, array step: 0x10 /
tushki7	0:60d829a0353a	3501	__IO uint32_t TCTRL; /*< Timer Control Register, array offset: 0x108, array step: 0x10 /
tushki7	0:60d829a0353a	3502	__IO uint32_t TFLG; /*< Timer Flag Register, array offset: 0x10C, array step: 0x10 /
tushki7	0:60d829a0353a	3503	} CHANNEL[4];
tushki7	0:60d829a0353a	3504	} PIT_Type;
tushki7	0:60d829a0353a	3505
tushki7	0:60d829a0353a	3506	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3507	-- PIT Register Masks
tushki7	0:60d829a0353a	3508	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3509
tushki7	0:60d829a0353a	3510	/**
tushki7	0:60d829a0353a	3511	* @addtogroup PIT_Register_Masks PIT Register Masks
tushki7	0:60d829a0353a	3512	* @{
tushki7	0:60d829a0353a	3513	*/
tushki7	0:60d829a0353a	3514
tushki7	0:60d829a0353a	3515	/* MCR Bit Fields */
tushki7	0:60d829a0353a	3516	#define PIT_MCR_FRZ_MASK 0x1u
tushki7	0:60d829a0353a	3517	#define PIT_MCR_FRZ_SHIFT 0
tushki7	0:60d829a0353a	3518	#define PIT_MCR_MDIS_MASK 0x2u
tushki7	0:60d829a0353a	3519	#define PIT_MCR_MDIS_SHIFT 1
tushki7	0:60d829a0353a	3520	/* LDVAL Bit Fields */
tushki7	0:60d829a0353a	3521	#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	3522	#define PIT_LDVAL_TSV_SHIFT 0
tushki7	0:60d829a0353a	3523	#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
tushki7	0:60d829a0353a	3524	/* CVAL Bit Fields */
tushki7	0:60d829a0353a	3525	#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	3526	#define PIT_CVAL_TVL_SHIFT 0
tushki7	0:60d829a0353a	3527	#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
tushki7	0:60d829a0353a	3528	/* TCTRL Bit Fields */
tushki7	0:60d829a0353a	3529	#define PIT_TCTRL_TEN_MASK 0x1u
tushki7	0:60d829a0353a	3530	#define PIT_TCTRL_TEN_SHIFT 0
tushki7	0:60d829a0353a	3531	#define PIT_TCTRL_TIE_MASK 0x2u
tushki7	0:60d829a0353a	3532	#define PIT_TCTRL_TIE_SHIFT 1
tushki7	0:60d829a0353a	3533	/* TFLG Bit Fields */
tushki7	0:60d829a0353a	3534	#define PIT_TFLG_TIF_MASK 0x1u
tushki7	0:60d829a0353a	3535	#define PIT_TFLG_TIF_SHIFT 0
tushki7	0:60d829a0353a	3536
tushki7	0:60d829a0353a	3537	/**
tushki7	0:60d829a0353a	3538	* @}
tushki7	0:60d829a0353a	3539	/ / end of group PIT_Register_Masks */
tushki7	0:60d829a0353a	3540
tushki7	0:60d829a0353a	3541
tushki7	0:60d829a0353a	3542	/* PIT - Peripheral instance base addresses */
tushki7	0:60d829a0353a	3543	/** Peripheral PIT base address */
tushki7	0:60d829a0353a	3544	#define PIT_BASE (0x40037000u)
tushki7	0:60d829a0353a	3545	/** Peripheral PIT base pointer */
tushki7	0:60d829a0353a	3546	#define PIT ((PIT_Type *)PIT_BASE)
tushki7	0:60d829a0353a	3547
tushki7	0:60d829a0353a	3548	/**
tushki7	0:60d829a0353a	3549	* @}
tushki7	0:60d829a0353a	3550	/ / end of group PIT_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	3551
tushki7	0:60d829a0353a	3552
tushki7	0:60d829a0353a	3553	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3554	-- PMC Peripheral Access Layer
tushki7	0:60d829a0353a	3555	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3556
tushki7	0:60d829a0353a	3557	/**
tushki7	0:60d829a0353a	3558	* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
tushki7	0:60d829a0353a	3559	* @{
tushki7	0:60d829a0353a	3560	*/
tushki7	0:60d829a0353a	3561
tushki7	0:60d829a0353a	3562	/** PMC - Register Layout Typedef */
tushki7	0:60d829a0353a	3563	typedef struct {
tushki7	0:60d829a0353a	3564	__IO uint8_t LVDSC1; /*< Low Voltage Detect Status and Control 1 Register, offset: 0x0 /
tushki7	0:60d829a0353a	3565	__IO uint8_t LVDSC2; /*< Low Voltage Detect Status and Control 2 Register, offset: 0x1 /
tushki7	0:60d829a0353a	3566	__IO uint8_t REGSC; /*< Regulator Status and Control Register, offset: 0x2 /
tushki7	0:60d829a0353a	3567	} PMC_Type;
tushki7	0:60d829a0353a	3568
tushki7	0:60d829a0353a	3569	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3570	-- PMC Register Masks
tushki7	0:60d829a0353a	3571	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3572
tushki7	0:60d829a0353a	3573	/**
tushki7	0:60d829a0353a	3574	* @addtogroup PMC_Register_Masks PMC Register Masks
tushki7	0:60d829a0353a	3575	* @{
tushki7	0:60d829a0353a	3576	*/
tushki7	0:60d829a0353a	3577
tushki7	0:60d829a0353a	3578	/* LVDSC1 Bit Fields */
tushki7	0:60d829a0353a	3579	#define PMC_LVDSC1_LVDV_MASK 0x3u
tushki7	0:60d829a0353a	3580	#define PMC_LVDSC1_LVDV_SHIFT 0
tushki7	0:60d829a0353a	3581	#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
tushki7	0:60d829a0353a	3582	#define PMC_LVDSC1_LVDRE_MASK 0x10u
tushki7	0:60d829a0353a	3583	#define PMC_LVDSC1_LVDRE_SHIFT 4
tushki7	0:60d829a0353a	3584	#define PMC_LVDSC1_LVDIE_MASK 0x20u
tushki7	0:60d829a0353a	3585	#define PMC_LVDSC1_LVDIE_SHIFT 5
tushki7	0:60d829a0353a	3586	#define PMC_LVDSC1_LVDACK_MASK 0x40u
tushki7	0:60d829a0353a	3587	#define PMC_LVDSC1_LVDACK_SHIFT 6
tushki7	0:60d829a0353a	3588	#define PMC_LVDSC1_LVDF_MASK 0x80u
tushki7	0:60d829a0353a	3589	#define PMC_LVDSC1_LVDF_SHIFT 7
tushki7	0:60d829a0353a	3590	/* LVDSC2 Bit Fields */
tushki7	0:60d829a0353a	3591	#define PMC_LVDSC2_LVWV_MASK 0x3u
tushki7	0:60d829a0353a	3592	#define PMC_LVDSC2_LVWV_SHIFT 0
tushki7	0:60d829a0353a	3593	#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
tushki7	0:60d829a0353a	3594	#define PMC_LVDSC2_LVWIE_MASK 0x20u
tushki7	0:60d829a0353a	3595	#define PMC_LVDSC2_LVWIE_SHIFT 5
tushki7	0:60d829a0353a	3596	#define PMC_LVDSC2_LVWACK_MASK 0x40u
tushki7	0:60d829a0353a	3597	#define PMC_LVDSC2_LVWACK_SHIFT 6
tushki7	0:60d829a0353a	3598	#define PMC_LVDSC2_LVWF_MASK 0x80u
tushki7	0:60d829a0353a	3599	#define PMC_LVDSC2_LVWF_SHIFT 7
tushki7	0:60d829a0353a	3600	/* REGSC Bit Fields */
tushki7	0:60d829a0353a	3601	#define PMC_REGSC_BGBE_MASK 0x1u
tushki7	0:60d829a0353a	3602	#define PMC_REGSC_BGBE_SHIFT 0
tushki7	0:60d829a0353a	3603	#define PMC_REGSC_REGONS_MASK 0x4u
tushki7	0:60d829a0353a	3604	#define PMC_REGSC_REGONS_SHIFT 2
tushki7	0:60d829a0353a	3605	#define PMC_REGSC_ACKISO_MASK 0x8u
tushki7	0:60d829a0353a	3606	#define PMC_REGSC_ACKISO_SHIFT 3
tushki7	0:60d829a0353a	3607
tushki7	0:60d829a0353a	3608	/**
tushki7	0:60d829a0353a	3609	* @}
tushki7	0:60d829a0353a	3610	/ / end of group PMC_Register_Masks */
tushki7	0:60d829a0353a	3611
tushki7	0:60d829a0353a	3612
tushki7	0:60d829a0353a	3613	/* PMC - Peripheral instance base addresses */
tushki7	0:60d829a0353a	3614	/** Peripheral PMC base address */
tushki7	0:60d829a0353a	3615	#define PMC_BASE (0x4007D000u)
tushki7	0:60d829a0353a	3616	/** Peripheral PMC base pointer */
tushki7	0:60d829a0353a	3617	#define PMC ((PMC_Type *)PMC_BASE)
tushki7	0:60d829a0353a	3618
tushki7	0:60d829a0353a	3619	/**
tushki7	0:60d829a0353a	3620	* @}
tushki7	0:60d829a0353a	3621	/ / end of group PMC_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	3622
tushki7	0:60d829a0353a	3623
tushki7	0:60d829a0353a	3624	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3625	-- PORT Peripheral Access Layer
tushki7	0:60d829a0353a	3626	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3627
tushki7	0:60d829a0353a	3628	/**
tushki7	0:60d829a0353a	3629	* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
tushki7	0:60d829a0353a	3630	* @{
tushki7	0:60d829a0353a	3631	*/
tushki7	0:60d829a0353a	3632
tushki7	0:60d829a0353a	3633	/** PORT - Register Layout Typedef */
tushki7	0:60d829a0353a	3634	typedef struct {
tushki7	0:60d829a0353a	3635	__IO uint32_t PCR[32]; /*< Pin Control Register n, array offset: 0x0, array step: 0x4 /
tushki7	0:60d829a0353a	3636	__O uint32_t GPCLR; /*< Global Pin Control Low Register, offset: 0x80 /
tushki7	0:60d829a0353a	3637	__O uint32_t GPCHR; /*< Global Pin Control High Register, offset: 0x84 /
tushki7	0:60d829a0353a	3638	uint8_t RESERVED_0[24];
tushki7	0:60d829a0353a	3639	__IO uint32_t ISFR; /*< Interrupt Status Flag Register, offset: 0xA0 /
tushki7	0:60d829a0353a	3640	uint8_t RESERVED_1[28];
tushki7	0:60d829a0353a	3641	__IO uint32_t DFER; /*< Digital Filter Enable Register, offset: 0xC0 /
tushki7	0:60d829a0353a	3642	__IO uint32_t DFCR; /*< Digital Filter Clock Register, offset: 0xC4 /
tushki7	0:60d829a0353a	3643	__IO uint32_t DFWR; /*< Digital Filter Width Register, offset: 0xC8 /
tushki7	0:60d829a0353a	3644	} PORT_Type;
tushki7	0:60d829a0353a	3645
tushki7	0:60d829a0353a	3646	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3647	-- PORT Register Masks
tushki7	0:60d829a0353a	3648	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3649
tushki7	0:60d829a0353a	3650	/**
tushki7	0:60d829a0353a	3651	* @addtogroup PORT_Register_Masks PORT Register Masks
tushki7	0:60d829a0353a	3652	* @{
tushki7	0:60d829a0353a	3653	*/
tushki7	0:60d829a0353a	3654
tushki7	0:60d829a0353a	3655	/* PCR Bit Fields */
tushki7	0:60d829a0353a	3656	#define PORT_PCR_PS_MASK 0x1u
tushki7	0:60d829a0353a	3657	#define PORT_PCR_PS_SHIFT 0
tushki7	0:60d829a0353a	3658	#define PORT_PCR_PE_MASK 0x2u
tushki7	0:60d829a0353a	3659	#define PORT_PCR_PE_SHIFT 1
tushki7	0:60d829a0353a	3660	#define PORT_PCR_SRE_MASK 0x4u
tushki7	0:60d829a0353a	3661	#define PORT_PCR_SRE_SHIFT 2
tushki7	0:60d829a0353a	3662	#define PORT_PCR_PFE_MASK 0x10u
tushki7	0:60d829a0353a	3663	#define PORT_PCR_PFE_SHIFT 4
tushki7	0:60d829a0353a	3664	#define PORT_PCR_ODE_MASK 0x20u
tushki7	0:60d829a0353a	3665	#define PORT_PCR_ODE_SHIFT 5
tushki7	0:60d829a0353a	3666	#define PORT_PCR_DSE_MASK 0x40u
tushki7	0:60d829a0353a	3667	#define PORT_PCR_DSE_SHIFT 6
tushki7	0:60d829a0353a	3668	#define PORT_PCR_MUX_MASK 0x700u
tushki7	0:60d829a0353a	3669	#define PORT_PCR_MUX_SHIFT 8
tushki7	0:60d829a0353a	3670	#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
tushki7	0:60d829a0353a	3671	#define PORT_PCR_LK_MASK 0x8000u
tushki7	0:60d829a0353a	3672	#define PORT_PCR_LK_SHIFT 15
tushki7	0:60d829a0353a	3673	#define PORT_PCR_IRQC_MASK 0xF0000u
tushki7	0:60d829a0353a	3674	#define PORT_PCR_IRQC_SHIFT 16
tushki7	0:60d829a0353a	3675	#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
tushki7	0:60d829a0353a	3676	#define PORT_PCR_ISF_MASK 0x1000000u
tushki7	0:60d829a0353a	3677	#define PORT_PCR_ISF_SHIFT 24
tushki7	0:60d829a0353a	3678	/* GPCLR Bit Fields */
tushki7	0:60d829a0353a	3679	#define PORT_GPCLR_GPWD_MASK 0xFFFFu
tushki7	0:60d829a0353a	3680	#define PORT_GPCLR_GPWD_SHIFT 0
tushki7	0:60d829a0353a	3681	#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
tushki7	0:60d829a0353a	3682	#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	3683	#define PORT_GPCLR_GPWE_SHIFT 16
tushki7	0:60d829a0353a	3684	#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
tushki7	0:60d829a0353a	3685	/* GPCHR Bit Fields */
tushki7	0:60d829a0353a	3686	#define PORT_GPCHR_GPWD_MASK 0xFFFFu
tushki7	0:60d829a0353a	3687	#define PORT_GPCHR_GPWD_SHIFT 0
tushki7	0:60d829a0353a	3688	#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
tushki7	0:60d829a0353a	3689	#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	3690	#define PORT_GPCHR_GPWE_SHIFT 16
tushki7	0:60d829a0353a	3691	#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
tushki7	0:60d829a0353a	3692	/* ISFR Bit Fields */
tushki7	0:60d829a0353a	3693	#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	3694	#define PORT_ISFR_ISF_SHIFT 0
tushki7	0:60d829a0353a	3695	#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
tushki7	0:60d829a0353a	3696	/* DFER Bit Fields */
tushki7	0:60d829a0353a	3697	#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	3698	#define PORT_DFER_DFE_SHIFT 0
tushki7	0:60d829a0353a	3699	#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
tushki7	0:60d829a0353a	3700	/* DFCR Bit Fields */
tushki7	0:60d829a0353a	3701	#define PORT_DFCR_CS_MASK 0x1u
tushki7	0:60d829a0353a	3702	#define PORT_DFCR_CS_SHIFT 0
tushki7	0:60d829a0353a	3703	/* DFWR Bit Fields */
tushki7	0:60d829a0353a	3704	#define PORT_DFWR_FILT_MASK 0x1Fu
tushki7	0:60d829a0353a	3705	#define PORT_DFWR_FILT_SHIFT 0
tushki7	0:60d829a0353a	3706	#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
tushki7	0:60d829a0353a	3707
tushki7	0:60d829a0353a	3708	/**
tushki7	0:60d829a0353a	3709	* @}
tushki7	0:60d829a0353a	3710	/ / end of group PORT_Register_Masks */
tushki7	0:60d829a0353a	3711
tushki7	0:60d829a0353a	3712
tushki7	0:60d829a0353a	3713	/* PORT - Peripheral instance base addresses */
tushki7	0:60d829a0353a	3714	/** Peripheral PORTA base address */
tushki7	0:60d829a0353a	3715	#define PORTA_BASE (0x40049000u)
tushki7	0:60d829a0353a	3716	/** Peripheral PORTA base pointer */
tushki7	0:60d829a0353a	3717	#define PORTA ((PORT_Type *)PORTA_BASE)
tushki7	0:60d829a0353a	3718	/** Peripheral PORTB base address */
tushki7	0:60d829a0353a	3719	#define PORTB_BASE (0x4004A000u)
tushki7	0:60d829a0353a	3720	/** Peripheral PORTB base pointer */
tushki7	0:60d829a0353a	3721	#define PORTB ((PORT_Type *)PORTB_BASE)
tushki7	0:60d829a0353a	3722	/** Peripheral PORTC base address */
tushki7	0:60d829a0353a	3723	#define PORTC_BASE (0x4004B000u)
tushki7	0:60d829a0353a	3724	/** Peripheral PORTC base pointer */
tushki7	0:60d829a0353a	3725	#define PORTC ((PORT_Type *)PORTC_BASE)
tushki7	0:60d829a0353a	3726	/** Peripheral PORTD base address */
tushki7	0:60d829a0353a	3727	#define PORTD_BASE (0x4004C000u)
tushki7	0:60d829a0353a	3728	/** Peripheral PORTD base pointer */
tushki7	0:60d829a0353a	3729	#define PORTD ((PORT_Type *)PORTD_BASE)
tushki7	0:60d829a0353a	3730	/** Peripheral PORTE base address */
tushki7	0:60d829a0353a	3731	#define PORTE_BASE (0x4004D000u)
tushki7	0:60d829a0353a	3732	/** Peripheral PORTE base pointer */
tushki7	0:60d829a0353a	3733	#define PORTE ((PORT_Type *)PORTE_BASE)
tushki7	0:60d829a0353a	3734
tushki7	0:60d829a0353a	3735	/**
tushki7	0:60d829a0353a	3736	* @}
tushki7	0:60d829a0353a	3737	/ / end of group PORT_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	3738
tushki7	0:60d829a0353a	3739
tushki7	0:60d829a0353a	3740	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3741	-- RCM Peripheral Access Layer
tushki7	0:60d829a0353a	3742	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3743
tushki7	0:60d829a0353a	3744	/**
tushki7	0:60d829a0353a	3745	* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
tushki7	0:60d829a0353a	3746	* @{
tushki7	0:60d829a0353a	3747	*/
tushki7	0:60d829a0353a	3748
tushki7	0:60d829a0353a	3749	/** RCM - Register Layout Typedef */
tushki7	0:60d829a0353a	3750	typedef struct {
tushki7	0:60d829a0353a	3751	__I uint8_t SRS0; /*< System Reset Status Register 0, offset: 0x0 /
tushki7	0:60d829a0353a	3752	__I uint8_t SRS1; /*< System Reset Status Register 1, offset: 0x1 /
tushki7	0:60d829a0353a	3753	uint8_t RESERVED_0[2];
tushki7	0:60d829a0353a	3754	__IO uint8_t RPFC; /*< Reset Pin Filter Control Register, offset: 0x4 /
tushki7	0:60d829a0353a	3755	__IO uint8_t RPFW; /*< Reset Pin Filter Width Register, offset: 0x5 /
tushki7	0:60d829a0353a	3756	uint8_t RESERVED_1[1];
tushki7	0:60d829a0353a	3757	__I uint8_t MR; /*< Mode Register, offset: 0x7 /
tushki7	0:60d829a0353a	3758	} RCM_Type;
tushki7	0:60d829a0353a	3759
tushki7	0:60d829a0353a	3760	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3761	-- RCM Register Masks
tushki7	0:60d829a0353a	3762	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3763
tushki7	0:60d829a0353a	3764	/**
tushki7	0:60d829a0353a	3765	* @addtogroup RCM_Register_Masks RCM Register Masks
tushki7	0:60d829a0353a	3766	* @{
tushki7	0:60d829a0353a	3767	*/
tushki7	0:60d829a0353a	3768
tushki7	0:60d829a0353a	3769	/* SRS0 Bit Fields */
tushki7	0:60d829a0353a	3770	#define RCM_SRS0_WAKEUP_MASK 0x1u
tushki7	0:60d829a0353a	3771	#define RCM_SRS0_WAKEUP_SHIFT 0
tushki7	0:60d829a0353a	3772	#define RCM_SRS0_LVD_MASK 0x2u
tushki7	0:60d829a0353a	3773	#define RCM_SRS0_LVD_SHIFT 1
tushki7	0:60d829a0353a	3774	#define RCM_SRS0_LOC_MASK 0x4u
tushki7	0:60d829a0353a	3775	#define RCM_SRS0_LOC_SHIFT 2
tushki7	0:60d829a0353a	3776	#define RCM_SRS0_LOL_MASK 0x8u
tushki7	0:60d829a0353a	3777	#define RCM_SRS0_LOL_SHIFT 3
tushki7	0:60d829a0353a	3778	#define RCM_SRS0_WDOG_MASK 0x20u
tushki7	0:60d829a0353a	3779	#define RCM_SRS0_WDOG_SHIFT 5
tushki7	0:60d829a0353a	3780	#define RCM_SRS0_PIN_MASK 0x40u
tushki7	0:60d829a0353a	3781	#define RCM_SRS0_PIN_SHIFT 6
tushki7	0:60d829a0353a	3782	#define RCM_SRS0_POR_MASK 0x80u
tushki7	0:60d829a0353a	3783	#define RCM_SRS0_POR_SHIFT 7
tushki7	0:60d829a0353a	3784	/* SRS1 Bit Fields */
tushki7	0:60d829a0353a	3785	#define RCM_SRS1_JTAG_MASK 0x1u
tushki7	0:60d829a0353a	3786	#define RCM_SRS1_JTAG_SHIFT 0
tushki7	0:60d829a0353a	3787	#define RCM_SRS1_LOCKUP_MASK 0x2u
tushki7	0:60d829a0353a	3788	#define RCM_SRS1_LOCKUP_SHIFT 1
tushki7	0:60d829a0353a	3789	#define RCM_SRS1_SW_MASK 0x4u
tushki7	0:60d829a0353a	3790	#define RCM_SRS1_SW_SHIFT 2
tushki7	0:60d829a0353a	3791	#define RCM_SRS1_MDM_AP_MASK 0x8u
tushki7	0:60d829a0353a	3792	#define RCM_SRS1_MDM_AP_SHIFT 3
tushki7	0:60d829a0353a	3793	#define RCM_SRS1_EZPT_MASK 0x10u
tushki7	0:60d829a0353a	3794	#define RCM_SRS1_EZPT_SHIFT 4
tushki7	0:60d829a0353a	3795	#define RCM_SRS1_SACKERR_MASK 0x20u
tushki7	0:60d829a0353a	3796	#define RCM_SRS1_SACKERR_SHIFT 5
tushki7	0:60d829a0353a	3797	/* RPFC Bit Fields */
tushki7	0:60d829a0353a	3798	#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
tushki7	0:60d829a0353a	3799	#define RCM_RPFC_RSTFLTSRW_SHIFT 0
tushki7	0:60d829a0353a	3800	#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
tushki7	0:60d829a0353a	3801	#define RCM_RPFC_RSTFLTSS_MASK 0x4u
tushki7	0:60d829a0353a	3802	#define RCM_RPFC_RSTFLTSS_SHIFT 2
tushki7	0:60d829a0353a	3803	/* RPFW Bit Fields */
tushki7	0:60d829a0353a	3804	#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
tushki7	0:60d829a0353a	3805	#define RCM_RPFW_RSTFLTSEL_SHIFT 0
tushki7	0:60d829a0353a	3806	#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
tushki7	0:60d829a0353a	3807	/* MR Bit Fields */
tushki7	0:60d829a0353a	3808	#define RCM_MR_EZP_MS_MASK 0x2u
tushki7	0:60d829a0353a	3809	#define RCM_MR_EZP_MS_SHIFT 1
tushki7	0:60d829a0353a	3810
tushki7	0:60d829a0353a	3811	/**
tushki7	0:60d829a0353a	3812	* @}
tushki7	0:60d829a0353a	3813	/ / end of group RCM_Register_Masks */
tushki7	0:60d829a0353a	3814
tushki7	0:60d829a0353a	3815
tushki7	0:60d829a0353a	3816	/* RCM - Peripheral instance base addresses */
tushki7	0:60d829a0353a	3817	/** Peripheral RCM base address */
tushki7	0:60d829a0353a	3818	#define RCM_BASE (0x4007F000u)
tushki7	0:60d829a0353a	3819	/** Peripheral RCM base pointer */
tushki7	0:60d829a0353a	3820	#define RCM ((RCM_Type *)RCM_BASE)
tushki7	0:60d829a0353a	3821
tushki7	0:60d829a0353a	3822	/**
tushki7	0:60d829a0353a	3823	* @}
tushki7	0:60d829a0353a	3824	/ / end of group RCM_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	3825
tushki7	0:60d829a0353a	3826
tushki7	0:60d829a0353a	3827	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3828	-- RFSYS Peripheral Access Layer
tushki7	0:60d829a0353a	3829	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3830
tushki7	0:60d829a0353a	3831	/**
tushki7	0:60d829a0353a	3832	* @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
tushki7	0:60d829a0353a	3833	* @{
tushki7	0:60d829a0353a	3834	*/
tushki7	0:60d829a0353a	3835
tushki7	0:60d829a0353a	3836	/** RFSYS - Register Layout Typedef */
tushki7	0:60d829a0353a	3837	typedef struct {
tushki7	0:60d829a0353a	3838	__IO uint32_t REG[8]; /*< Register file register, array offset: 0x0, array step: 0x4 /
tushki7	0:60d829a0353a	3839	} RFSYS_Type;
tushki7	0:60d829a0353a	3840
tushki7	0:60d829a0353a	3841	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3842	-- RFSYS Register Masks
tushki7	0:60d829a0353a	3843	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3844
tushki7	0:60d829a0353a	3845	/**
tushki7	0:60d829a0353a	3846	* @addtogroup RFSYS_Register_Masks RFSYS Register Masks
tushki7	0:60d829a0353a	3847	* @{
tushki7	0:60d829a0353a	3848	*/
tushki7	0:60d829a0353a	3849
tushki7	0:60d829a0353a	3850	/* REG Bit Fields */
tushki7	0:60d829a0353a	3851	#define RFSYS_REG_LL_MASK 0xFFu
tushki7	0:60d829a0353a	3852	#define RFSYS_REG_LL_SHIFT 0
tushki7	0:60d829a0353a	3853	#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
tushki7	0:60d829a0353a	3854	#define RFSYS_REG_LH_MASK 0xFF00u
tushki7	0:60d829a0353a	3855	#define RFSYS_REG_LH_SHIFT 8
tushki7	0:60d829a0353a	3856	#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
tushki7	0:60d829a0353a	3857	#define RFSYS_REG_HL_MASK 0xFF0000u
tushki7	0:60d829a0353a	3858	#define RFSYS_REG_HL_SHIFT 16
tushki7	0:60d829a0353a	3859	#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
tushki7	0:60d829a0353a	3860	#define RFSYS_REG_HH_MASK 0xFF000000u
tushki7	0:60d829a0353a	3861	#define RFSYS_REG_HH_SHIFT 24
tushki7	0:60d829a0353a	3862	#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
tushki7	0:60d829a0353a	3863
tushki7	0:60d829a0353a	3864	/**
tushki7	0:60d829a0353a	3865	* @}
tushki7	0:60d829a0353a	3866	/ / end of group RFSYS_Register_Masks */
tushki7	0:60d829a0353a	3867
tushki7	0:60d829a0353a	3868
tushki7	0:60d829a0353a	3869	/* RFSYS - Peripheral instance base addresses */
tushki7	0:60d829a0353a	3870	/** Peripheral RFSYS base address */
tushki7	0:60d829a0353a	3871	#define RFSYS_BASE (0x40041000u)
tushki7	0:60d829a0353a	3872	/** Peripheral RFSYS base pointer */
tushki7	0:60d829a0353a	3873	#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
tushki7	0:60d829a0353a	3874
tushki7	0:60d829a0353a	3875	/**
tushki7	0:60d829a0353a	3876	* @}
tushki7	0:60d829a0353a	3877	/ / end of group RFSYS_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	3878
tushki7	0:60d829a0353a	3879
tushki7	0:60d829a0353a	3880	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3881	-- RFVBAT Peripheral Access Layer
tushki7	0:60d829a0353a	3882	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3883
tushki7	0:60d829a0353a	3884	/**
tushki7	0:60d829a0353a	3885	* @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
tushki7	0:60d829a0353a	3886	* @{
tushki7	0:60d829a0353a	3887	*/
tushki7	0:60d829a0353a	3888
tushki7	0:60d829a0353a	3889	/** RFVBAT - Register Layout Typedef */
tushki7	0:60d829a0353a	3890	typedef struct {
tushki7	0:60d829a0353a	3891	__IO uint32_t REG[8]; /*< VBAT register file register, array offset: 0x0, array step: 0x4 /
tushki7	0:60d829a0353a	3892	} RFVBAT_Type;
tushki7	0:60d829a0353a	3893
tushki7	0:60d829a0353a	3894	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3895	-- RFVBAT Register Masks
tushki7	0:60d829a0353a	3896	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3897
tushki7	0:60d829a0353a	3898	/**
tushki7	0:60d829a0353a	3899	* @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
tushki7	0:60d829a0353a	3900	* @{
tushki7	0:60d829a0353a	3901	*/
tushki7	0:60d829a0353a	3902
tushki7	0:60d829a0353a	3903	/* REG Bit Fields */
tushki7	0:60d829a0353a	3904	#define RFVBAT_REG_LL_MASK 0xFFu
tushki7	0:60d829a0353a	3905	#define RFVBAT_REG_LL_SHIFT 0
tushki7	0:60d829a0353a	3906	#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
tushki7	0:60d829a0353a	3907	#define RFVBAT_REG_LH_MASK 0xFF00u
tushki7	0:60d829a0353a	3908	#define RFVBAT_REG_LH_SHIFT 8
tushki7	0:60d829a0353a	3909	#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
tushki7	0:60d829a0353a	3910	#define RFVBAT_REG_HL_MASK 0xFF0000u
tushki7	0:60d829a0353a	3911	#define RFVBAT_REG_HL_SHIFT 16
tushki7	0:60d829a0353a	3912	#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
tushki7	0:60d829a0353a	3913	#define RFVBAT_REG_HH_MASK 0xFF000000u
tushki7	0:60d829a0353a	3914	#define RFVBAT_REG_HH_SHIFT 24
tushki7	0:60d829a0353a	3915	#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
tushki7	0:60d829a0353a	3916
tushki7	0:60d829a0353a	3917	/**
tushki7	0:60d829a0353a	3918	* @}
tushki7	0:60d829a0353a	3919	/ / end of group RFVBAT_Register_Masks */
tushki7	0:60d829a0353a	3920
tushki7	0:60d829a0353a	3921
tushki7	0:60d829a0353a	3922	/* RFVBAT - Peripheral instance base addresses */
tushki7	0:60d829a0353a	3923	/** Peripheral RFVBAT base address */
tushki7	0:60d829a0353a	3924	#define RFVBAT_BASE (0x4003E000u)
tushki7	0:60d829a0353a	3925	/** Peripheral RFVBAT base pointer */
tushki7	0:60d829a0353a	3926	#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
tushki7	0:60d829a0353a	3927
tushki7	0:60d829a0353a	3928	/**
tushki7	0:60d829a0353a	3929	* @}
tushki7	0:60d829a0353a	3930	/ / end of group RFVBAT_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	3931
tushki7	0:60d829a0353a	3932
tushki7	0:60d829a0353a	3933	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3934	-- RTC Peripheral Access Layer
tushki7	0:60d829a0353a	3935	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3936
tushki7	0:60d829a0353a	3937	/**
tushki7	0:60d829a0353a	3938	* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
tushki7	0:60d829a0353a	3939	* @{
tushki7	0:60d829a0353a	3940	*/
tushki7	0:60d829a0353a	3941
tushki7	0:60d829a0353a	3942	/** RTC - Register Layout Typedef */
tushki7	0:60d829a0353a	3943	typedef struct {
tushki7	0:60d829a0353a	3944	__IO uint32_t TSR; /*< RTC Time Seconds Register, offset: 0x0 /
tushki7	0:60d829a0353a	3945	__IO uint32_t TPR; /*< RTC Time Prescaler Register, offset: 0x4 /
tushki7	0:60d829a0353a	3946	__IO uint32_t TAR; /*< RTC Time Alarm Register, offset: 0x8 /
tushki7	0:60d829a0353a	3947	__IO uint32_t TCR; /*< RTC Time Compensation Register, offset: 0xC /
tushki7	0:60d829a0353a	3948	__IO uint32_t CR; /*< RTC Control Register, offset: 0x10 /
tushki7	0:60d829a0353a	3949	__IO uint32_t SR; /*< RTC Status Register, offset: 0x14 /
tushki7	0:60d829a0353a	3950	__IO uint32_t LR; /*< RTC Lock Register, offset: 0x18 /
tushki7	0:60d829a0353a	3951	__IO uint32_t IER; /*< RTC Interrupt Enable Register, offset: 0x1C /
tushki7	0:60d829a0353a	3952	uint8_t RESERVED_0[2016];
tushki7	0:60d829a0353a	3953	__IO uint32_t WAR; /*< RTC Write Access Register, offset: 0x800 /
tushki7	0:60d829a0353a	3954	__IO uint32_t RAR; /*< RTC Read Access Register, offset: 0x804 /
tushki7	0:60d829a0353a	3955	} RTC_Type;
tushki7	0:60d829a0353a	3956
tushki7	0:60d829a0353a	3957	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	3958	-- RTC Register Masks
tushki7	0:60d829a0353a	3959	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	3960
tushki7	0:60d829a0353a	3961	/**
tushki7	0:60d829a0353a	3962	* @addtogroup RTC_Register_Masks RTC Register Masks
tushki7	0:60d829a0353a	3963	* @{
tushki7	0:60d829a0353a	3964	*/
tushki7	0:60d829a0353a	3965
tushki7	0:60d829a0353a	3966	/* TSR Bit Fields */
tushki7	0:60d829a0353a	3967	#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	3968	#define RTC_TSR_TSR_SHIFT 0
tushki7	0:60d829a0353a	3969	#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
tushki7	0:60d829a0353a	3970	/* TPR Bit Fields */
tushki7	0:60d829a0353a	3971	#define RTC_TPR_TPR_MASK 0xFFFFu
tushki7	0:60d829a0353a	3972	#define RTC_TPR_TPR_SHIFT 0
tushki7	0:60d829a0353a	3973	#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
tushki7	0:60d829a0353a	3974	/* TAR Bit Fields */
tushki7	0:60d829a0353a	3975	#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	3976	#define RTC_TAR_TAR_SHIFT 0
tushki7	0:60d829a0353a	3977	#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
tushki7	0:60d829a0353a	3978	/* TCR Bit Fields */
tushki7	0:60d829a0353a	3979	#define RTC_TCR_TCR_MASK 0xFFu
tushki7	0:60d829a0353a	3980	#define RTC_TCR_TCR_SHIFT 0
tushki7	0:60d829a0353a	3981	#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
tushki7	0:60d829a0353a	3982	#define RTC_TCR_CIR_MASK 0xFF00u
tushki7	0:60d829a0353a	3983	#define RTC_TCR_CIR_SHIFT 8
tushki7	0:60d829a0353a	3984	#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
tushki7	0:60d829a0353a	3985	#define RTC_TCR_TCV_MASK 0xFF0000u
tushki7	0:60d829a0353a	3986	#define RTC_TCR_TCV_SHIFT 16
tushki7	0:60d829a0353a	3987	#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
tushki7	0:60d829a0353a	3988	#define RTC_TCR_CIC_MASK 0xFF000000u
tushki7	0:60d829a0353a	3989	#define RTC_TCR_CIC_SHIFT 24
tushki7	0:60d829a0353a	3990	#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
tushki7	0:60d829a0353a	3991	/* CR Bit Fields */
tushki7	0:60d829a0353a	3992	#define RTC_CR_SWR_MASK 0x1u
tushki7	0:60d829a0353a	3993	#define RTC_CR_SWR_SHIFT 0
tushki7	0:60d829a0353a	3994	#define RTC_CR_WPE_MASK 0x2u
tushki7	0:60d829a0353a	3995	#define RTC_CR_WPE_SHIFT 1
tushki7	0:60d829a0353a	3996	#define RTC_CR_SUP_MASK 0x4u
tushki7	0:60d829a0353a	3997	#define RTC_CR_SUP_SHIFT 2
tushki7	0:60d829a0353a	3998	#define RTC_CR_UM_MASK 0x8u
tushki7	0:60d829a0353a	3999	#define RTC_CR_UM_SHIFT 3
tushki7	0:60d829a0353a	4000	#define RTC_CR_OSCE_MASK 0x100u
tushki7	0:60d829a0353a	4001	#define RTC_CR_OSCE_SHIFT 8
tushki7	0:60d829a0353a	4002	#define RTC_CR_CLKO_MASK 0x200u
tushki7	0:60d829a0353a	4003	#define RTC_CR_CLKO_SHIFT 9
tushki7	0:60d829a0353a	4004	#define RTC_CR_SC16P_MASK 0x400u
tushki7	0:60d829a0353a	4005	#define RTC_CR_SC16P_SHIFT 10
tushki7	0:60d829a0353a	4006	#define RTC_CR_SC8P_MASK 0x800u
tushki7	0:60d829a0353a	4007	#define RTC_CR_SC8P_SHIFT 11
tushki7	0:60d829a0353a	4008	#define RTC_CR_SC4P_MASK 0x1000u
tushki7	0:60d829a0353a	4009	#define RTC_CR_SC4P_SHIFT 12
tushki7	0:60d829a0353a	4010	#define RTC_CR_SC2P_MASK 0x2000u
tushki7	0:60d829a0353a	4011	#define RTC_CR_SC2P_SHIFT 13
tushki7	0:60d829a0353a	4012	/* SR Bit Fields */
tushki7	0:60d829a0353a	4013	#define RTC_SR_TIF_MASK 0x1u
tushki7	0:60d829a0353a	4014	#define RTC_SR_TIF_SHIFT 0
tushki7	0:60d829a0353a	4015	#define RTC_SR_TOF_MASK 0x2u
tushki7	0:60d829a0353a	4016	#define RTC_SR_TOF_SHIFT 1
tushki7	0:60d829a0353a	4017	#define RTC_SR_TAF_MASK 0x4u
tushki7	0:60d829a0353a	4018	#define RTC_SR_TAF_SHIFT 2
tushki7	0:60d829a0353a	4019	#define RTC_SR_TCE_MASK 0x10u
tushki7	0:60d829a0353a	4020	#define RTC_SR_TCE_SHIFT 4
tushki7	0:60d829a0353a	4021	/* LR Bit Fields */
tushki7	0:60d829a0353a	4022	#define RTC_LR_TCL_MASK 0x8u
tushki7	0:60d829a0353a	4023	#define RTC_LR_TCL_SHIFT 3
tushki7	0:60d829a0353a	4024	#define RTC_LR_CRL_MASK 0x10u
tushki7	0:60d829a0353a	4025	#define RTC_LR_CRL_SHIFT 4
tushki7	0:60d829a0353a	4026	#define RTC_LR_SRL_MASK 0x20u
tushki7	0:60d829a0353a	4027	#define RTC_LR_SRL_SHIFT 5
tushki7	0:60d829a0353a	4028	#define RTC_LR_LRL_MASK 0x40u
tushki7	0:60d829a0353a	4029	#define RTC_LR_LRL_SHIFT 6
tushki7	0:60d829a0353a	4030	/* IER Bit Fields */
tushki7	0:60d829a0353a	4031	#define RTC_IER_TIIE_MASK 0x1u
tushki7	0:60d829a0353a	4032	#define RTC_IER_TIIE_SHIFT 0
tushki7	0:60d829a0353a	4033	#define RTC_IER_TOIE_MASK 0x2u
tushki7	0:60d829a0353a	4034	#define RTC_IER_TOIE_SHIFT 1
tushki7	0:60d829a0353a	4035	#define RTC_IER_TAIE_MASK 0x4u
tushki7	0:60d829a0353a	4036	#define RTC_IER_TAIE_SHIFT 2
tushki7	0:60d829a0353a	4037	#define RTC_IER_TSIE_MASK 0x10u
tushki7	0:60d829a0353a	4038	#define RTC_IER_TSIE_SHIFT 4
tushki7	0:60d829a0353a	4039	/* WAR Bit Fields */
tushki7	0:60d829a0353a	4040	#define RTC_WAR_TSRW_MASK 0x1u
tushki7	0:60d829a0353a	4041	#define RTC_WAR_TSRW_SHIFT 0
tushki7	0:60d829a0353a	4042	#define RTC_WAR_TPRW_MASK 0x2u
tushki7	0:60d829a0353a	4043	#define RTC_WAR_TPRW_SHIFT 1
tushki7	0:60d829a0353a	4044	#define RTC_WAR_TARW_MASK 0x4u
tushki7	0:60d829a0353a	4045	#define RTC_WAR_TARW_SHIFT 2
tushki7	0:60d829a0353a	4046	#define RTC_WAR_TCRW_MASK 0x8u
tushki7	0:60d829a0353a	4047	#define RTC_WAR_TCRW_SHIFT 3
tushki7	0:60d829a0353a	4048	#define RTC_WAR_CRW_MASK 0x10u
tushki7	0:60d829a0353a	4049	#define RTC_WAR_CRW_SHIFT 4
tushki7	0:60d829a0353a	4050	#define RTC_WAR_SRW_MASK 0x20u
tushki7	0:60d829a0353a	4051	#define RTC_WAR_SRW_SHIFT 5
tushki7	0:60d829a0353a	4052	#define RTC_WAR_LRW_MASK 0x40u
tushki7	0:60d829a0353a	4053	#define RTC_WAR_LRW_SHIFT 6
tushki7	0:60d829a0353a	4054	#define RTC_WAR_IERW_MASK 0x80u
tushki7	0:60d829a0353a	4055	#define RTC_WAR_IERW_SHIFT 7
tushki7	0:60d829a0353a	4056	/* RAR Bit Fields */
tushki7	0:60d829a0353a	4057	#define RTC_RAR_TSRR_MASK 0x1u
tushki7	0:60d829a0353a	4058	#define RTC_RAR_TSRR_SHIFT 0
tushki7	0:60d829a0353a	4059	#define RTC_RAR_TPRR_MASK 0x2u
tushki7	0:60d829a0353a	4060	#define RTC_RAR_TPRR_SHIFT 1
tushki7	0:60d829a0353a	4061	#define RTC_RAR_TARR_MASK 0x4u
tushki7	0:60d829a0353a	4062	#define RTC_RAR_TARR_SHIFT 2
tushki7	0:60d829a0353a	4063	#define RTC_RAR_TCRR_MASK 0x8u
tushki7	0:60d829a0353a	4064	#define RTC_RAR_TCRR_SHIFT 3
tushki7	0:60d829a0353a	4065	#define RTC_RAR_CRR_MASK 0x10u
tushki7	0:60d829a0353a	4066	#define RTC_RAR_CRR_SHIFT 4
tushki7	0:60d829a0353a	4067	#define RTC_RAR_SRR_MASK 0x20u
tushki7	0:60d829a0353a	4068	#define RTC_RAR_SRR_SHIFT 5
tushki7	0:60d829a0353a	4069	#define RTC_RAR_LRR_MASK 0x40u
tushki7	0:60d829a0353a	4070	#define RTC_RAR_LRR_SHIFT 6
tushki7	0:60d829a0353a	4071	#define RTC_RAR_IERR_MASK 0x80u
tushki7	0:60d829a0353a	4072	#define RTC_RAR_IERR_SHIFT 7
tushki7	0:60d829a0353a	4073
tushki7	0:60d829a0353a	4074	/**
tushki7	0:60d829a0353a	4075	* @}
tushki7	0:60d829a0353a	4076	/ / end of group RTC_Register_Masks */
tushki7	0:60d829a0353a	4077
tushki7	0:60d829a0353a	4078
tushki7	0:60d829a0353a	4079	/* RTC - Peripheral instance base addresses */
tushki7	0:60d829a0353a	4080	/** Peripheral RTC base address */
tushki7	0:60d829a0353a	4081	#define RTC_BASE (0x4003D000u)
tushki7	0:60d829a0353a	4082	/** Peripheral RTC base pointer */
tushki7	0:60d829a0353a	4083	#define RTC ((RTC_Type *)RTC_BASE)
tushki7	0:60d829a0353a	4084
tushki7	0:60d829a0353a	4085	/**
tushki7	0:60d829a0353a	4086	* @}
tushki7	0:60d829a0353a	4087	/ / end of group RTC_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	4088
tushki7	0:60d829a0353a	4089
tushki7	0:60d829a0353a	4090	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	4091	-- SIM Peripheral Access Layer
tushki7	0:60d829a0353a	4092	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	4093
tushki7	0:60d829a0353a	4094	/**
tushki7	0:60d829a0353a	4095	* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
tushki7	0:60d829a0353a	4096	* @{
tushki7	0:60d829a0353a	4097	*/
tushki7	0:60d829a0353a	4098
tushki7	0:60d829a0353a	4099	/** SIM - Register Layout Typedef */
tushki7	0:60d829a0353a	4100	typedef struct {
tushki7	0:60d829a0353a	4101	__IO uint32_t SOPT1; /*< System Options Register 1, offset: 0x0 /
tushki7	0:60d829a0353a	4102	__IO uint32_t SOPT1CFG; /*< SOPT1 Configuration Register, offset: 0x4 /
tushki7	0:60d829a0353a	4103	uint8_t RESERVED_0[4092];
tushki7	0:60d829a0353a	4104	__IO uint32_t SOPT2; /*< System Options Register 2, offset: 0x1004 /
tushki7	0:60d829a0353a	4105	uint8_t RESERVED_1[4];
tushki7	0:60d829a0353a	4106	__IO uint32_t SOPT4; /*< System Options Register 4, offset: 0x100C /
tushki7	0:60d829a0353a	4107	__IO uint32_t SOPT5; /*< System Options Register 5, offset: 0x1010 /
tushki7	0:60d829a0353a	4108	uint8_t RESERVED_2[4];
tushki7	0:60d829a0353a	4109	__IO uint32_t SOPT7; /*< System Options Register 7, offset: 0x1018 /
tushki7	0:60d829a0353a	4110	uint8_t RESERVED_3[8];
tushki7	0:60d829a0353a	4111	__I uint32_t SDID; /*< System Device Identification Register, offset: 0x1024 /
tushki7	0:60d829a0353a	4112	__IO uint32_t SCGC1; /*< System Clock Gating Control Register 1, offset: 0x1028 /
tushki7	0:60d829a0353a	4113	__IO uint32_t SCGC2; /*< System Clock Gating Control Register 2, offset: 0x102C /
tushki7	0:60d829a0353a	4114	__IO uint32_t SCGC3; /*< System Clock Gating Control Register 3, offset: 0x1030 /
tushki7	0:60d829a0353a	4115	__IO uint32_t SCGC4; /*< System Clock Gating Control Register 4, offset: 0x1034 /
tushki7	0:60d829a0353a	4116	__IO uint32_t SCGC5; /*< System Clock Gating Control Register 5, offset: 0x1038 /
tushki7	0:60d829a0353a	4117	__IO uint32_t SCGC6; /*< System Clock Gating Control Register 6, offset: 0x103C /
tushki7	0:60d829a0353a	4118	__IO uint32_t SCGC7; /*< System Clock Gating Control Register 7, offset: 0x1040 /
tushki7	0:60d829a0353a	4119	__IO uint32_t CLKDIV1; /*< System Clock Divider Register 1, offset: 0x1044 /
tushki7	0:60d829a0353a	4120	__IO uint32_t CLKDIV2; /*< System Clock Divider Register 2, offset: 0x1048 /
tushki7	0:60d829a0353a	4121	__IO uint32_t FCFG1; /*< Flash Configuration Register 1, offset: 0x104C /
tushki7	0:60d829a0353a	4122	__I uint32_t FCFG2; /*< Flash Configuration Register 2, offset: 0x1050 /
tushki7	0:60d829a0353a	4123	__I uint32_t UIDH; /*< Unique Identification Register High, offset: 0x1054 /
tushki7	0:60d829a0353a	4124	__I uint32_t UIDMH; /*< Unique Identification Register Mid-High, offset: 0x1058 /
tushki7	0:60d829a0353a	4125	__I uint32_t UIDML; /*< Unique Identification Register Mid Low, offset: 0x105C /
tushki7	0:60d829a0353a	4126	__I uint32_t UIDL; /*< Unique Identification Register Low, offset: 0x1060 /
tushki7	0:60d829a0353a	4127	} SIM_Type;
tushki7	0:60d829a0353a	4128
tushki7	0:60d829a0353a	4129	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	4130	-- SIM Register Masks
tushki7	0:60d829a0353a	4131	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	4132
tushki7	0:60d829a0353a	4133	/**
tushki7	0:60d829a0353a	4134	* @addtogroup SIM_Register_Masks SIM Register Masks
tushki7	0:60d829a0353a	4135	* @{
tushki7	0:60d829a0353a	4136	*/
tushki7	0:60d829a0353a	4137
tushki7	0:60d829a0353a	4138	/* SOPT1 Bit Fields */
tushki7	0:60d829a0353a	4139	#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
tushki7	0:60d829a0353a	4140	#define SIM_SOPT1_RAMSIZE_SHIFT 12
tushki7	0:60d829a0353a	4141	#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
tushki7	0:60d829a0353a	4142	#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
tushki7	0:60d829a0353a	4143	#define SIM_SOPT1_OSC32KSEL_SHIFT 18
tushki7	0:60d829a0353a	4144	#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
tushki7	0:60d829a0353a	4145	#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
tushki7	0:60d829a0353a	4146	#define SIM_SOPT1_USBVSTBY_SHIFT 29
tushki7	0:60d829a0353a	4147	#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
tushki7	0:60d829a0353a	4148	#define SIM_SOPT1_USBSSTBY_SHIFT 30
tushki7	0:60d829a0353a	4149	#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
tushki7	0:60d829a0353a	4150	#define SIM_SOPT1_USBREGEN_SHIFT 31
tushki7	0:60d829a0353a	4151	/* SOPT1CFG Bit Fields */
tushki7	0:60d829a0353a	4152	#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
tushki7	0:60d829a0353a	4153	#define SIM_SOPT1CFG_URWE_SHIFT 24
tushki7	0:60d829a0353a	4154	#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
tushki7	0:60d829a0353a	4155	#define SIM_SOPT1CFG_UVSWE_SHIFT 25
tushki7	0:60d829a0353a	4156	#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
tushki7	0:60d829a0353a	4157	#define SIM_SOPT1CFG_USSWE_SHIFT 26
tushki7	0:60d829a0353a	4158	/* SOPT2 Bit Fields */
tushki7	0:60d829a0353a	4159	#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
tushki7	0:60d829a0353a	4160	#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
tushki7	0:60d829a0353a	4161	#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
tushki7	0:60d829a0353a	4162	#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
tushki7	0:60d829a0353a	4163	#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
tushki7	0:60d829a0353a	4164	#define SIM_SOPT2_PTD7PAD_MASK 0x800u
tushki7	0:60d829a0353a	4165	#define SIM_SOPT2_PTD7PAD_SHIFT 11
tushki7	0:60d829a0353a	4166	#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
tushki7	0:60d829a0353a	4167	#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
tushki7	0:60d829a0353a	4168	#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
tushki7	0:60d829a0353a	4169	#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
tushki7	0:60d829a0353a	4170	#define SIM_SOPT2_USBSRC_MASK 0x40000u
tushki7	0:60d829a0353a	4171	#define SIM_SOPT2_USBSRC_SHIFT 18
tushki7	0:60d829a0353a	4172	/* SOPT4 Bit Fields */
tushki7	0:60d829a0353a	4173	#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
tushki7	0:60d829a0353a	4174	#define SIM_SOPT4_FTM0FLT0_SHIFT 0
tushki7	0:60d829a0353a	4175	#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
tushki7	0:60d829a0353a	4176	#define SIM_SOPT4_FTM0FLT1_SHIFT 1
tushki7	0:60d829a0353a	4177	#define SIM_SOPT4_FTM0FLT2_MASK 0x4u
tushki7	0:60d829a0353a	4178	#define SIM_SOPT4_FTM0FLT2_SHIFT 2
tushki7	0:60d829a0353a	4179	#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
tushki7	0:60d829a0353a	4180	#define SIM_SOPT4_FTM1FLT0_SHIFT 4
tushki7	0:60d829a0353a	4181	#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
tushki7	0:60d829a0353a	4182	#define SIM_SOPT4_FTM2FLT0_SHIFT 8
tushki7	0:60d829a0353a	4183	#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
tushki7	0:60d829a0353a	4184	#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
tushki7	0:60d829a0353a	4185	#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
tushki7	0:60d829a0353a	4186	#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
tushki7	0:60d829a0353a	4187	#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
tushki7	0:60d829a0353a	4188	#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
tushki7	0:60d829a0353a	4189	#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
tushki7	0:60d829a0353a	4190	#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
tushki7	0:60d829a0353a	4191	#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
tushki7	0:60d829a0353a	4192	#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
tushki7	0:60d829a0353a	4193	#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
tushki7	0:60d829a0353a	4194	#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
tushki7	0:60d829a0353a	4195	#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
tushki7	0:60d829a0353a	4196	#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
tushki7	0:60d829a0353a	4197	#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
tushki7	0:60d829a0353a	4198	#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
tushki7	0:60d829a0353a	4199	/* SOPT5 Bit Fields */
tushki7	0:60d829a0353a	4200	#define SIM_SOPT5_UART0TXSRC_MASK 0x1u
tushki7	0:60d829a0353a	4201	#define SIM_SOPT5_UART0TXSRC_SHIFT 0
tushki7	0:60d829a0353a	4202	#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
tushki7	0:60d829a0353a	4203	#define SIM_SOPT5_UART0RXSRC_SHIFT 2
tushki7	0:60d829a0353a	4204	#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
tushki7	0:60d829a0353a	4205	#define SIM_SOPT5_UART1TXSRC_MASK 0x10u
tushki7	0:60d829a0353a	4206	#define SIM_SOPT5_UART1TXSRC_SHIFT 4
tushki7	0:60d829a0353a	4207	#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
tushki7	0:60d829a0353a	4208	#define SIM_SOPT5_UART1RXSRC_SHIFT 6
tushki7	0:60d829a0353a	4209	#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
tushki7	0:60d829a0353a	4210	/* SOPT7 Bit Fields */
tushki7	0:60d829a0353a	4211	#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
tushki7	0:60d829a0353a	4212	#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
tushki7	0:60d829a0353a	4213	#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
tushki7	0:60d829a0353a	4214	#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
tushki7	0:60d829a0353a	4215	#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
tushki7	0:60d829a0353a	4216	#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
tushki7	0:60d829a0353a	4217	#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
tushki7	0:60d829a0353a	4218	#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
tushki7	0:60d829a0353a	4219	#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
tushki7	0:60d829a0353a	4220	#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
tushki7	0:60d829a0353a	4221	#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
tushki7	0:60d829a0353a	4222	#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
tushki7	0:60d829a0353a	4223	#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
tushki7	0:60d829a0353a	4224	#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
tushki7	0:60d829a0353a	4225	/* SDID Bit Fields */
tushki7	0:60d829a0353a	4226	#define SIM_SDID_PINID_MASK 0xFu
tushki7	0:60d829a0353a	4227	#define SIM_SDID_PINID_SHIFT 0
tushki7	0:60d829a0353a	4228	#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
tushki7	0:60d829a0353a	4229	#define SIM_SDID_FAMID_MASK 0x70u
tushki7	0:60d829a0353a	4230	#define SIM_SDID_FAMID_SHIFT 4
tushki7	0:60d829a0353a	4231	#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
tushki7	0:60d829a0353a	4232	#define SIM_SDID_REVID_MASK 0xF000u
tushki7	0:60d829a0353a	4233	#define SIM_SDID_REVID_SHIFT 12
tushki7	0:60d829a0353a	4234	#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
tushki7	0:60d829a0353a	4235	/* SCGC2 Bit Fields */
tushki7	0:60d829a0353a	4236	#define SIM_SCGC2_DAC0_MASK 0x1000u
tushki7	0:60d829a0353a	4237	#define SIM_SCGC2_DAC0_SHIFT 12
tushki7	0:60d829a0353a	4238	/* SCGC3 Bit Fields */
tushki7	0:60d829a0353a	4239	#define SIM_SCGC3_FTM2_MASK 0x1000000u
tushki7	0:60d829a0353a	4240	#define SIM_SCGC3_FTM2_SHIFT 24
tushki7	0:60d829a0353a	4241	#define SIM_SCGC3_ADC1_MASK 0x8000000u
tushki7	0:60d829a0353a	4242	#define SIM_SCGC3_ADC1_SHIFT 27
tushki7	0:60d829a0353a	4243	/* SCGC4 Bit Fields */
tushki7	0:60d829a0353a	4244	#define SIM_SCGC4_EWM_MASK 0x2u
tushki7	0:60d829a0353a	4245	#define SIM_SCGC4_EWM_SHIFT 1
tushki7	0:60d829a0353a	4246	#define SIM_SCGC4_CMT_MASK 0x4u
tushki7	0:60d829a0353a	4247	#define SIM_SCGC4_CMT_SHIFT 2
tushki7	0:60d829a0353a	4248	#define SIM_SCGC4_I2C0_MASK 0x40u
tushki7	0:60d829a0353a	4249	#define SIM_SCGC4_I2C0_SHIFT 6
tushki7	0:60d829a0353a	4250	#define SIM_SCGC4_I2C1_MASK 0x80u
tushki7	0:60d829a0353a	4251	#define SIM_SCGC4_I2C1_SHIFT 7
tushki7	0:60d829a0353a	4252	#define SIM_SCGC4_UART0_MASK 0x400u
tushki7	0:60d829a0353a	4253	#define SIM_SCGC4_UART0_SHIFT 10
tushki7	0:60d829a0353a	4254	#define SIM_SCGC4_UART1_MASK 0x800u
tushki7	0:60d829a0353a	4255	#define SIM_SCGC4_UART1_SHIFT 11
tushki7	0:60d829a0353a	4256	#define SIM_SCGC4_UART2_MASK 0x1000u
tushki7	0:60d829a0353a	4257	#define SIM_SCGC4_UART2_SHIFT 12
tushki7	0:60d829a0353a	4258	#define SIM_SCGC4_USBOTG_MASK 0x40000u
tushki7	0:60d829a0353a	4259	#define SIM_SCGC4_USBOTG_SHIFT 18
tushki7	0:60d829a0353a	4260	#define SIM_SCGC4_CMP_MASK 0x80000u
tushki7	0:60d829a0353a	4261	#define SIM_SCGC4_CMP_SHIFT 19
tushki7	0:60d829a0353a	4262	#define SIM_SCGC4_VREF_MASK 0x100000u
tushki7	0:60d829a0353a	4263	#define SIM_SCGC4_VREF_SHIFT 20
tushki7	0:60d829a0353a	4264	/* SCGC5 Bit Fields */
tushki7	0:60d829a0353a	4265	#define SIM_SCGC5_LPTIMER_MASK 0x1u
tushki7	0:60d829a0353a	4266	#define SIM_SCGC5_LPTIMER_SHIFT 0
tushki7	0:60d829a0353a	4267	#define SIM_SCGC5_TSI_MASK 0x20u
tushki7	0:60d829a0353a	4268	#define SIM_SCGC5_TSI_SHIFT 5
tushki7	0:60d829a0353a	4269	#define SIM_SCGC5_PORTA_MASK 0x200u
tushki7	0:60d829a0353a	4270	#define SIM_SCGC5_PORTA_SHIFT 9
tushki7	0:60d829a0353a	4271	#define SIM_SCGC5_PORTB_MASK 0x400u
tushki7	0:60d829a0353a	4272	#define SIM_SCGC5_PORTB_SHIFT 10
tushki7	0:60d829a0353a	4273	#define SIM_SCGC5_PORTC_MASK 0x800u
tushki7	0:60d829a0353a	4274	#define SIM_SCGC5_PORTC_SHIFT 11
tushki7	0:60d829a0353a	4275	#define SIM_SCGC5_PORTD_MASK 0x1000u
tushki7	0:60d829a0353a	4276	#define SIM_SCGC5_PORTD_SHIFT 12
tushki7	0:60d829a0353a	4277	#define SIM_SCGC5_PORTE_MASK 0x2000u
tushki7	0:60d829a0353a	4278	#define SIM_SCGC5_PORTE_SHIFT 13
tushki7	0:60d829a0353a	4279	/* SCGC6 Bit Fields */
tushki7	0:60d829a0353a	4280	#define SIM_SCGC6_FTFL_MASK 0x1u
tushki7	0:60d829a0353a	4281	#define SIM_SCGC6_FTFL_SHIFT 0
tushki7	0:60d829a0353a	4282	#define SIM_SCGC6_DMAMUX_MASK 0x2u
tushki7	0:60d829a0353a	4283	#define SIM_SCGC6_DMAMUX_SHIFT 1
tushki7	0:60d829a0353a	4284	#define SIM_SCGC6_FLEXCAN0_MASK 0x10u
tushki7	0:60d829a0353a	4285	#define SIM_SCGC6_FLEXCAN0_SHIFT 4
tushki7	0:60d829a0353a	4286	#define SIM_SCGC6_SPI0_MASK 0x1000u
tushki7	0:60d829a0353a	4287	#define SIM_SCGC6_SPI0_SHIFT 12
tushki7	0:60d829a0353a	4288	#define SIM_SCGC6_SPI1_MASK 0x2000u
tushki7	0:60d829a0353a	4289	#define SIM_SCGC6_SPI1_SHIFT 13
tushki7	0:60d829a0353a	4290	#define SIM_SCGC6_I2S_MASK 0x8000u
tushki7	0:60d829a0353a	4291	#define SIM_SCGC6_I2S_SHIFT 15
tushki7	0:60d829a0353a	4292	#define SIM_SCGC6_CRC_MASK 0x40000u
tushki7	0:60d829a0353a	4293	#define SIM_SCGC6_CRC_SHIFT 18
tushki7	0:60d829a0353a	4294	#define SIM_SCGC6_USBDCD_MASK 0x200000u
tushki7	0:60d829a0353a	4295	#define SIM_SCGC6_USBDCD_SHIFT 21
tushki7	0:60d829a0353a	4296	#define SIM_SCGC6_PDB_MASK 0x400000u
tushki7	0:60d829a0353a	4297	#define SIM_SCGC6_PDB_SHIFT 22
tushki7	0:60d829a0353a	4298	#define SIM_SCGC6_PIT_MASK 0x800000u
tushki7	0:60d829a0353a	4299	#define SIM_SCGC6_PIT_SHIFT 23
tushki7	0:60d829a0353a	4300	#define SIM_SCGC6_FTM0_MASK 0x1000000u
tushki7	0:60d829a0353a	4301	#define SIM_SCGC6_FTM0_SHIFT 24
tushki7	0:60d829a0353a	4302	#define SIM_SCGC6_FTM1_MASK 0x2000000u
tushki7	0:60d829a0353a	4303	#define SIM_SCGC6_FTM1_SHIFT 25
tushki7	0:60d829a0353a	4304	#define SIM_SCGC6_ADC0_MASK 0x8000000u
tushki7	0:60d829a0353a	4305	#define SIM_SCGC6_ADC0_SHIFT 27
tushki7	0:60d829a0353a	4306	#define SIM_SCGC6_RTC_MASK 0x20000000u
tushki7	0:60d829a0353a	4307	#define SIM_SCGC6_RTC_SHIFT 29
tushki7	0:60d829a0353a	4308	/* SCGC7 Bit Fields */
tushki7	0:60d829a0353a	4309	#define SIM_SCGC7_DMA_MASK 0x2u
tushki7	0:60d829a0353a	4310	#define SIM_SCGC7_DMA_SHIFT 1
tushki7	0:60d829a0353a	4311	/* CLKDIV1 Bit Fields */
tushki7	0:60d829a0353a	4312	#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
tushki7	0:60d829a0353a	4313	#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
tushki7	0:60d829a0353a	4314	#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
tushki7	0:60d829a0353a	4315	#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
tushki7	0:60d829a0353a	4316	#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
tushki7	0:60d829a0353a	4317	#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
tushki7	0:60d829a0353a	4318	#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
tushki7	0:60d829a0353a	4319	#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
tushki7	0:60d829a0353a	4320	#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
tushki7	0:60d829a0353a	4321	/* CLKDIV2 Bit Fields */
tushki7	0:60d829a0353a	4322	#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
tushki7	0:60d829a0353a	4323	#define SIM_CLKDIV2_USBFRAC_SHIFT 0
tushki7	0:60d829a0353a	4324	#define SIM_CLKDIV2_USBDIV_MASK 0xEu
tushki7	0:60d829a0353a	4325	#define SIM_CLKDIV2_USBDIV_SHIFT 1
tushki7	0:60d829a0353a	4326	#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
tushki7	0:60d829a0353a	4327	/* FCFG1 Bit Fields */
tushki7	0:60d829a0353a	4328	#define SIM_FCFG1_FLASHDIS_MASK 0x1u
tushki7	0:60d829a0353a	4329	#define SIM_FCFG1_FLASHDIS_SHIFT 0
tushki7	0:60d829a0353a	4330	#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
tushki7	0:60d829a0353a	4331	#define SIM_FCFG1_FLASHDOZE_SHIFT 1
tushki7	0:60d829a0353a	4332	#define SIM_FCFG1_DEPART_MASK 0xF00u
tushki7	0:60d829a0353a	4333	#define SIM_FCFG1_DEPART_SHIFT 8
tushki7	0:60d829a0353a	4334	#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
tushki7	0:60d829a0353a	4335	#define SIM_FCFG1_EESIZE_MASK 0xF0000u
tushki7	0:60d829a0353a	4336	#define SIM_FCFG1_EESIZE_SHIFT 16
tushki7	0:60d829a0353a	4337	#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
tushki7	0:60d829a0353a	4338	#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
tushki7	0:60d829a0353a	4339	#define SIM_FCFG1_PFSIZE_SHIFT 24
tushki7	0:60d829a0353a	4340	#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
tushki7	0:60d829a0353a	4341	#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
tushki7	0:60d829a0353a	4342	#define SIM_FCFG1_NVMSIZE_SHIFT 28
tushki7	0:60d829a0353a	4343	#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
tushki7	0:60d829a0353a	4344	/* FCFG2 Bit Fields */
tushki7	0:60d829a0353a	4345	#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
tushki7	0:60d829a0353a	4346	#define SIM_FCFG2_MAXADDR1_SHIFT 16
tushki7	0:60d829a0353a	4347	#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
tushki7	0:60d829a0353a	4348	#define SIM_FCFG2_PFLSH_MASK 0x800000u
tushki7	0:60d829a0353a	4349	#define SIM_FCFG2_PFLSH_SHIFT 23
tushki7	0:60d829a0353a	4350	#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
tushki7	0:60d829a0353a	4351	#define SIM_FCFG2_MAXADDR0_SHIFT 24
tushki7	0:60d829a0353a	4352	#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
tushki7	0:60d829a0353a	4353	/* UIDH Bit Fields */
tushki7	0:60d829a0353a	4354	#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	4355	#define SIM_UIDH_UID_SHIFT 0
tushki7	0:60d829a0353a	4356	#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
tushki7	0:60d829a0353a	4357	/* UIDMH Bit Fields */
tushki7	0:60d829a0353a	4358	#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	4359	#define SIM_UIDMH_UID_SHIFT 0
tushki7	0:60d829a0353a	4360	#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
tushki7	0:60d829a0353a	4361	/* UIDML Bit Fields */
tushki7	0:60d829a0353a	4362	#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	4363	#define SIM_UIDML_UID_SHIFT 0
tushki7	0:60d829a0353a	4364	#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
tushki7	0:60d829a0353a	4365	/* UIDL Bit Fields */
tushki7	0:60d829a0353a	4366	#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	4367	#define SIM_UIDL_UID_SHIFT 0
tushki7	0:60d829a0353a	4368	#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
tushki7	0:60d829a0353a	4369
tushki7	0:60d829a0353a	4370	/**
tushki7	0:60d829a0353a	4371	* @}
tushki7	0:60d829a0353a	4372	/ / end of group SIM_Register_Masks */
tushki7	0:60d829a0353a	4373
tushki7	0:60d829a0353a	4374
tushki7	0:60d829a0353a	4375	/* SIM - Peripheral instance base addresses */
tushki7	0:60d829a0353a	4376	/** Peripheral SIM base address */
tushki7	0:60d829a0353a	4377	#define SIM_BASE (0x40047000u)
tushki7	0:60d829a0353a	4378	/** Peripheral SIM base pointer */
tushki7	0:60d829a0353a	4379	#define SIM ((SIM_Type *)SIM_BASE)
tushki7	0:60d829a0353a	4380
tushki7	0:60d829a0353a	4381	/**
tushki7	0:60d829a0353a	4382	* @}
tushki7	0:60d829a0353a	4383	/ / end of group SIM_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	4384
tushki7	0:60d829a0353a	4385
tushki7	0:60d829a0353a	4386	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	4387	-- SMC Peripheral Access Layer
tushki7	0:60d829a0353a	4388	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	4389
tushki7	0:60d829a0353a	4390	/**
tushki7	0:60d829a0353a	4391	* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
tushki7	0:60d829a0353a	4392	* @{
tushki7	0:60d829a0353a	4393	*/
tushki7	0:60d829a0353a	4394
tushki7	0:60d829a0353a	4395	/** SMC - Register Layout Typedef */
tushki7	0:60d829a0353a	4396	typedef struct {
tushki7	0:60d829a0353a	4397	__IO uint8_t PMPROT; /*< Power Mode Protection Register, offset: 0x0 /
tushki7	0:60d829a0353a	4398	__IO uint8_t PMCTRL; /*< Power Mode Control Register, offset: 0x1 /
tushki7	0:60d829a0353a	4399	__IO uint8_t VLLSCTRL; /*< VLLS Control Register, offset: 0x2 /
tushki7	0:60d829a0353a	4400	__I uint8_t PMSTAT; /*< Power Mode Status Register, offset: 0x3 /
tushki7	0:60d829a0353a	4401	} SMC_Type;
tushki7	0:60d829a0353a	4402
tushki7	0:60d829a0353a	4403	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	4404	-- SMC Register Masks
tushki7	0:60d829a0353a	4405	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	4406
tushki7	0:60d829a0353a	4407	/**
tushki7	0:60d829a0353a	4408	* @addtogroup SMC_Register_Masks SMC Register Masks
tushki7	0:60d829a0353a	4409	* @{
tushki7	0:60d829a0353a	4410	*/
tushki7	0:60d829a0353a	4411
tushki7	0:60d829a0353a	4412	/* PMPROT Bit Fields */
tushki7	0:60d829a0353a	4413	#define SMC_PMPROT_AVLLS_MASK 0x2u
tushki7	0:60d829a0353a	4414	#define SMC_PMPROT_AVLLS_SHIFT 1
tushki7	0:60d829a0353a	4415	#define SMC_PMPROT_ALLS_MASK 0x8u
tushki7	0:60d829a0353a	4416	#define SMC_PMPROT_ALLS_SHIFT 3
tushki7	0:60d829a0353a	4417	#define SMC_PMPROT_AVLP_MASK 0x20u
tushki7	0:60d829a0353a	4418	#define SMC_PMPROT_AVLP_SHIFT 5
tushki7	0:60d829a0353a	4419	/* PMCTRL Bit Fields */
tushki7	0:60d829a0353a	4420	#define SMC_PMCTRL_STOPM_MASK 0x7u
tushki7	0:60d829a0353a	4421	#define SMC_PMCTRL_STOPM_SHIFT 0
tushki7	0:60d829a0353a	4422	#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
tushki7	0:60d829a0353a	4423	#define SMC_PMCTRL_STOPA_MASK 0x8u
tushki7	0:60d829a0353a	4424	#define SMC_PMCTRL_STOPA_SHIFT 3
tushki7	0:60d829a0353a	4425	#define SMC_PMCTRL_RUNM_MASK 0x60u
tushki7	0:60d829a0353a	4426	#define SMC_PMCTRL_RUNM_SHIFT 5
tushki7	0:60d829a0353a	4427	#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
tushki7	0:60d829a0353a	4428	#define SMC_PMCTRL_LPWUI_MASK 0x80u
tushki7	0:60d829a0353a	4429	#define SMC_PMCTRL_LPWUI_SHIFT 7
tushki7	0:60d829a0353a	4430	/* VLLSCTRL Bit Fields */
tushki7	0:60d829a0353a	4431	#define SMC_VLLSCTRL_VLLSM_MASK 0x7u
tushki7	0:60d829a0353a	4432	#define SMC_VLLSCTRL_VLLSM_SHIFT 0
tushki7	0:60d829a0353a	4433	#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
tushki7	0:60d829a0353a	4434	#define SMC_VLLSCTRL_PORPO_MASK 0x20u
tushki7	0:60d829a0353a	4435	#define SMC_VLLSCTRL_PORPO_SHIFT 5
tushki7	0:60d829a0353a	4436	/* PMSTAT Bit Fields */
tushki7	0:60d829a0353a	4437	#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
tushki7	0:60d829a0353a	4438	#define SMC_PMSTAT_PMSTAT_SHIFT 0
tushki7	0:60d829a0353a	4439	#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
tushki7	0:60d829a0353a	4440
tushki7	0:60d829a0353a	4441	/**
tushki7	0:60d829a0353a	4442	* @}
tushki7	0:60d829a0353a	4443	/ / end of group SMC_Register_Masks */
tushki7	0:60d829a0353a	4444
tushki7	0:60d829a0353a	4445
tushki7	0:60d829a0353a	4446	/* SMC - Peripheral instance base addresses */
tushki7	0:60d829a0353a	4447	/** Peripheral SMC base address */
tushki7	0:60d829a0353a	4448	#define SMC_BASE (0x4007E000u)
tushki7	0:60d829a0353a	4449	/** Peripheral SMC base pointer */
tushki7	0:60d829a0353a	4450	#define SMC ((SMC_Type *)SMC_BASE)
tushki7	0:60d829a0353a	4451
tushki7	0:60d829a0353a	4452	/**
tushki7	0:60d829a0353a	4453	* @}
tushki7	0:60d829a0353a	4454	/ / end of group SMC_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	4455
tushki7	0:60d829a0353a	4456
tushki7	0:60d829a0353a	4457	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	4458	-- SPI Peripheral Access Layer
tushki7	0:60d829a0353a	4459	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	4460
tushki7	0:60d829a0353a	4461	/**
tushki7	0:60d829a0353a	4462	* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
tushki7	0:60d829a0353a	4463	* @{
tushki7	0:60d829a0353a	4464	*/
tushki7	0:60d829a0353a	4465
tushki7	0:60d829a0353a	4466	/** SPI - Register Layout Typedef */
tushki7	0:60d829a0353a	4467	typedef struct {
tushki7	0:60d829a0353a	4468	__IO uint32_t MCR; /*< DSPI Module Configuration Register, offset: 0x0 /
tushki7	0:60d829a0353a	4469	uint8_t RESERVED_0[4];
tushki7	0:60d829a0353a	4470	__IO uint32_t TCR; /*< DSPI Transfer Count Register, offset: 0x8 /
tushki7	0:60d829a0353a	4471	union { /* offset: 0xC */
tushki7	0:60d829a0353a	4472	__IO uint32_t CTAR[2]; /*< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 /
tushki7	0:60d829a0353a	4473	__IO uint32_t CTAR_SLAVE[1]; /*< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 /
tushki7	0:60d829a0353a	4474	};
tushki7	0:60d829a0353a	4475	uint8_t RESERVED_1[24];
tushki7	0:60d829a0353a	4476	__IO uint32_t SR; /*< DSPI Status Register, offset: 0x2C /
tushki7	0:60d829a0353a	4477	__IO uint32_t RSER; /*< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 /
tushki7	0:60d829a0353a	4478	union { /* offset: 0x34 */
tushki7	0:60d829a0353a	4479	__IO uint32_t PUSHR; /*< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 /
tushki7	0:60d829a0353a	4480	__IO uint32_t PUSHR_SLAVE; /*< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 /
tushki7	0:60d829a0353a	4481	};
tushki7	0:60d829a0353a	4482	__I uint32_t POPR; /*< DSPI POP RX FIFO Register, offset: 0x38 /
tushki7	0:60d829a0353a	4483	__I uint32_t TXFR0; /*< DSPI Transmit FIFO Registers, offset: 0x3C /
tushki7	0:60d829a0353a	4484	__I uint32_t TXFR1; /*< DSPI Transmit FIFO Registers, offset: 0x40 /
tushki7	0:60d829a0353a	4485	__I uint32_t TXFR2; /*< DSPI Transmit FIFO Registers, offset: 0x44 /
tushki7	0:60d829a0353a	4486	__I uint32_t TXFR3; /*< DSPI Transmit FIFO Registers, offset: 0x48 /
tushki7	0:60d829a0353a	4487	uint8_t RESERVED_2[48];
tushki7	0:60d829a0353a	4488	__I uint32_t RXFR0; /*< DSPI Receive FIFO Registers, offset: 0x7C /
tushki7	0:60d829a0353a	4489	__I uint32_t RXFR1; /*< DSPI Receive FIFO Registers, offset: 0x80 /
tushki7	0:60d829a0353a	4490	__I uint32_t RXFR2; /*< DSPI Receive FIFO Registers, offset: 0x84 /
tushki7	0:60d829a0353a	4491	__I uint32_t RXFR3; /*< DSPI Receive FIFO Registers, offset: 0x88 /
tushki7	0:60d829a0353a	4492	} SPI_Type;
tushki7	0:60d829a0353a	4493
tushki7	0:60d829a0353a	4494	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	4495	-- SPI Register Masks
tushki7	0:60d829a0353a	4496	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	4497
tushki7	0:60d829a0353a	4498	/**
tushki7	0:60d829a0353a	4499	* @addtogroup SPI_Register_Masks SPI Register Masks
tushki7	0:60d829a0353a	4500	* @{
tushki7	0:60d829a0353a	4501	*/
tushki7	0:60d829a0353a	4502
tushki7	0:60d829a0353a	4503	/* MCR Bit Fields */
tushki7	0:60d829a0353a	4504	#define SPI_MCR_HALT_MASK 0x1u
tushki7	0:60d829a0353a	4505	#define SPI_MCR_HALT_SHIFT 0
tushki7	0:60d829a0353a	4506	#define SPI_MCR_SMPL_PT_MASK 0x300u
tushki7	0:60d829a0353a	4507	#define SPI_MCR_SMPL_PT_SHIFT 8
tushki7	0:60d829a0353a	4508	#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
tushki7	0:60d829a0353a	4509	#define SPI_MCR_CLR_RXF_MASK 0x400u
tushki7	0:60d829a0353a	4510	#define SPI_MCR_CLR_RXF_SHIFT 10
tushki7	0:60d829a0353a	4511	#define SPI_MCR_CLR_TXF_MASK 0x800u
tushki7	0:60d829a0353a	4512	#define SPI_MCR_CLR_TXF_SHIFT 11
tushki7	0:60d829a0353a	4513	#define SPI_MCR_DIS_RXF_MASK 0x1000u
tushki7	0:60d829a0353a	4514	#define SPI_MCR_DIS_RXF_SHIFT 12
tushki7	0:60d829a0353a	4515	#define SPI_MCR_DIS_TXF_MASK 0x2000u
tushki7	0:60d829a0353a	4516	#define SPI_MCR_DIS_TXF_SHIFT 13
tushki7	0:60d829a0353a	4517	#define SPI_MCR_MDIS_MASK 0x4000u
tushki7	0:60d829a0353a	4518	#define SPI_MCR_MDIS_SHIFT 14
tushki7	0:60d829a0353a	4519	#define SPI_MCR_DOZE_MASK 0x8000u
tushki7	0:60d829a0353a	4520	#define SPI_MCR_DOZE_SHIFT 15
tushki7	0:60d829a0353a	4521	#define SPI_MCR_PCSIS_MASK 0x3F0000u
tushki7	0:60d829a0353a	4522	#define SPI_MCR_PCSIS_SHIFT 16
tushki7	0:60d829a0353a	4523	#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
tushki7	0:60d829a0353a	4524	#define SPI_MCR_ROOE_MASK 0x1000000u
tushki7	0:60d829a0353a	4525	#define SPI_MCR_ROOE_SHIFT 24
tushki7	0:60d829a0353a	4526	#define SPI_MCR_PCSSE_MASK 0x2000000u
tushki7	0:60d829a0353a	4527	#define SPI_MCR_PCSSE_SHIFT 25
tushki7	0:60d829a0353a	4528	#define SPI_MCR_MTFE_MASK 0x4000000u
tushki7	0:60d829a0353a	4529	#define SPI_MCR_MTFE_SHIFT 26
tushki7	0:60d829a0353a	4530	#define SPI_MCR_FRZ_MASK 0x8000000u
tushki7	0:60d829a0353a	4531	#define SPI_MCR_FRZ_SHIFT 27
tushki7	0:60d829a0353a	4532	#define SPI_MCR_DCONF_MASK 0x30000000u
tushki7	0:60d829a0353a	4533	#define SPI_MCR_DCONF_SHIFT 28
tushki7	0:60d829a0353a	4534	#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
tushki7	0:60d829a0353a	4535	#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
tushki7	0:60d829a0353a	4536	#define SPI_MCR_CONT_SCKE_SHIFT 30
tushki7	0:60d829a0353a	4537	#define SPI_MCR_MSTR_MASK 0x80000000u
tushki7	0:60d829a0353a	4538	#define SPI_MCR_MSTR_SHIFT 31
tushki7	0:60d829a0353a	4539	/* TCR Bit Fields */
tushki7	0:60d829a0353a	4540	#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4541	#define SPI_TCR_SPI_TCNT_SHIFT 16
tushki7	0:60d829a0353a	4542	#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
tushki7	0:60d829a0353a	4543	/* CTAR Bit Fields */
tushki7	0:60d829a0353a	4544	#define SPI_CTAR_BR_MASK 0xFu
tushki7	0:60d829a0353a	4545	#define SPI_CTAR_BR_SHIFT 0
tushki7	0:60d829a0353a	4546	#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
tushki7	0:60d829a0353a	4547	#define SPI_CTAR_DT_MASK 0xF0u
tushki7	0:60d829a0353a	4548	#define SPI_CTAR_DT_SHIFT 4
tushki7	0:60d829a0353a	4549	#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
tushki7	0:60d829a0353a	4550	#define SPI_CTAR_ASC_MASK 0xF00u
tushki7	0:60d829a0353a	4551	#define SPI_CTAR_ASC_SHIFT 8
tushki7	0:60d829a0353a	4552	#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
tushki7	0:60d829a0353a	4553	#define SPI_CTAR_CSSCK_MASK 0xF000u
tushki7	0:60d829a0353a	4554	#define SPI_CTAR_CSSCK_SHIFT 12
tushki7	0:60d829a0353a	4555	#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
tushki7	0:60d829a0353a	4556	#define SPI_CTAR_PBR_MASK 0x30000u
tushki7	0:60d829a0353a	4557	#define SPI_CTAR_PBR_SHIFT 16
tushki7	0:60d829a0353a	4558	#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
tushki7	0:60d829a0353a	4559	#define SPI_CTAR_PDT_MASK 0xC0000u
tushki7	0:60d829a0353a	4560	#define SPI_CTAR_PDT_SHIFT 18
tushki7	0:60d829a0353a	4561	#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
tushki7	0:60d829a0353a	4562	#define SPI_CTAR_PASC_MASK 0x300000u
tushki7	0:60d829a0353a	4563	#define SPI_CTAR_PASC_SHIFT 20
tushki7	0:60d829a0353a	4564	#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
tushki7	0:60d829a0353a	4565	#define SPI_CTAR_PCSSCK_MASK 0xC00000u
tushki7	0:60d829a0353a	4566	#define SPI_CTAR_PCSSCK_SHIFT 22
tushki7	0:60d829a0353a	4567	#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
tushki7	0:60d829a0353a	4568	#define SPI_CTAR_LSBFE_MASK 0x1000000u
tushki7	0:60d829a0353a	4569	#define SPI_CTAR_LSBFE_SHIFT 24
tushki7	0:60d829a0353a	4570	#define SPI_CTAR_CPHA_MASK 0x2000000u
tushki7	0:60d829a0353a	4571	#define SPI_CTAR_CPHA_SHIFT 25
tushki7	0:60d829a0353a	4572	#define SPI_CTAR_CPOL_MASK 0x4000000u
tushki7	0:60d829a0353a	4573	#define SPI_CTAR_CPOL_SHIFT 26
tushki7	0:60d829a0353a	4574	#define SPI_CTAR_FMSZ_MASK 0x78000000u
tushki7	0:60d829a0353a	4575	#define SPI_CTAR_FMSZ_SHIFT 27
tushki7	0:60d829a0353a	4576	#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
tushki7	0:60d829a0353a	4577	#define SPI_CTAR_DBR_MASK 0x80000000u
tushki7	0:60d829a0353a	4578	#define SPI_CTAR_DBR_SHIFT 31
tushki7	0:60d829a0353a	4579	/* CTAR_SLAVE Bit Fields */
tushki7	0:60d829a0353a	4580	#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
tushki7	0:60d829a0353a	4581	#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
tushki7	0:60d829a0353a	4582	#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
tushki7	0:60d829a0353a	4583	#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
tushki7	0:60d829a0353a	4584	#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
tushki7	0:60d829a0353a	4585	#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
tushki7	0:60d829a0353a	4586	#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
tushki7	0:60d829a0353a	4587	/* SR Bit Fields */
tushki7	0:60d829a0353a	4588	#define SPI_SR_POPNXTPTR_MASK 0xFu
tushki7	0:60d829a0353a	4589	#define SPI_SR_POPNXTPTR_SHIFT 0
tushki7	0:60d829a0353a	4590	#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
tushki7	0:60d829a0353a	4591	#define SPI_SR_RXCTR_MASK 0xF0u
tushki7	0:60d829a0353a	4592	#define SPI_SR_RXCTR_SHIFT 4
tushki7	0:60d829a0353a	4593	#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
tushki7	0:60d829a0353a	4594	#define SPI_SR_TXNXTPTR_MASK 0xF00u
tushki7	0:60d829a0353a	4595	#define SPI_SR_TXNXTPTR_SHIFT 8
tushki7	0:60d829a0353a	4596	#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
tushki7	0:60d829a0353a	4597	#define SPI_SR_TXCTR_MASK 0xF000u
tushki7	0:60d829a0353a	4598	#define SPI_SR_TXCTR_SHIFT 12
tushki7	0:60d829a0353a	4599	#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
tushki7	0:60d829a0353a	4600	#define SPI_SR_RFDF_MASK 0x20000u
tushki7	0:60d829a0353a	4601	#define SPI_SR_RFDF_SHIFT 17
tushki7	0:60d829a0353a	4602	#define SPI_SR_RFOF_MASK 0x80000u
tushki7	0:60d829a0353a	4603	#define SPI_SR_RFOF_SHIFT 19
tushki7	0:60d829a0353a	4604	#define SPI_SR_TFFF_MASK 0x2000000u
tushki7	0:60d829a0353a	4605	#define SPI_SR_TFFF_SHIFT 25
tushki7	0:60d829a0353a	4606	#define SPI_SR_TFUF_MASK 0x8000000u
tushki7	0:60d829a0353a	4607	#define SPI_SR_TFUF_SHIFT 27
tushki7	0:60d829a0353a	4608	#define SPI_SR_EOQF_MASK 0x10000000u
tushki7	0:60d829a0353a	4609	#define SPI_SR_EOQF_SHIFT 28
tushki7	0:60d829a0353a	4610	#define SPI_SR_TXRXS_MASK 0x40000000u
tushki7	0:60d829a0353a	4611	#define SPI_SR_TXRXS_SHIFT 30
tushki7	0:60d829a0353a	4612	#define SPI_SR_TCF_MASK 0x80000000u
tushki7	0:60d829a0353a	4613	#define SPI_SR_TCF_SHIFT 31
tushki7	0:60d829a0353a	4614	/* RSER Bit Fields */
tushki7	0:60d829a0353a	4615	#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
tushki7	0:60d829a0353a	4616	#define SPI_RSER_RFDF_DIRS_SHIFT 16
tushki7	0:60d829a0353a	4617	#define SPI_RSER_RFDF_RE_MASK 0x20000u
tushki7	0:60d829a0353a	4618	#define SPI_RSER_RFDF_RE_SHIFT 17
tushki7	0:60d829a0353a	4619	#define SPI_RSER_RFOF_RE_MASK 0x80000u
tushki7	0:60d829a0353a	4620	#define SPI_RSER_RFOF_RE_SHIFT 19
tushki7	0:60d829a0353a	4621	#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
tushki7	0:60d829a0353a	4622	#define SPI_RSER_TFFF_DIRS_SHIFT 24
tushki7	0:60d829a0353a	4623	#define SPI_RSER_TFFF_RE_MASK 0x2000000u
tushki7	0:60d829a0353a	4624	#define SPI_RSER_TFFF_RE_SHIFT 25
tushki7	0:60d829a0353a	4625	#define SPI_RSER_TFUF_RE_MASK 0x8000000u
tushki7	0:60d829a0353a	4626	#define SPI_RSER_TFUF_RE_SHIFT 27
tushki7	0:60d829a0353a	4627	#define SPI_RSER_EOQF_RE_MASK 0x10000000u
tushki7	0:60d829a0353a	4628	#define SPI_RSER_EOQF_RE_SHIFT 28
tushki7	0:60d829a0353a	4629	#define SPI_RSER_TCF_RE_MASK 0x80000000u
tushki7	0:60d829a0353a	4630	#define SPI_RSER_TCF_RE_SHIFT 31
tushki7	0:60d829a0353a	4631	/* PUSHR Bit Fields */
tushki7	0:60d829a0353a	4632	#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
tushki7	0:60d829a0353a	4633	#define SPI_PUSHR_TXDATA_SHIFT 0
tushki7	0:60d829a0353a	4634	#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
tushki7	0:60d829a0353a	4635	#define SPI_PUSHR_PCS_MASK 0x3F0000u
tushki7	0:60d829a0353a	4636	#define SPI_PUSHR_PCS_SHIFT 16
tushki7	0:60d829a0353a	4637	#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
tushki7	0:60d829a0353a	4638	#define SPI_PUSHR_CTCNT_MASK 0x4000000u
tushki7	0:60d829a0353a	4639	#define SPI_PUSHR_CTCNT_SHIFT 26
tushki7	0:60d829a0353a	4640	#define SPI_PUSHR_EOQ_MASK 0x8000000u
tushki7	0:60d829a0353a	4641	#define SPI_PUSHR_EOQ_SHIFT 27
tushki7	0:60d829a0353a	4642	#define SPI_PUSHR_CTAS_MASK 0x70000000u
tushki7	0:60d829a0353a	4643	#define SPI_PUSHR_CTAS_SHIFT 28
tushki7	0:60d829a0353a	4644	#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
tushki7	0:60d829a0353a	4645	#define SPI_PUSHR_CONT_MASK 0x80000000u
tushki7	0:60d829a0353a	4646	#define SPI_PUSHR_CONT_SHIFT 31
tushki7	0:60d829a0353a	4647	/* PUSHR_SLAVE Bit Fields */
tushki7	0:60d829a0353a	4648	#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	4649	#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
tushki7	0:60d829a0353a	4650	#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
tushki7	0:60d829a0353a	4651	/* POPR Bit Fields */
tushki7	0:60d829a0353a	4652	#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	4653	#define SPI_POPR_RXDATA_SHIFT 0
tushki7	0:60d829a0353a	4654	#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
tushki7	0:60d829a0353a	4655	/* TXFR0 Bit Fields */
tushki7	0:60d829a0353a	4656	#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
tushki7	0:60d829a0353a	4657	#define SPI_TXFR0_TXDATA_SHIFT 0
tushki7	0:60d829a0353a	4658	#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
tushki7	0:60d829a0353a	4659	#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4660	#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
tushki7	0:60d829a0353a	4661	#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
tushki7	0:60d829a0353a	4662	/* TXFR1 Bit Fields */
tushki7	0:60d829a0353a	4663	#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
tushki7	0:60d829a0353a	4664	#define SPI_TXFR1_TXDATA_SHIFT 0
tushki7	0:60d829a0353a	4665	#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
tushki7	0:60d829a0353a	4666	#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4667	#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
tushki7	0:60d829a0353a	4668	#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
tushki7	0:60d829a0353a	4669	/* TXFR2 Bit Fields */
tushki7	0:60d829a0353a	4670	#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
tushki7	0:60d829a0353a	4671	#define SPI_TXFR2_TXDATA_SHIFT 0
tushki7	0:60d829a0353a	4672	#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
tushki7	0:60d829a0353a	4673	#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4674	#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
tushki7	0:60d829a0353a	4675	#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
tushki7	0:60d829a0353a	4676	/* TXFR3 Bit Fields */
tushki7	0:60d829a0353a	4677	#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
tushki7	0:60d829a0353a	4678	#define SPI_TXFR3_TXDATA_SHIFT 0
tushki7	0:60d829a0353a	4679	#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
tushki7	0:60d829a0353a	4680	#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4681	#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
tushki7	0:60d829a0353a	4682	#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
tushki7	0:60d829a0353a	4683	/* RXFR0 Bit Fields */
tushki7	0:60d829a0353a	4684	#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	4685	#define SPI_RXFR0_RXDATA_SHIFT 0
tushki7	0:60d829a0353a	4686	#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
tushki7	0:60d829a0353a	4687	/* RXFR1 Bit Fields */
tushki7	0:60d829a0353a	4688	#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	4689	#define SPI_RXFR1_RXDATA_SHIFT 0
tushki7	0:60d829a0353a	4690	#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
tushki7	0:60d829a0353a	4691	/* RXFR2 Bit Fields */
tushki7	0:60d829a0353a	4692	#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	4693	#define SPI_RXFR2_RXDATA_SHIFT 0
tushki7	0:60d829a0353a	4694	#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
tushki7	0:60d829a0353a	4695	/* RXFR3 Bit Fields */
tushki7	0:60d829a0353a	4696	#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
tushki7	0:60d829a0353a	4697	#define SPI_RXFR3_RXDATA_SHIFT 0
tushki7	0:60d829a0353a	4698	#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
tushki7	0:60d829a0353a	4699
tushki7	0:60d829a0353a	4700	/**
tushki7	0:60d829a0353a	4701	* @}
tushki7	0:60d829a0353a	4702	/ / end of group SPI_Register_Masks */
tushki7	0:60d829a0353a	4703
tushki7	0:60d829a0353a	4704
tushki7	0:60d829a0353a	4705	/* SPI - Peripheral instance base addresses */
tushki7	0:60d829a0353a	4706	/** Peripheral SPI0 base address */
tushki7	0:60d829a0353a	4707	#define SPI0_BASE (0x4002C000u)
tushki7	0:60d829a0353a	4708	/** Peripheral SPI0 base pointer */
tushki7	0:60d829a0353a	4709	#define SPI0 ((SPI_Type *)SPI0_BASE)
tushki7	0:60d829a0353a	4710
tushki7	0:60d829a0353a	4711	/**
tushki7	0:60d829a0353a	4712	* @}
tushki7	0:60d829a0353a	4713	/ / end of group SPI_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	4714
tushki7	0:60d829a0353a	4715
tushki7	0:60d829a0353a	4716	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	4717	-- TSI Peripheral Access Layer
tushki7	0:60d829a0353a	4718	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	4719
tushki7	0:60d829a0353a	4720	/**
tushki7	0:60d829a0353a	4721	* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
tushki7	0:60d829a0353a	4722	* @{
tushki7	0:60d829a0353a	4723	*/
tushki7	0:60d829a0353a	4724
tushki7	0:60d829a0353a	4725	/** TSI - Register Layout Typedef */
tushki7	0:60d829a0353a	4726	typedef struct {
tushki7	0:60d829a0353a	4727	__IO uint32_t GENCS; /*< General Control and Status Register, offset: 0x0 /
tushki7	0:60d829a0353a	4728	__IO uint32_t SCANC; /*< SCAN Control Register, offset: 0x4 /
tushki7	0:60d829a0353a	4729	__IO uint32_t PEN; /*< Pin Enable Register, offset: 0x8 /
tushki7	0:60d829a0353a	4730	__I uint32_t WUCNTR; /*< Wake-Up Channel Counter Register, offset: 0xC /
tushki7	0:60d829a0353a	4731	uint8_t RESERVED_0[240];
tushki7	0:60d829a0353a	4732	__I uint32_t CNTR1; /*< Counter Register, offset: 0x100 /
tushki7	0:60d829a0353a	4733	__I uint32_t CNTR3; /*< Counter Register, offset: 0x104 /
tushki7	0:60d829a0353a	4734	__I uint32_t CNTR5; /*< Counter Register, offset: 0x108 /
tushki7	0:60d829a0353a	4735	__I uint32_t CNTR7; /*< Counter Register, offset: 0x10C /
tushki7	0:60d829a0353a	4736	__I uint32_t CNTR9; /*< Counter Register, offset: 0x110 /
tushki7	0:60d829a0353a	4737	__I uint32_t CNTR11; /*< Counter Register, offset: 0x114 /
tushki7	0:60d829a0353a	4738	__I uint32_t CNTR13; /*< Counter Register, offset: 0x118 /
tushki7	0:60d829a0353a	4739	__I uint32_t CNTR15; /*< Counter Register, offset: 0x11C /
tushki7	0:60d829a0353a	4740	__IO uint32_t THRESHOLD; /*< Low Power Channel Threshold Register, offset: 0x120 /
tushki7	0:60d829a0353a	4741	} TSI_Type;
tushki7	0:60d829a0353a	4742
tushki7	0:60d829a0353a	4743	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	4744	-- TSI Register Masks
tushki7	0:60d829a0353a	4745	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	4746
tushki7	0:60d829a0353a	4747	/**
tushki7	0:60d829a0353a	4748	* @addtogroup TSI_Register_Masks TSI Register Masks
tushki7	0:60d829a0353a	4749	* @{
tushki7	0:60d829a0353a	4750	*/
tushki7	0:60d829a0353a	4751
tushki7	0:60d829a0353a	4752	/* GENCS Bit Fields */
tushki7	0:60d829a0353a	4753	#define TSI_GENCS_STPE_MASK 0x1u
tushki7	0:60d829a0353a	4754	#define TSI_GENCS_STPE_SHIFT 0
tushki7	0:60d829a0353a	4755	#define TSI_GENCS_STM_MASK 0x2u
tushki7	0:60d829a0353a	4756	#define TSI_GENCS_STM_SHIFT 1
tushki7	0:60d829a0353a	4757	#define TSI_GENCS_ESOR_MASK 0x10u
tushki7	0:60d829a0353a	4758	#define TSI_GENCS_ESOR_SHIFT 4
tushki7	0:60d829a0353a	4759	#define TSI_GENCS_ERIE_MASK 0x20u
tushki7	0:60d829a0353a	4760	#define TSI_GENCS_ERIE_SHIFT 5
tushki7	0:60d829a0353a	4761	#define TSI_GENCS_TSIIE_MASK 0x40u
tushki7	0:60d829a0353a	4762	#define TSI_GENCS_TSIIE_SHIFT 6
tushki7	0:60d829a0353a	4763	#define TSI_GENCS_TSIEN_MASK 0x80u
tushki7	0:60d829a0353a	4764	#define TSI_GENCS_TSIEN_SHIFT 7
tushki7	0:60d829a0353a	4765	#define TSI_GENCS_SWTS_MASK 0x100u
tushki7	0:60d829a0353a	4766	#define TSI_GENCS_SWTS_SHIFT 8
tushki7	0:60d829a0353a	4767	#define TSI_GENCS_SCNIP_MASK 0x200u
tushki7	0:60d829a0353a	4768	#define TSI_GENCS_SCNIP_SHIFT 9
tushki7	0:60d829a0353a	4769	#define TSI_GENCS_OVRF_MASK 0x1000u
tushki7	0:60d829a0353a	4770	#define TSI_GENCS_OVRF_SHIFT 12
tushki7	0:60d829a0353a	4771	#define TSI_GENCS_EXTERF_MASK 0x2000u
tushki7	0:60d829a0353a	4772	#define TSI_GENCS_EXTERF_SHIFT 13
tushki7	0:60d829a0353a	4773	#define TSI_GENCS_OUTRGF_MASK 0x4000u
tushki7	0:60d829a0353a	4774	#define TSI_GENCS_OUTRGF_SHIFT 14
tushki7	0:60d829a0353a	4775	#define TSI_GENCS_EOSF_MASK 0x8000u
tushki7	0:60d829a0353a	4776	#define TSI_GENCS_EOSF_SHIFT 15
tushki7	0:60d829a0353a	4777	#define TSI_GENCS_PS_MASK 0x70000u
tushki7	0:60d829a0353a	4778	#define TSI_GENCS_PS_SHIFT 16
tushki7	0:60d829a0353a	4779	#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
tushki7	0:60d829a0353a	4780	#define TSI_GENCS_NSCN_MASK 0xF80000u
tushki7	0:60d829a0353a	4781	#define TSI_GENCS_NSCN_SHIFT 19
tushki7	0:60d829a0353a	4782	#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
tushki7	0:60d829a0353a	4783	#define TSI_GENCS_LPSCNITV_MASK 0xF000000u
tushki7	0:60d829a0353a	4784	#define TSI_GENCS_LPSCNITV_SHIFT 24
tushki7	0:60d829a0353a	4785	#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
tushki7	0:60d829a0353a	4786	#define TSI_GENCS_LPCLKS_MASK 0x10000000u
tushki7	0:60d829a0353a	4787	#define TSI_GENCS_LPCLKS_SHIFT 28
tushki7	0:60d829a0353a	4788	/* SCANC Bit Fields */
tushki7	0:60d829a0353a	4789	#define TSI_SCANC_AMPSC_MASK 0x7u
tushki7	0:60d829a0353a	4790	#define TSI_SCANC_AMPSC_SHIFT 0
tushki7	0:60d829a0353a	4791	#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
tushki7	0:60d829a0353a	4792	#define TSI_SCANC_AMCLKS_MASK 0x18u
tushki7	0:60d829a0353a	4793	#define TSI_SCANC_AMCLKS_SHIFT 3
tushki7	0:60d829a0353a	4794	#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
tushki7	0:60d829a0353a	4795	#define TSI_SCANC_SMOD_MASK 0xFF00u
tushki7	0:60d829a0353a	4796	#define TSI_SCANC_SMOD_SHIFT 8
tushki7	0:60d829a0353a	4797	#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
tushki7	0:60d829a0353a	4798	#define TSI_SCANC_EXTCHRG_MASK 0xF0000u
tushki7	0:60d829a0353a	4799	#define TSI_SCANC_EXTCHRG_SHIFT 16
tushki7	0:60d829a0353a	4800	#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
tushki7	0:60d829a0353a	4801	#define TSI_SCANC_REFCHRG_MASK 0xF000000u
tushki7	0:60d829a0353a	4802	#define TSI_SCANC_REFCHRG_SHIFT 24
tushki7	0:60d829a0353a	4803	#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
tushki7	0:60d829a0353a	4804	/* PEN Bit Fields */
tushki7	0:60d829a0353a	4805	#define TSI_PEN_PEN0_MASK 0x1u
tushki7	0:60d829a0353a	4806	#define TSI_PEN_PEN0_SHIFT 0
tushki7	0:60d829a0353a	4807	#define TSI_PEN_PEN1_MASK 0x2u
tushki7	0:60d829a0353a	4808	#define TSI_PEN_PEN1_SHIFT 1
tushki7	0:60d829a0353a	4809	#define TSI_PEN_PEN2_MASK 0x4u
tushki7	0:60d829a0353a	4810	#define TSI_PEN_PEN2_SHIFT 2
tushki7	0:60d829a0353a	4811	#define TSI_PEN_PEN3_MASK 0x8u
tushki7	0:60d829a0353a	4812	#define TSI_PEN_PEN3_SHIFT 3
tushki7	0:60d829a0353a	4813	#define TSI_PEN_PEN4_MASK 0x10u
tushki7	0:60d829a0353a	4814	#define TSI_PEN_PEN4_SHIFT 4
tushki7	0:60d829a0353a	4815	#define TSI_PEN_PEN5_MASK 0x20u
tushki7	0:60d829a0353a	4816	#define TSI_PEN_PEN5_SHIFT 5
tushki7	0:60d829a0353a	4817	#define TSI_PEN_PEN6_MASK 0x40u
tushki7	0:60d829a0353a	4818	#define TSI_PEN_PEN6_SHIFT 6
tushki7	0:60d829a0353a	4819	#define TSI_PEN_PEN7_MASK 0x80u
tushki7	0:60d829a0353a	4820	#define TSI_PEN_PEN7_SHIFT 7
tushki7	0:60d829a0353a	4821	#define TSI_PEN_PEN8_MASK 0x100u
tushki7	0:60d829a0353a	4822	#define TSI_PEN_PEN8_SHIFT 8
tushki7	0:60d829a0353a	4823	#define TSI_PEN_PEN9_MASK 0x200u
tushki7	0:60d829a0353a	4824	#define TSI_PEN_PEN9_SHIFT 9
tushki7	0:60d829a0353a	4825	#define TSI_PEN_PEN10_MASK 0x400u
tushki7	0:60d829a0353a	4826	#define TSI_PEN_PEN10_SHIFT 10
tushki7	0:60d829a0353a	4827	#define TSI_PEN_PEN11_MASK 0x800u
tushki7	0:60d829a0353a	4828	#define TSI_PEN_PEN11_SHIFT 11
tushki7	0:60d829a0353a	4829	#define TSI_PEN_PEN12_MASK 0x1000u
tushki7	0:60d829a0353a	4830	#define TSI_PEN_PEN12_SHIFT 12
tushki7	0:60d829a0353a	4831	#define TSI_PEN_PEN13_MASK 0x2000u
tushki7	0:60d829a0353a	4832	#define TSI_PEN_PEN13_SHIFT 13
tushki7	0:60d829a0353a	4833	#define TSI_PEN_PEN14_MASK 0x4000u
tushki7	0:60d829a0353a	4834	#define TSI_PEN_PEN14_SHIFT 14
tushki7	0:60d829a0353a	4835	#define TSI_PEN_PEN15_MASK 0x8000u
tushki7	0:60d829a0353a	4836	#define TSI_PEN_PEN15_SHIFT 15
tushki7	0:60d829a0353a	4837	#define TSI_PEN_LPSP_MASK 0xF0000u
tushki7	0:60d829a0353a	4838	#define TSI_PEN_LPSP_SHIFT 16
tushki7	0:60d829a0353a	4839	#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
tushki7	0:60d829a0353a	4840	/* WUCNTR Bit Fields */
tushki7	0:60d829a0353a	4841	#define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
tushki7	0:60d829a0353a	4842	#define TSI_WUCNTR_WUCNT_SHIFT 0
tushki7	0:60d829a0353a	4843	#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
tushki7	0:60d829a0353a	4844	/* CNTR1 Bit Fields */
tushki7	0:60d829a0353a	4845	#define TSI_CNTR1_CTN1_MASK 0xFFFFu
tushki7	0:60d829a0353a	4846	#define TSI_CNTR1_CTN1_SHIFT 0
tushki7	0:60d829a0353a	4847	#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
tushki7	0:60d829a0353a	4848	#define TSI_CNTR1_CTN_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4849	#define TSI_CNTR1_CTN_SHIFT 16
tushki7	0:60d829a0353a	4850	#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
tushki7	0:60d829a0353a	4851	/* CNTR3 Bit Fields */
tushki7	0:60d829a0353a	4852	#define TSI_CNTR3_CTN1_MASK 0xFFFFu
tushki7	0:60d829a0353a	4853	#define TSI_CNTR3_CTN1_SHIFT 0
tushki7	0:60d829a0353a	4854	#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
tushki7	0:60d829a0353a	4855	#define TSI_CNTR3_CTN_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4856	#define TSI_CNTR3_CTN_SHIFT 16
tushki7	0:60d829a0353a	4857	#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
tushki7	0:60d829a0353a	4858	/* CNTR5 Bit Fields */
tushki7	0:60d829a0353a	4859	#define TSI_CNTR5_CTN1_MASK 0xFFFFu
tushki7	0:60d829a0353a	4860	#define TSI_CNTR5_CTN1_SHIFT 0
tushki7	0:60d829a0353a	4861	#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
tushki7	0:60d829a0353a	4862	#define TSI_CNTR5_CTN_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4863	#define TSI_CNTR5_CTN_SHIFT 16
tushki7	0:60d829a0353a	4864	#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
tushki7	0:60d829a0353a	4865	/* CNTR7 Bit Fields */
tushki7	0:60d829a0353a	4866	#define TSI_CNTR7_CTN1_MASK 0xFFFFu
tushki7	0:60d829a0353a	4867	#define TSI_CNTR7_CTN1_SHIFT 0
tushki7	0:60d829a0353a	4868	#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
tushki7	0:60d829a0353a	4869	#define TSI_CNTR7_CTN_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4870	#define TSI_CNTR7_CTN_SHIFT 16
tushki7	0:60d829a0353a	4871	#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
tushki7	0:60d829a0353a	4872	/* CNTR9 Bit Fields */
tushki7	0:60d829a0353a	4873	#define TSI_CNTR9_CTN1_MASK 0xFFFFu
tushki7	0:60d829a0353a	4874	#define TSI_CNTR9_CTN1_SHIFT 0
tushki7	0:60d829a0353a	4875	#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
tushki7	0:60d829a0353a	4876	#define TSI_CNTR9_CTN_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4877	#define TSI_CNTR9_CTN_SHIFT 16
tushki7	0:60d829a0353a	4878	#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
tushki7	0:60d829a0353a	4879	/* CNTR11 Bit Fields */
tushki7	0:60d829a0353a	4880	#define TSI_CNTR11_CTN1_MASK 0xFFFFu
tushki7	0:60d829a0353a	4881	#define TSI_CNTR11_CTN1_SHIFT 0
tushki7	0:60d829a0353a	4882	#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
tushki7	0:60d829a0353a	4883	#define TSI_CNTR11_CTN_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4884	#define TSI_CNTR11_CTN_SHIFT 16
tushki7	0:60d829a0353a	4885	#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
tushki7	0:60d829a0353a	4886	/* CNTR13 Bit Fields */
tushki7	0:60d829a0353a	4887	#define TSI_CNTR13_CTN1_MASK 0xFFFFu
tushki7	0:60d829a0353a	4888	#define TSI_CNTR13_CTN1_SHIFT 0
tushki7	0:60d829a0353a	4889	#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
tushki7	0:60d829a0353a	4890	#define TSI_CNTR13_CTN_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4891	#define TSI_CNTR13_CTN_SHIFT 16
tushki7	0:60d829a0353a	4892	#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
tushki7	0:60d829a0353a	4893	/* CNTR15 Bit Fields */
tushki7	0:60d829a0353a	4894	#define TSI_CNTR15_CTN1_MASK 0xFFFFu
tushki7	0:60d829a0353a	4895	#define TSI_CNTR15_CTN1_SHIFT 0
tushki7	0:60d829a0353a	4896	#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
tushki7	0:60d829a0353a	4897	#define TSI_CNTR15_CTN_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4898	#define TSI_CNTR15_CTN_SHIFT 16
tushki7	0:60d829a0353a	4899	#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
tushki7	0:60d829a0353a	4900	/* THRESHOLD Bit Fields */
tushki7	0:60d829a0353a	4901	#define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
tushki7	0:60d829a0353a	4902	#define TSI_THRESHOLD_HTHH_SHIFT 0
tushki7	0:60d829a0353a	4903	#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
tushki7	0:60d829a0353a	4904	#define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
tushki7	0:60d829a0353a	4905	#define TSI_THRESHOLD_LTHH_SHIFT 16
tushki7	0:60d829a0353a	4906	#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
tushki7	0:60d829a0353a	4907
tushki7	0:60d829a0353a	4908	/**
tushki7	0:60d829a0353a	4909	* @}
tushki7	0:60d829a0353a	4910	/ / end of group TSI_Register_Masks */
tushki7	0:60d829a0353a	4911
tushki7	0:60d829a0353a	4912
tushki7	0:60d829a0353a	4913	/* TSI - Peripheral instance base addresses */
tushki7	0:60d829a0353a	4914	/** Peripheral TSI0 base address */
tushki7	0:60d829a0353a	4915	#define TSI0_BASE (0x40045000u)
tushki7	0:60d829a0353a	4916	/** Peripheral TSI0 base pointer */
tushki7	0:60d829a0353a	4917	#define TSI0 ((TSI_Type *)TSI0_BASE)
tushki7	0:60d829a0353a	4918
tushki7	0:60d829a0353a	4919	/**
tushki7	0:60d829a0353a	4920	* @}
tushki7	0:60d829a0353a	4921	/ / end of group TSI_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	4922
tushki7	0:60d829a0353a	4923
tushki7	0:60d829a0353a	4924	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	4925	-- UART Peripheral Access Layer
tushki7	0:60d829a0353a	4926	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	4927
tushki7	0:60d829a0353a	4928	/**
tushki7	0:60d829a0353a	4929	* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
tushki7	0:60d829a0353a	4930	* @{
tushki7	0:60d829a0353a	4931	*/
tushki7	0:60d829a0353a	4932
tushki7	0:60d829a0353a	4933	/** UART - Register Layout Typedef */
tushki7	0:60d829a0353a	4934	typedef struct {
tushki7	0:60d829a0353a	4935	__IO uint8_t BDH; /*< UART Baud Rate Registers:High, offset: 0x0 /
tushki7	0:60d829a0353a	4936	__IO uint8_t BDL; /*< UART Baud Rate Registers: Low, offset: 0x1 /
tushki7	0:60d829a0353a	4937	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
tushki7	0:60d829a0353a	4938	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
tushki7	0:60d829a0353a	4939	__I uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
tushki7	0:60d829a0353a	4940	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
tushki7	0:60d829a0353a	4941	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
tushki7	0:60d829a0353a	4942	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
tushki7	0:60d829a0353a	4943	__IO uint8_t MA1; /*< UART Match Address Registers 1, offset: 0x8 /
tushki7	0:60d829a0353a	4944	__IO uint8_t MA2; /*< UART Match Address Registers 2, offset: 0x9 /
tushki7	0:60d829a0353a	4945	__IO uint8_t C4; /*< UART Control Register 4, offset: 0xA /
tushki7	0:60d829a0353a	4946	__IO uint8_t C5; /*< UART Control Register 5, offset: 0xB /
tushki7	0:60d829a0353a	4947	__I uint8_t ED; /*< UART Extended Data Register, offset: 0xC /
tushki7	0:60d829a0353a	4948	__IO uint8_t MODEM; /*< UART Modem Register, offset: 0xD /
tushki7	0:60d829a0353a	4949	__IO uint8_t IR; /*< UART Infrared Register, offset: 0xE /
tushki7	0:60d829a0353a	4950	uint8_t RESERVED_0[1];
tushki7	0:60d829a0353a	4951	__IO uint8_t PFIFO; /*< UART FIFO Parameters, offset: 0x10 /
tushki7	0:60d829a0353a	4952	__IO uint8_t CFIFO; /*< UART FIFO Control Register, offset: 0x11 /
tushki7	0:60d829a0353a	4953	__IO uint8_t SFIFO; /*< UART FIFO Status Register, offset: 0x12 /
tushki7	0:60d829a0353a	4954	__IO uint8_t TWFIFO; /*< UART FIFO Transmit Watermark, offset: 0x13 /
tushki7	0:60d829a0353a	4955	__I uint8_t TCFIFO; /*< UART FIFO Transmit Count, offset: 0x14 /
tushki7	0:60d829a0353a	4956	__IO uint8_t RWFIFO; /*< UART FIFO Receive Watermark, offset: 0x15 /
tushki7	0:60d829a0353a	4957	__I uint8_t RCFIFO; /*< UART FIFO Receive Count, offset: 0x16 /
tushki7	0:60d829a0353a	4958	uint8_t RESERVED_1[1];
tushki7	0:60d829a0353a	4959	__IO uint8_t C7816; /*< UART 7816 Control Register, offset: 0x18 /
tushki7	0:60d829a0353a	4960	__IO uint8_t IE7816; /*< UART 7816 Interrupt Enable Register, offset: 0x19 /
tushki7	0:60d829a0353a	4961	__IO uint8_t IS7816; /*< UART 7816 Interrupt Status Register, offset: 0x1A /
tushki7	0:60d829a0353a	4962	union { /* offset: 0x1B */
tushki7	0:60d829a0353a	4963	__IO uint8_t WP7816_T_TYPE0; /*< UART 7816 Wait Parameter Register, offset: 0x1B /
tushki7	0:60d829a0353a	4964	__IO uint8_t WP7816_T_TYPE1; /*< UART 7816 Wait Parameter Register, offset: 0x1B /
tushki7	0:60d829a0353a	4965	};
tushki7	0:60d829a0353a	4966	__IO uint8_t WN7816; /*< UART 7816 Wait N Register, offset: 0x1C /
tushki7	0:60d829a0353a	4967	__IO uint8_t WF7816; /*< UART 7816 Wait FD Register, offset: 0x1D /
tushki7	0:60d829a0353a	4968	__IO uint8_t ET7816; /*< UART 7816 Error Threshold Register, offset: 0x1E /
tushki7	0:60d829a0353a	4969	__IO uint8_t TL7816; /*< UART 7816 Transmit Length Register, offset: 0x1F /
tushki7	0:60d829a0353a	4970	uint8_t RESERVED_2[1];
tushki7	0:60d829a0353a	4971	__IO uint8_t C6; /*< UART CEA709.1-B Control Register 6, offset: 0x21 /
tushki7	0:60d829a0353a	4972	__IO uint8_t PCTH; /*< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 /
tushki7	0:60d829a0353a	4973	__IO uint8_t PCTL; /*< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 /
tushki7	0:60d829a0353a	4974	__IO uint8_t B1T; /*< UART CEA709.1-B Beta1 Timer, offset: 0x24 /
tushki7	0:60d829a0353a	4975	__IO uint8_t SDTH; /*< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 /
tushki7	0:60d829a0353a	4976	__IO uint8_t SDTL; /*< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 /
tushki7	0:60d829a0353a	4977	__IO uint8_t PRE; /*< UART CEA709.1-B Preamble, offset: 0x27 /
tushki7	0:60d829a0353a	4978	__IO uint8_t TPL; /*< UART CEA709.1-B Transmit Packet Length, offset: 0x28 /
tushki7	0:60d829a0353a	4979	__IO uint8_t IE; /*< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 /
tushki7	0:60d829a0353a	4980	__IO uint8_t WB; /*< UART CEA709.1-B WBASE, offset: 0x2A /
tushki7	0:60d829a0353a	4981	__IO uint8_t S3; /*< UART CEA709.1-B Status Register, offset: 0x2B /
tushki7	0:60d829a0353a	4982	__IO uint8_t S4; /*< UART CEA709.1-B Status Register, offset: 0x2C /
tushki7	0:60d829a0353a	4983	__I uint8_t RPL; /*< UART CEA709.1-B Received Packet Length, offset: 0x2D /
tushki7	0:60d829a0353a	4984	__I uint8_t RPREL; /*< UART CEA709.1-B Received Preamble Length, offset: 0x2E /
tushki7	0:60d829a0353a	4985	__IO uint8_t CPW; /*< UART CEA709.1-B Collision Pulse Width, offset: 0x2F /
tushki7	0:60d829a0353a	4986	__IO uint8_t RIDT; /*< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 /
tushki7	0:60d829a0353a	4987	__IO uint8_t TIDT; /*< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 /
tushki7	0:60d829a0353a	4988	} UART_Type;
tushki7	0:60d829a0353a	4989
tushki7	0:60d829a0353a	4990	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	4991	-- UART Register Masks
tushki7	0:60d829a0353a	4992	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	4993
tushki7	0:60d829a0353a	4994	/**
tushki7	0:60d829a0353a	4995	* @addtogroup UART_Register_Masks UART Register Masks
tushki7	0:60d829a0353a	4996	* @{
tushki7	0:60d829a0353a	4997	*/
tushki7	0:60d829a0353a	4998
tushki7	0:60d829a0353a	4999	/* BDH Bit Fields */
tushki7	0:60d829a0353a	5000	#define UART_BDH_SBR_MASK 0x1Fu
tushki7	0:60d829a0353a	5001	#define UART_BDH_SBR_SHIFT 0
tushki7	0:60d829a0353a	5002	#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
tushki7	0:60d829a0353a	5003	#define UART_BDH_RXEDGIE_MASK 0x40u
tushki7	0:60d829a0353a	5004	#define UART_BDH_RXEDGIE_SHIFT 6
tushki7	0:60d829a0353a	5005	#define UART_BDH_LBKDIE_MASK 0x80u
tushki7	0:60d829a0353a	5006	#define UART_BDH_LBKDIE_SHIFT 7
tushki7	0:60d829a0353a	5007	/* BDL Bit Fields */
tushki7	0:60d829a0353a	5008	#define UART_BDL_SBR_MASK 0xFFu
tushki7	0:60d829a0353a	5009	#define UART_BDL_SBR_SHIFT 0
tushki7	0:60d829a0353a	5010	#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
tushki7	0:60d829a0353a	5011	/* C1 Bit Fields */
tushki7	0:60d829a0353a	5012	#define UART_C1_PT_MASK 0x1u
tushki7	0:60d829a0353a	5013	#define UART_C1_PT_SHIFT 0
tushki7	0:60d829a0353a	5014	#define UART_C1_PE_MASK 0x2u
tushki7	0:60d829a0353a	5015	#define UART_C1_PE_SHIFT 1
tushki7	0:60d829a0353a	5016	#define UART_C1_ILT_MASK 0x4u
tushki7	0:60d829a0353a	5017	#define UART_C1_ILT_SHIFT 2
tushki7	0:60d829a0353a	5018	#define UART_C1_WAKE_MASK 0x8u
tushki7	0:60d829a0353a	5019	#define UART_C1_WAKE_SHIFT 3
tushki7	0:60d829a0353a	5020	#define UART_C1_M_MASK 0x10u
tushki7	0:60d829a0353a	5021	#define UART_C1_M_SHIFT 4
tushki7	0:60d829a0353a	5022	#define UART_C1_RSRC_MASK 0x20u
tushki7	0:60d829a0353a	5023	#define UART_C1_RSRC_SHIFT 5
tushki7	0:60d829a0353a	5024	#define UART_C1_UARTSWAI_MASK 0x40u
tushki7	0:60d829a0353a	5025	#define UART_C1_UARTSWAI_SHIFT 6
tushki7	0:60d829a0353a	5026	#define UART_C1_LOOPS_MASK 0x80u
tushki7	0:60d829a0353a	5027	#define UART_C1_LOOPS_SHIFT 7
tushki7	0:60d829a0353a	5028	/* C2 Bit Fields */
tushki7	0:60d829a0353a	5029	#define UART_C2_SBK_MASK 0x1u
tushki7	0:60d829a0353a	5030	#define UART_C2_SBK_SHIFT 0
tushki7	0:60d829a0353a	5031	#define UART_C2_RWU_MASK 0x2u
tushki7	0:60d829a0353a	5032	#define UART_C2_RWU_SHIFT 1
tushki7	0:60d829a0353a	5033	#define UART_C2_RE_MASK 0x4u
tushki7	0:60d829a0353a	5034	#define UART_C2_RE_SHIFT 2
tushki7	0:60d829a0353a	5035	#define UART_C2_TE_MASK 0x8u
tushki7	0:60d829a0353a	5036	#define UART_C2_TE_SHIFT 3
tushki7	0:60d829a0353a	5037	#define UART_C2_ILIE_MASK 0x10u
tushki7	0:60d829a0353a	5038	#define UART_C2_ILIE_SHIFT 4
tushki7	0:60d829a0353a	5039	#define UART_C2_RIE_MASK 0x20u
tushki7	0:60d829a0353a	5040	#define UART_C2_RIE_SHIFT 5
tushki7	0:60d829a0353a	5041	#define UART_C2_TCIE_MASK 0x40u
tushki7	0:60d829a0353a	5042	#define UART_C2_TCIE_SHIFT 6
tushki7	0:60d829a0353a	5043	#define UART_C2_TIE_MASK 0x80u
tushki7	0:60d829a0353a	5044	#define UART_C2_TIE_SHIFT 7
tushki7	0:60d829a0353a	5045	/* S1 Bit Fields */
tushki7	0:60d829a0353a	5046	#define UART_S1_PF_MASK 0x1u
tushki7	0:60d829a0353a	5047	#define UART_S1_PF_SHIFT 0
tushki7	0:60d829a0353a	5048	#define UART_S1_FE_MASK 0x2u
tushki7	0:60d829a0353a	5049	#define UART_S1_FE_SHIFT 1
tushki7	0:60d829a0353a	5050	#define UART_S1_NF_MASK 0x4u
tushki7	0:60d829a0353a	5051	#define UART_S1_NF_SHIFT 2
tushki7	0:60d829a0353a	5052	#define UART_S1_OR_MASK 0x8u
tushki7	0:60d829a0353a	5053	#define UART_S1_OR_SHIFT 3
tushki7	0:60d829a0353a	5054	#define UART_S1_IDLE_MASK 0x10u
tushki7	0:60d829a0353a	5055	#define UART_S1_IDLE_SHIFT 4
tushki7	0:60d829a0353a	5056	#define UART_S1_RDRF_MASK 0x20u
tushki7	0:60d829a0353a	5057	#define UART_S1_RDRF_SHIFT 5
tushki7	0:60d829a0353a	5058	#define UART_S1_TC_MASK 0x40u
tushki7	0:60d829a0353a	5059	#define UART_S1_TC_SHIFT 6
tushki7	0:60d829a0353a	5060	#define UART_S1_TDRE_MASK 0x80u
tushki7	0:60d829a0353a	5061	#define UART_S1_TDRE_SHIFT 7
tushki7	0:60d829a0353a	5062	/* S2 Bit Fields */
tushki7	0:60d829a0353a	5063	#define UART_S2_RAF_MASK 0x1u
tushki7	0:60d829a0353a	5064	#define UART_S2_RAF_SHIFT 0
tushki7	0:60d829a0353a	5065	#define UART_S2_LBKDE_MASK 0x2u
tushki7	0:60d829a0353a	5066	#define UART_S2_LBKDE_SHIFT 1
tushki7	0:60d829a0353a	5067	#define UART_S2_BRK13_MASK 0x4u
tushki7	0:60d829a0353a	5068	#define UART_S2_BRK13_SHIFT 2
tushki7	0:60d829a0353a	5069	#define UART_S2_RWUID_MASK 0x8u
tushki7	0:60d829a0353a	5070	#define UART_S2_RWUID_SHIFT 3
tushki7	0:60d829a0353a	5071	#define UART_S2_RXINV_MASK 0x10u
tushki7	0:60d829a0353a	5072	#define UART_S2_RXINV_SHIFT 4
tushki7	0:60d829a0353a	5073	#define UART_S2_MSBF_MASK 0x20u
tushki7	0:60d829a0353a	5074	#define UART_S2_MSBF_SHIFT 5
tushki7	0:60d829a0353a	5075	#define UART_S2_RXEDGIF_MASK 0x40u
tushki7	0:60d829a0353a	5076	#define UART_S2_RXEDGIF_SHIFT 6
tushki7	0:60d829a0353a	5077	#define UART_S2_LBKDIF_MASK 0x80u
tushki7	0:60d829a0353a	5078	#define UART_S2_LBKDIF_SHIFT 7
tushki7	0:60d829a0353a	5079	/* C3 Bit Fields */
tushki7	0:60d829a0353a	5080	#define UART_C3_PEIE_MASK 0x1u
tushki7	0:60d829a0353a	5081	#define UART_C3_PEIE_SHIFT 0
tushki7	0:60d829a0353a	5082	#define UART_C3_FEIE_MASK 0x2u
tushki7	0:60d829a0353a	5083	#define UART_C3_FEIE_SHIFT 1
tushki7	0:60d829a0353a	5084	#define UART_C3_NEIE_MASK 0x4u
tushki7	0:60d829a0353a	5085	#define UART_C3_NEIE_SHIFT 2
tushki7	0:60d829a0353a	5086	#define UART_C3_ORIE_MASK 0x8u
tushki7	0:60d829a0353a	5087	#define UART_C3_ORIE_SHIFT 3
tushki7	0:60d829a0353a	5088	#define UART_C3_TXINV_MASK 0x10u
tushki7	0:60d829a0353a	5089	#define UART_C3_TXINV_SHIFT 4
tushki7	0:60d829a0353a	5090	#define UART_C3_TXDIR_MASK 0x20u
tushki7	0:60d829a0353a	5091	#define UART_C3_TXDIR_SHIFT 5
tushki7	0:60d829a0353a	5092	#define UART_C3_T8_MASK 0x40u
tushki7	0:60d829a0353a	5093	#define UART_C3_T8_SHIFT 6
tushki7	0:60d829a0353a	5094	#define UART_C3_R8_MASK 0x80u
tushki7	0:60d829a0353a	5095	#define UART_C3_R8_SHIFT 7
tushki7	0:60d829a0353a	5096	/* D Bit Fields */
tushki7	0:60d829a0353a	5097	#define UART_D_RT_MASK 0xFFu
tushki7	0:60d829a0353a	5098	#define UART_D_RT_SHIFT 0
tushki7	0:60d829a0353a	5099	#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
tushki7	0:60d829a0353a	5100	/* MA1 Bit Fields */
tushki7	0:60d829a0353a	5101	#define UART_MA1_MA_MASK 0xFFu
tushki7	0:60d829a0353a	5102	#define UART_MA1_MA_SHIFT 0
tushki7	0:60d829a0353a	5103	#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
tushki7	0:60d829a0353a	5104	/* MA2 Bit Fields */
tushki7	0:60d829a0353a	5105	#define UART_MA2_MA_MASK 0xFFu
tushki7	0:60d829a0353a	5106	#define UART_MA2_MA_SHIFT 0
tushki7	0:60d829a0353a	5107	#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
tushki7	0:60d829a0353a	5108	/* C4 Bit Fields */
tushki7	0:60d829a0353a	5109	#define UART_C4_BRFA_MASK 0x1Fu
tushki7	0:60d829a0353a	5110	#define UART_C4_BRFA_SHIFT 0
tushki7	0:60d829a0353a	5111	#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
tushki7	0:60d829a0353a	5112	#define UART_C4_M10_MASK 0x20u
tushki7	0:60d829a0353a	5113	#define UART_C4_M10_SHIFT 5
tushki7	0:60d829a0353a	5114	#define UART_C4_MAEN2_MASK 0x40u
tushki7	0:60d829a0353a	5115	#define UART_C4_MAEN2_SHIFT 6
tushki7	0:60d829a0353a	5116	#define UART_C4_MAEN1_MASK 0x80u
tushki7	0:60d829a0353a	5117	#define UART_C4_MAEN1_SHIFT 7
tushki7	0:60d829a0353a	5118	/* C5 Bit Fields */
tushki7	0:60d829a0353a	5119	#define UART_C5_RDMAS_MASK 0x20u
tushki7	0:60d829a0353a	5120	#define UART_C5_RDMAS_SHIFT 5
tushki7	0:60d829a0353a	5121	#define UART_C5_TDMAS_MASK 0x80u
tushki7	0:60d829a0353a	5122	#define UART_C5_TDMAS_SHIFT 7
tushki7	0:60d829a0353a	5123	/* ED Bit Fields */
tushki7	0:60d829a0353a	5124	#define UART_ED_PARITYE_MASK 0x40u
tushki7	0:60d829a0353a	5125	#define UART_ED_PARITYE_SHIFT 6
tushki7	0:60d829a0353a	5126	#define UART_ED_NOISY_MASK 0x80u
tushki7	0:60d829a0353a	5127	#define UART_ED_NOISY_SHIFT 7
tushki7	0:60d829a0353a	5128	/* MODEM Bit Fields */
tushki7	0:60d829a0353a	5129	#define UART_MODEM_TXCTSE_MASK 0x1u
tushki7	0:60d829a0353a	5130	#define UART_MODEM_TXCTSE_SHIFT 0
tushki7	0:60d829a0353a	5131	#define UART_MODEM_TXRTSE_MASK 0x2u
tushki7	0:60d829a0353a	5132	#define UART_MODEM_TXRTSE_SHIFT 1
tushki7	0:60d829a0353a	5133	#define UART_MODEM_TXRTSPOL_MASK 0x4u
tushki7	0:60d829a0353a	5134	#define UART_MODEM_TXRTSPOL_SHIFT 2
tushki7	0:60d829a0353a	5135	#define UART_MODEM_RXRTSE_MASK 0x8u
tushki7	0:60d829a0353a	5136	#define UART_MODEM_RXRTSE_SHIFT 3
tushki7	0:60d829a0353a	5137	/* IR Bit Fields */
tushki7	0:60d829a0353a	5138	#define UART_IR_TNP_MASK 0x3u
tushki7	0:60d829a0353a	5139	#define UART_IR_TNP_SHIFT 0
tushki7	0:60d829a0353a	5140	#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
tushki7	0:60d829a0353a	5141	#define UART_IR_IREN_MASK 0x4u
tushki7	0:60d829a0353a	5142	#define UART_IR_IREN_SHIFT 2
tushki7	0:60d829a0353a	5143	/* PFIFO Bit Fields */
tushki7	0:60d829a0353a	5144	#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
tushki7	0:60d829a0353a	5145	#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
tushki7	0:60d829a0353a	5146	#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
tushki7	0:60d829a0353a	5147	#define UART_PFIFO_RXFE_MASK 0x8u
tushki7	0:60d829a0353a	5148	#define UART_PFIFO_RXFE_SHIFT 3
tushki7	0:60d829a0353a	5149	#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
tushki7	0:60d829a0353a	5150	#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
tushki7	0:60d829a0353a	5151	#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
tushki7	0:60d829a0353a	5152	#define UART_PFIFO_TXFE_MASK 0x80u
tushki7	0:60d829a0353a	5153	#define UART_PFIFO_TXFE_SHIFT 7
tushki7	0:60d829a0353a	5154	/* CFIFO Bit Fields */
tushki7	0:60d829a0353a	5155	#define UART_CFIFO_RXUFE_MASK 0x1u
tushki7	0:60d829a0353a	5156	#define UART_CFIFO_RXUFE_SHIFT 0
tushki7	0:60d829a0353a	5157	#define UART_CFIFO_TXOFE_MASK 0x2u
tushki7	0:60d829a0353a	5158	#define UART_CFIFO_TXOFE_SHIFT 1
tushki7	0:60d829a0353a	5159	#define UART_CFIFO_RXFLUSH_MASK 0x40u
tushki7	0:60d829a0353a	5160	#define UART_CFIFO_RXFLUSH_SHIFT 6
tushki7	0:60d829a0353a	5161	#define UART_CFIFO_TXFLUSH_MASK 0x80u
tushki7	0:60d829a0353a	5162	#define UART_CFIFO_TXFLUSH_SHIFT 7
tushki7	0:60d829a0353a	5163	/* SFIFO Bit Fields */
tushki7	0:60d829a0353a	5164	#define UART_SFIFO_RXUF_MASK 0x1u
tushki7	0:60d829a0353a	5165	#define UART_SFIFO_RXUF_SHIFT 0
tushki7	0:60d829a0353a	5166	#define UART_SFIFO_TXOF_MASK 0x2u
tushki7	0:60d829a0353a	5167	#define UART_SFIFO_TXOF_SHIFT 1
tushki7	0:60d829a0353a	5168	#define UART_SFIFO_RXEMPT_MASK 0x40u
tushki7	0:60d829a0353a	5169	#define UART_SFIFO_RXEMPT_SHIFT 6
tushki7	0:60d829a0353a	5170	#define UART_SFIFO_TXEMPT_MASK 0x80u
tushki7	0:60d829a0353a	5171	#define UART_SFIFO_TXEMPT_SHIFT 7
tushki7	0:60d829a0353a	5172	/* TWFIFO Bit Fields */
tushki7	0:60d829a0353a	5173	#define UART_TWFIFO_TXWATER_MASK 0xFFu
tushki7	0:60d829a0353a	5174	#define UART_TWFIFO_TXWATER_SHIFT 0
tushki7	0:60d829a0353a	5175	#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
tushki7	0:60d829a0353a	5176	/* TCFIFO Bit Fields */
tushki7	0:60d829a0353a	5177	#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
tushki7	0:60d829a0353a	5178	#define UART_TCFIFO_TXCOUNT_SHIFT 0
tushki7	0:60d829a0353a	5179	#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
tushki7	0:60d829a0353a	5180	/* RWFIFO Bit Fields */
tushki7	0:60d829a0353a	5181	#define UART_RWFIFO_RXWATER_MASK 0xFFu
tushki7	0:60d829a0353a	5182	#define UART_RWFIFO_RXWATER_SHIFT 0
tushki7	0:60d829a0353a	5183	#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
tushki7	0:60d829a0353a	5184	/* RCFIFO Bit Fields */
tushki7	0:60d829a0353a	5185	#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
tushki7	0:60d829a0353a	5186	#define UART_RCFIFO_RXCOUNT_SHIFT 0
tushki7	0:60d829a0353a	5187	#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
tushki7	0:60d829a0353a	5188	/* C7816 Bit Fields */
tushki7	0:60d829a0353a	5189	#define UART_C7816_ISO_7816E_MASK 0x1u
tushki7	0:60d829a0353a	5190	#define UART_C7816_ISO_7816E_SHIFT 0
tushki7	0:60d829a0353a	5191	#define UART_C7816_TTYPE_MASK 0x2u
tushki7	0:60d829a0353a	5192	#define UART_C7816_TTYPE_SHIFT 1
tushki7	0:60d829a0353a	5193	#define UART_C7816_INIT_MASK 0x4u
tushki7	0:60d829a0353a	5194	#define UART_C7816_INIT_SHIFT 2
tushki7	0:60d829a0353a	5195	#define UART_C7816_ANACK_MASK 0x8u
tushki7	0:60d829a0353a	5196	#define UART_C7816_ANACK_SHIFT 3
tushki7	0:60d829a0353a	5197	#define UART_C7816_ONACK_MASK 0x10u
tushki7	0:60d829a0353a	5198	#define UART_C7816_ONACK_SHIFT 4
tushki7	0:60d829a0353a	5199	/* IE7816 Bit Fields */
tushki7	0:60d829a0353a	5200	#define UART_IE7816_RXTE_MASK 0x1u
tushki7	0:60d829a0353a	5201	#define UART_IE7816_RXTE_SHIFT 0
tushki7	0:60d829a0353a	5202	#define UART_IE7816_TXTE_MASK 0x2u
tushki7	0:60d829a0353a	5203	#define UART_IE7816_TXTE_SHIFT 1
tushki7	0:60d829a0353a	5204	#define UART_IE7816_GTVE_MASK 0x4u
tushki7	0:60d829a0353a	5205	#define UART_IE7816_GTVE_SHIFT 2
tushki7	0:60d829a0353a	5206	#define UART_IE7816_INITDE_MASK 0x10u
tushki7	0:60d829a0353a	5207	#define UART_IE7816_INITDE_SHIFT 4
tushki7	0:60d829a0353a	5208	#define UART_IE7816_BWTE_MASK 0x20u
tushki7	0:60d829a0353a	5209	#define UART_IE7816_BWTE_SHIFT 5
tushki7	0:60d829a0353a	5210	#define UART_IE7816_CWTE_MASK 0x40u
tushki7	0:60d829a0353a	5211	#define UART_IE7816_CWTE_SHIFT 6
tushki7	0:60d829a0353a	5212	#define UART_IE7816_WTE_MASK 0x80u
tushki7	0:60d829a0353a	5213	#define UART_IE7816_WTE_SHIFT 7
tushki7	0:60d829a0353a	5214	/* IS7816 Bit Fields */
tushki7	0:60d829a0353a	5215	#define UART_IS7816_RXT_MASK 0x1u
tushki7	0:60d829a0353a	5216	#define UART_IS7816_RXT_SHIFT 0
tushki7	0:60d829a0353a	5217	#define UART_IS7816_TXT_MASK 0x2u
tushki7	0:60d829a0353a	5218	#define UART_IS7816_TXT_SHIFT 1
tushki7	0:60d829a0353a	5219	#define UART_IS7816_GTV_MASK 0x4u
tushki7	0:60d829a0353a	5220	#define UART_IS7816_GTV_SHIFT 2
tushki7	0:60d829a0353a	5221	#define UART_IS7816_INITD_MASK 0x10u
tushki7	0:60d829a0353a	5222	#define UART_IS7816_INITD_SHIFT 4
tushki7	0:60d829a0353a	5223	#define UART_IS7816_BWT_MASK 0x20u
tushki7	0:60d829a0353a	5224	#define UART_IS7816_BWT_SHIFT 5
tushki7	0:60d829a0353a	5225	#define UART_IS7816_CWT_MASK 0x40u
tushki7	0:60d829a0353a	5226	#define UART_IS7816_CWT_SHIFT 6
tushki7	0:60d829a0353a	5227	#define UART_IS7816_WT_MASK 0x80u
tushki7	0:60d829a0353a	5228	#define UART_IS7816_WT_SHIFT 7
tushki7	0:60d829a0353a	5229	/* WP7816_T_TYPE0 Bit Fields */
tushki7	0:60d829a0353a	5230	#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
tushki7	0:60d829a0353a	5231	#define UART_WP7816_T_TYPE0_WI_SHIFT 0
tushki7	0:60d829a0353a	5232	#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
tushki7	0:60d829a0353a	5233	/* WP7816_T_TYPE1 Bit Fields */
tushki7	0:60d829a0353a	5234	#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
tushki7	0:60d829a0353a	5235	#define UART_WP7816_T_TYPE1_BWI_SHIFT 0
tushki7	0:60d829a0353a	5236	#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
tushki7	0:60d829a0353a	5237	#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
tushki7	0:60d829a0353a	5238	#define UART_WP7816_T_TYPE1_CWI_SHIFT 4
tushki7	0:60d829a0353a	5239	#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
tushki7	0:60d829a0353a	5240	/* WN7816 Bit Fields */
tushki7	0:60d829a0353a	5241	#define UART_WN7816_GTN_MASK 0xFFu
tushki7	0:60d829a0353a	5242	#define UART_WN7816_GTN_SHIFT 0
tushki7	0:60d829a0353a	5243	#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
tushki7	0:60d829a0353a	5244	/* WF7816 Bit Fields */
tushki7	0:60d829a0353a	5245	#define UART_WF7816_GTFD_MASK 0xFFu
tushki7	0:60d829a0353a	5246	#define UART_WF7816_GTFD_SHIFT 0
tushki7	0:60d829a0353a	5247	#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
tushki7	0:60d829a0353a	5248	/* ET7816 Bit Fields */
tushki7	0:60d829a0353a	5249	#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
tushki7	0:60d829a0353a	5250	#define UART_ET7816_RXTHRESHOLD_SHIFT 0
tushki7	0:60d829a0353a	5251	#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
tushki7	0:60d829a0353a	5252	#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
tushki7	0:60d829a0353a	5253	#define UART_ET7816_TXTHRESHOLD_SHIFT 4
tushki7	0:60d829a0353a	5254	#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
tushki7	0:60d829a0353a	5255	/* TL7816 Bit Fields */
tushki7	0:60d829a0353a	5256	#define UART_TL7816_TLEN_MASK 0xFFu
tushki7	0:60d829a0353a	5257	#define UART_TL7816_TLEN_SHIFT 0
tushki7	0:60d829a0353a	5258	#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
tushki7	0:60d829a0353a	5259	/* C6 Bit Fields */
tushki7	0:60d829a0353a	5260	#define UART_C6_CP_MASK 0x10u
tushki7	0:60d829a0353a	5261	#define UART_C6_CP_SHIFT 4
tushki7	0:60d829a0353a	5262	#define UART_C6_CE_MASK 0x20u
tushki7	0:60d829a0353a	5263	#define UART_C6_CE_SHIFT 5
tushki7	0:60d829a0353a	5264	#define UART_C6_TX709_MASK 0x40u
tushki7	0:60d829a0353a	5265	#define UART_C6_TX709_SHIFT 6
tushki7	0:60d829a0353a	5266	#define UART_C6_EN709_MASK 0x80u
tushki7	0:60d829a0353a	5267	#define UART_C6_EN709_SHIFT 7
tushki7	0:60d829a0353a	5268	/* PCTH Bit Fields */
tushki7	0:60d829a0353a	5269	#define UART_PCTH_PCTH_MASK 0xFFu
tushki7	0:60d829a0353a	5270	#define UART_PCTH_PCTH_SHIFT 0
tushki7	0:60d829a0353a	5271	#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
tushki7	0:60d829a0353a	5272	/* PCTL Bit Fields */
tushki7	0:60d829a0353a	5273	#define UART_PCTL_PCTL_MASK 0xFFu
tushki7	0:60d829a0353a	5274	#define UART_PCTL_PCTL_SHIFT 0
tushki7	0:60d829a0353a	5275	#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
tushki7	0:60d829a0353a	5276	/* B1T Bit Fields */
tushki7	0:60d829a0353a	5277	#define UART_B1T_B1T_MASK 0xFFu
tushki7	0:60d829a0353a	5278	#define UART_B1T_B1T_SHIFT 0
tushki7	0:60d829a0353a	5279	#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
tushki7	0:60d829a0353a	5280	/* SDTH Bit Fields */
tushki7	0:60d829a0353a	5281	#define UART_SDTH_SDTH_MASK 0xFFu
tushki7	0:60d829a0353a	5282	#define UART_SDTH_SDTH_SHIFT 0
tushki7	0:60d829a0353a	5283	#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
tushki7	0:60d829a0353a	5284	/* SDTL Bit Fields */
tushki7	0:60d829a0353a	5285	#define UART_SDTL_SDTL_MASK 0xFFu
tushki7	0:60d829a0353a	5286	#define UART_SDTL_SDTL_SHIFT 0
tushki7	0:60d829a0353a	5287	#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
tushki7	0:60d829a0353a	5288	/* PRE Bit Fields */
tushki7	0:60d829a0353a	5289	#define UART_PRE_PREAMBLE_MASK 0xFFu
tushki7	0:60d829a0353a	5290	#define UART_PRE_PREAMBLE_SHIFT 0
tushki7	0:60d829a0353a	5291	#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
tushki7	0:60d829a0353a	5292	/* TPL Bit Fields */
tushki7	0:60d829a0353a	5293	#define UART_TPL_TPL_MASK 0xFFu
tushki7	0:60d829a0353a	5294	#define UART_TPL_TPL_SHIFT 0
tushki7	0:60d829a0353a	5295	#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
tushki7	0:60d829a0353a	5296	/* IE Bit Fields */
tushki7	0:60d829a0353a	5297	#define UART_IE_TXFIE_MASK 0x1u
tushki7	0:60d829a0353a	5298	#define UART_IE_TXFIE_SHIFT 0
tushki7	0:60d829a0353a	5299	#define UART_IE_PSIE_MASK 0x2u
tushki7	0:60d829a0353a	5300	#define UART_IE_PSIE_SHIFT 1
tushki7	0:60d829a0353a	5301	#define UART_IE_PCTEIE_MASK 0x4u
tushki7	0:60d829a0353a	5302	#define UART_IE_PCTEIE_SHIFT 2
tushki7	0:60d829a0353a	5303	#define UART_IE_PTXIE_MASK 0x8u
tushki7	0:60d829a0353a	5304	#define UART_IE_PTXIE_SHIFT 3
tushki7	0:60d829a0353a	5305	#define UART_IE_PRXIE_MASK 0x10u
tushki7	0:60d829a0353a	5306	#define UART_IE_PRXIE_SHIFT 4
tushki7	0:60d829a0353a	5307	#define UART_IE_ISDIE_MASK 0x20u
tushki7	0:60d829a0353a	5308	#define UART_IE_ISDIE_SHIFT 5
tushki7	0:60d829a0353a	5309	#define UART_IE_WBEIE_MASK 0x40u
tushki7	0:60d829a0353a	5310	#define UART_IE_WBEIE_SHIFT 6
tushki7	0:60d829a0353a	5311	/* WB Bit Fields */
tushki7	0:60d829a0353a	5312	#define UART_WB_WBASE_MASK 0xFFu
tushki7	0:60d829a0353a	5313	#define UART_WB_WBASE_SHIFT 0
tushki7	0:60d829a0353a	5314	#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
tushki7	0:60d829a0353a	5315	/* S3 Bit Fields */
tushki7	0:60d829a0353a	5316	#define UART_S3_TXFF_MASK 0x1u
tushki7	0:60d829a0353a	5317	#define UART_S3_TXFF_SHIFT 0
tushki7	0:60d829a0353a	5318	#define UART_S3_PSF_MASK 0x2u
tushki7	0:60d829a0353a	5319	#define UART_S3_PSF_SHIFT 1
tushki7	0:60d829a0353a	5320	#define UART_S3_PCTEF_MASK 0x4u
tushki7	0:60d829a0353a	5321	#define UART_S3_PCTEF_SHIFT 2
tushki7	0:60d829a0353a	5322	#define UART_S3_PTXF_MASK 0x8u
tushki7	0:60d829a0353a	5323	#define UART_S3_PTXF_SHIFT 3
tushki7	0:60d829a0353a	5324	#define UART_S3_PRXF_MASK 0x10u
tushki7	0:60d829a0353a	5325	#define UART_S3_PRXF_SHIFT 4
tushki7	0:60d829a0353a	5326	#define UART_S3_ISD_MASK 0x20u
tushki7	0:60d829a0353a	5327	#define UART_S3_ISD_SHIFT 5
tushki7	0:60d829a0353a	5328	#define UART_S3_WBEF_MASK 0x40u
tushki7	0:60d829a0353a	5329	#define UART_S3_WBEF_SHIFT 6
tushki7	0:60d829a0353a	5330	#define UART_S3_PEF_MASK 0x80u
tushki7	0:60d829a0353a	5331	#define UART_S3_PEF_SHIFT 7
tushki7	0:60d829a0353a	5332	/* S4 Bit Fields */
tushki7	0:60d829a0353a	5333	#define UART_S4_FE_MASK 0x1u
tushki7	0:60d829a0353a	5334	#define UART_S4_FE_SHIFT 0
tushki7	0:60d829a0353a	5335	#define UART_S4_ILCV_MASK 0x2u
tushki7	0:60d829a0353a	5336	#define UART_S4_ILCV_SHIFT 1
tushki7	0:60d829a0353a	5337	#define UART_S4_CDET_MASK 0xCu
tushki7	0:60d829a0353a	5338	#define UART_S4_CDET_SHIFT 2
tushki7	0:60d829a0353a	5339	#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
tushki7	0:60d829a0353a	5340	#define UART_S4_INITF_MASK 0x10u
tushki7	0:60d829a0353a	5341	#define UART_S4_INITF_SHIFT 4
tushki7	0:60d829a0353a	5342	/* RPL Bit Fields */
tushki7	0:60d829a0353a	5343	#define UART_RPL_RPL_MASK 0xFFu
tushki7	0:60d829a0353a	5344	#define UART_RPL_RPL_SHIFT 0
tushki7	0:60d829a0353a	5345	#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
tushki7	0:60d829a0353a	5346	/* RPREL Bit Fields */
tushki7	0:60d829a0353a	5347	#define UART_RPREL_RPREL_MASK 0xFFu
tushki7	0:60d829a0353a	5348	#define UART_RPREL_RPREL_SHIFT 0
tushki7	0:60d829a0353a	5349	#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
tushki7	0:60d829a0353a	5350	/* CPW Bit Fields */
tushki7	0:60d829a0353a	5351	#define UART_CPW_CPW_MASK 0xFFu
tushki7	0:60d829a0353a	5352	#define UART_CPW_CPW_SHIFT 0
tushki7	0:60d829a0353a	5353	#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
tushki7	0:60d829a0353a	5354	/* RIDT Bit Fields */
tushki7	0:60d829a0353a	5355	#define UART_RIDT_RIDT_MASK 0xFFu
tushki7	0:60d829a0353a	5356	#define UART_RIDT_RIDT_SHIFT 0
tushki7	0:60d829a0353a	5357	#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
tushki7	0:60d829a0353a	5358	/* TIDT Bit Fields */
tushki7	0:60d829a0353a	5359	#define UART_TIDT_TIDT_MASK 0xFFu
tushki7	0:60d829a0353a	5360	#define UART_TIDT_TIDT_SHIFT 0
tushki7	0:60d829a0353a	5361	#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
tushki7	0:60d829a0353a	5362
tushki7	0:60d829a0353a	5363	/**
tushki7	0:60d829a0353a	5364	* @}
tushki7	0:60d829a0353a	5365	/ / end of group UART_Register_Masks */
tushki7	0:60d829a0353a	5366
tushki7	0:60d829a0353a	5367
tushki7	0:60d829a0353a	5368	/* UART - Peripheral instance base addresses */
tushki7	0:60d829a0353a	5369	/** Peripheral UART0 base address */
tushki7	0:60d829a0353a	5370	#define UART0_BASE (0x4006A000u)
tushki7	0:60d829a0353a	5371	/** Peripheral UART0 base pointer */
tushki7	0:60d829a0353a	5372	#define UART0 ((UART_Type *)UART0_BASE)
tushki7	0:60d829a0353a	5373	/** Peripheral UART1 base address */
tushki7	0:60d829a0353a	5374	#define UART1_BASE (0x4006B000u)
tushki7	0:60d829a0353a	5375	/** Peripheral UART1 base pointer */
tushki7	0:60d829a0353a	5376	#define UART1 ((UART_Type *)UART1_BASE)
tushki7	0:60d829a0353a	5377	/** Peripheral UART2 base address */
tushki7	0:60d829a0353a	5378	#define UART2_BASE (0x4006C000u)
tushki7	0:60d829a0353a	5379	/** Peripheral UART2 base pointer */
tushki7	0:60d829a0353a	5380	#define UART2 ((UART_Type *)UART2_BASE)
tushki7	0:60d829a0353a	5381
tushki7	0:60d829a0353a	5382	/**
tushki7	0:60d829a0353a	5383	* @}
tushki7	0:60d829a0353a	5384	/ / end of group UART_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	5385
tushki7	0:60d829a0353a	5386
tushki7	0:60d829a0353a	5387	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	5388	-- USB Peripheral Access Layer
tushki7	0:60d829a0353a	5389	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	5390
tushki7	0:60d829a0353a	5391	/**
tushki7	0:60d829a0353a	5392	* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
tushki7	0:60d829a0353a	5393	* @{
tushki7	0:60d829a0353a	5394	*/
tushki7	0:60d829a0353a	5395
tushki7	0:60d829a0353a	5396	/** USB - Register Layout Typedef */
tushki7	0:60d829a0353a	5397	typedef struct {
tushki7	0:60d829a0353a	5398	__I uint8_t PERID; /*< Peripheral ID Register, offset: 0x0 /
tushki7	0:60d829a0353a	5399	uint8_t RESERVED_0[3];
tushki7	0:60d829a0353a	5400	__I uint8_t IDCOMP; /*< Peripheral ID Complement Register, offset: 0x4 /
tushki7	0:60d829a0353a	5401	uint8_t RESERVED_1[3];
tushki7	0:60d829a0353a	5402	__I uint8_t REV; /*< Peripheral Revision Register, offset: 0x8 /
tushki7	0:60d829a0353a	5403	uint8_t RESERVED_2[3];
tushki7	0:60d829a0353a	5404	__I uint8_t ADDINFO; /*< Peripheral Additional Info Register, offset: 0xC /
tushki7	0:60d829a0353a	5405	uint8_t RESERVED_3[3];
tushki7	0:60d829a0353a	5406	__IO uint8_t OTGISTAT; /*< OTG Interrupt Status Register, offset: 0x10 /
tushki7	0:60d829a0353a	5407	uint8_t RESERVED_4[3];
tushki7	0:60d829a0353a	5408	__IO uint8_t OTGICR; /*< OTG Interrupt Control Register, offset: 0x14 /
tushki7	0:60d829a0353a	5409	uint8_t RESERVED_5[3];
tushki7	0:60d829a0353a	5410	__IO uint8_t OTGSTAT; /*< OTG Status Register, offset: 0x18 /
tushki7	0:60d829a0353a	5411	uint8_t RESERVED_6[3];
tushki7	0:60d829a0353a	5412	__IO uint8_t OTGCTL; /*< OTG Control Register, offset: 0x1C /
tushki7	0:60d829a0353a	5413	uint8_t RESERVED_7[99];
tushki7	0:60d829a0353a	5414	__IO uint8_t ISTAT; /*< Interrupt Status Register, offset: 0x80 /
tushki7	0:60d829a0353a	5415	uint8_t RESERVED_8[3];
tushki7	0:60d829a0353a	5416	__IO uint8_t INTEN; /*< Interrupt Enable Register, offset: 0x84 /
tushki7	0:60d829a0353a	5417	uint8_t RESERVED_9[3];
tushki7	0:60d829a0353a	5418	__IO uint8_t ERRSTAT; /*< Error Interrupt Status Register, offset: 0x88 /
tushki7	0:60d829a0353a	5419	uint8_t RESERVED_10[3];
tushki7	0:60d829a0353a	5420	__IO uint8_t ERREN; /*< Error Interrupt Enable Register, offset: 0x8C /
tushki7	0:60d829a0353a	5421	uint8_t RESERVED_11[3];
tushki7	0:60d829a0353a	5422	__I uint8_t STAT; /*< Status Register, offset: 0x90 /
tushki7	0:60d829a0353a	5423	uint8_t RESERVED_12[3];
tushki7	0:60d829a0353a	5424	__IO uint8_t CTL; /*< Control Register, offset: 0x94 /
tushki7	0:60d829a0353a	5425	uint8_t RESERVED_13[3];
tushki7	0:60d829a0353a	5426	__IO uint8_t ADDR; /*< Address Register, offset: 0x98 /
tushki7	0:60d829a0353a	5427	uint8_t RESERVED_14[3];
tushki7	0:60d829a0353a	5428	__IO uint8_t BDTPAGE1; /*< BDT Page Register 1, offset: 0x9C /
tushki7	0:60d829a0353a	5429	uint8_t RESERVED_15[3];
tushki7	0:60d829a0353a	5430	__IO uint8_t FRMNUML; /*< Frame Number Register Low, offset: 0xA0 /
tushki7	0:60d829a0353a	5431	uint8_t RESERVED_16[3];
tushki7	0:60d829a0353a	5432	__IO uint8_t FRMNUMH; /*< Frame Number Register High, offset: 0xA4 /
tushki7	0:60d829a0353a	5433	uint8_t RESERVED_17[3];
tushki7	0:60d829a0353a	5434	__IO uint8_t TOKEN; /*< Token Register, offset: 0xA8 /
tushki7	0:60d829a0353a	5435	uint8_t RESERVED_18[3];
tushki7	0:60d829a0353a	5436	__IO uint8_t SOFTHLD; /*< SOF Threshold Register, offset: 0xAC /
tushki7	0:60d829a0353a	5437	uint8_t RESERVED_19[3];
tushki7	0:60d829a0353a	5438	__IO uint8_t BDTPAGE2; /*< BDT Page Register 2, offset: 0xB0 /
tushki7	0:60d829a0353a	5439	uint8_t RESERVED_20[3];
tushki7	0:60d829a0353a	5440	__IO uint8_t BDTPAGE3; /*< BDT Page Register 3, offset: 0xB4 /
tushki7	0:60d829a0353a	5441	uint8_t RESERVED_21[11];
tushki7	0:60d829a0353a	5442	struct { /* offset: 0xC0, array step: 0x4 */
tushki7	0:60d829a0353a	5443	__IO uint8_t ENDPT; /*< Endpoint Control Register, array offset: 0xC0, array step: 0x4 /
tushki7	0:60d829a0353a	5444	uint8_t RESERVED_0[3];
tushki7	0:60d829a0353a	5445	} ENDPOINT[16];
tushki7	0:60d829a0353a	5446	__IO uint8_t USBCTRL; /*< USB Control Register, offset: 0x100 /
tushki7	0:60d829a0353a	5447	uint8_t RESERVED_22[3];
tushki7	0:60d829a0353a	5448	__I uint8_t OBSERVE; /*< USB OTG Observe Register, offset: 0x104 /
tushki7	0:60d829a0353a	5449	uint8_t RESERVED_23[3];
tushki7	0:60d829a0353a	5450	__IO uint8_t CONTROL; /*< USB OTG Control Register, offset: 0x108 /
tushki7	0:60d829a0353a	5451	uint8_t RESERVED_24[3];
tushki7	0:60d829a0353a	5452	__IO uint8_t USBTRC0; /*< USB Transceiver Control Register 0, offset: 0x10C /
tushki7	0:60d829a0353a	5453	uint8_t RESERVED_25[7];
tushki7	0:60d829a0353a	5454	__IO uint8_t USBFRMADJUST; /*< Frame Adjust Register, offset: 0x114 /
tushki7	0:60d829a0353a	5455	} USB_Type;
tushki7	0:60d829a0353a	5456
tushki7	0:60d829a0353a	5457	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	5458	-- USB Register Masks
tushki7	0:60d829a0353a	5459	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	5460
tushki7	0:60d829a0353a	5461	/**
tushki7	0:60d829a0353a	5462	* @addtogroup USB_Register_Masks USB Register Masks
tushki7	0:60d829a0353a	5463	* @{
tushki7	0:60d829a0353a	5464	*/
tushki7	0:60d829a0353a	5465
tushki7	0:60d829a0353a	5466	/* PERID Bit Fields */
tushki7	0:60d829a0353a	5467	#define USB_PERID_ID_MASK 0x3Fu
tushki7	0:60d829a0353a	5468	#define USB_PERID_ID_SHIFT 0
tushki7	0:60d829a0353a	5469	#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
tushki7	0:60d829a0353a	5470	/* IDCOMP Bit Fields */
tushki7	0:60d829a0353a	5471	#define USB_IDCOMP_NID_MASK 0x3Fu
tushki7	0:60d829a0353a	5472	#define USB_IDCOMP_NID_SHIFT 0
tushki7	0:60d829a0353a	5473	#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
tushki7	0:60d829a0353a	5474	/* REV Bit Fields */
tushki7	0:60d829a0353a	5475	#define USB_REV_REV_MASK 0xFFu
tushki7	0:60d829a0353a	5476	#define USB_REV_REV_SHIFT 0
tushki7	0:60d829a0353a	5477	#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
tushki7	0:60d829a0353a	5478	/* ADDINFO Bit Fields */
tushki7	0:60d829a0353a	5479	#define USB_ADDINFO_IEHOST_MASK 0x1u
tushki7	0:60d829a0353a	5480	#define USB_ADDINFO_IEHOST_SHIFT 0
tushki7	0:60d829a0353a	5481	#define USB_ADDINFO_IRQNUM_MASK 0xF8u
tushki7	0:60d829a0353a	5482	#define USB_ADDINFO_IRQNUM_SHIFT 3
tushki7	0:60d829a0353a	5483	#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
tushki7	0:60d829a0353a	5484	/* OTGISTAT Bit Fields */
tushki7	0:60d829a0353a	5485	#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
tushki7	0:60d829a0353a	5486	#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
tushki7	0:60d829a0353a	5487	#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
tushki7	0:60d829a0353a	5488	#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
tushki7	0:60d829a0353a	5489	#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
tushki7	0:60d829a0353a	5490	#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
tushki7	0:60d829a0353a	5491	#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
tushki7	0:60d829a0353a	5492	#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
tushki7	0:60d829a0353a	5493	#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
tushki7	0:60d829a0353a	5494	#define USB_OTGISTAT_ONEMSEC_SHIFT 6
tushki7	0:60d829a0353a	5495	#define USB_OTGISTAT_IDCHG_MASK 0x80u
tushki7	0:60d829a0353a	5496	#define USB_OTGISTAT_IDCHG_SHIFT 7
tushki7	0:60d829a0353a	5497	/* OTGICR Bit Fields */
tushki7	0:60d829a0353a	5498	#define USB_OTGICR_AVBUSEN_MASK 0x1u
tushki7	0:60d829a0353a	5499	#define USB_OTGICR_AVBUSEN_SHIFT 0
tushki7	0:60d829a0353a	5500	#define USB_OTGICR_BSESSEN_MASK 0x4u
tushki7	0:60d829a0353a	5501	#define USB_OTGICR_BSESSEN_SHIFT 2
tushki7	0:60d829a0353a	5502	#define USB_OTGICR_SESSVLDEN_MASK 0x8u
tushki7	0:60d829a0353a	5503	#define USB_OTGICR_SESSVLDEN_SHIFT 3
tushki7	0:60d829a0353a	5504	#define USB_OTGICR_LINESTATEEN_MASK 0x20u
tushki7	0:60d829a0353a	5505	#define USB_OTGICR_LINESTATEEN_SHIFT 5
tushki7	0:60d829a0353a	5506	#define USB_OTGICR_ONEMSECEN_MASK 0x40u
tushki7	0:60d829a0353a	5507	#define USB_OTGICR_ONEMSECEN_SHIFT 6
tushki7	0:60d829a0353a	5508	#define USB_OTGICR_IDEN_MASK 0x80u
tushki7	0:60d829a0353a	5509	#define USB_OTGICR_IDEN_SHIFT 7
tushki7	0:60d829a0353a	5510	/* OTGSTAT Bit Fields */
tushki7	0:60d829a0353a	5511	#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
tushki7	0:60d829a0353a	5512	#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
tushki7	0:60d829a0353a	5513	#define USB_OTGSTAT_BSESSEND_MASK 0x4u
tushki7	0:60d829a0353a	5514	#define USB_OTGSTAT_BSESSEND_SHIFT 2
tushki7	0:60d829a0353a	5515	#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
tushki7	0:60d829a0353a	5516	#define USB_OTGSTAT_SESS_VLD_SHIFT 3
tushki7	0:60d829a0353a	5517	#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
tushki7	0:60d829a0353a	5518	#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
tushki7	0:60d829a0353a	5519	#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
tushki7	0:60d829a0353a	5520	#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
tushki7	0:60d829a0353a	5521	#define USB_OTGSTAT_ID_MASK 0x80u
tushki7	0:60d829a0353a	5522	#define USB_OTGSTAT_ID_SHIFT 7
tushki7	0:60d829a0353a	5523	/* OTGCTL Bit Fields */
tushki7	0:60d829a0353a	5524	#define USB_OTGCTL_OTGEN_MASK 0x4u
tushki7	0:60d829a0353a	5525	#define USB_OTGCTL_OTGEN_SHIFT 2
tushki7	0:60d829a0353a	5526	#define USB_OTGCTL_DMLOW_MASK 0x10u
tushki7	0:60d829a0353a	5527	#define USB_OTGCTL_DMLOW_SHIFT 4
tushki7	0:60d829a0353a	5528	#define USB_OTGCTL_DPLOW_MASK 0x20u
tushki7	0:60d829a0353a	5529	#define USB_OTGCTL_DPLOW_SHIFT 5
tushki7	0:60d829a0353a	5530	#define USB_OTGCTL_DPHIGH_MASK 0x80u
tushki7	0:60d829a0353a	5531	#define USB_OTGCTL_DPHIGH_SHIFT 7
tushki7	0:60d829a0353a	5532	/* ISTAT Bit Fields */
tushki7	0:60d829a0353a	5533	#define USB_ISTAT_USBRST_MASK 0x1u
tushki7	0:60d829a0353a	5534	#define USB_ISTAT_USBRST_SHIFT 0
tushki7	0:60d829a0353a	5535	#define USB_ISTAT_ERROR_MASK 0x2u
tushki7	0:60d829a0353a	5536	#define USB_ISTAT_ERROR_SHIFT 1
tushki7	0:60d829a0353a	5537	#define USB_ISTAT_SOFTOK_MASK 0x4u
tushki7	0:60d829a0353a	5538	#define USB_ISTAT_SOFTOK_SHIFT 2
tushki7	0:60d829a0353a	5539	#define USB_ISTAT_TOKDNE_MASK 0x8u
tushki7	0:60d829a0353a	5540	#define USB_ISTAT_TOKDNE_SHIFT 3
tushki7	0:60d829a0353a	5541	#define USB_ISTAT_SLEEP_MASK 0x10u
tushki7	0:60d829a0353a	5542	#define USB_ISTAT_SLEEP_SHIFT 4
tushki7	0:60d829a0353a	5543	#define USB_ISTAT_RESUME_MASK 0x20u
tushki7	0:60d829a0353a	5544	#define USB_ISTAT_RESUME_SHIFT 5
tushki7	0:60d829a0353a	5545	#define USB_ISTAT_ATTACH_MASK 0x40u
tushki7	0:60d829a0353a	5546	#define USB_ISTAT_ATTACH_SHIFT 6
tushki7	0:60d829a0353a	5547	#define USB_ISTAT_STALL_MASK 0x80u
tushki7	0:60d829a0353a	5548	#define USB_ISTAT_STALL_SHIFT 7
tushki7	0:60d829a0353a	5549	/* INTEN Bit Fields */
tushki7	0:60d829a0353a	5550	#define USB_INTEN_USBRSTEN_MASK 0x1u
tushki7	0:60d829a0353a	5551	#define USB_INTEN_USBRSTEN_SHIFT 0
tushki7	0:60d829a0353a	5552	#define USB_INTEN_ERROREN_MASK 0x2u
tushki7	0:60d829a0353a	5553	#define USB_INTEN_ERROREN_SHIFT 1
tushki7	0:60d829a0353a	5554	#define USB_INTEN_SOFTOKEN_MASK 0x4u
tushki7	0:60d829a0353a	5555	#define USB_INTEN_SOFTOKEN_SHIFT 2
tushki7	0:60d829a0353a	5556	#define USB_INTEN_TOKDNEEN_MASK 0x8u
tushki7	0:60d829a0353a	5557	#define USB_INTEN_TOKDNEEN_SHIFT 3
tushki7	0:60d829a0353a	5558	#define USB_INTEN_SLEEPEN_MASK 0x10u
tushki7	0:60d829a0353a	5559	#define USB_INTEN_SLEEPEN_SHIFT 4
tushki7	0:60d829a0353a	5560	#define USB_INTEN_RESUMEEN_MASK 0x20u
tushki7	0:60d829a0353a	5561	#define USB_INTEN_RESUMEEN_SHIFT 5
tushki7	0:60d829a0353a	5562	#define USB_INTEN_ATTACHEN_MASK 0x40u
tushki7	0:60d829a0353a	5563	#define USB_INTEN_ATTACHEN_SHIFT 6
tushki7	0:60d829a0353a	5564	#define USB_INTEN_STALLEN_MASK 0x80u
tushki7	0:60d829a0353a	5565	#define USB_INTEN_STALLEN_SHIFT 7
tushki7	0:60d829a0353a	5566	/* ERRSTAT Bit Fields */
tushki7	0:60d829a0353a	5567	#define USB_ERRSTAT_PIDERR_MASK 0x1u
tushki7	0:60d829a0353a	5568	#define USB_ERRSTAT_PIDERR_SHIFT 0
tushki7	0:60d829a0353a	5569	#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
tushki7	0:60d829a0353a	5570	#define USB_ERRSTAT_CRC5EOF_SHIFT 1
tushki7	0:60d829a0353a	5571	#define USB_ERRSTAT_CRC16_MASK 0x4u
tushki7	0:60d829a0353a	5572	#define USB_ERRSTAT_CRC16_SHIFT 2
tushki7	0:60d829a0353a	5573	#define USB_ERRSTAT_DFN8_MASK 0x8u
tushki7	0:60d829a0353a	5574	#define USB_ERRSTAT_DFN8_SHIFT 3
tushki7	0:60d829a0353a	5575	#define USB_ERRSTAT_BTOERR_MASK 0x10u
tushki7	0:60d829a0353a	5576	#define USB_ERRSTAT_BTOERR_SHIFT 4
tushki7	0:60d829a0353a	5577	#define USB_ERRSTAT_DMAERR_MASK 0x20u
tushki7	0:60d829a0353a	5578	#define USB_ERRSTAT_DMAERR_SHIFT 5
tushki7	0:60d829a0353a	5579	#define USB_ERRSTAT_BTSERR_MASK 0x80u
tushki7	0:60d829a0353a	5580	#define USB_ERRSTAT_BTSERR_SHIFT 7
tushki7	0:60d829a0353a	5581	/* ERREN Bit Fields */
tushki7	0:60d829a0353a	5582	#define USB_ERREN_PIDERREN_MASK 0x1u
tushki7	0:60d829a0353a	5583	#define USB_ERREN_PIDERREN_SHIFT 0
tushki7	0:60d829a0353a	5584	#define USB_ERREN_CRC5EOFEN_MASK 0x2u
tushki7	0:60d829a0353a	5585	#define USB_ERREN_CRC5EOFEN_SHIFT 1
tushki7	0:60d829a0353a	5586	#define USB_ERREN_CRC16EN_MASK 0x4u
tushki7	0:60d829a0353a	5587	#define USB_ERREN_CRC16EN_SHIFT 2
tushki7	0:60d829a0353a	5588	#define USB_ERREN_DFN8EN_MASK 0x8u
tushki7	0:60d829a0353a	5589	#define USB_ERREN_DFN8EN_SHIFT 3
tushki7	0:60d829a0353a	5590	#define USB_ERREN_BTOERREN_MASK 0x10u
tushki7	0:60d829a0353a	5591	#define USB_ERREN_BTOERREN_SHIFT 4
tushki7	0:60d829a0353a	5592	#define USB_ERREN_DMAERREN_MASK 0x20u
tushki7	0:60d829a0353a	5593	#define USB_ERREN_DMAERREN_SHIFT 5
tushki7	0:60d829a0353a	5594	#define USB_ERREN_BTSERREN_MASK 0x80u
tushki7	0:60d829a0353a	5595	#define USB_ERREN_BTSERREN_SHIFT 7
tushki7	0:60d829a0353a	5596	/* STAT Bit Fields */
tushki7	0:60d829a0353a	5597	#define USB_STAT_ODD_MASK 0x4u
tushki7	0:60d829a0353a	5598	#define USB_STAT_ODD_SHIFT 2
tushki7	0:60d829a0353a	5599	#define USB_STAT_TX_MASK 0x8u
tushki7	0:60d829a0353a	5600	#define USB_STAT_TX_SHIFT 3
tushki7	0:60d829a0353a	5601	#define USB_STAT_ENDP_MASK 0xF0u
tushki7	0:60d829a0353a	5602	#define USB_STAT_ENDP_SHIFT 4
tushki7	0:60d829a0353a	5603	#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
tushki7	0:60d829a0353a	5604	/* CTL Bit Fields */
tushki7	0:60d829a0353a	5605	#define USB_CTL_USBENSOFEN_MASK 0x1u
tushki7	0:60d829a0353a	5606	#define USB_CTL_USBENSOFEN_SHIFT 0
tushki7	0:60d829a0353a	5607	#define USB_CTL_ODDRST_MASK 0x2u
tushki7	0:60d829a0353a	5608	#define USB_CTL_ODDRST_SHIFT 1
tushki7	0:60d829a0353a	5609	#define USB_CTL_RESUME_MASK 0x4u
tushki7	0:60d829a0353a	5610	#define USB_CTL_RESUME_SHIFT 2
tushki7	0:60d829a0353a	5611	#define USB_CTL_HOSTMODEEN_MASK 0x8u
tushki7	0:60d829a0353a	5612	#define USB_CTL_HOSTMODEEN_SHIFT 3
tushki7	0:60d829a0353a	5613	#define USB_CTL_RESET_MASK 0x10u
tushki7	0:60d829a0353a	5614	#define USB_CTL_RESET_SHIFT 4
tushki7	0:60d829a0353a	5615	#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
tushki7	0:60d829a0353a	5616	#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
tushki7	0:60d829a0353a	5617	#define USB_CTL_SE0_MASK 0x40u
tushki7	0:60d829a0353a	5618	#define USB_CTL_SE0_SHIFT 6
tushki7	0:60d829a0353a	5619	#define USB_CTL_JSTATE_MASK 0x80u
tushki7	0:60d829a0353a	5620	#define USB_CTL_JSTATE_SHIFT 7
tushki7	0:60d829a0353a	5621	/* ADDR Bit Fields */
tushki7	0:60d829a0353a	5622	#define USB_ADDR_ADDR_MASK 0x7Fu
tushki7	0:60d829a0353a	5623	#define USB_ADDR_ADDR_SHIFT 0
tushki7	0:60d829a0353a	5624	#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
tushki7	0:60d829a0353a	5625	#define USB_ADDR_LSEN_MASK 0x80u
tushki7	0:60d829a0353a	5626	#define USB_ADDR_LSEN_SHIFT 7
tushki7	0:60d829a0353a	5627	/* BDTPAGE1 Bit Fields */
tushki7	0:60d829a0353a	5628	#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
tushki7	0:60d829a0353a	5629	#define USB_BDTPAGE1_BDTBA_SHIFT 1
tushki7	0:60d829a0353a	5630	#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
tushki7	0:60d829a0353a	5631	/* FRMNUML Bit Fields */
tushki7	0:60d829a0353a	5632	#define USB_FRMNUML_FRM_MASK 0xFFu
tushki7	0:60d829a0353a	5633	#define USB_FRMNUML_FRM_SHIFT 0
tushki7	0:60d829a0353a	5634	#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
tushki7	0:60d829a0353a	5635	/* FRMNUMH Bit Fields */
tushki7	0:60d829a0353a	5636	#define USB_FRMNUMH_FRM_MASK 0x7u
tushki7	0:60d829a0353a	5637	#define USB_FRMNUMH_FRM_SHIFT 0
tushki7	0:60d829a0353a	5638	#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
tushki7	0:60d829a0353a	5639	/* TOKEN Bit Fields */
tushki7	0:60d829a0353a	5640	#define USB_TOKEN_TOKENENDPT_MASK 0xFu
tushki7	0:60d829a0353a	5641	#define USB_TOKEN_TOKENENDPT_SHIFT 0
tushki7	0:60d829a0353a	5642	#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
tushki7	0:60d829a0353a	5643	#define USB_TOKEN_TOKENPID_MASK 0xF0u
tushki7	0:60d829a0353a	5644	#define USB_TOKEN_TOKENPID_SHIFT 4
tushki7	0:60d829a0353a	5645	#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
tushki7	0:60d829a0353a	5646	/* SOFTHLD Bit Fields */
tushki7	0:60d829a0353a	5647	#define USB_SOFTHLD_CNT_MASK 0xFFu
tushki7	0:60d829a0353a	5648	#define USB_SOFTHLD_CNT_SHIFT 0
tushki7	0:60d829a0353a	5649	#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
tushki7	0:60d829a0353a	5650	/* BDTPAGE2 Bit Fields */
tushki7	0:60d829a0353a	5651	#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
tushki7	0:60d829a0353a	5652	#define USB_BDTPAGE2_BDTBA_SHIFT 0
tushki7	0:60d829a0353a	5653	#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
tushki7	0:60d829a0353a	5654	/* BDTPAGE3 Bit Fields */
tushki7	0:60d829a0353a	5655	#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
tushki7	0:60d829a0353a	5656	#define USB_BDTPAGE3_BDTBA_SHIFT 0
tushki7	0:60d829a0353a	5657	#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
tushki7	0:60d829a0353a	5658	/* ENDPT Bit Fields */
tushki7	0:60d829a0353a	5659	#define USB_ENDPT_EPHSHK_MASK 0x1u
tushki7	0:60d829a0353a	5660	#define USB_ENDPT_EPHSHK_SHIFT 0
tushki7	0:60d829a0353a	5661	#define USB_ENDPT_EPSTALL_MASK 0x2u
tushki7	0:60d829a0353a	5662	#define USB_ENDPT_EPSTALL_SHIFT 1
tushki7	0:60d829a0353a	5663	#define USB_ENDPT_EPTXEN_MASK 0x4u
tushki7	0:60d829a0353a	5664	#define USB_ENDPT_EPTXEN_SHIFT 2
tushki7	0:60d829a0353a	5665	#define USB_ENDPT_EPRXEN_MASK 0x8u
tushki7	0:60d829a0353a	5666	#define USB_ENDPT_EPRXEN_SHIFT 3
tushki7	0:60d829a0353a	5667	#define USB_ENDPT_EPCTLDIS_MASK 0x10u
tushki7	0:60d829a0353a	5668	#define USB_ENDPT_EPCTLDIS_SHIFT 4
tushki7	0:60d829a0353a	5669	#define USB_ENDPT_RETRYDIS_MASK 0x40u
tushki7	0:60d829a0353a	5670	#define USB_ENDPT_RETRYDIS_SHIFT 6
tushki7	0:60d829a0353a	5671	#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
tushki7	0:60d829a0353a	5672	#define USB_ENDPT_HOSTWOHUB_SHIFT 7
tushki7	0:60d829a0353a	5673	/* USBCTRL Bit Fields */
tushki7	0:60d829a0353a	5674	#define USB_USBCTRL_PDE_MASK 0x40u
tushki7	0:60d829a0353a	5675	#define USB_USBCTRL_PDE_SHIFT 6
tushki7	0:60d829a0353a	5676	#define USB_USBCTRL_SUSP_MASK 0x80u
tushki7	0:60d829a0353a	5677	#define USB_USBCTRL_SUSP_SHIFT 7
tushki7	0:60d829a0353a	5678	/* OBSERVE Bit Fields */
tushki7	0:60d829a0353a	5679	#define USB_OBSERVE_DMPD_MASK 0x10u
tushki7	0:60d829a0353a	5680	#define USB_OBSERVE_DMPD_SHIFT 4
tushki7	0:60d829a0353a	5681	#define USB_OBSERVE_DPPD_MASK 0x40u
tushki7	0:60d829a0353a	5682	#define USB_OBSERVE_DPPD_SHIFT 6
tushki7	0:60d829a0353a	5683	#define USB_OBSERVE_DPPU_MASK 0x80u
tushki7	0:60d829a0353a	5684	#define USB_OBSERVE_DPPU_SHIFT 7
tushki7	0:60d829a0353a	5685	/* CONTROL Bit Fields */
tushki7	0:60d829a0353a	5686	#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
tushki7	0:60d829a0353a	5687	#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
tushki7	0:60d829a0353a	5688	/* USBTRC0 Bit Fields */
tushki7	0:60d829a0353a	5689	#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
tushki7	0:60d829a0353a	5690	#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
tushki7	0:60d829a0353a	5691	#define USB_USBTRC0_SYNC_DET_MASK 0x2u
tushki7	0:60d829a0353a	5692	#define USB_USBTRC0_SYNC_DET_SHIFT 1
tushki7	0:60d829a0353a	5693	#define USB_USBTRC0_USBRESMEN_MASK 0x20u
tushki7	0:60d829a0353a	5694	#define USB_USBTRC0_USBRESMEN_SHIFT 5
tushki7	0:60d829a0353a	5695	#define USB_USBTRC0_USBRESET_MASK 0x80u
tushki7	0:60d829a0353a	5696	#define USB_USBTRC0_USBRESET_SHIFT 7
tushki7	0:60d829a0353a	5697	/* USBFRMADJUST Bit Fields */
tushki7	0:60d829a0353a	5698	#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
tushki7	0:60d829a0353a	5699	#define USB_USBFRMADJUST_ADJ_SHIFT 0
tushki7	0:60d829a0353a	5700	#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
tushki7	0:60d829a0353a	5701
tushki7	0:60d829a0353a	5702	/**
tushki7	0:60d829a0353a	5703	* @}
tushki7	0:60d829a0353a	5704	/ / end of group USB_Register_Masks */
tushki7	0:60d829a0353a	5705
tushki7	0:60d829a0353a	5706
tushki7	0:60d829a0353a	5707	/* USB - Peripheral instance base addresses */
tushki7	0:60d829a0353a	5708	/** Peripheral USB0 base address */
tushki7	0:60d829a0353a	5709	#define USB0_BASE (0x40072000u)
tushki7	0:60d829a0353a	5710	/** Peripheral USB0 base pointer */
tushki7	0:60d829a0353a	5711	#define USB0 ((USB_Type *)USB0_BASE)
tushki7	0:60d829a0353a	5712
tushki7	0:60d829a0353a	5713	/**
tushki7	0:60d829a0353a	5714	* @}
tushki7	0:60d829a0353a	5715	/ / end of group USB_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	5716
tushki7	0:60d829a0353a	5717
tushki7	0:60d829a0353a	5718	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	5719	-- USBDCD Peripheral Access Layer
tushki7	0:60d829a0353a	5720	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	5721
tushki7	0:60d829a0353a	5722	/**
tushki7	0:60d829a0353a	5723	* @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
tushki7	0:60d829a0353a	5724	* @{
tushki7	0:60d829a0353a	5725	*/
tushki7	0:60d829a0353a	5726
tushki7	0:60d829a0353a	5727	/** USBDCD - Register Layout Typedef */
tushki7	0:60d829a0353a	5728	typedef struct {
tushki7	0:60d829a0353a	5729	__IO uint32_t CONTROL; /*< Control Register, offset: 0x0 /
tushki7	0:60d829a0353a	5730	__IO uint32_t CLOCK; /*< Clock Register, offset: 0x4 /
tushki7	0:60d829a0353a	5731	__I uint32_t STATUS; /*< Status Register, offset: 0x8 /
tushki7	0:60d829a0353a	5732	uint8_t RESERVED_0[4];
tushki7	0:60d829a0353a	5733	__IO uint32_t TIMER0; /*< TIMER0 Register, offset: 0x10 /
tushki7	0:60d829a0353a	5734	__IO uint32_t TIMER1; /*< , offset: 0x14 /
tushki7	0:60d829a0353a	5735	__IO uint32_t TIMER2; /*< , offset: 0x18 /
tushki7	0:60d829a0353a	5736	} USBDCD_Type;
tushki7	0:60d829a0353a	5737
tushki7	0:60d829a0353a	5738	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	5739	-- USBDCD Register Masks
tushki7	0:60d829a0353a	5740	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	5741
tushki7	0:60d829a0353a	5742	/**
tushki7	0:60d829a0353a	5743	* @addtogroup USBDCD_Register_Masks USBDCD Register Masks
tushki7	0:60d829a0353a	5744	* @{
tushki7	0:60d829a0353a	5745	*/
tushki7	0:60d829a0353a	5746
tushki7	0:60d829a0353a	5747	/* CONTROL Bit Fields */
tushki7	0:60d829a0353a	5748	#define USBDCD_CONTROL_IACK_MASK 0x1u
tushki7	0:60d829a0353a	5749	#define USBDCD_CONTROL_IACK_SHIFT 0
tushki7	0:60d829a0353a	5750	#define USBDCD_CONTROL_IF_MASK 0x100u
tushki7	0:60d829a0353a	5751	#define USBDCD_CONTROL_IF_SHIFT 8
tushki7	0:60d829a0353a	5752	#define USBDCD_CONTROL_IE_MASK 0x10000u
tushki7	0:60d829a0353a	5753	#define USBDCD_CONTROL_IE_SHIFT 16
tushki7	0:60d829a0353a	5754	#define USBDCD_CONTROL_START_MASK 0x1000000u
tushki7	0:60d829a0353a	5755	#define USBDCD_CONTROL_START_SHIFT 24
tushki7	0:60d829a0353a	5756	#define USBDCD_CONTROL_SR_MASK 0x2000000u
tushki7	0:60d829a0353a	5757	#define USBDCD_CONTROL_SR_SHIFT 25
tushki7	0:60d829a0353a	5758	/* CLOCK Bit Fields */
tushki7	0:60d829a0353a	5759	#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
tushki7	0:60d829a0353a	5760	#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
tushki7	0:60d829a0353a	5761	#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
tushki7	0:60d829a0353a	5762	#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
tushki7	0:60d829a0353a	5763	#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
tushki7	0:60d829a0353a	5764	/* STATUS Bit Fields */
tushki7	0:60d829a0353a	5765	#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
tushki7	0:60d829a0353a	5766	#define USBDCD_STATUS_SEQ_RES_SHIFT 16
tushki7	0:60d829a0353a	5767	#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
tushki7	0:60d829a0353a	5768	#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
tushki7	0:60d829a0353a	5769	#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
tushki7	0:60d829a0353a	5770	#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
tushki7	0:60d829a0353a	5771	#define USBDCD_STATUS_ERR_MASK 0x100000u
tushki7	0:60d829a0353a	5772	#define USBDCD_STATUS_ERR_SHIFT 20
tushki7	0:60d829a0353a	5773	#define USBDCD_STATUS_TO_MASK 0x200000u
tushki7	0:60d829a0353a	5774	#define USBDCD_STATUS_TO_SHIFT 21
tushki7	0:60d829a0353a	5775	#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
tushki7	0:60d829a0353a	5776	#define USBDCD_STATUS_ACTIVE_SHIFT 22
tushki7	0:60d829a0353a	5777	/* TIMER0 Bit Fields */
tushki7	0:60d829a0353a	5778	#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
tushki7	0:60d829a0353a	5779	#define USBDCD_TIMER0_TUNITCON_SHIFT 0
tushki7	0:60d829a0353a	5780	#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
tushki7	0:60d829a0353a	5781	#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
tushki7	0:60d829a0353a	5782	#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
tushki7	0:60d829a0353a	5783	#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
tushki7	0:60d829a0353a	5784	/* TIMER1 Bit Fields */
tushki7	0:60d829a0353a	5785	#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
tushki7	0:60d829a0353a	5786	#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
tushki7	0:60d829a0353a	5787	#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
tushki7	0:60d829a0353a	5788	#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
tushki7	0:60d829a0353a	5789	#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
tushki7	0:60d829a0353a	5790	#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
tushki7	0:60d829a0353a	5791	/* TIMER2 Bit Fields */
tushki7	0:60d829a0353a	5792	#define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
tushki7	0:60d829a0353a	5793	#define USBDCD_TIMER2_CHECK_DM_SHIFT 0
tushki7	0:60d829a0353a	5794	#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
tushki7	0:60d829a0353a	5795	#define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
tushki7	0:60d829a0353a	5796	#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
tushki7	0:60d829a0353a	5797	#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
tushki7	0:60d829a0353a	5798
tushki7	0:60d829a0353a	5799	/**
tushki7	0:60d829a0353a	5800	* @}
tushki7	0:60d829a0353a	5801	/ / end of group USBDCD_Register_Masks */
tushki7	0:60d829a0353a	5802
tushki7	0:60d829a0353a	5803
tushki7	0:60d829a0353a	5804	/* USBDCD - Peripheral instance base addresses */
tushki7	0:60d829a0353a	5805	/** Peripheral USBDCD base address */
tushki7	0:60d829a0353a	5806	#define USBDCD_BASE (0x40035000u)
tushki7	0:60d829a0353a	5807	/** Peripheral USBDCD base pointer */
tushki7	0:60d829a0353a	5808	#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
tushki7	0:60d829a0353a	5809
tushki7	0:60d829a0353a	5810	/**
tushki7	0:60d829a0353a	5811	* @}
tushki7	0:60d829a0353a	5812	/ / end of group USBDCD_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	5813
tushki7	0:60d829a0353a	5814
tushki7	0:60d829a0353a	5815	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	5816	-- VREF Peripheral Access Layer
tushki7	0:60d829a0353a	5817	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	5818
tushki7	0:60d829a0353a	5819	/**
tushki7	0:60d829a0353a	5820	* @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
tushki7	0:60d829a0353a	5821	* @{
tushki7	0:60d829a0353a	5822	*/
tushki7	0:60d829a0353a	5823
tushki7	0:60d829a0353a	5824	/** VREF - Register Layout Typedef */
tushki7	0:60d829a0353a	5825	typedef struct {
tushki7	0:60d829a0353a	5826	__IO uint8_t TRM; /*< VREF Trim Register, offset: 0x0 /
tushki7	0:60d829a0353a	5827	__IO uint8_t SC; /*< VREF Status and Control Register, offset: 0x1 /
tushki7	0:60d829a0353a	5828	} VREF_Type;
tushki7	0:60d829a0353a	5829
tushki7	0:60d829a0353a	5830	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	5831	-- VREF Register Masks
tushki7	0:60d829a0353a	5832	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	5833
tushki7	0:60d829a0353a	5834	/**
tushki7	0:60d829a0353a	5835	* @addtogroup VREF_Register_Masks VREF Register Masks
tushki7	0:60d829a0353a	5836	* @{
tushki7	0:60d829a0353a	5837	*/
tushki7	0:60d829a0353a	5838
tushki7	0:60d829a0353a	5839	/* TRM Bit Fields */
tushki7	0:60d829a0353a	5840	#define VREF_TRM_TRIM_MASK 0x3Fu
tushki7	0:60d829a0353a	5841	#define VREF_TRM_TRIM_SHIFT 0
tushki7	0:60d829a0353a	5842	#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
tushki7	0:60d829a0353a	5843	#define VREF_TRM_CHOPEN_MASK 0x40u
tushki7	0:60d829a0353a	5844	#define VREF_TRM_CHOPEN_SHIFT 6
tushki7	0:60d829a0353a	5845	/* SC Bit Fields */
tushki7	0:60d829a0353a	5846	#define VREF_SC_MODE_LV_MASK 0x3u
tushki7	0:60d829a0353a	5847	#define VREF_SC_MODE_LV_SHIFT 0
tushki7	0:60d829a0353a	5848	#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
tushki7	0:60d829a0353a	5849	#define VREF_SC_VREFST_MASK 0x4u
tushki7	0:60d829a0353a	5850	#define VREF_SC_VREFST_SHIFT 2
tushki7	0:60d829a0353a	5851	#define VREF_SC_REGEN_MASK 0x40u
tushki7	0:60d829a0353a	5852	#define VREF_SC_REGEN_SHIFT 6
tushki7	0:60d829a0353a	5853	#define VREF_SC_VREFEN_MASK 0x80u
tushki7	0:60d829a0353a	5854	#define VREF_SC_VREFEN_SHIFT 7
tushki7	0:60d829a0353a	5855
tushki7	0:60d829a0353a	5856	/**
tushki7	0:60d829a0353a	5857	* @}
tushki7	0:60d829a0353a	5858	/ / end of group VREF_Register_Masks */
tushki7	0:60d829a0353a	5859
tushki7	0:60d829a0353a	5860
tushki7	0:60d829a0353a	5861	/* VREF - Peripheral instance base addresses */
tushki7	0:60d829a0353a	5862	/** Peripheral VREF base address */
tushki7	0:60d829a0353a	5863	#define VREF_BASE (0x40074000u)
tushki7	0:60d829a0353a	5864	/** Peripheral VREF base pointer */
tushki7	0:60d829a0353a	5865	#define VREF ((VREF_Type *)VREF_BASE)
tushki7	0:60d829a0353a	5866
tushki7	0:60d829a0353a	5867	/**
tushki7	0:60d829a0353a	5868	* @}
tushki7	0:60d829a0353a	5869	/ / end of group VREF_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	5870
tushki7	0:60d829a0353a	5871
tushki7	0:60d829a0353a	5872	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	5873	-- WDOG Peripheral Access Layer
tushki7	0:60d829a0353a	5874	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	5875
tushki7	0:60d829a0353a	5876	/**
tushki7	0:60d829a0353a	5877	* @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
tushki7	0:60d829a0353a	5878	* @{
tushki7	0:60d829a0353a	5879	*/
tushki7	0:60d829a0353a	5880
tushki7	0:60d829a0353a	5881	/** WDOG - Register Layout Typedef */
tushki7	0:60d829a0353a	5882	typedef struct {
tushki7	0:60d829a0353a	5883	__IO uint16_t STCTRLH; /*< Watchdog Status and Control Register High, offset: 0x0 /
tushki7	0:60d829a0353a	5884	__IO uint16_t STCTRLL; /*< Watchdog Status and Control Register Low, offset: 0x2 /
tushki7	0:60d829a0353a	5885	__IO uint16_t TOVALH; /*< Watchdog Time-out Value Register High, offset: 0x4 /
tushki7	0:60d829a0353a	5886	__IO uint16_t TOVALL; /*< Watchdog Time-out Value Register Low, offset: 0x6 /
tushki7	0:60d829a0353a	5887	__IO uint16_t WINH; /*< Watchdog Window Register High, offset: 0x8 /
tushki7	0:60d829a0353a	5888	__IO uint16_t WINL; /*< Watchdog Window Register Low, offset: 0xA /
tushki7	0:60d829a0353a	5889	__IO uint16_t REFRESH; /*< Watchdog Refresh Register, offset: 0xC /
tushki7	0:60d829a0353a	5890	__IO uint16_t UNLOCK; /*< Watchdog Unlock Register, offset: 0xE /
tushki7	0:60d829a0353a	5891	__IO uint16_t TMROUTH; /*< Watchdog Timer Output Register High, offset: 0x10 /
tushki7	0:60d829a0353a	5892	__IO uint16_t TMROUTL; /*< Watchdog Timer Output Register Low, offset: 0x12 /
tushki7	0:60d829a0353a	5893	__IO uint16_t RSTCNT; /*< Watchdog Reset Count Register, offset: 0x14 /
tushki7	0:60d829a0353a	5894	__IO uint16_t PRESC; /*< Watchdog Prescaler Register, offset: 0x16 /
tushki7	0:60d829a0353a	5895	} WDOG_Type;
tushki7	0:60d829a0353a	5896
tushki7	0:60d829a0353a	5897	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	5898	-- WDOG Register Masks
tushki7	0:60d829a0353a	5899	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	5900
tushki7	0:60d829a0353a	5901	/**
tushki7	0:60d829a0353a	5902	* @addtogroup WDOG_Register_Masks WDOG Register Masks
tushki7	0:60d829a0353a	5903	* @{
tushki7	0:60d829a0353a	5904	*/
tushki7	0:60d829a0353a	5905
tushki7	0:60d829a0353a	5906	/* STCTRLH Bit Fields */
tushki7	0:60d829a0353a	5907	#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
tushki7	0:60d829a0353a	5908	#define WDOG_STCTRLH_WDOGEN_SHIFT 0
tushki7	0:60d829a0353a	5909	#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
tushki7	0:60d829a0353a	5910	#define WDOG_STCTRLH_CLKSRC_SHIFT 1
tushki7	0:60d829a0353a	5911	#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
tushki7	0:60d829a0353a	5912	#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
tushki7	0:60d829a0353a	5913	#define WDOG_STCTRLH_WINEN_MASK 0x8u
tushki7	0:60d829a0353a	5914	#define WDOG_STCTRLH_WINEN_SHIFT 3
tushki7	0:60d829a0353a	5915	#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
tushki7	0:60d829a0353a	5916	#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
tushki7	0:60d829a0353a	5917	#define WDOG_STCTRLH_DBGEN_MASK 0x20u
tushki7	0:60d829a0353a	5918	#define WDOG_STCTRLH_DBGEN_SHIFT 5
tushki7	0:60d829a0353a	5919	#define WDOG_STCTRLH_STOPEN_MASK 0x40u
tushki7	0:60d829a0353a	5920	#define WDOG_STCTRLH_STOPEN_SHIFT 6
tushki7	0:60d829a0353a	5921	#define WDOG_STCTRLH_WAITEN_MASK 0x80u
tushki7	0:60d829a0353a	5922	#define WDOG_STCTRLH_WAITEN_SHIFT 7
tushki7	0:60d829a0353a	5923	#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
tushki7	0:60d829a0353a	5924	#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
tushki7	0:60d829a0353a	5925	#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
tushki7	0:60d829a0353a	5926	#define WDOG_STCTRLH_TESTSEL_SHIFT 11
tushki7	0:60d829a0353a	5927	#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
tushki7	0:60d829a0353a	5928	#define WDOG_STCTRLH_BYTESEL_SHIFT 12
tushki7	0:60d829a0353a	5929	#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
tushki7	0:60d829a0353a	5930	#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
tushki7	0:60d829a0353a	5931	#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
tushki7	0:60d829a0353a	5932	/* STCTRLL Bit Fields */
tushki7	0:60d829a0353a	5933	#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
tushki7	0:60d829a0353a	5934	#define WDOG_STCTRLL_INTFLG_SHIFT 15
tushki7	0:60d829a0353a	5935	/* TOVALH Bit Fields */
tushki7	0:60d829a0353a	5936	#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
tushki7	0:60d829a0353a	5937	#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
tushki7	0:60d829a0353a	5938	#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
tushki7	0:60d829a0353a	5939	/* TOVALL Bit Fields */
tushki7	0:60d829a0353a	5940	#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
tushki7	0:60d829a0353a	5941	#define WDOG_TOVALL_TOVALLOW_SHIFT 0
tushki7	0:60d829a0353a	5942	#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
tushki7	0:60d829a0353a	5943	/* WINH Bit Fields */
tushki7	0:60d829a0353a	5944	#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
tushki7	0:60d829a0353a	5945	#define WDOG_WINH_WINHIGH_SHIFT 0
tushki7	0:60d829a0353a	5946	#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
tushki7	0:60d829a0353a	5947	/* WINL Bit Fields */
tushki7	0:60d829a0353a	5948	#define WDOG_WINL_WINLOW_MASK 0xFFFFu
tushki7	0:60d829a0353a	5949	#define WDOG_WINL_WINLOW_SHIFT 0
tushki7	0:60d829a0353a	5950	#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
tushki7	0:60d829a0353a	5951	/* REFRESH Bit Fields */
tushki7	0:60d829a0353a	5952	#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
tushki7	0:60d829a0353a	5953	#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
tushki7	0:60d829a0353a	5954	#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
tushki7	0:60d829a0353a	5955	/* UNLOCK Bit Fields */
tushki7	0:60d829a0353a	5956	#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
tushki7	0:60d829a0353a	5957	#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
tushki7	0:60d829a0353a	5958	#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
tushki7	0:60d829a0353a	5959	/* TMROUTH Bit Fields */
tushki7	0:60d829a0353a	5960	#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
tushki7	0:60d829a0353a	5961	#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
tushki7	0:60d829a0353a	5962	#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
tushki7	0:60d829a0353a	5963	/* TMROUTL Bit Fields */
tushki7	0:60d829a0353a	5964	#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
tushki7	0:60d829a0353a	5965	#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
tushki7	0:60d829a0353a	5966	#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
tushki7	0:60d829a0353a	5967	/* RSTCNT Bit Fields */
tushki7	0:60d829a0353a	5968	#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
tushki7	0:60d829a0353a	5969	#define WDOG_RSTCNT_RSTCNT_SHIFT 0
tushki7	0:60d829a0353a	5970	#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
tushki7	0:60d829a0353a	5971	/* PRESC Bit Fields */
tushki7	0:60d829a0353a	5972	#define WDOG_PRESC_PRESCVAL_MASK 0x700u
tushki7	0:60d829a0353a	5973	#define WDOG_PRESC_PRESCVAL_SHIFT 8
tushki7	0:60d829a0353a	5974	#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
tushki7	0:60d829a0353a	5975
tushki7	0:60d829a0353a	5976	/**
tushki7	0:60d829a0353a	5977	* @}
tushki7	0:60d829a0353a	5978	/ / end of group WDOG_Register_Masks */
tushki7	0:60d829a0353a	5979
tushki7	0:60d829a0353a	5980
tushki7	0:60d829a0353a	5981	/* WDOG - Peripheral instance base addresses */
tushki7	0:60d829a0353a	5982	/** Peripheral WDOG base address */
tushki7	0:60d829a0353a	5983	#define WDOG_BASE (0x40052000u)
tushki7	0:60d829a0353a	5984	/** Peripheral WDOG base pointer */
tushki7	0:60d829a0353a	5985	#define WDOG ((WDOG_Type *)WDOG_BASE)
tushki7	0:60d829a0353a	5986
tushki7	0:60d829a0353a	5987	/**
tushki7	0:60d829a0353a	5988	* @}
tushki7	0:60d829a0353a	5989	/ / end of group WDOG_Peripheral_Access_Layer */
tushki7	0:60d829a0353a	5990
tushki7	0:60d829a0353a	5991
tushki7	0:60d829a0353a	5992	/*
tushki7	0:60d829a0353a	5993	** End of section using anonymous unions
tushki7	0:60d829a0353a	5994	*/
tushki7	0:60d829a0353a	5995
tushki7	0:60d829a0353a	5996	#if defined(__ARMCC_VERSION)
tushki7	0:60d829a0353a	5997	#pragma pop
tushki7	0:60d829a0353a	5998	#elif defined(__CWCC__)
tushki7	0:60d829a0353a	5999	#pragma pop
tushki7	0:60d829a0353a	6000	#elif defined(__GNUC__)
tushki7	0:60d829a0353a	6001	/* leave anonymous unions enabled */
tushki7	0:60d829a0353a	6002	#elif defined(__IAR_SYSTEMS_ICC__)
tushki7	0:60d829a0353a	6003	#pragma language=default
tushki7	0:60d829a0353a	6004	#else
tushki7	0:60d829a0353a	6005	#error Not supported compiler type
tushki7	0:60d829a0353a	6006	#endif
tushki7	0:60d829a0353a	6007
tushki7	0:60d829a0353a	6008	/**
tushki7	0:60d829a0353a	6009	* @}
tushki7	0:60d829a0353a	6010	/ / end of group Peripheral_access_layer */
tushki7	0:60d829a0353a	6011
tushki7	0:60d829a0353a	6012
tushki7	0:60d829a0353a	6013	/* ----------------------------------------------------------------------------
tushki7	0:60d829a0353a	6014	-- Backward Compatibility
tushki7	0:60d829a0353a	6015	---------------------------------------------------------------------------- */
tushki7	0:60d829a0353a	6016
tushki7	0:60d829a0353a	6017	/**
tushki7	0:60d829a0353a	6018	* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
tushki7	0:60d829a0353a	6019	* @{
tushki7	0:60d829a0353a	6020	*/
tushki7	0:60d829a0353a	6021
tushki7	0:60d829a0353a	6022	/* No backward compatibility issues. */
tushki7	0:60d829a0353a	6023
tushki7	0:60d829a0353a	6024	/**
tushki7	0:60d829a0353a	6025	* @}
tushki7	0:60d829a0353a	6026	/ / end of group Backward_Compatibility_Symbols */
tushki7	0:60d829a0353a	6027
tushki7	0:60d829a0353a	6028
tushki7	0:60d829a0353a	6029	#endif /* #if !defined(MK20D5_H_) */
tushki7	0:60d829a0353a	6030
tushki7	0:60d829a0353a	6031	/* MK20D5.h, eof. */
tushki7	0:60d829a0353a	6032

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Type:	Program
Created:	11 Apr 2015
Imports:	100
Forks:	0
Commits:	2
Dependents:	0
Dependencies:	1
Followers:	2

mbed/TARGET_TEENSY3_1/MK20DX256.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

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