Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_SSCI824/core_cm4_simd.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a 
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /**************************************************************************//**
tushki7 0:60d829a0353a 2 * @file core_cm4_simd.h
tushki7 0:60d829a0353a 3 * @brief CMSIS Cortex-M4 SIMD Header File
tushki7 0:60d829a0353a 4 * @version V3.20
tushki7 0:60d829a0353a 5 * @date 25. February 2013
tushki7 0:60d829a0353a 6 *
tushki7 0:60d829a0353a 7 * @note
tushki7 0:60d829a0353a 8 *
tushki7 0:60d829a0353a 9 ******************************************************************************/
tushki7 0:60d829a0353a 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
tushki7 0:60d829a0353a 11
tushki7 0:60d829a0353a 12 All rights reserved.
tushki7 0:60d829a0353a 13 Redistribution and use in source and binary forms, with or without
tushki7 0:60d829a0353a 14 modification, are permitted provided that the following conditions are met:
tushki7 0:60d829a0353a 15 - Redistributions of source code must retain the above copyright
tushki7 0:60d829a0353a 16 notice, this list of conditions and the following disclaimer.
tushki7 0:60d829a0353a 17 - Redistributions in binary form must reproduce the above copyright
tushki7 0:60d829a0353a 18 notice, this list of conditions and the following disclaimer in the
tushki7 0:60d829a0353a 19 documentation and/or other materials provided with the distribution.
tushki7 0:60d829a0353a 20 - Neither the name of ARM nor the names of its contributors may be used
tushki7 0:60d829a0353a 21 to endorse or promote products derived from this software without
tushki7 0:60d829a0353a 22 specific prior written permission.
tushki7 0:60d829a0353a 23 *
tushki7 0:60d829a0353a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
tushki7 0:60d829a0353a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
tushki7 0:60d829a0353a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
tushki7 0:60d829a0353a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
tushki7 0:60d829a0353a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
tushki7 0:60d829a0353a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
tushki7 0:60d829a0353a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
tushki7 0:60d829a0353a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
tushki7 0:60d829a0353a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
tushki7 0:60d829a0353a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
tushki7 0:60d829a0353a 34 POSSIBILITY OF SUCH DAMAGE.
tushki7 0:60d829a0353a 35 ---------------------------------------------------------------------------*/
tushki7 0:60d829a0353a 36
tushki7 0:60d829a0353a 37
tushki7 0:60d829a0353a 38 #ifdef __cplusplus
tushki7 0:60d829a0353a 39 extern "C" {
tushki7 0:60d829a0353a 40 #endif
tushki7 0:60d829a0353a 41
tushki7 0:60d829a0353a 42 #ifndef __CORE_CM4_SIMD_H
tushki7 0:60d829a0353a 43 #define __CORE_CM4_SIMD_H
tushki7 0:60d829a0353a 44
tushki7 0:60d829a0353a 45
tushki7 0:60d829a0353a 46 /*******************************************************************************
tushki7 0:60d829a0353a 47 * Hardware Abstraction Layer
tushki7 0:60d829a0353a 48 ******************************************************************************/
tushki7 0:60d829a0353a 49
tushki7 0:60d829a0353a 50
tushki7 0:60d829a0353a 51 /* ################### Compiler specific Intrinsics ########################### */
tushki7 0:60d829a0353a 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
tushki7 0:60d829a0353a 53 Access to dedicated SIMD instructions
tushki7 0:60d829a0353a 54 @{
tushki7 0:60d829a0353a 55 */
tushki7 0:60d829a0353a 56
tushki7 0:60d829a0353a 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
tushki7 0:60d829a0353a 58 /* ARM armcc specific functions */
tushki7 0:60d829a0353a 59
tushki7 0:60d829a0353a 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
tushki7 0:60d829a0353a 61 #define __SADD8 __sadd8
tushki7 0:60d829a0353a 62 #define __QADD8 __qadd8
tushki7 0:60d829a0353a 63 #define __SHADD8 __shadd8
tushki7 0:60d829a0353a 64 #define __UADD8 __uadd8
tushki7 0:60d829a0353a 65 #define __UQADD8 __uqadd8
tushki7 0:60d829a0353a 66 #define __UHADD8 __uhadd8
tushki7 0:60d829a0353a 67 #define __SSUB8 __ssub8
tushki7 0:60d829a0353a 68 #define __QSUB8 __qsub8
tushki7 0:60d829a0353a 69 #define __SHSUB8 __shsub8
tushki7 0:60d829a0353a 70 #define __USUB8 __usub8
tushki7 0:60d829a0353a 71 #define __UQSUB8 __uqsub8
tushki7 0:60d829a0353a 72 #define __UHSUB8 __uhsub8
tushki7 0:60d829a0353a 73 #define __SADD16 __sadd16
tushki7 0:60d829a0353a 74 #define __QADD16 __qadd16
tushki7 0:60d829a0353a 75 #define __SHADD16 __shadd16
tushki7 0:60d829a0353a 76 #define __UADD16 __uadd16
tushki7 0:60d829a0353a 77 #define __UQADD16 __uqadd16
tushki7 0:60d829a0353a 78 #define __UHADD16 __uhadd16
tushki7 0:60d829a0353a 79 #define __SSUB16 __ssub16
tushki7 0:60d829a0353a 80 #define __QSUB16 __qsub16
tushki7 0:60d829a0353a 81 #define __SHSUB16 __shsub16
tushki7 0:60d829a0353a 82 #define __USUB16 __usub16
tushki7 0:60d829a0353a 83 #define __UQSUB16 __uqsub16
tushki7 0:60d829a0353a 84 #define __UHSUB16 __uhsub16
tushki7 0:60d829a0353a 85 #define __SASX __sasx
tushki7 0:60d829a0353a 86 #define __QASX __qasx
tushki7 0:60d829a0353a 87 #define __SHASX __shasx
tushki7 0:60d829a0353a 88 #define __UASX __uasx
tushki7 0:60d829a0353a 89 #define __UQASX __uqasx
tushki7 0:60d829a0353a 90 #define __UHASX __uhasx
tushki7 0:60d829a0353a 91 #define __SSAX __ssax
tushki7 0:60d829a0353a 92 #define __QSAX __qsax
tushki7 0:60d829a0353a 93 #define __SHSAX __shsax
tushki7 0:60d829a0353a 94 #define __USAX __usax
tushki7 0:60d829a0353a 95 #define __UQSAX __uqsax
tushki7 0:60d829a0353a 96 #define __UHSAX __uhsax
tushki7 0:60d829a0353a 97 #define __USAD8 __usad8
tushki7 0:60d829a0353a 98 #define __USADA8 __usada8
tushki7 0:60d829a0353a 99 #define __SSAT16 __ssat16
tushki7 0:60d829a0353a 100 #define __USAT16 __usat16
tushki7 0:60d829a0353a 101 #define __UXTB16 __uxtb16
tushki7 0:60d829a0353a 102 #define __UXTAB16 __uxtab16
tushki7 0:60d829a0353a 103 #define __SXTB16 __sxtb16
tushki7 0:60d829a0353a 104 #define __SXTAB16 __sxtab16
tushki7 0:60d829a0353a 105 #define __SMUAD __smuad
tushki7 0:60d829a0353a 106 #define __SMUADX __smuadx
tushki7 0:60d829a0353a 107 #define __SMLAD __smlad
tushki7 0:60d829a0353a 108 #define __SMLADX __smladx
tushki7 0:60d829a0353a 109 #define __SMLALD __smlald
tushki7 0:60d829a0353a 110 #define __SMLALDX __smlaldx
tushki7 0:60d829a0353a 111 #define __SMUSD __smusd
tushki7 0:60d829a0353a 112 #define __SMUSDX __smusdx
tushki7 0:60d829a0353a 113 #define __SMLSD __smlsd
tushki7 0:60d829a0353a 114 #define __SMLSDX __smlsdx
tushki7 0:60d829a0353a 115 #define __SMLSLD __smlsld
tushki7 0:60d829a0353a 116 #define __SMLSLDX __smlsldx
tushki7 0:60d829a0353a 117 #define __SEL __sel
tushki7 0:60d829a0353a 118 #define __QADD __qadd
tushki7 0:60d829a0353a 119 #define __QSUB __qsub
tushki7 0:60d829a0353a 120
tushki7 0:60d829a0353a 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
tushki7 0:60d829a0353a 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
tushki7 0:60d829a0353a 123
tushki7 0:60d829a0353a 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
tushki7 0:60d829a0353a 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
tushki7 0:60d829a0353a 126
tushki7 0:60d829a0353a 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
tushki7 0:60d829a0353a 128 ((int64_t)(ARG3) << 32) ) >> 32))
tushki7 0:60d829a0353a 129
tushki7 0:60d829a0353a 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
tushki7 0:60d829a0353a 131
tushki7 0:60d829a0353a 132
tushki7 0:60d829a0353a 133
tushki7 0:60d829a0353a 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
tushki7 0:60d829a0353a 135 /* IAR iccarm specific functions */
tushki7 0:60d829a0353a 136
tushki7 0:60d829a0353a 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
tushki7 0:60d829a0353a 138 #include <cmsis_iar.h>
tushki7 0:60d829a0353a 139
tushki7 0:60d829a0353a 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
tushki7 0:60d829a0353a 141
tushki7 0:60d829a0353a 142
tushki7 0:60d829a0353a 143
tushki7 0:60d829a0353a 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
tushki7 0:60d829a0353a 145 /* TI CCS specific functions */
tushki7 0:60d829a0353a 146
tushki7 0:60d829a0353a 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
tushki7 0:60d829a0353a 148 #include <cmsis_ccs.h>
tushki7 0:60d829a0353a 149
tushki7 0:60d829a0353a 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
tushki7 0:60d829a0353a 151
tushki7 0:60d829a0353a 152
tushki7 0:60d829a0353a 153
tushki7 0:60d829a0353a 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
tushki7 0:60d829a0353a 155 /* GNU gcc specific functions */
tushki7 0:60d829a0353a 156
tushki7 0:60d829a0353a 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
tushki7 0:60d829a0353a 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 159 {
tushki7 0:60d829a0353a 160 uint32_t result;
tushki7 0:60d829a0353a 161
tushki7 0:60d829a0353a 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 163 return(result);
tushki7 0:60d829a0353a 164 }
tushki7 0:60d829a0353a 165
tushki7 0:60d829a0353a 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 167 {
tushki7 0:60d829a0353a 168 uint32_t result;
tushki7 0:60d829a0353a 169
tushki7 0:60d829a0353a 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 171 return(result);
tushki7 0:60d829a0353a 172 }
tushki7 0:60d829a0353a 173
tushki7 0:60d829a0353a 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 175 {
tushki7 0:60d829a0353a 176 uint32_t result;
tushki7 0:60d829a0353a 177
tushki7 0:60d829a0353a 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 179 return(result);
tushki7 0:60d829a0353a 180 }
tushki7 0:60d829a0353a 181
tushki7 0:60d829a0353a 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 183 {
tushki7 0:60d829a0353a 184 uint32_t result;
tushki7 0:60d829a0353a 185
tushki7 0:60d829a0353a 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 187 return(result);
tushki7 0:60d829a0353a 188 }
tushki7 0:60d829a0353a 189
tushki7 0:60d829a0353a 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 191 {
tushki7 0:60d829a0353a 192 uint32_t result;
tushki7 0:60d829a0353a 193
tushki7 0:60d829a0353a 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 195 return(result);
tushki7 0:60d829a0353a 196 }
tushki7 0:60d829a0353a 197
tushki7 0:60d829a0353a 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 199 {
tushki7 0:60d829a0353a 200 uint32_t result;
tushki7 0:60d829a0353a 201
tushki7 0:60d829a0353a 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 203 return(result);
tushki7 0:60d829a0353a 204 }
tushki7 0:60d829a0353a 205
tushki7 0:60d829a0353a 206
tushki7 0:60d829a0353a 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 208 {
tushki7 0:60d829a0353a 209 uint32_t result;
tushki7 0:60d829a0353a 210
tushki7 0:60d829a0353a 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 212 return(result);
tushki7 0:60d829a0353a 213 }
tushki7 0:60d829a0353a 214
tushki7 0:60d829a0353a 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 216 {
tushki7 0:60d829a0353a 217 uint32_t result;
tushki7 0:60d829a0353a 218
tushki7 0:60d829a0353a 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 220 return(result);
tushki7 0:60d829a0353a 221 }
tushki7 0:60d829a0353a 222
tushki7 0:60d829a0353a 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 224 {
tushki7 0:60d829a0353a 225 uint32_t result;
tushki7 0:60d829a0353a 226
tushki7 0:60d829a0353a 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 228 return(result);
tushki7 0:60d829a0353a 229 }
tushki7 0:60d829a0353a 230
tushki7 0:60d829a0353a 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 232 {
tushki7 0:60d829a0353a 233 uint32_t result;
tushki7 0:60d829a0353a 234
tushki7 0:60d829a0353a 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 236 return(result);
tushki7 0:60d829a0353a 237 }
tushki7 0:60d829a0353a 238
tushki7 0:60d829a0353a 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 240 {
tushki7 0:60d829a0353a 241 uint32_t result;
tushki7 0:60d829a0353a 242
tushki7 0:60d829a0353a 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 244 return(result);
tushki7 0:60d829a0353a 245 }
tushki7 0:60d829a0353a 246
tushki7 0:60d829a0353a 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 248 {
tushki7 0:60d829a0353a 249 uint32_t result;
tushki7 0:60d829a0353a 250
tushki7 0:60d829a0353a 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 252 return(result);
tushki7 0:60d829a0353a 253 }
tushki7 0:60d829a0353a 254
tushki7 0:60d829a0353a 255
tushki7 0:60d829a0353a 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 257 {
tushki7 0:60d829a0353a 258 uint32_t result;
tushki7 0:60d829a0353a 259
tushki7 0:60d829a0353a 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 261 return(result);
tushki7 0:60d829a0353a 262 }
tushki7 0:60d829a0353a 263
tushki7 0:60d829a0353a 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 265 {
tushki7 0:60d829a0353a 266 uint32_t result;
tushki7 0:60d829a0353a 267
tushki7 0:60d829a0353a 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 269 return(result);
tushki7 0:60d829a0353a 270 }
tushki7 0:60d829a0353a 271
tushki7 0:60d829a0353a 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 273 {
tushki7 0:60d829a0353a 274 uint32_t result;
tushki7 0:60d829a0353a 275
tushki7 0:60d829a0353a 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 277 return(result);
tushki7 0:60d829a0353a 278 }
tushki7 0:60d829a0353a 279
tushki7 0:60d829a0353a 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 281 {
tushki7 0:60d829a0353a 282 uint32_t result;
tushki7 0:60d829a0353a 283
tushki7 0:60d829a0353a 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 285 return(result);
tushki7 0:60d829a0353a 286 }
tushki7 0:60d829a0353a 287
tushki7 0:60d829a0353a 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 289 {
tushki7 0:60d829a0353a 290 uint32_t result;
tushki7 0:60d829a0353a 291
tushki7 0:60d829a0353a 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 293 return(result);
tushki7 0:60d829a0353a 294 }
tushki7 0:60d829a0353a 295
tushki7 0:60d829a0353a 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 297 {
tushki7 0:60d829a0353a 298 uint32_t result;
tushki7 0:60d829a0353a 299
tushki7 0:60d829a0353a 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 301 return(result);
tushki7 0:60d829a0353a 302 }
tushki7 0:60d829a0353a 303
tushki7 0:60d829a0353a 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 305 {
tushki7 0:60d829a0353a 306 uint32_t result;
tushki7 0:60d829a0353a 307
tushki7 0:60d829a0353a 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 309 return(result);
tushki7 0:60d829a0353a 310 }
tushki7 0:60d829a0353a 311
tushki7 0:60d829a0353a 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 313 {
tushki7 0:60d829a0353a 314 uint32_t result;
tushki7 0:60d829a0353a 315
tushki7 0:60d829a0353a 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 317 return(result);
tushki7 0:60d829a0353a 318 }
tushki7 0:60d829a0353a 319
tushki7 0:60d829a0353a 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 321 {
tushki7 0:60d829a0353a 322 uint32_t result;
tushki7 0:60d829a0353a 323
tushki7 0:60d829a0353a 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 325 return(result);
tushki7 0:60d829a0353a 326 }
tushki7 0:60d829a0353a 327
tushki7 0:60d829a0353a 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 329 {
tushki7 0:60d829a0353a 330 uint32_t result;
tushki7 0:60d829a0353a 331
tushki7 0:60d829a0353a 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 333 return(result);
tushki7 0:60d829a0353a 334 }
tushki7 0:60d829a0353a 335
tushki7 0:60d829a0353a 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 337 {
tushki7 0:60d829a0353a 338 uint32_t result;
tushki7 0:60d829a0353a 339
tushki7 0:60d829a0353a 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 341 return(result);
tushki7 0:60d829a0353a 342 }
tushki7 0:60d829a0353a 343
tushki7 0:60d829a0353a 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 345 {
tushki7 0:60d829a0353a 346 uint32_t result;
tushki7 0:60d829a0353a 347
tushki7 0:60d829a0353a 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 349 return(result);
tushki7 0:60d829a0353a 350 }
tushki7 0:60d829a0353a 351
tushki7 0:60d829a0353a 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 353 {
tushki7 0:60d829a0353a 354 uint32_t result;
tushki7 0:60d829a0353a 355
tushki7 0:60d829a0353a 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 357 return(result);
tushki7 0:60d829a0353a 358 }
tushki7 0:60d829a0353a 359
tushki7 0:60d829a0353a 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 361 {
tushki7 0:60d829a0353a 362 uint32_t result;
tushki7 0:60d829a0353a 363
tushki7 0:60d829a0353a 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 365 return(result);
tushki7 0:60d829a0353a 366 }
tushki7 0:60d829a0353a 367
tushki7 0:60d829a0353a 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 369 {
tushki7 0:60d829a0353a 370 uint32_t result;
tushki7 0:60d829a0353a 371
tushki7 0:60d829a0353a 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 373 return(result);
tushki7 0:60d829a0353a 374 }
tushki7 0:60d829a0353a 375
tushki7 0:60d829a0353a 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 377 {
tushki7 0:60d829a0353a 378 uint32_t result;
tushki7 0:60d829a0353a 379
tushki7 0:60d829a0353a 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 381 return(result);
tushki7 0:60d829a0353a 382 }
tushki7 0:60d829a0353a 383
tushki7 0:60d829a0353a 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 385 {
tushki7 0:60d829a0353a 386 uint32_t result;
tushki7 0:60d829a0353a 387
tushki7 0:60d829a0353a 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 389 return(result);
tushki7 0:60d829a0353a 390 }
tushki7 0:60d829a0353a 391
tushki7 0:60d829a0353a 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 393 {
tushki7 0:60d829a0353a 394 uint32_t result;
tushki7 0:60d829a0353a 395
tushki7 0:60d829a0353a 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 397 return(result);
tushki7 0:60d829a0353a 398 }
tushki7 0:60d829a0353a 399
tushki7 0:60d829a0353a 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 401 {
tushki7 0:60d829a0353a 402 uint32_t result;
tushki7 0:60d829a0353a 403
tushki7 0:60d829a0353a 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 405 return(result);
tushki7 0:60d829a0353a 406 }
tushki7 0:60d829a0353a 407
tushki7 0:60d829a0353a 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 409 {
tushki7 0:60d829a0353a 410 uint32_t result;
tushki7 0:60d829a0353a 411
tushki7 0:60d829a0353a 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 413 return(result);
tushki7 0:60d829a0353a 414 }
tushki7 0:60d829a0353a 415
tushki7 0:60d829a0353a 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 417 {
tushki7 0:60d829a0353a 418 uint32_t result;
tushki7 0:60d829a0353a 419
tushki7 0:60d829a0353a 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 421 return(result);
tushki7 0:60d829a0353a 422 }
tushki7 0:60d829a0353a 423
tushki7 0:60d829a0353a 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 425 {
tushki7 0:60d829a0353a 426 uint32_t result;
tushki7 0:60d829a0353a 427
tushki7 0:60d829a0353a 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 429 return(result);
tushki7 0:60d829a0353a 430 }
tushki7 0:60d829a0353a 431
tushki7 0:60d829a0353a 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 433 {
tushki7 0:60d829a0353a 434 uint32_t result;
tushki7 0:60d829a0353a 435
tushki7 0:60d829a0353a 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 437 return(result);
tushki7 0:60d829a0353a 438 }
tushki7 0:60d829a0353a 439
tushki7 0:60d829a0353a 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 441 {
tushki7 0:60d829a0353a 442 uint32_t result;
tushki7 0:60d829a0353a 443
tushki7 0:60d829a0353a 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 445 return(result);
tushki7 0:60d829a0353a 446 }
tushki7 0:60d829a0353a 447
tushki7 0:60d829a0353a 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 449 {
tushki7 0:60d829a0353a 450 uint32_t result;
tushki7 0:60d829a0353a 451
tushki7 0:60d829a0353a 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 453 return(result);
tushki7 0:60d829a0353a 454 }
tushki7 0:60d829a0353a 455
tushki7 0:60d829a0353a 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
tushki7 0:60d829a0353a 457 {
tushki7 0:60d829a0353a 458 uint32_t result;
tushki7 0:60d829a0353a 459
tushki7 0:60d829a0353a 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
tushki7 0:60d829a0353a 461 return(result);
tushki7 0:60d829a0353a 462 }
tushki7 0:60d829a0353a 463
tushki7 0:60d829a0353a 464 #define __SSAT16(ARG1,ARG2) \
tushki7 0:60d829a0353a 465 ({ \
tushki7 0:60d829a0353a 466 uint32_t __RES, __ARG1 = (ARG1); \
tushki7 0:60d829a0353a 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
tushki7 0:60d829a0353a 468 __RES; \
tushki7 0:60d829a0353a 469 })
tushki7 0:60d829a0353a 470
tushki7 0:60d829a0353a 471 #define __USAT16(ARG1,ARG2) \
tushki7 0:60d829a0353a 472 ({ \
tushki7 0:60d829a0353a 473 uint32_t __RES, __ARG1 = (ARG1); \
tushki7 0:60d829a0353a 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
tushki7 0:60d829a0353a 475 __RES; \
tushki7 0:60d829a0353a 476 })
tushki7 0:60d829a0353a 477
tushki7 0:60d829a0353a 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
tushki7 0:60d829a0353a 479 {
tushki7 0:60d829a0353a 480 uint32_t result;
tushki7 0:60d829a0353a 481
tushki7 0:60d829a0353a 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
tushki7 0:60d829a0353a 483 return(result);
tushki7 0:60d829a0353a 484 }
tushki7 0:60d829a0353a 485
tushki7 0:60d829a0353a 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 487 {
tushki7 0:60d829a0353a 488 uint32_t result;
tushki7 0:60d829a0353a 489
tushki7 0:60d829a0353a 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 491 return(result);
tushki7 0:60d829a0353a 492 }
tushki7 0:60d829a0353a 493
tushki7 0:60d829a0353a 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
tushki7 0:60d829a0353a 495 {
tushki7 0:60d829a0353a 496 uint32_t result;
tushki7 0:60d829a0353a 497
tushki7 0:60d829a0353a 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
tushki7 0:60d829a0353a 499 return(result);
tushki7 0:60d829a0353a 500 }
tushki7 0:60d829a0353a 501
tushki7 0:60d829a0353a 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 503 {
tushki7 0:60d829a0353a 504 uint32_t result;
tushki7 0:60d829a0353a 505
tushki7 0:60d829a0353a 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 507 return(result);
tushki7 0:60d829a0353a 508 }
tushki7 0:60d829a0353a 509
tushki7 0:60d829a0353a 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 511 {
tushki7 0:60d829a0353a 512 uint32_t result;
tushki7 0:60d829a0353a 513
tushki7 0:60d829a0353a 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 515 return(result);
tushki7 0:60d829a0353a 516 }
tushki7 0:60d829a0353a 517
tushki7 0:60d829a0353a 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 519 {
tushki7 0:60d829a0353a 520 uint32_t result;
tushki7 0:60d829a0353a 521
tushki7 0:60d829a0353a 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 523 return(result);
tushki7 0:60d829a0353a 524 }
tushki7 0:60d829a0353a 525
tushki7 0:60d829a0353a 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
tushki7 0:60d829a0353a 527 {
tushki7 0:60d829a0353a 528 uint32_t result;
tushki7 0:60d829a0353a 529
tushki7 0:60d829a0353a 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
tushki7 0:60d829a0353a 531 return(result);
tushki7 0:60d829a0353a 532 }
tushki7 0:60d829a0353a 533
tushki7 0:60d829a0353a 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
tushki7 0:60d829a0353a 535 {
tushki7 0:60d829a0353a 536 uint32_t result;
tushki7 0:60d829a0353a 537
tushki7 0:60d829a0353a 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
tushki7 0:60d829a0353a 539 return(result);
tushki7 0:60d829a0353a 540 }
tushki7 0:60d829a0353a 541
tushki7 0:60d829a0353a 542 #define __SMLALD(ARG1,ARG2,ARG3) \
tushki7 0:60d829a0353a 543 ({ \
tushki7 0:60d829a0353a 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
tushki7 0:60d829a0353a 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
tushki7 0:60d829a0353a 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
tushki7 0:60d829a0353a 547 })
tushki7 0:60d829a0353a 548
tushki7 0:60d829a0353a 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
tushki7 0:60d829a0353a 550 ({ \
tushki7 0:60d829a0353a 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
tushki7 0:60d829a0353a 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
tushki7 0:60d829a0353a 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
tushki7 0:60d829a0353a 554 })
tushki7 0:60d829a0353a 555
tushki7 0:60d829a0353a 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 557 {
tushki7 0:60d829a0353a 558 uint32_t result;
tushki7 0:60d829a0353a 559
tushki7 0:60d829a0353a 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 561 return(result);
tushki7 0:60d829a0353a 562 }
tushki7 0:60d829a0353a 563
tushki7 0:60d829a0353a 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 565 {
tushki7 0:60d829a0353a 566 uint32_t result;
tushki7 0:60d829a0353a 567
tushki7 0:60d829a0353a 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 569 return(result);
tushki7 0:60d829a0353a 570 }
tushki7 0:60d829a0353a 571
tushki7 0:60d829a0353a 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
tushki7 0:60d829a0353a 573 {
tushki7 0:60d829a0353a 574 uint32_t result;
tushki7 0:60d829a0353a 575
tushki7 0:60d829a0353a 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
tushki7 0:60d829a0353a 577 return(result);
tushki7 0:60d829a0353a 578 }
tushki7 0:60d829a0353a 579
tushki7 0:60d829a0353a 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
tushki7 0:60d829a0353a 581 {
tushki7 0:60d829a0353a 582 uint32_t result;
tushki7 0:60d829a0353a 583
tushki7 0:60d829a0353a 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
tushki7 0:60d829a0353a 585 return(result);
tushki7 0:60d829a0353a 586 }
tushki7 0:60d829a0353a 587
tushki7 0:60d829a0353a 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
tushki7 0:60d829a0353a 589 ({ \
tushki7 0:60d829a0353a 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
tushki7 0:60d829a0353a 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
tushki7 0:60d829a0353a 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
tushki7 0:60d829a0353a 593 })
tushki7 0:60d829a0353a 594
tushki7 0:60d829a0353a 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
tushki7 0:60d829a0353a 596 ({ \
tushki7 0:60d829a0353a 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
tushki7 0:60d829a0353a 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
tushki7 0:60d829a0353a 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
tushki7 0:60d829a0353a 600 })
tushki7 0:60d829a0353a 601
tushki7 0:60d829a0353a 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 603 {
tushki7 0:60d829a0353a 604 uint32_t result;
tushki7 0:60d829a0353a 605
tushki7 0:60d829a0353a 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 607 return(result);
tushki7 0:60d829a0353a 608 }
tushki7 0:60d829a0353a 609
tushki7 0:60d829a0353a 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 611 {
tushki7 0:60d829a0353a 612 uint32_t result;
tushki7 0:60d829a0353a 613
tushki7 0:60d829a0353a 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 615 return(result);
tushki7 0:60d829a0353a 616 }
tushki7 0:60d829a0353a 617
tushki7 0:60d829a0353a 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
tushki7 0:60d829a0353a 619 {
tushki7 0:60d829a0353a 620 uint32_t result;
tushki7 0:60d829a0353a 621
tushki7 0:60d829a0353a 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
tushki7 0:60d829a0353a 623 return(result);
tushki7 0:60d829a0353a 624 }
tushki7 0:60d829a0353a 625
tushki7 0:60d829a0353a 626 #define __PKHBT(ARG1,ARG2,ARG3) \
tushki7 0:60d829a0353a 627 ({ \
tushki7 0:60d829a0353a 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
tushki7 0:60d829a0353a 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
tushki7 0:60d829a0353a 630 __RES; \
tushki7 0:60d829a0353a 631 })
tushki7 0:60d829a0353a 632
tushki7 0:60d829a0353a 633 #define __PKHTB(ARG1,ARG2,ARG3) \
tushki7 0:60d829a0353a 634 ({ \
tushki7 0:60d829a0353a 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
tushki7 0:60d829a0353a 636 if (ARG3 == 0) \
tushki7 0:60d829a0353a 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
tushki7 0:60d829a0353a 638 else \
tushki7 0:60d829a0353a 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
tushki7 0:60d829a0353a 640 __RES; \
tushki7 0:60d829a0353a 641 })
tushki7 0:60d829a0353a 642
tushki7 0:60d829a0353a 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
tushki7 0:60d829a0353a 644 {
tushki7 0:60d829a0353a 645 int32_t result;
tushki7 0:60d829a0353a 646
tushki7 0:60d829a0353a 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
tushki7 0:60d829a0353a 648 return(result);
tushki7 0:60d829a0353a 649 }
tushki7 0:60d829a0353a 650
tushki7 0:60d829a0353a 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
tushki7 0:60d829a0353a 652
tushki7 0:60d829a0353a 653
tushki7 0:60d829a0353a 654
tushki7 0:60d829a0353a 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
tushki7 0:60d829a0353a 656 /* TASKING carm specific functions */
tushki7 0:60d829a0353a 657
tushki7 0:60d829a0353a 658
tushki7 0:60d829a0353a 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
tushki7 0:60d829a0353a 660 /* not yet supported */
tushki7 0:60d829a0353a 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
tushki7 0:60d829a0353a 662
tushki7 0:60d829a0353a 663
tushki7 0:60d829a0353a 664 #endif
tushki7 0:60d829a0353a 665
tushki7 0:60d829a0353a 666 /*@} end of group CMSIS_SIMD_intrinsics */
tushki7 0:60d829a0353a 667
tushki7 0:60d829a0353a 668
tushki7 0:60d829a0353a 669 #endif /* __CORE_CM4_SIMD_H */
tushki7 0:60d829a0353a 670
tushki7 0:60d829a0353a 671 #ifdef __cplusplus
tushki7 0:60d829a0353a 672 }
tushki7 0:60d829a0353a 673 #endif