Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_RZ_A1H/rspi_iobitmask.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a 
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /*******************************************************************************
tushki7 0:60d829a0353a 2 * DISCLAIMER
tushki7 0:60d829a0353a 3 * This software is supplied by Renesas Electronics Corporation and is only
tushki7 0:60d829a0353a 4 * intended for use with Renesas products. No other uses are authorized. This
tushki7 0:60d829a0353a 5 * software is owned by Renesas Electronics Corporation and is protected under
tushki7 0:60d829a0353a 6 * all applicable laws, including copyright laws.
tushki7 0:60d829a0353a 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
tushki7 0:60d829a0353a 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
tushki7 0:60d829a0353a 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
tushki7 0:60d829a0353a 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
tushki7 0:60d829a0353a 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
tushki7 0:60d829a0353a 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
tushki7 0:60d829a0353a 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
tushki7 0:60d829a0353a 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
tushki7 0:60d829a0353a 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
tushki7 0:60d829a0353a 16 * Renesas reserves the right, without notice, to make changes to this software
tushki7 0:60d829a0353a 17 * and to discontinue the availability of this software. By using this software,
tushki7 0:60d829a0353a 18 * you agree to the additional terms and conditions found by accessing the
tushki7 0:60d829a0353a 19 * following link:
tushki7 0:60d829a0353a 20 * http://www.renesas.com/disclaimer
tushki7 0:60d829a0353a 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
tushki7 0:60d829a0353a 22 *******************************************************************************/
tushki7 0:60d829a0353a 23 /*******************************************************************************
tushki7 0:60d829a0353a 24 * File Name : rspi_iobitmask.h
tushki7 0:60d829a0353a 25 * $Rev: 1114 $
tushki7 0:60d829a0353a 26 * $Date:: 2014-07-09 14:56:39 +0900#$
tushki7 0:60d829a0353a 27 * Description : Renesas Serial Peripheral Interface register define header
tushki7 0:60d829a0353a 28 *******************************************************************************/
tushki7 0:60d829a0353a 29 #ifndef RSPI_IOBITMASK_H
tushki7 0:60d829a0353a 30 #define RSPI_IOBITMASK_H
tushki7 0:60d829a0353a 31
tushki7 0:60d829a0353a 32
tushki7 0:60d829a0353a 33 /* ==== Mask values for IO registers ==== */
tushki7 0:60d829a0353a 34 #define RSPIn_SPCR_MODFEN (0x04u)
tushki7 0:60d829a0353a 35 #define RSPIn_SPCR_MSTR (0x08u)
tushki7 0:60d829a0353a 36 #define RSPIn_SPCR_SPEIE (0x10u)
tushki7 0:60d829a0353a 37 #define RSPIn_SPCR_SPTIE (0x20u)
tushki7 0:60d829a0353a 38 #define RSPIn_SPCR_SPE (0x40u)
tushki7 0:60d829a0353a 39 #define RSPIn_SPCR_SPRIE (0x80u)
tushki7 0:60d829a0353a 40
tushki7 0:60d829a0353a 41 #define RSPIn_SSLP_SSL0P (0x01u)
tushki7 0:60d829a0353a 42
tushki7 0:60d829a0353a 43 #define RSPIn_SPPCR_SPLP (0x01u)
tushki7 0:60d829a0353a 44 #define RSPIn_SPPCR_MOIFV (0x10u)
tushki7 0:60d829a0353a 45 #define RSPIn_SPPCR_MOIFE (0x20u)
tushki7 0:60d829a0353a 46
tushki7 0:60d829a0353a 47 #define RSPIn_SPSR_OVRF (0x01u)
tushki7 0:60d829a0353a 48 #define RSPIn_SPSR_MODF (0x04u)
tushki7 0:60d829a0353a 49 #define RSPIn_SPSR_SPTEF (0x20u)
tushki7 0:60d829a0353a 50 #define RSPIn_SPSR_TEND (0x40u)
tushki7 0:60d829a0353a 51 #define RSPIn_SPSR_SPRF (0x80u)
tushki7 0:60d829a0353a 52
tushki7 0:60d829a0353a 53 #define RSPIn_SPDR_UINT32 (0xFFFFFFFFuL)
tushki7 0:60d829a0353a 54
tushki7 0:60d829a0353a 55 #define RSPIn_SPDR_UINT16 (0xFFFFu)
tushki7 0:60d829a0353a 56
tushki7 0:60d829a0353a 57 #define RSPIn_SPDR_UINT8 (0xFFu)
tushki7 0:60d829a0353a 58
tushki7 0:60d829a0353a 59 #define RSPIn_SPSCR_SPSLN (0x03u)
tushki7 0:60d829a0353a 60
tushki7 0:60d829a0353a 61 #define RSPIn_SPSSR_SPCP (0x03u)
tushki7 0:60d829a0353a 62
tushki7 0:60d829a0353a 63 #define RSPIn_SPBR_SPR (0xFFu)
tushki7 0:60d829a0353a 64
tushki7 0:60d829a0353a 65 #define RSPIn_SPDCR_SPLW (0x60u)
tushki7 0:60d829a0353a 66 #define RSPIn_SPDCR_TXDMY (0x80u)
tushki7 0:60d829a0353a 67
tushki7 0:60d829a0353a 68 #define RSPIn_SPCKD_SCKDL (0x07u)
tushki7 0:60d829a0353a 69
tushki7 0:60d829a0353a 70 #define RSPIn_SSLND_SLNDL (0x07u)
tushki7 0:60d829a0353a 71
tushki7 0:60d829a0353a 72 #define RSPIn_SPND_SPNDL (0x07u)
tushki7 0:60d829a0353a 73
tushki7 0:60d829a0353a 74 #define RSPIn_SPCMD0_CPHA (0x0001u)
tushki7 0:60d829a0353a 75 #define RSPIn_SPCMD0_CPOL (0x0002u)
tushki7 0:60d829a0353a 76 #define RSPIn_SPCMD0_BRDV (0x000Cu)
tushki7 0:60d829a0353a 77 #define RSPIn_SPCMD0_SSLKP (0x0080u)
tushki7 0:60d829a0353a 78 #define RSPIn_SPCMD0_SPB (0x0F00u)
tushki7 0:60d829a0353a 79 #define RSPIn_SPCMD0_LSBF (0x1000u)
tushki7 0:60d829a0353a 80 #define RSPIn_SPCMD0_SPNDEN (0x2000u)
tushki7 0:60d829a0353a 81 #define RSPIn_SPCMD0_SLNDEN (0x4000u)
tushki7 0:60d829a0353a 82 #define RSPIn_SPCMD0_SCKDEN (0x8000u)
tushki7 0:60d829a0353a 83
tushki7 0:60d829a0353a 84 #define RSPIn_SPCMD1_CPHA (0x0001u)
tushki7 0:60d829a0353a 85 #define RSPIn_SPCMD1_CPOL (0x0002u)
tushki7 0:60d829a0353a 86 #define RSPIn_SPCMD1_BRDV (0x000Cu)
tushki7 0:60d829a0353a 87 #define RSPIn_SPCMD1_SSLKP (0x0080u)
tushki7 0:60d829a0353a 88 #define RSPIn_SPCMD1_SPB (0x0F00u)
tushki7 0:60d829a0353a 89 #define RSPIn_SPCMD1_LSBF (0x1000u)
tushki7 0:60d829a0353a 90 #define RSPIn_SPCMD1_SPNDEN (0x2000u)
tushki7 0:60d829a0353a 91 #define RSPIn_SPCMD1_SLNDEN (0x4000u)
tushki7 0:60d829a0353a 92 #define RSPIn_SPCMD1_SCKDEN (0x8000u)
tushki7 0:60d829a0353a 93
tushki7 0:60d829a0353a 94 #define RSPIn_SPCMD2_CPHA (0x0001u)
tushki7 0:60d829a0353a 95 #define RSPIn_SPCMD2_CPOL (0x0002u)
tushki7 0:60d829a0353a 96 #define RSPIn_SPCMD2_BRDV (0x000Cu)
tushki7 0:60d829a0353a 97 #define RSPIn_SPCMD2_SSLKP (0x0080u)
tushki7 0:60d829a0353a 98 #define RSPIn_SPCMD2_SPB (0x0F00u)
tushki7 0:60d829a0353a 99 #define RSPIn_SPCMD2_LSBF (0x1000u)
tushki7 0:60d829a0353a 100 #define RSPIn_SPCMD2_SPNDEN (0x2000u)
tushki7 0:60d829a0353a 101 #define RSPIn_SPCMD2_SLNDEN (0x4000u)
tushki7 0:60d829a0353a 102 #define RSPIn_SPCMD2_SCKDEN (0x8000u)
tushki7 0:60d829a0353a 103
tushki7 0:60d829a0353a 104 #define RSPIn_SPCMD3_CPHA (0x0001u)
tushki7 0:60d829a0353a 105 #define RSPIn_SPCMD3_CPOL (0x0002u)
tushki7 0:60d829a0353a 106 #define RSPIn_SPCMD3_BRDV (0x000Cu)
tushki7 0:60d829a0353a 107 #define RSPIn_SPCMD3_SSLKP (0x0080u)
tushki7 0:60d829a0353a 108 #define RSPIn_SPCMD3_SPB (0x0F00u)
tushki7 0:60d829a0353a 109 #define RSPIn_SPCMD3_LSBF (0x1000u)
tushki7 0:60d829a0353a 110 #define RSPIn_SPCMD3_SPNDEN (0x2000u)
tushki7 0:60d829a0353a 111 #define RSPIn_SPCMD3_SLNDEN (0x4000u)
tushki7 0:60d829a0353a 112 #define RSPIn_SPCMD3_SCKDEN (0x8000u)
tushki7 0:60d829a0353a 113
tushki7 0:60d829a0353a 114 #define RSPIn_SPBFCR_RXTRG (0x07u)
tushki7 0:60d829a0353a 115 #define RSPIn_SPBFCR_TXTRG (0x30u)
tushki7 0:60d829a0353a 116 #define RSPIn_SPBFCR_RXRST (0x40u)
tushki7 0:60d829a0353a 117 #define RSPIn_SPBFCR_TXRST (0x80u)
tushki7 0:60d829a0353a 118
tushki7 0:60d829a0353a 119 #define RSPIn_SPBFDR_R (0x003Fu)
tushki7 0:60d829a0353a 120 #define RSPIn_SPBFDR_T (0x0F00u)
tushki7 0:60d829a0353a 121
tushki7 0:60d829a0353a 122
tushki7 0:60d829a0353a 123 /* ==== Shift values for IO registers ==== */
tushki7 0:60d829a0353a 124 #define RSPIn_SPCR_MODFEN_SHIFT (2u)
tushki7 0:60d829a0353a 125 #define RSPIn_SPCR_MSTR_SHIFT (3u)
tushki7 0:60d829a0353a 126 #define RSPIn_SPCR_SPEIE_SHIFT (4u)
tushki7 0:60d829a0353a 127 #define RSPIn_SPCR_SPTIE_SHIFT (5u)
tushki7 0:60d829a0353a 128 #define RSPIn_SPCR_SPE_SHIFT (6u)
tushki7 0:60d829a0353a 129 #define RSPIn_SPCR_SPRIE_SHIFT (7u)
tushki7 0:60d829a0353a 130
tushki7 0:60d829a0353a 131 #define RSPIn_SSLP_SSL0P_SHIFT (0u)
tushki7 0:60d829a0353a 132
tushki7 0:60d829a0353a 133 #define RSPIn_SPPCR_SPLP_SHIFT (0u)
tushki7 0:60d829a0353a 134 #define RSPIn_SPPCR_MOIFV_SHIFT (4u)
tushki7 0:60d829a0353a 135 #define RSPIn_SPPCR_MOIFE_SHIFT (5u)
tushki7 0:60d829a0353a 136
tushki7 0:60d829a0353a 137 #define RSPIn_SPSR_OVRF_SHIFT (0u)
tushki7 0:60d829a0353a 138 #define RSPIn_SPSR_MODF_SHIFT (2u)
tushki7 0:60d829a0353a 139 #define RSPIn_SPSR_SPTEF_SHIFT (5u)
tushki7 0:60d829a0353a 140 #define RSPIn_SPSR_TEND_SHIFT (6u)
tushki7 0:60d829a0353a 141 #define RSPIn_SPSR_SPRF_SHIFT (7u)
tushki7 0:60d829a0353a 142
tushki7 0:60d829a0353a 143 #define RSPIn_SPDR_UINT32_SHIFT (0u)
tushki7 0:60d829a0353a 144
tushki7 0:60d829a0353a 145 #define RSPIn_SPDR_UINT16_SHIFT (0u)
tushki7 0:60d829a0353a 146
tushki7 0:60d829a0353a 147 #define RSPIn_SPDR_UINT8_SHIFT (0u)
tushki7 0:60d829a0353a 148
tushki7 0:60d829a0353a 149 #define RSPIn_SPSCR_SPSLN_SHIFT (0u)
tushki7 0:60d829a0353a 150
tushki7 0:60d829a0353a 151 #define RSPIn_SPSSR_SPCP_SHIFT (0u)
tushki7 0:60d829a0353a 152
tushki7 0:60d829a0353a 153 #define RSPIn_SPBR_SPR_SHIFT (0u)
tushki7 0:60d829a0353a 154
tushki7 0:60d829a0353a 155 #define RSPIn_SPDCR_SPLW_SHIFT (5u)
tushki7 0:60d829a0353a 156 #define RSPIn_SPDCR_TXDMY_SHIFT (7u)
tushki7 0:60d829a0353a 157
tushki7 0:60d829a0353a 158 #define RSPIn_SPCKD_SCKDL_SHIFT (0u)
tushki7 0:60d829a0353a 159
tushki7 0:60d829a0353a 160 #define RSPIn_SSLND_SLNDL_SHIFT (0u)
tushki7 0:60d829a0353a 161
tushki7 0:60d829a0353a 162 #define RSPIn_SPND_SPNDL_SHIFT (0u)
tushki7 0:60d829a0353a 163
tushki7 0:60d829a0353a 164 #define RSPIn_SPCMD0_CPHA_SHIFT (0u)
tushki7 0:60d829a0353a 165 #define RSPIn_SPCMD0_CPOL_SHIFT (1u)
tushki7 0:60d829a0353a 166 #define RSPIn_SPCMD0_BRDV_SHIFT (2u)
tushki7 0:60d829a0353a 167 #define RSPIn_SPCMD0_SSLKP_SHIFT (7u)
tushki7 0:60d829a0353a 168 #define RSPIn_SPCMD0_SPB_SHIFT (8u)
tushki7 0:60d829a0353a 169 #define RSPIn_SPCMD0_LSBF_SHIFT (12u)
tushki7 0:60d829a0353a 170 #define RSPIn_SPCMD0_SPNDEN_SHIFT (13u)
tushki7 0:60d829a0353a 171 #define RSPIn_SPCMD0_SLNDEN_SHIFT (14u)
tushki7 0:60d829a0353a 172 #define RSPIn_SPCMD0_SCKDEN_SHIFT (15u)
tushki7 0:60d829a0353a 173
tushki7 0:60d829a0353a 174 #define RSPIn_SPCMD1_CPHA_SHIFT (0u)
tushki7 0:60d829a0353a 175 #define RSPIn_SPCMD1_CPOL_SHIFT (1u)
tushki7 0:60d829a0353a 176 #define RSPIn_SPCMD1_BRDV_SHIFT (2u)
tushki7 0:60d829a0353a 177 #define RSPIn_SPCMD1_SSLKP_SHIFT (7u)
tushki7 0:60d829a0353a 178 #define RSPIn_SPCMD1_SPB_SHIFT (8u)
tushki7 0:60d829a0353a 179 #define RSPIn_SPCMD1_LSBF_SHIFT (12u)
tushki7 0:60d829a0353a 180 #define RSPIn_SPCMD1_SPNDEN_SHIFT (13u)
tushki7 0:60d829a0353a 181 #define RSPIn_SPCMD1_SLNDEN_SHIFT (14u)
tushki7 0:60d829a0353a 182 #define RSPIn_SPCMD1_SCKDEN_SHIFT (15u)
tushki7 0:60d829a0353a 183
tushki7 0:60d829a0353a 184 #define RSPIn_SPCMD2_CPHA_SHIFT (0u)
tushki7 0:60d829a0353a 185 #define RSPIn_SPCMD2_CPOL_SHIFT (1u)
tushki7 0:60d829a0353a 186 #define RSPIn_SPCMD2_BRDV_SHIFT (2u)
tushki7 0:60d829a0353a 187 #define RSPIn_SPCMD2_SSLKP_SHIFT (7u)
tushki7 0:60d829a0353a 188 #define RSPIn_SPCMD2_SPB_SHIFT (8u)
tushki7 0:60d829a0353a 189 #define RSPIn_SPCMD2_LSBF_SHIFT (12u)
tushki7 0:60d829a0353a 190 #define RSPIn_SPCMD2_SPNDEN_SHIFT (13u)
tushki7 0:60d829a0353a 191 #define RSPIn_SPCMD2_SLNDEN_SHIFT (14u)
tushki7 0:60d829a0353a 192 #define RSPIn_SPCMD2_SCKDEN_SHIFT (15u)
tushki7 0:60d829a0353a 193
tushki7 0:60d829a0353a 194 #define RSPIn_SPCMD3_CPHA_SHIFT (0u)
tushki7 0:60d829a0353a 195 #define RSPIn_SPCMD3_CPOL_SHIFT (1u)
tushki7 0:60d829a0353a 196 #define RSPIn_SPCMD3_BRDV_SHIFT (2u)
tushki7 0:60d829a0353a 197 #define RSPIn_SPCMD3_SSLKP_SHIFT (7u)
tushki7 0:60d829a0353a 198 #define RSPIn_SPCMD3_SPB_SHIFT (8u)
tushki7 0:60d829a0353a 199 #define RSPIn_SPCMD3_LSBF_SHIFT (12u)
tushki7 0:60d829a0353a 200 #define RSPIn_SPCMD3_SPNDEN_SHIFT (13u)
tushki7 0:60d829a0353a 201 #define RSPIn_SPCMD3_SLNDEN_SHIFT (14u)
tushki7 0:60d829a0353a 202 #define RSPIn_SPCMD3_SCKDEN_SHIFT (15u)
tushki7 0:60d829a0353a 203
tushki7 0:60d829a0353a 204 #define RSPIn_SPBFCR_RXTRG_SHIFT (0u)
tushki7 0:60d829a0353a 205 #define RSPIn_SPBFCR_TXTRG_SHIFT (4u)
tushki7 0:60d829a0353a 206 #define RSPIn_SPBFCR_RXRST_SHIFT (6u)
tushki7 0:60d829a0353a 207 #define RSPIn_SPBFCR_TXRST_SHIFT (7u)
tushki7 0:60d829a0353a 208
tushki7 0:60d829a0353a 209 #define RSPIn_SPBFDR_R_SHIFT (0u)
tushki7 0:60d829a0353a 210 #define RSPIn_SPBFDR_T_SHIFT (8u)
tushki7 0:60d829a0353a 211
tushki7 0:60d829a0353a 212
tushki7 0:60d829a0353a 213 #endif /* RSPI_IOBITMASK_H */
tushki7 0:60d829a0353a 214
tushki7 0:60d829a0353a 215 /* End of File */