Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_RZ_A1H/core_cm0plus.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a 
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /**************************************************************************//**
tushki7 0:60d829a0353a 2 * @file core_cm0plus.h
tushki7 0:60d829a0353a 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
tushki7 0:60d829a0353a 4 * @version V3.20
tushki7 0:60d829a0353a 5 * @date 25. February 2013
tushki7 0:60d829a0353a 6 *
tushki7 0:60d829a0353a 7 * @note
tushki7 0:60d829a0353a 8 *
tushki7 0:60d829a0353a 9 ******************************************************************************/
tushki7 0:60d829a0353a 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
tushki7 0:60d829a0353a 11
tushki7 0:60d829a0353a 12 All rights reserved.
tushki7 0:60d829a0353a 13 Redistribution and use in source and binary forms, with or without
tushki7 0:60d829a0353a 14 modification, are permitted provided that the following conditions are met:
tushki7 0:60d829a0353a 15 - Redistributions of source code must retain the above copyright
tushki7 0:60d829a0353a 16 notice, this list of conditions and the following disclaimer.
tushki7 0:60d829a0353a 17 - Redistributions in binary form must reproduce the above copyright
tushki7 0:60d829a0353a 18 notice, this list of conditions and the following disclaimer in the
tushki7 0:60d829a0353a 19 documentation and/or other materials provided with the distribution.
tushki7 0:60d829a0353a 20 - Neither the name of ARM nor the names of its contributors may be used
tushki7 0:60d829a0353a 21 to endorse or promote products derived from this software without
tushki7 0:60d829a0353a 22 specific prior written permission.
tushki7 0:60d829a0353a 23 *
tushki7 0:60d829a0353a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
tushki7 0:60d829a0353a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
tushki7 0:60d829a0353a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
tushki7 0:60d829a0353a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
tushki7 0:60d829a0353a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
tushki7 0:60d829a0353a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
tushki7 0:60d829a0353a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
tushki7 0:60d829a0353a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
tushki7 0:60d829a0353a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
tushki7 0:60d829a0353a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
tushki7 0:60d829a0353a 34 POSSIBILITY OF SUCH DAMAGE.
tushki7 0:60d829a0353a 35 ---------------------------------------------------------------------------*/
tushki7 0:60d829a0353a 36
tushki7 0:60d829a0353a 37
tushki7 0:60d829a0353a 38 #if defined ( __ICCARM__ )
tushki7 0:60d829a0353a 39 #pragma system_include /* treat file as system include file for MISRA check */
tushki7 0:60d829a0353a 40 #endif
tushki7 0:60d829a0353a 41
tushki7 0:60d829a0353a 42 #ifdef __cplusplus
tushki7 0:60d829a0353a 43 extern "C" {
tushki7 0:60d829a0353a 44 #endif
tushki7 0:60d829a0353a 45
tushki7 0:60d829a0353a 46 #ifndef __CORE_CM0PLUS_H_GENERIC
tushki7 0:60d829a0353a 47 #define __CORE_CM0PLUS_H_GENERIC
tushki7 0:60d829a0353a 48
tushki7 0:60d829a0353a 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
tushki7 0:60d829a0353a 50 CMSIS violates the following MISRA-C:2004 rules:
tushki7 0:60d829a0353a 51
tushki7 0:60d829a0353a 52 \li Required Rule 8.5, object/function definition in header file.<br>
tushki7 0:60d829a0353a 53 Function definitions in header files are used to allow 'inlining'.
tushki7 0:60d829a0353a 54
tushki7 0:60d829a0353a 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
tushki7 0:60d829a0353a 56 Unions are used for effective representation of core registers.
tushki7 0:60d829a0353a 57
tushki7 0:60d829a0353a 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
tushki7 0:60d829a0353a 59 Function-like macros are used to allow more efficient code.
tushki7 0:60d829a0353a 60 */
tushki7 0:60d829a0353a 61
tushki7 0:60d829a0353a 62
tushki7 0:60d829a0353a 63 /*******************************************************************************
tushki7 0:60d829a0353a 64 * CMSIS definitions
tushki7 0:60d829a0353a 65 ******************************************************************************/
tushki7 0:60d829a0353a 66 /** \ingroup Cortex-M0+
tushki7 0:60d829a0353a 67 @{
tushki7 0:60d829a0353a 68 */
tushki7 0:60d829a0353a 69
tushki7 0:60d829a0353a 70 /* CMSIS CM0P definitions */
tushki7 0:60d829a0353a 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
tushki7 0:60d829a0353a 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
tushki7 0:60d829a0353a 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
tushki7 0:60d829a0353a 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
tushki7 0:60d829a0353a 75
tushki7 0:60d829a0353a 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
tushki7 0:60d829a0353a 77
tushki7 0:60d829a0353a 78
tushki7 0:60d829a0353a 79 #if defined ( __CC_ARM )
tushki7 0:60d829a0353a 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
tushki7 0:60d829a0353a 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
tushki7 0:60d829a0353a 82 #define __STATIC_INLINE static __inline
tushki7 0:60d829a0353a 83
tushki7 0:60d829a0353a 84 #elif defined ( __ICCARM__ )
tushki7 0:60d829a0353a 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
tushki7 0:60d829a0353a 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
tushki7 0:60d829a0353a 87 #define __STATIC_INLINE static inline
tushki7 0:60d829a0353a 88
tushki7 0:60d829a0353a 89 #elif defined ( __GNUC__ )
tushki7 0:60d829a0353a 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
tushki7 0:60d829a0353a 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
tushki7 0:60d829a0353a 92 #define __STATIC_INLINE static inline
tushki7 0:60d829a0353a 93
tushki7 0:60d829a0353a 94 #elif defined ( __TASKING__ )
tushki7 0:60d829a0353a 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
tushki7 0:60d829a0353a 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
tushki7 0:60d829a0353a 97 #define __STATIC_INLINE static inline
tushki7 0:60d829a0353a 98
tushki7 0:60d829a0353a 99 #endif
tushki7 0:60d829a0353a 100
tushki7 0:60d829a0353a 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
tushki7 0:60d829a0353a 102 */
tushki7 0:60d829a0353a 103 #define __FPU_USED 0
tushki7 0:60d829a0353a 104
tushki7 0:60d829a0353a 105 #if defined ( __CC_ARM )
tushki7 0:60d829a0353a 106 #if defined __TARGET_FPU_VFP
tushki7 0:60d829a0353a 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
tushki7 0:60d829a0353a 108 #endif
tushki7 0:60d829a0353a 109
tushki7 0:60d829a0353a 110 #elif defined ( __ICCARM__ )
tushki7 0:60d829a0353a 111 #if defined __ARMVFP__
tushki7 0:60d829a0353a 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
tushki7 0:60d829a0353a 113 #endif
tushki7 0:60d829a0353a 114
tushki7 0:60d829a0353a 115 #elif defined ( __GNUC__ )
tushki7 0:60d829a0353a 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
tushki7 0:60d829a0353a 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
tushki7 0:60d829a0353a 118 #endif
tushki7 0:60d829a0353a 119
tushki7 0:60d829a0353a 120 #elif defined ( __TASKING__ )
tushki7 0:60d829a0353a 121 #if defined __FPU_VFP__
tushki7 0:60d829a0353a 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
tushki7 0:60d829a0353a 123 #endif
tushki7 0:60d829a0353a 124 #endif
tushki7 0:60d829a0353a 125
tushki7 0:60d829a0353a 126 #include <stdint.h> /* standard types definitions */
tushki7 0:60d829a0353a 127 #include <core_cmInstr.h> /* Core Instruction Access */
tushki7 0:60d829a0353a 128 #include <core_cmFunc.h> /* Core Function Access */
tushki7 0:60d829a0353a 129
tushki7 0:60d829a0353a 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
tushki7 0:60d829a0353a 131
tushki7 0:60d829a0353a 132 #ifndef __CMSIS_GENERIC
tushki7 0:60d829a0353a 133
tushki7 0:60d829a0353a 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
tushki7 0:60d829a0353a 135 #define __CORE_CM0PLUS_H_DEPENDANT
tushki7 0:60d829a0353a 136
tushki7 0:60d829a0353a 137 /* check device defines and use defaults */
tushki7 0:60d829a0353a 138 #if defined __CHECK_DEVICE_DEFINES
tushki7 0:60d829a0353a 139 #ifndef __CM0PLUS_REV
tushki7 0:60d829a0353a 140 #define __CM0PLUS_REV 0x0000
tushki7 0:60d829a0353a 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
tushki7 0:60d829a0353a 142 #endif
tushki7 0:60d829a0353a 143
tushki7 0:60d829a0353a 144 #ifndef __MPU_PRESENT
tushki7 0:60d829a0353a 145 #define __MPU_PRESENT 0
tushki7 0:60d829a0353a 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
tushki7 0:60d829a0353a 147 #endif
tushki7 0:60d829a0353a 148
tushki7 0:60d829a0353a 149 #ifndef __VTOR_PRESENT
tushki7 0:60d829a0353a 150 #define __VTOR_PRESENT 0
tushki7 0:60d829a0353a 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
tushki7 0:60d829a0353a 152 #endif
tushki7 0:60d829a0353a 153
tushki7 0:60d829a0353a 154 #ifndef __NVIC_PRIO_BITS
tushki7 0:60d829a0353a 155 #define __NVIC_PRIO_BITS 2
tushki7 0:60d829a0353a 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
tushki7 0:60d829a0353a 157 #endif
tushki7 0:60d829a0353a 158
tushki7 0:60d829a0353a 159 #ifndef __Vendor_SysTickConfig
tushki7 0:60d829a0353a 160 #define __Vendor_SysTickConfig 0
tushki7 0:60d829a0353a 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
tushki7 0:60d829a0353a 162 #endif
tushki7 0:60d829a0353a 163 #endif
tushki7 0:60d829a0353a 164
tushki7 0:60d829a0353a 165 /* IO definitions (access restrictions to peripheral registers) */
tushki7 0:60d829a0353a 166 /**
tushki7 0:60d829a0353a 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
tushki7 0:60d829a0353a 168
tushki7 0:60d829a0353a 169 <strong>IO Type Qualifiers</strong> are used
tushki7 0:60d829a0353a 170 \li to specify the access to peripheral variables.
tushki7 0:60d829a0353a 171 \li for automatic generation of peripheral register debug information.
tushki7 0:60d829a0353a 172 */
tushki7 0:60d829a0353a 173 #ifdef __cplusplus
tushki7 0:60d829a0353a 174 #define __I volatile /*!< Defines 'read only' permissions */
tushki7 0:60d829a0353a 175 #else
tushki7 0:60d829a0353a 176 #define __I volatile const /*!< Defines 'read only' permissions */
tushki7 0:60d829a0353a 177 #endif
tushki7 0:60d829a0353a 178 #define __O volatile /*!< Defines 'write only' permissions */
tushki7 0:60d829a0353a 179 #define __IO volatile /*!< Defines 'read / write' permissions */
tushki7 0:60d829a0353a 180
tushki7 0:60d829a0353a 181 /*@} end of group Cortex-M0+ */
tushki7 0:60d829a0353a 182
tushki7 0:60d829a0353a 183
tushki7 0:60d829a0353a 184
tushki7 0:60d829a0353a 185 /*******************************************************************************
tushki7 0:60d829a0353a 186 * Register Abstraction
tushki7 0:60d829a0353a 187 Core Register contain:
tushki7 0:60d829a0353a 188 - Core Register
tushki7 0:60d829a0353a 189 - Core NVIC Register
tushki7 0:60d829a0353a 190 - Core SCB Register
tushki7 0:60d829a0353a 191 - Core SysTick Register
tushki7 0:60d829a0353a 192 - Core MPU Register
tushki7 0:60d829a0353a 193 ******************************************************************************/
tushki7 0:60d829a0353a 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
tushki7 0:60d829a0353a 195 \brief Type definitions and defines for Cortex-M processor based devices.
tushki7 0:60d829a0353a 196 */
tushki7 0:60d829a0353a 197
tushki7 0:60d829a0353a 198 /** \ingroup CMSIS_core_register
tushki7 0:60d829a0353a 199 \defgroup CMSIS_CORE Status and Control Registers
tushki7 0:60d829a0353a 200 \brief Core Register type definitions.
tushki7 0:60d829a0353a 201 @{
tushki7 0:60d829a0353a 202 */
tushki7 0:60d829a0353a 203
tushki7 0:60d829a0353a 204 /** \brief Union type to access the Application Program Status Register (APSR).
tushki7 0:60d829a0353a 205 */
tushki7 0:60d829a0353a 206 typedef union
tushki7 0:60d829a0353a 207 {
tushki7 0:60d829a0353a 208 struct
tushki7 0:60d829a0353a 209 {
tushki7 0:60d829a0353a 210 #if (__CORTEX_M != 0x04)
tushki7 0:60d829a0353a 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
tushki7 0:60d829a0353a 212 #else
tushki7 0:60d829a0353a 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
tushki7 0:60d829a0353a 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
tushki7 0:60d829a0353a 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
tushki7 0:60d829a0353a 216 #endif
tushki7 0:60d829a0353a 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
tushki7 0:60d829a0353a 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
tushki7 0:60d829a0353a 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
tushki7 0:60d829a0353a 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
tushki7 0:60d829a0353a 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
tushki7 0:60d829a0353a 222 } b; /*!< Structure used for bit access */
tushki7 0:60d829a0353a 223 uint32_t w; /*!< Type used for word access */
tushki7 0:60d829a0353a 224 } APSR_Type;
tushki7 0:60d829a0353a 225
tushki7 0:60d829a0353a 226
tushki7 0:60d829a0353a 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
tushki7 0:60d829a0353a 228 */
tushki7 0:60d829a0353a 229 typedef union
tushki7 0:60d829a0353a 230 {
tushki7 0:60d829a0353a 231 struct
tushki7 0:60d829a0353a 232 {
tushki7 0:60d829a0353a 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
tushki7 0:60d829a0353a 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
tushki7 0:60d829a0353a 235 } b; /*!< Structure used for bit access */
tushki7 0:60d829a0353a 236 uint32_t w; /*!< Type used for word access */
tushki7 0:60d829a0353a 237 } IPSR_Type;
tushki7 0:60d829a0353a 238
tushki7 0:60d829a0353a 239
tushki7 0:60d829a0353a 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
tushki7 0:60d829a0353a 241 */
tushki7 0:60d829a0353a 242 typedef union
tushki7 0:60d829a0353a 243 {
tushki7 0:60d829a0353a 244 struct
tushki7 0:60d829a0353a 245 {
tushki7 0:60d829a0353a 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
tushki7 0:60d829a0353a 247 #if (__CORTEX_M != 0x04)
tushki7 0:60d829a0353a 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
tushki7 0:60d829a0353a 249 #else
tushki7 0:60d829a0353a 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
tushki7 0:60d829a0353a 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
tushki7 0:60d829a0353a 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
tushki7 0:60d829a0353a 253 #endif
tushki7 0:60d829a0353a 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
tushki7 0:60d829a0353a 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
tushki7 0:60d829a0353a 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
tushki7 0:60d829a0353a 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
tushki7 0:60d829a0353a 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
tushki7 0:60d829a0353a 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
tushki7 0:60d829a0353a 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
tushki7 0:60d829a0353a 261 } b; /*!< Structure used for bit access */
tushki7 0:60d829a0353a 262 uint32_t w; /*!< Type used for word access */
tushki7 0:60d829a0353a 263 } xPSR_Type;
tushki7 0:60d829a0353a 264
tushki7 0:60d829a0353a 265
tushki7 0:60d829a0353a 266 /** \brief Union type to access the Control Registers (CONTROL).
tushki7 0:60d829a0353a 267 */
tushki7 0:60d829a0353a 268 typedef union
tushki7 0:60d829a0353a 269 {
tushki7 0:60d829a0353a 270 struct
tushki7 0:60d829a0353a 271 {
tushki7 0:60d829a0353a 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
tushki7 0:60d829a0353a 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
tushki7 0:60d829a0353a 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
tushki7 0:60d829a0353a 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
tushki7 0:60d829a0353a 276 } b; /*!< Structure used for bit access */
tushki7 0:60d829a0353a 277 uint32_t w; /*!< Type used for word access */
tushki7 0:60d829a0353a 278 } CONTROL_Type;
tushki7 0:60d829a0353a 279
tushki7 0:60d829a0353a 280 /*@} end of group CMSIS_CORE */
tushki7 0:60d829a0353a 281
tushki7 0:60d829a0353a 282
tushki7 0:60d829a0353a 283 /** \ingroup CMSIS_core_register
tushki7 0:60d829a0353a 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
tushki7 0:60d829a0353a 285 \brief Type definitions for the NVIC Registers
tushki7 0:60d829a0353a 286 @{
tushki7 0:60d829a0353a 287 */
tushki7 0:60d829a0353a 288
tushki7 0:60d829a0353a 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
tushki7 0:60d829a0353a 290 */
tushki7 0:60d829a0353a 291 typedef struct
tushki7 0:60d829a0353a 292 {
tushki7 0:60d829a0353a 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
tushki7 0:60d829a0353a 294 uint32_t RESERVED0[31];
tushki7 0:60d829a0353a 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
tushki7 0:60d829a0353a 296 uint32_t RSERVED1[31];
tushki7 0:60d829a0353a 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
tushki7 0:60d829a0353a 298 uint32_t RESERVED2[31];
tushki7 0:60d829a0353a 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
tushki7 0:60d829a0353a 300 uint32_t RESERVED3[31];
tushki7 0:60d829a0353a 301 uint32_t RESERVED4[64];
tushki7 0:60d829a0353a 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
tushki7 0:60d829a0353a 303 } NVIC_Type;
tushki7 0:60d829a0353a 304
tushki7 0:60d829a0353a 305 /*@} end of group CMSIS_NVIC */
tushki7 0:60d829a0353a 306
tushki7 0:60d829a0353a 307
tushki7 0:60d829a0353a 308 /** \ingroup CMSIS_core_register
tushki7 0:60d829a0353a 309 \defgroup CMSIS_SCB System Control Block (SCB)
tushki7 0:60d829a0353a 310 \brief Type definitions for the System Control Block Registers
tushki7 0:60d829a0353a 311 @{
tushki7 0:60d829a0353a 312 */
tushki7 0:60d829a0353a 313
tushki7 0:60d829a0353a 314 /** \brief Structure type to access the System Control Block (SCB).
tushki7 0:60d829a0353a 315 */
tushki7 0:60d829a0353a 316 typedef struct
tushki7 0:60d829a0353a 317 {
tushki7 0:60d829a0353a 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
tushki7 0:60d829a0353a 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
tushki7 0:60d829a0353a 320 #if (__VTOR_PRESENT == 1)
tushki7 0:60d829a0353a 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
tushki7 0:60d829a0353a 322 #else
tushki7 0:60d829a0353a 323 uint32_t RESERVED0;
tushki7 0:60d829a0353a 324 #endif
tushki7 0:60d829a0353a 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
tushki7 0:60d829a0353a 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
tushki7 0:60d829a0353a 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
tushki7 0:60d829a0353a 328 uint32_t RESERVED1;
tushki7 0:60d829a0353a 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
tushki7 0:60d829a0353a 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
tushki7 0:60d829a0353a 331 } SCB_Type;
tushki7 0:60d829a0353a 332
tushki7 0:60d829a0353a 333 /* SCB CPUID Register Definitions */
tushki7 0:60d829a0353a 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
tushki7 0:60d829a0353a 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
tushki7 0:60d829a0353a 336
tushki7 0:60d829a0353a 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
tushki7 0:60d829a0353a 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
tushki7 0:60d829a0353a 339
tushki7 0:60d829a0353a 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
tushki7 0:60d829a0353a 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
tushki7 0:60d829a0353a 342
tushki7 0:60d829a0353a 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
tushki7 0:60d829a0353a 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
tushki7 0:60d829a0353a 345
tushki7 0:60d829a0353a 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
tushki7 0:60d829a0353a 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
tushki7 0:60d829a0353a 348
tushki7 0:60d829a0353a 349 /* SCB Interrupt Control State Register Definitions */
tushki7 0:60d829a0353a 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
tushki7 0:60d829a0353a 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
tushki7 0:60d829a0353a 352
tushki7 0:60d829a0353a 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
tushki7 0:60d829a0353a 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
tushki7 0:60d829a0353a 355
tushki7 0:60d829a0353a 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
tushki7 0:60d829a0353a 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
tushki7 0:60d829a0353a 358
tushki7 0:60d829a0353a 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
tushki7 0:60d829a0353a 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
tushki7 0:60d829a0353a 361
tushki7 0:60d829a0353a 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
tushki7 0:60d829a0353a 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
tushki7 0:60d829a0353a 364
tushki7 0:60d829a0353a 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
tushki7 0:60d829a0353a 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
tushki7 0:60d829a0353a 367
tushki7 0:60d829a0353a 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
tushki7 0:60d829a0353a 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
tushki7 0:60d829a0353a 370
tushki7 0:60d829a0353a 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
tushki7 0:60d829a0353a 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
tushki7 0:60d829a0353a 373
tushki7 0:60d829a0353a 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
tushki7 0:60d829a0353a 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
tushki7 0:60d829a0353a 376
tushki7 0:60d829a0353a 377 #if (__VTOR_PRESENT == 1)
tushki7 0:60d829a0353a 378 /* SCB Interrupt Control State Register Definitions */
tushki7 0:60d829a0353a 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
tushki7 0:60d829a0353a 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
tushki7 0:60d829a0353a 381 #endif
tushki7 0:60d829a0353a 382
tushki7 0:60d829a0353a 383 /* SCB Application Interrupt and Reset Control Register Definitions */
tushki7 0:60d829a0353a 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
tushki7 0:60d829a0353a 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
tushki7 0:60d829a0353a 386
tushki7 0:60d829a0353a 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
tushki7 0:60d829a0353a 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
tushki7 0:60d829a0353a 389
tushki7 0:60d829a0353a 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
tushki7 0:60d829a0353a 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
tushki7 0:60d829a0353a 392
tushki7 0:60d829a0353a 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
tushki7 0:60d829a0353a 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
tushki7 0:60d829a0353a 395
tushki7 0:60d829a0353a 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
tushki7 0:60d829a0353a 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
tushki7 0:60d829a0353a 398
tushki7 0:60d829a0353a 399 /* SCB System Control Register Definitions */
tushki7 0:60d829a0353a 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
tushki7 0:60d829a0353a 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
tushki7 0:60d829a0353a 402
tushki7 0:60d829a0353a 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
tushki7 0:60d829a0353a 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
tushki7 0:60d829a0353a 405
tushki7 0:60d829a0353a 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
tushki7 0:60d829a0353a 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
tushki7 0:60d829a0353a 408
tushki7 0:60d829a0353a 409 /* SCB Configuration Control Register Definitions */
tushki7 0:60d829a0353a 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
tushki7 0:60d829a0353a 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
tushki7 0:60d829a0353a 412
tushki7 0:60d829a0353a 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
tushki7 0:60d829a0353a 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
tushki7 0:60d829a0353a 415
tushki7 0:60d829a0353a 416 /* SCB System Handler Control and State Register Definitions */
tushki7 0:60d829a0353a 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
tushki7 0:60d829a0353a 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
tushki7 0:60d829a0353a 419
tushki7 0:60d829a0353a 420 /*@} end of group CMSIS_SCB */
tushki7 0:60d829a0353a 421
tushki7 0:60d829a0353a 422
tushki7 0:60d829a0353a 423 /** \ingroup CMSIS_core_register
tushki7 0:60d829a0353a 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
tushki7 0:60d829a0353a 425 \brief Type definitions for the System Timer Registers.
tushki7 0:60d829a0353a 426 @{
tushki7 0:60d829a0353a 427 */
tushki7 0:60d829a0353a 428
tushki7 0:60d829a0353a 429 /** \brief Structure type to access the System Timer (SysTick).
tushki7 0:60d829a0353a 430 */
tushki7 0:60d829a0353a 431 typedef struct
tushki7 0:60d829a0353a 432 {
tushki7 0:60d829a0353a 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
tushki7 0:60d829a0353a 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
tushki7 0:60d829a0353a 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
tushki7 0:60d829a0353a 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
tushki7 0:60d829a0353a 437 } SysTick_Type;
tushki7 0:60d829a0353a 438
tushki7 0:60d829a0353a 439 /* SysTick Control / Status Register Definitions */
tushki7 0:60d829a0353a 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
tushki7 0:60d829a0353a 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
tushki7 0:60d829a0353a 442
tushki7 0:60d829a0353a 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
tushki7 0:60d829a0353a 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
tushki7 0:60d829a0353a 445
tushki7 0:60d829a0353a 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
tushki7 0:60d829a0353a 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
tushki7 0:60d829a0353a 448
tushki7 0:60d829a0353a 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
tushki7 0:60d829a0353a 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
tushki7 0:60d829a0353a 451
tushki7 0:60d829a0353a 452 /* SysTick Reload Register Definitions */
tushki7 0:60d829a0353a 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
tushki7 0:60d829a0353a 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
tushki7 0:60d829a0353a 455
tushki7 0:60d829a0353a 456 /* SysTick Current Register Definitions */
tushki7 0:60d829a0353a 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
tushki7 0:60d829a0353a 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
tushki7 0:60d829a0353a 459
tushki7 0:60d829a0353a 460 /* SysTick Calibration Register Definitions */
tushki7 0:60d829a0353a 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
tushki7 0:60d829a0353a 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
tushki7 0:60d829a0353a 463
tushki7 0:60d829a0353a 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
tushki7 0:60d829a0353a 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
tushki7 0:60d829a0353a 466
tushki7 0:60d829a0353a 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
tushki7 0:60d829a0353a 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
tushki7 0:60d829a0353a 469
tushki7 0:60d829a0353a 470 /*@} end of group CMSIS_SysTick */
tushki7 0:60d829a0353a 471
tushki7 0:60d829a0353a 472 #if (__MPU_PRESENT == 1)
tushki7 0:60d829a0353a 473 /** \ingroup CMSIS_core_register
tushki7 0:60d829a0353a 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
tushki7 0:60d829a0353a 475 \brief Type definitions for the Memory Protection Unit (MPU)
tushki7 0:60d829a0353a 476 @{
tushki7 0:60d829a0353a 477 */
tushki7 0:60d829a0353a 478
tushki7 0:60d829a0353a 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
tushki7 0:60d829a0353a 480 */
tushki7 0:60d829a0353a 481 typedef struct
tushki7 0:60d829a0353a 482 {
tushki7 0:60d829a0353a 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
tushki7 0:60d829a0353a 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
tushki7 0:60d829a0353a 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
tushki7 0:60d829a0353a 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
tushki7 0:60d829a0353a 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
tushki7 0:60d829a0353a 488 } MPU_Type;
tushki7 0:60d829a0353a 489
tushki7 0:60d829a0353a 490 /* MPU Type Register */
tushki7 0:60d829a0353a 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
tushki7 0:60d829a0353a 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
tushki7 0:60d829a0353a 493
tushki7 0:60d829a0353a 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
tushki7 0:60d829a0353a 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
tushki7 0:60d829a0353a 496
tushki7 0:60d829a0353a 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
tushki7 0:60d829a0353a 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
tushki7 0:60d829a0353a 499
tushki7 0:60d829a0353a 500 /* MPU Control Register */
tushki7 0:60d829a0353a 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
tushki7 0:60d829a0353a 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
tushki7 0:60d829a0353a 503
tushki7 0:60d829a0353a 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
tushki7 0:60d829a0353a 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
tushki7 0:60d829a0353a 506
tushki7 0:60d829a0353a 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
tushki7 0:60d829a0353a 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
tushki7 0:60d829a0353a 509
tushki7 0:60d829a0353a 510 /* MPU Region Number Register */
tushki7 0:60d829a0353a 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
tushki7 0:60d829a0353a 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
tushki7 0:60d829a0353a 513
tushki7 0:60d829a0353a 514 /* MPU Region Base Address Register */
tushki7 0:60d829a0353a 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
tushki7 0:60d829a0353a 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
tushki7 0:60d829a0353a 517
tushki7 0:60d829a0353a 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
tushki7 0:60d829a0353a 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
tushki7 0:60d829a0353a 520
tushki7 0:60d829a0353a 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
tushki7 0:60d829a0353a 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
tushki7 0:60d829a0353a 523
tushki7 0:60d829a0353a 524 /* MPU Region Attribute and Size Register */
tushki7 0:60d829a0353a 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
tushki7 0:60d829a0353a 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
tushki7 0:60d829a0353a 527
tushki7 0:60d829a0353a 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
tushki7 0:60d829a0353a 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
tushki7 0:60d829a0353a 530
tushki7 0:60d829a0353a 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
tushki7 0:60d829a0353a 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
tushki7 0:60d829a0353a 533
tushki7 0:60d829a0353a 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
tushki7 0:60d829a0353a 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
tushki7 0:60d829a0353a 536
tushki7 0:60d829a0353a 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
tushki7 0:60d829a0353a 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
tushki7 0:60d829a0353a 539
tushki7 0:60d829a0353a 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
tushki7 0:60d829a0353a 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
tushki7 0:60d829a0353a 542
tushki7 0:60d829a0353a 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
tushki7 0:60d829a0353a 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
tushki7 0:60d829a0353a 545
tushki7 0:60d829a0353a 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
tushki7 0:60d829a0353a 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
tushki7 0:60d829a0353a 548
tushki7 0:60d829a0353a 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
tushki7 0:60d829a0353a 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
tushki7 0:60d829a0353a 551
tushki7 0:60d829a0353a 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
tushki7 0:60d829a0353a 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
tushki7 0:60d829a0353a 554
tushki7 0:60d829a0353a 555 /*@} end of group CMSIS_MPU */
tushki7 0:60d829a0353a 556 #endif
tushki7 0:60d829a0353a 557
tushki7 0:60d829a0353a 558
tushki7 0:60d829a0353a 559 /** \ingroup CMSIS_core_register
tushki7 0:60d829a0353a 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
tushki7 0:60d829a0353a 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
tushki7 0:60d829a0353a 562 are only accessible over DAP and not via processor. Therefore
tushki7 0:60d829a0353a 563 they are not covered by the Cortex-M0 header file.
tushki7 0:60d829a0353a 564 @{
tushki7 0:60d829a0353a 565 */
tushki7 0:60d829a0353a 566 /*@} end of group CMSIS_CoreDebug */
tushki7 0:60d829a0353a 567
tushki7 0:60d829a0353a 568
tushki7 0:60d829a0353a 569 /** \ingroup CMSIS_core_register
tushki7 0:60d829a0353a 570 \defgroup CMSIS_core_base Core Definitions
tushki7 0:60d829a0353a 571 \brief Definitions for base addresses, unions, and structures.
tushki7 0:60d829a0353a 572 @{
tushki7 0:60d829a0353a 573 */
tushki7 0:60d829a0353a 574
tushki7 0:60d829a0353a 575 /* Memory mapping of Cortex-M0+ Hardware */
tushki7 0:60d829a0353a 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
tushki7 0:60d829a0353a 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
tushki7 0:60d829a0353a 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
tushki7 0:60d829a0353a 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
tushki7 0:60d829a0353a 580
tushki7 0:60d829a0353a 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
tushki7 0:60d829a0353a 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
tushki7 0:60d829a0353a 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
tushki7 0:60d829a0353a 584
tushki7 0:60d829a0353a 585 #if (__MPU_PRESENT == 1)
tushki7 0:60d829a0353a 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
tushki7 0:60d829a0353a 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
tushki7 0:60d829a0353a 588 #endif
tushki7 0:60d829a0353a 589
tushki7 0:60d829a0353a 590 /*@} */
tushki7 0:60d829a0353a 591
tushki7 0:60d829a0353a 592
tushki7 0:60d829a0353a 593
tushki7 0:60d829a0353a 594 /*******************************************************************************
tushki7 0:60d829a0353a 595 * Hardware Abstraction Layer
tushki7 0:60d829a0353a 596 Core Function Interface contains:
tushki7 0:60d829a0353a 597 - Core NVIC Functions
tushki7 0:60d829a0353a 598 - Core SysTick Functions
tushki7 0:60d829a0353a 599 - Core Register Access Functions
tushki7 0:60d829a0353a 600 ******************************************************************************/
tushki7 0:60d829a0353a 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
tushki7 0:60d829a0353a 602 */
tushki7 0:60d829a0353a 603
tushki7 0:60d829a0353a 604
tushki7 0:60d829a0353a 605
tushki7 0:60d829a0353a 606 /* ########################## NVIC functions #################################### */
tushki7 0:60d829a0353a 607 /** \ingroup CMSIS_Core_FunctionInterface
tushki7 0:60d829a0353a 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
tushki7 0:60d829a0353a 609 \brief Functions that manage interrupts and exceptions via the NVIC.
tushki7 0:60d829a0353a 610 @{
tushki7 0:60d829a0353a 611 */
tushki7 0:60d829a0353a 612
tushki7 0:60d829a0353a 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
tushki7 0:60d829a0353a 614 /* The following MACROS handle generation of the register offset and byte masks */
tushki7 0:60d829a0353a 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
tushki7 0:60d829a0353a 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
tushki7 0:60d829a0353a 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
tushki7 0:60d829a0353a 618
tushki7 0:60d829a0353a 619
tushki7 0:60d829a0353a 620 /** \brief Enable External Interrupt
tushki7 0:60d829a0353a 621
tushki7 0:60d829a0353a 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
tushki7 0:60d829a0353a 623
tushki7 0:60d829a0353a 624 \param [in] IRQn External interrupt number. Value cannot be negative.
tushki7 0:60d829a0353a 625 */
tushki7 0:60d829a0353a 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
tushki7 0:60d829a0353a 627 {
tushki7 0:60d829a0353a 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
tushki7 0:60d829a0353a 629 }
tushki7 0:60d829a0353a 630
tushki7 0:60d829a0353a 631
tushki7 0:60d829a0353a 632 /** \brief Disable External Interrupt
tushki7 0:60d829a0353a 633
tushki7 0:60d829a0353a 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
tushki7 0:60d829a0353a 635
tushki7 0:60d829a0353a 636 \param [in] IRQn External interrupt number. Value cannot be negative.
tushki7 0:60d829a0353a 637 */
tushki7 0:60d829a0353a 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
tushki7 0:60d829a0353a 639 {
tushki7 0:60d829a0353a 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
tushki7 0:60d829a0353a 641 }
tushki7 0:60d829a0353a 642
tushki7 0:60d829a0353a 643
tushki7 0:60d829a0353a 644 /** \brief Get Pending Interrupt
tushki7 0:60d829a0353a 645
tushki7 0:60d829a0353a 646 The function reads the pending register in the NVIC and returns the pending bit
tushki7 0:60d829a0353a 647 for the specified interrupt.
tushki7 0:60d829a0353a 648
tushki7 0:60d829a0353a 649 \param [in] IRQn Interrupt number.
tushki7 0:60d829a0353a 650
tushki7 0:60d829a0353a 651 \return 0 Interrupt status is not pending.
tushki7 0:60d829a0353a 652 \return 1 Interrupt status is pending.
tushki7 0:60d829a0353a 653 */
tushki7 0:60d829a0353a 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
tushki7 0:60d829a0353a 655 {
tushki7 0:60d829a0353a 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
tushki7 0:60d829a0353a 657 }
tushki7 0:60d829a0353a 658
tushki7 0:60d829a0353a 659
tushki7 0:60d829a0353a 660 /** \brief Set Pending Interrupt
tushki7 0:60d829a0353a 661
tushki7 0:60d829a0353a 662 The function sets the pending bit of an external interrupt.
tushki7 0:60d829a0353a 663
tushki7 0:60d829a0353a 664 \param [in] IRQn Interrupt number. Value cannot be negative.
tushki7 0:60d829a0353a 665 */
tushki7 0:60d829a0353a 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
tushki7 0:60d829a0353a 667 {
tushki7 0:60d829a0353a 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
tushki7 0:60d829a0353a 669 }
tushki7 0:60d829a0353a 670
tushki7 0:60d829a0353a 671
tushki7 0:60d829a0353a 672 /** \brief Clear Pending Interrupt
tushki7 0:60d829a0353a 673
tushki7 0:60d829a0353a 674 The function clears the pending bit of an external interrupt.
tushki7 0:60d829a0353a 675
tushki7 0:60d829a0353a 676 \param [in] IRQn External interrupt number. Value cannot be negative.
tushki7 0:60d829a0353a 677 */
tushki7 0:60d829a0353a 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
tushki7 0:60d829a0353a 679 {
tushki7 0:60d829a0353a 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
tushki7 0:60d829a0353a 681 }
tushki7 0:60d829a0353a 682
tushki7 0:60d829a0353a 683
tushki7 0:60d829a0353a 684 /** \brief Set Interrupt Priority
tushki7 0:60d829a0353a 685
tushki7 0:60d829a0353a 686 The function sets the priority of an interrupt.
tushki7 0:60d829a0353a 687
tushki7 0:60d829a0353a 688 \note The priority cannot be set for every core interrupt.
tushki7 0:60d829a0353a 689
tushki7 0:60d829a0353a 690 \param [in] IRQn Interrupt number.
tushki7 0:60d829a0353a 691 \param [in] priority Priority to set.
tushki7 0:60d829a0353a 692 */
tushki7 0:60d829a0353a 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
tushki7 0:60d829a0353a 694 {
tushki7 0:60d829a0353a 695 if(IRQn < 0) {
tushki7 0:60d829a0353a 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
tushki7 0:60d829a0353a 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
tushki7 0:60d829a0353a 698 else {
tushki7 0:60d829a0353a 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
tushki7 0:60d829a0353a 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
tushki7 0:60d829a0353a 701 }
tushki7 0:60d829a0353a 702
tushki7 0:60d829a0353a 703
tushki7 0:60d829a0353a 704 /** \brief Get Interrupt Priority
tushki7 0:60d829a0353a 705
tushki7 0:60d829a0353a 706 The function reads the priority of an interrupt. The interrupt
tushki7 0:60d829a0353a 707 number can be positive to specify an external (device specific)
tushki7 0:60d829a0353a 708 interrupt, or negative to specify an internal (core) interrupt.
tushki7 0:60d829a0353a 709
tushki7 0:60d829a0353a 710
tushki7 0:60d829a0353a 711 \param [in] IRQn Interrupt number.
tushki7 0:60d829a0353a 712 \return Interrupt Priority. Value is aligned automatically to the implemented
tushki7 0:60d829a0353a 713 priority bits of the microcontroller.
tushki7 0:60d829a0353a 714 */
tushki7 0:60d829a0353a 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
tushki7 0:60d829a0353a 716 {
tushki7 0:60d829a0353a 717
tushki7 0:60d829a0353a 718 if(IRQn < 0) {
tushki7 0:60d829a0353a 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
tushki7 0:60d829a0353a 720 else {
tushki7 0:60d829a0353a 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
tushki7 0:60d829a0353a 722 }
tushki7 0:60d829a0353a 723
tushki7 0:60d829a0353a 724
tushki7 0:60d829a0353a 725 /** \brief System Reset
tushki7 0:60d829a0353a 726
tushki7 0:60d829a0353a 727 The function initiates a system reset request to reset the MCU.
tushki7 0:60d829a0353a 728 */
tushki7 0:60d829a0353a 729 __STATIC_INLINE void NVIC_SystemReset(void)
tushki7 0:60d829a0353a 730 {
tushki7 0:60d829a0353a 731 __DSB(); /* Ensure all outstanding memory accesses included
tushki7 0:60d829a0353a 732 buffered write are completed before reset */
tushki7 0:60d829a0353a 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
tushki7 0:60d829a0353a 734 SCB_AIRCR_SYSRESETREQ_Msk);
tushki7 0:60d829a0353a 735 __DSB(); /* Ensure completion of memory access */
tushki7 0:60d829a0353a 736 while(1); /* wait until reset */
tushki7 0:60d829a0353a 737 }
tushki7 0:60d829a0353a 738
tushki7 0:60d829a0353a 739 /*@} end of CMSIS_Core_NVICFunctions */
tushki7 0:60d829a0353a 740
tushki7 0:60d829a0353a 741
tushki7 0:60d829a0353a 742
tushki7 0:60d829a0353a 743 /* ################################## SysTick function ############################################ */
tushki7 0:60d829a0353a 744 /** \ingroup CMSIS_Core_FunctionInterface
tushki7 0:60d829a0353a 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
tushki7 0:60d829a0353a 746 \brief Functions that configure the System.
tushki7 0:60d829a0353a 747 @{
tushki7 0:60d829a0353a 748 */
tushki7 0:60d829a0353a 749
tushki7 0:60d829a0353a 750 #if (__Vendor_SysTickConfig == 0)
tushki7 0:60d829a0353a 751
tushki7 0:60d829a0353a 752 /** \brief System Tick Configuration
tushki7 0:60d829a0353a 753
tushki7 0:60d829a0353a 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
tushki7 0:60d829a0353a 755 Counter is in free running mode to generate periodic interrupts.
tushki7 0:60d829a0353a 756
tushki7 0:60d829a0353a 757 \param [in] ticks Number of ticks between two interrupts.
tushki7 0:60d829a0353a 758
tushki7 0:60d829a0353a 759 \return 0 Function succeeded.
tushki7 0:60d829a0353a 760 \return 1 Function failed.
tushki7 0:60d829a0353a 761
tushki7 0:60d829a0353a 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
tushki7 0:60d829a0353a 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
tushki7 0:60d829a0353a 764 must contain a vendor-specific implementation of this function.
tushki7 0:60d829a0353a 765
tushki7 0:60d829a0353a 766 */
tushki7 0:60d829a0353a 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
tushki7 0:60d829a0353a 768 {
tushki7 0:60d829a0353a 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
tushki7 0:60d829a0353a 770
tushki7 0:60d829a0353a 771 SysTick->LOAD = ticks - 1; /* set reload register */
tushki7 0:60d829a0353a 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
tushki7 0:60d829a0353a 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
tushki7 0:60d829a0353a 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
tushki7 0:60d829a0353a 775 SysTick_CTRL_TICKINT_Msk |
tushki7 0:60d829a0353a 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
tushki7 0:60d829a0353a 777 return (0); /* Function successful */
tushki7 0:60d829a0353a 778 }
tushki7 0:60d829a0353a 779
tushki7 0:60d829a0353a 780 #endif
tushki7 0:60d829a0353a 781
tushki7 0:60d829a0353a 782 /*@} end of CMSIS_Core_SysTickFunctions */
tushki7 0:60d829a0353a 783
tushki7 0:60d829a0353a 784
tushki7 0:60d829a0353a 785
tushki7 0:60d829a0353a 786
tushki7 0:60d829a0353a 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
tushki7 0:60d829a0353a 788
tushki7 0:60d829a0353a 789 #endif /* __CMSIS_GENERIC */
tushki7 0:60d829a0353a 790
tushki7 0:60d829a0353a 791 #ifdef __cplusplus
tushki7 0:60d829a0353a 792 }
tushki7 0:60d829a0353a 793 #endif