FRDM_K64F_LCD - A simple 128x32 graphical LCD program to quicksta…

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A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies: C12832

mbed/TARGET_NUCLEO_F411RE/stm32f4xx_hal_rcc_ex.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:: tushki7
Date:: Sun Apr 12 15:45:52 2015 +0000
Revision:: 1:eb68c94a8ee5
Parent:: 0:60d829a0353a

A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

User	Revision	Line number	New contents of line
tushki7	0:60d829a0353a	1	/**
tushki7	0:60d829a0353a	2	******************************************************************************
tushki7	0:60d829a0353a	3	* @file stm32f4xx_hal_rcc_ex.h
tushki7	0:60d829a0353a	4	* @author MCD Application Team
tushki7	0:60d829a0353a	5	* @version V1.1.0
tushki7	0:60d829a0353a	6	* @date 19-June-2014
tushki7	0:60d829a0353a	7	* @brief Header file of RCC HAL Extension module.
tushki7	0:60d829a0353a	8	******************************************************************************
tushki7	0:60d829a0353a	9	* @attention
tushki7	0:60d829a0353a	10	*
tushki7	0:60d829a0353a	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
tushki7	0:60d829a0353a	12	*
tushki7	0:60d829a0353a	13	* Redistribution and use in source and binary forms, with or without modification,
tushki7	0:60d829a0353a	14	* are permitted provided that the following conditions are met:
tushki7	0:60d829a0353a	15	* 1. Redistributions of source code must retain the above copyright notice,
tushki7	0:60d829a0353a	16	* this list of conditions and the following disclaimer.
tushki7	0:60d829a0353a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
tushki7	0:60d829a0353a	18	* this list of conditions and the following disclaimer in the documentation
tushki7	0:60d829a0353a	19	* and/or other materials provided with the distribution.
tushki7	0:60d829a0353a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
tushki7	0:60d829a0353a	21	* may be used to endorse or promote products derived from this software
tushki7	0:60d829a0353a	22	* without specific prior written permission.
tushki7	0:60d829a0353a	23	*
tushki7	0:60d829a0353a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
tushki7	0:60d829a0353a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
tushki7	0:60d829a0353a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
tushki7	0:60d829a0353a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
tushki7	0:60d829a0353a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
tushki7	0:60d829a0353a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
tushki7	0:60d829a0353a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
tushki7	0:60d829a0353a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
tushki7	0:60d829a0353a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
tushki7	0:60d829a0353a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
tushki7	0:60d829a0353a	34	*
tushki7	0:60d829a0353a	35	******************************************************************************
tushki7	0:60d829a0353a	36	*/
tushki7	0:60d829a0353a	37
tushki7	0:60d829a0353a	38	/* Define to prevent recursive inclusion -------------------------------------*/
tushki7	0:60d829a0353a	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
tushki7	0:60d829a0353a	40	#define __STM32F4xx_HAL_RCC_EX_H
tushki7	0:60d829a0353a	41
tushki7	0:60d829a0353a	42	#ifdef __cplusplus
tushki7	0:60d829a0353a	43	extern "C" {
tushki7	0:60d829a0353a	44	#endif
tushki7	0:60d829a0353a	45
tushki7	0:60d829a0353a	46	/* Includes ------------------------------------------------------------------*/
tushki7	0:60d829a0353a	47	#include "stm32f4xx_hal_def.h"
tushki7	0:60d829a0353a	48
tushki7	0:60d829a0353a	49	/** @addtogroup STM32F4xx_HAL_Driver
tushki7	0:60d829a0353a	50	* @{
tushki7	0:60d829a0353a	51	*/
tushki7	0:60d829a0353a	52
tushki7	0:60d829a0353a	53	/** @addtogroup RCCEx
tushki7	0:60d829a0353a	54	* @{
tushki7	0:60d829a0353a	55	*/
tushki7	0:60d829a0353a	56
tushki7	0:60d829a0353a	57	/* Exported types ------------------------------------------------------------*/
tushki7	0:60d829a0353a	58	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	59	/**
tushki7	0:60d829a0353a	60	* @brief PLLI2S Clock structure definition
tushki7	0:60d829a0353a	61	*/
tushki7	0:60d829a0353a	62	typedef struct
tushki7	0:60d829a0353a	63	{
tushki7	0:60d829a0353a	64	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
tushki7	0:60d829a0353a	65	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
tushki7	0:60d829a0353a	66	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
tushki7	0:60d829a0353a	67
tushki7	0:60d829a0353a	68	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
tushki7	0:60d829a0353a	69	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
tushki7	0:60d829a0353a	70	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
tushki7	0:60d829a0353a	71
tushki7	0:60d829a0353a	72	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
tushki7	0:60d829a0353a	73	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
tushki7	0:60d829a0353a	74	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
tushki7	0:60d829a0353a	75	}RCC_PLLI2SInitTypeDef;
tushki7	0:60d829a0353a	76
tushki7	0:60d829a0353a	77	/**
tushki7	0:60d829a0353a	78	* @brief PLLSAI Clock structure definition
tushki7	0:60d829a0353a	79	*/
tushki7	0:60d829a0353a	80	typedef struct
tushki7	0:60d829a0353a	81	{
tushki7	0:60d829a0353a	82	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
tushki7	0:60d829a0353a	83	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
tushki7	0:60d829a0353a	84	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
tushki7	0:60d829a0353a	85
tushki7	0:60d829a0353a	86	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
tushki7	0:60d829a0353a	87	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
tushki7	0:60d829a0353a	88	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
tushki7	0:60d829a0353a	89
tushki7	0:60d829a0353a	90	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
tushki7	0:60d829a0353a	91	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
tushki7	0:60d829a0353a	92	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
tushki7	0:60d829a0353a	93
tushki7	0:60d829a0353a	94	}RCC_PLLSAIInitTypeDef;
tushki7	0:60d829a0353a	95	/**
tushki7	0:60d829a0353a	96	* @brief RCC extended clocks structure definition
tushki7	0:60d829a0353a	97	*/
tushki7	0:60d829a0353a	98	typedef struct
tushki7	0:60d829a0353a	99	{
tushki7	0:60d829a0353a	100	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
tushki7	0:60d829a0353a	101	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
tushki7	0:60d829a0353a	102
tushki7	0:60d829a0353a	103	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
tushki7	0:60d829a0353a	104	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
tushki7	0:60d829a0353a	105
tushki7	0:60d829a0353a	106	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
tushki7	0:60d829a0353a	107	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
tushki7	0:60d829a0353a	108
tushki7	0:60d829a0353a	109	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
tushki7	0:60d829a0353a	110	This parameter must be a number between Min_Data = 1 and Max_Data = 32
tushki7	0:60d829a0353a	111	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
tushki7	0:60d829a0353a	112
tushki7	0:60d829a0353a	113	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
tushki7	0:60d829a0353a	114	This parameter must be a number between Min_Data = 1 and Max_Data = 32
tushki7	0:60d829a0353a	115	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
tushki7	0:60d829a0353a	116
tushki7	0:60d829a0353a	117	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
tushki7	0:60d829a0353a	118	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
tushki7	0:60d829a0353a	119
tushki7	0:60d829a0353a	120	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
tushki7	0:60d829a0353a	121	This parameter can be a value of @ref RCC_RTC_Clock_Source */
tushki7	0:60d829a0353a	122
tushki7	0:60d829a0353a	123	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
tushki7	0:60d829a0353a	124	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
tushki7	0:60d829a0353a	125
tushki7	0:60d829a0353a	126	}RCC_PeriphCLKInitTypeDef;
tushki7	0:60d829a0353a	127	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
tushki7	0:60d829a0353a	128
tushki7	0:60d829a0353a	129	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
tushki7	0:60d829a0353a	130	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
tushki7	0:60d829a0353a	131	/**
tushki7	0:60d829a0353a	132	* @brief PLLI2S Clock structure definition
tushki7	0:60d829a0353a	133	*/
tushki7	0:60d829a0353a	134	typedef struct
tushki7	0:60d829a0353a	135	{
tushki7	0:60d829a0353a	136	#if defined(STM32F411xE)
tushki7	0:60d829a0353a	137	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
tushki7	0:60d829a0353a	138	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
tushki7	0:60d829a0353a	139	#endif /* STM32F411xE */
tushki7	0:60d829a0353a	140
tushki7	0:60d829a0353a	141	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
tushki7	0:60d829a0353a	142	This parameter must be a number between Min_Data = 192 and Max_Data = 432
tushki7	0:60d829a0353a	143	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
tushki7	0:60d829a0353a	144
tushki7	0:60d829a0353a	145	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
tushki7	0:60d829a0353a	146	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
tushki7	0:60d829a0353a	147	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
tushki7	0:60d829a0353a	148
tushki7	0:60d829a0353a	149	}RCC_PLLI2SInitTypeDef;
tushki7	0:60d829a0353a	150
tushki7	0:60d829a0353a	151
tushki7	0:60d829a0353a	152	/**
tushki7	0:60d829a0353a	153	* @brief RCC extended clocks structure definition
tushki7	0:60d829a0353a	154	*/
tushki7	0:60d829a0353a	155	typedef struct
tushki7	0:60d829a0353a	156	{
tushki7	0:60d829a0353a	157	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
tushki7	0:60d829a0353a	158	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
tushki7	0:60d829a0353a	159
tushki7	0:60d829a0353a	160	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
tushki7	0:60d829a0353a	161	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
tushki7	0:60d829a0353a	162
tushki7	0:60d829a0353a	163	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
tushki7	0:60d829a0353a	164	This parameter can be a value of @ref RCC_RTC_Clock_Source */
tushki7	0:60d829a0353a	165
tushki7	0:60d829a0353a	166	}RCC_PeriphCLKInitTypeDef;
tushki7	0:60d829a0353a	167	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
tushki7	0:60d829a0353a	168	/* Exported constants --------------------------------------------------------*/
tushki7	0:60d829a0353a	169	/** @defgroup RCCEx_Exported_Constants
tushki7	0:60d829a0353a	170	* @{
tushki7	0:60d829a0353a	171	*/
tushki7	0:60d829a0353a	172
tushki7	0:60d829a0353a	173	/** @defgroup RCCEx_Periph_Clock_Selection
tushki7	0:60d829a0353a	174	* @{
tushki7	0:60d829a0353a	175	*/
tushki7	0:60d829a0353a	176	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	177	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	178	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	179	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	180	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	181	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	182	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	183	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
tushki7	0:60d829a0353a	184	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
tushki7	0:60d829a0353a	185
tushki7	0:60d829a0353a	186	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
tushki7	0:60d829a0353a	187	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
tushki7	0:60d829a0353a	188	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	189	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	190	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
tushki7	0:60d829a0353a	191	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
tushki7	0:60d829a0353a	192
tushki7	0:60d829a0353a	193	/**
tushki7	0:60d829a0353a	194	* @}
tushki7	0:60d829a0353a	195	*/
tushki7	0:60d829a0353a	196
tushki7	0:60d829a0353a	197	/** @defgroup RCCEx_BitAddress_AliasRegion
tushki7	0:60d829a0353a	198	* @brief RCC registers bit address in the alias region
tushki7	0:60d829a0353a	199	* @{
tushki7	0:60d829a0353a	200	*/
tushki7	0:60d829a0353a	201	/* --- CR Register ---*/
tushki7	0:60d829a0353a	202	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	203	/* Alias word address of PLLSAION bit */
tushki7	0:60d829a0353a	204	#define PLLSAION_BitNumber 0x1C
tushki7	0:60d829a0353a	205	#define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
tushki7	0:60d829a0353a	206
tushki7	0:60d829a0353a	207	/* --- DCKCFGR Register ---*/
tushki7	0:60d829a0353a	208	/* Alias word address of TIMPRE bit */
tushki7	0:60d829a0353a	209	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
tushki7	0:60d829a0353a	210	#define TIMPRE_BitNumber 0x18
tushki7	0:60d829a0353a	211	#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
tushki7	0:60d829a0353a	212	/**
tushki7	0:60d829a0353a	213	* @}
tushki7	0:60d829a0353a	214	*/
tushki7	0:60d829a0353a	215
tushki7	0:60d829a0353a	216	/** @defgroup RCCEx_PLLI2S_Clock_Source
tushki7	0:60d829a0353a	217	* @{
tushki7	0:60d829a0353a	218	*/
tushki7	0:60d829a0353a	219	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
tushki7	0:60d829a0353a	220	/**
tushki7	0:60d829a0353a	221	* @}
tushki7	0:60d829a0353a	222	*/
tushki7	0:60d829a0353a	223
tushki7	0:60d829a0353a	224	/** @defgroup RCCEx_PLLSAI_Clock_Source
tushki7	0:60d829a0353a	225	* @{
tushki7	0:60d829a0353a	226	*/
tushki7	0:60d829a0353a	227	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
tushki7	0:60d829a0353a	228	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
tushki7	0:60d829a0353a	229	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
tushki7	0:60d829a0353a	230	/**
tushki7	0:60d829a0353a	231	* @}
tushki7	0:60d829a0353a	232	*/
tushki7	0:60d829a0353a	233
tushki7	0:60d829a0353a	234	/** @defgroup RCCEx_PLLSAI_DIVQ
tushki7	0:60d829a0353a	235	* @{
tushki7	0:60d829a0353a	236	*/
tushki7	0:60d829a0353a	237	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
tushki7	0:60d829a0353a	238	/**
tushki7	0:60d829a0353a	239	* @}
tushki7	0:60d829a0353a	240	*/
tushki7	0:60d829a0353a	241
tushki7	0:60d829a0353a	242	/** @defgroup RCCEx_PLLI2S_DIVQ
tushki7	0:60d829a0353a	243	* @{
tushki7	0:60d829a0353a	244	*/
tushki7	0:60d829a0353a	245	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
tushki7	0:60d829a0353a	246
tushki7	0:60d829a0353a	247	/**
tushki7	0:60d829a0353a	248	* @}
tushki7	0:60d829a0353a	249	*/
tushki7	0:60d829a0353a	250
tushki7	0:60d829a0353a	251	/** @defgroup RCCEx_PLLSAI_DIVR
tushki7	0:60d829a0353a	252	* @{
tushki7	0:60d829a0353a	253	*/
tushki7	0:60d829a0353a	254	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	255	#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	256	#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
tushki7	0:60d829a0353a	257	#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
tushki7	0:60d829a0353a	258	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
tushki7	0:60d829a0353a	259	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
tushki7	0:60d829a0353a	260	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
tushki7	0:60d829a0353a	261	((VALUE) == RCC_PLLSAIDIVR_16))
tushki7	0:60d829a0353a	262
tushki7	0:60d829a0353a	263	/**
tushki7	0:60d829a0353a	264	* @}
tushki7	0:60d829a0353a	265	*/
tushki7	0:60d829a0353a	266
tushki7	0:60d829a0353a	267	/** @defgroup RCCEx_SAI_BlockA_Clock_Source
tushki7	0:60d829a0353a	268	* @{
tushki7	0:60d829a0353a	269	*/
tushki7	0:60d829a0353a	270	#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	271	#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
tushki7	0:60d829a0353a	272	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
tushki7	0:60d829a0353a	273	/**
tushki7	0:60d829a0353a	274	* @}
tushki7	0:60d829a0353a	275	*/
tushki7	0:60d829a0353a	276
tushki7	0:60d829a0353a	277	/** @defgroup RCCEx_SAI_BlockB_Clock_Source
tushki7	0:60d829a0353a	278	* @{
tushki7	0:60d829a0353a	279	*/
tushki7	0:60d829a0353a	280	#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	281	#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
tushki7	0:60d829a0353a	282	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
tushki7	0:60d829a0353a	283	/**
tushki7	0:60d829a0353a	284	* @}
tushki7	0:60d829a0353a	285	*/
tushki7	0:60d829a0353a	286
tushki7	0:60d829a0353a	287	/** @defgroup RCCEx_TIM_PRescaler_Selection
tushki7	0:60d829a0353a	288	* @{
tushki7	0:60d829a0353a	289	*/
tushki7	0:60d829a0353a	290	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
tushki7	0:60d829a0353a	291	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
tushki7	0:60d829a0353a	292	/**
tushki7	0:60d829a0353a	293	* @}
tushki7	0:60d829a0353a	294	*/
tushki7	0:60d829a0353a	295	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
tushki7	0:60d829a0353a	296
tushki7	0:60d829a0353a	297	#if defined(STM32F411xE)
tushki7	0:60d829a0353a	298	/** @defgroup RCCEx_PLLI2S_PLLI2SM
tushki7	0:60d829a0353a	299	* @{
tushki7	0:60d829a0353a	300	*/
tushki7	0:60d829a0353a	301	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
tushki7	0:60d829a0353a	302	/**
tushki7	0:60d829a0353a	303	* @}
tushki7	0:60d829a0353a	304	*/
tushki7	0:60d829a0353a	305
tushki7	0:60d829a0353a	306	/** @defgroup RCCEx_LSE_Dual_Mode_Selection
tushki7	0:60d829a0353a	307	* @{
tushki7	0:60d829a0353a	308	*/
tushki7	0:60d829a0353a	309	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
tushki7	0:60d829a0353a	310	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
tushki7	0:60d829a0353a	311	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
tushki7	0:60d829a0353a	312	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
tushki7	0:60d829a0353a	313	/**
tushki7	0:60d829a0353a	314	* @}
tushki7	0:60d829a0353a	315	*/
tushki7	0:60d829a0353a	316
tushki7	0:60d829a0353a	317	#endif /* STM32F411xE */
tushki7	0:60d829a0353a	318	/**
tushki7	0:60d829a0353a	319	* @}
tushki7	0:60d829a0353a	320	*/
tushki7	0:60d829a0353a	321
tushki7	0:60d829a0353a	322	/* Exported macro ------------------------------------------------------------*/
tushki7	0:60d829a0353a	323
tushki7	0:60d829a0353a	324	/----------------------------------- STM32F42xxx/STM32F43xxx----------------------------------/
tushki7	0:60d829a0353a	325	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	326	/** @brief Enables or disables the AHB1 peripheral clock.
tushki7	0:60d829a0353a	327	* @note After reset, the peripheral clock (used for registers read/write access)
tushki7	0:60d829a0353a	328	* is disabled and the application software has to enable this clock before
tushki7	0:60d829a0353a	329	* using it.
tushki7	0:60d829a0353a	330	*/
tushki7	0:60d829a0353a	331	#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOIEN))
tushki7	0:60d829a0353a	332	#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOFEN))
tushki7	0:60d829a0353a	333	#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOGEN))
tushki7	0:60d829a0353a	334	#define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOJEN))
tushki7	0:60d829a0353a	335	#define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOKEN))
tushki7	0:60d829a0353a	336	#define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA2DEN))
tushki7	0:60d829a0353a	337	#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACEN))
tushki7	0:60d829a0353a	338	#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACTXEN))
tushki7	0:60d829a0353a	339	#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACRXEN))
tushki7	0:60d829a0353a	340	#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACPTPEN))
tushki7	0:60d829a0353a	341	#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_OTGHSEN))
tushki7	0:60d829a0353a	342	#define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_OTGHSULPIEN))
tushki7	0:60d829a0353a	343
tushki7	0:60d829a0353a	344	#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
tushki7	0:60d829a0353a	345	#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
tushki7	0:60d829a0353a	346	#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
tushki7	0:60d829a0353a	347	#define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
tushki7	0:60d829a0353a	348	#define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
tushki7	0:60d829a0353a	349	#define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
tushki7	0:60d829a0353a	350	#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
tushki7	0:60d829a0353a	351	#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
tushki7	0:60d829a0353a	352	#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
tushki7	0:60d829a0353a	353	#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
tushki7	0:60d829a0353a	354	#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
tushki7	0:60d829a0353a	355	#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
tushki7	0:60d829a0353a	356
tushki7	0:60d829a0353a	357	/**
tushki7	0:60d829a0353a	358	* @brief Enable ETHERNET clock.
tushki7	0:60d829a0353a	359	*/
tushki7	0:60d829a0353a	360	#define __ETH_CLK_ENABLE() do { \
tushki7	0:60d829a0353a	361	__ETHMAC_CLK_ENABLE(); \
tushki7	0:60d829a0353a	362	__ETHMACTX_CLK_ENABLE(); \
tushki7	0:60d829a0353a	363	__ETHMACRX_CLK_ENABLE(); \
tushki7	0:60d829a0353a	364	} while(0)
tushki7	0:60d829a0353a	365	/**
tushki7	0:60d829a0353a	366	* @brief Disable ETHERNET clock.
tushki7	0:60d829a0353a	367	*/
tushki7	0:60d829a0353a	368	#define __ETH_CLK_DISABLE() do { \
tushki7	0:60d829a0353a	369	__ETHMACTX_CLK_DISABLE(); \
tushki7	0:60d829a0353a	370	__ETHMACRX_CLK_DISABLE(); \
tushki7	0:60d829a0353a	371	__ETHMAC_CLK_DISABLE(); \
tushki7	0:60d829a0353a	372	} while(0)
tushki7	0:60d829a0353a	373
tushki7	0:60d829a0353a	374	/** @brief Enable or disable the AHB2 peripheral clock.
tushki7	0:60d829a0353a	375	* @note After reset, the peripheral clock (used for registers read/write access)
tushki7	0:60d829a0353a	376	* is disabled and the application software has to enable this clock before
tushki7	0:60d829a0353a	377	* using it.
tushki7	0:60d829a0353a	378	*/
tushki7	0:60d829a0353a	379
tushki7	0:60d829a0353a	380	#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_DCMIEN))
tushki7	0:60d829a0353a	381	#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
tushki7	0:60d829a0353a	382
tushki7	0:60d829a0353a	383	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	384	#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_CRYPEN))
tushki7	0:60d829a0353a	385	#define __HASH_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_HASHEN))
tushki7	0:60d829a0353a	386
tushki7	0:60d829a0353a	387	#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
tushki7	0:60d829a0353a	388	#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
tushki7	0:60d829a0353a	389	#endif /* STM32F437xx \|\| STM32F439xx */
tushki7	0:60d829a0353a	390
tushki7	0:60d829a0353a	391	/** @brief Enables or disables the AHB3 peripheral clock.
tushki7	0:60d829a0353a	392	* @note After reset, the peripheral clock (used for registers read/write access)
tushki7	0:60d829a0353a	393	* is disabled and the application software has to enable this clock before
tushki7	0:60d829a0353a	394	* using it.
tushki7	0:60d829a0353a	395	*/
tushki7	0:60d829a0353a	396	#define __FMC_CLK_ENABLE() (RCC->AHB3ENR \|= (RCC_AHB3ENR_FMCEN))
tushki7	0:60d829a0353a	397	#define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
tushki7	0:60d829a0353a	398
tushki7	0:60d829a0353a	399	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
tushki7	0:60d829a0353a	400	* @note After reset, the peripheral clock (used for registers read/write access)
tushki7	0:60d829a0353a	401	* is disabled and the application software has to enable this clock before
tushki7	0:60d829a0353a	402	* using it.
tushki7	0:60d829a0353a	403	*/
tushki7	0:60d829a0353a	404	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
tushki7	0:60d829a0353a	405	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
tushki7	0:60d829a0353a	406	#define __TIM12_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM12EN))
tushki7	0:60d829a0353a	407	#define __TIM13_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM13EN))
tushki7	0:60d829a0353a	408	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
tushki7	0:60d829a0353a	409	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
tushki7	0:60d829a0353a	410	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
tushki7	0:60d829a0353a	411	#define __UART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART4EN))
tushki7	0:60d829a0353a	412	#define __UART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART5EN))
tushki7	0:60d829a0353a	413	#define __CAN1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CAN1EN))
tushki7	0:60d829a0353a	414	#define __CAN2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CAN2EN))
tushki7	0:60d829a0353a	415	#define __DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
tushki7	0:60d829a0353a	416	#define __UART7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART7EN))
tushki7	0:60d829a0353a	417	#define __UART8_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART8EN))
tushki7	0:60d829a0353a	418
tushki7	0:60d829a0353a	419	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
tushki7	0:60d829a0353a	420	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
tushki7	0:60d829a0353a	421	#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
tushki7	0:60d829a0353a	422	#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
tushki7	0:60d829a0353a	423	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
tushki7	0:60d829a0353a	424	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
tushki7	0:60d829a0353a	425	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
tushki7	0:60d829a0353a	426	#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
tushki7	0:60d829a0353a	427	#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
tushki7	0:60d829a0353a	428	#define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
tushki7	0:60d829a0353a	429	#define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
tushki7	0:60d829a0353a	430	#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
tushki7	0:60d829a0353a	431	#define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
tushki7	0:60d829a0353a	432	#define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
tushki7	0:60d829a0353a	433
tushki7	0:60d829a0353a	434	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
tushki7	0:60d829a0353a	435	* @note After reset, the peripheral clock (used for registers read/write access)
tushki7	0:60d829a0353a	436	* is disabled and the application software has to enable this clock before
tushki7	0:60d829a0353a	437	* using it.
tushki7	0:60d829a0353a	438	*/
tushki7	0:60d829a0353a	439	#define __TIM8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM8EN))
tushki7	0:60d829a0353a	440	#define __ADC2_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC2EN))
tushki7	0:60d829a0353a	441	#define __ADC3_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC3EN))
tushki7	0:60d829a0353a	442	#define __SPI5_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI5EN))
tushki7	0:60d829a0353a	443	#define __SPI6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI6EN))
tushki7	0:60d829a0353a	444	#define __SAI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SAI1EN))
tushki7	0:60d829a0353a	445
tushki7	0:60d829a0353a	446	#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
tushki7	0:60d829a0353a	447	#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
tushki7	0:60d829a0353a	448	#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
tushki7	0:60d829a0353a	449	#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
tushki7	0:60d829a0353a	450	#define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
tushki7	0:60d829a0353a	451	#define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
tushki7	0:60d829a0353a	452
tushki7	0:60d829a0353a	453	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	454	#define __LTDC_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_LTDCEN))
tushki7	0:60d829a0353a	455
tushki7	0:60d829a0353a	456	#define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
tushki7	0:60d829a0353a	457	#endif /* STM32F429xx \|\| STM32F439xx */
tushki7	0:60d829a0353a	458
tushki7	0:60d829a0353a	459	/** @brief Force or release AHB1 peripheral reset.
tushki7	0:60d829a0353a	460	*/
tushki7	0:60d829a0353a	461	#define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
tushki7	0:60d829a0353a	462	#define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
tushki7	0:60d829a0353a	463	#define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
tushki7	0:60d829a0353a	464	#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
tushki7	0:60d829a0353a	465	#define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
tushki7	0:60d829a0353a	466	#define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
tushki7	0:60d829a0353a	467	#define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
tushki7	0:60d829a0353a	468	#define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
tushki7	0:60d829a0353a	469
tushki7	0:60d829a0353a	470	#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
tushki7	0:60d829a0353a	471	#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
tushki7	0:60d829a0353a	472	#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
tushki7	0:60d829a0353a	473	#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
tushki7	0:60d829a0353a	474	#define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
tushki7	0:60d829a0353a	475	#define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
tushki7	0:60d829a0353a	476	#define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
tushki7	0:60d829a0353a	477	#define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
tushki7	0:60d829a0353a	478
tushki7	0:60d829a0353a	479	/** @brief Force or release AHB2 peripheral reset.
tushki7	0:60d829a0353a	480	*/
tushki7	0:60d829a0353a	481	#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
tushki7	0:60d829a0353a	482	#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
tushki7	0:60d829a0353a	483
tushki7	0:60d829a0353a	484	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	485	#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
tushki7	0:60d829a0353a	486	#define __HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
tushki7	0:60d829a0353a	487
tushki7	0:60d829a0353a	488	#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
tushki7	0:60d829a0353a	489	#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
tushki7	0:60d829a0353a	490	#endif /* STM32F437xx \|\| STM32F439xx */
tushki7	0:60d829a0353a	491
tushki7	0:60d829a0353a	492	/** @brief Force or release AHB3 peripheral reset
tushki7	0:60d829a0353a	493	*/
tushki7	0:60d829a0353a	494	#define __FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
tushki7	0:60d829a0353a	495	#define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
tushki7	0:60d829a0353a	496
tushki7	0:60d829a0353a	497	/** @brief Force or release APB1 peripheral reset.
tushki7	0:60d829a0353a	498	*/
tushki7	0:60d829a0353a	499	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
tushki7	0:60d829a0353a	500	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
tushki7	0:60d829a0353a	501	#define __TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
tushki7	0:60d829a0353a	502	#define __TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
tushki7	0:60d829a0353a	503	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
tushki7	0:60d829a0353a	504	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
tushki7	0:60d829a0353a	505	#define __UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
tushki7	0:60d829a0353a	506	#define __UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
tushki7	0:60d829a0353a	507	#define __CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
tushki7	0:60d829a0353a	508	#define __CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
tushki7	0:60d829a0353a	509	#define __DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
tushki7	0:60d829a0353a	510	#define __UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
tushki7	0:60d829a0353a	511	#define __UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
tushki7	0:60d829a0353a	512
tushki7	0:60d829a0353a	513	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
tushki7	0:60d829a0353a	514	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
tushki7	0:60d829a0353a	515	#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
tushki7	0:60d829a0353a	516	#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
tushki7	0:60d829a0353a	517	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
tushki7	0:60d829a0353a	518	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
tushki7	0:60d829a0353a	519	#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
tushki7	0:60d829a0353a	520	#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
tushki7	0:60d829a0353a	521	#define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
tushki7	0:60d829a0353a	522	#define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
tushki7	0:60d829a0353a	523	#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
tushki7	0:60d829a0353a	524	#define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
tushki7	0:60d829a0353a	525	#define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
tushki7	0:60d829a0353a	526
tushki7	0:60d829a0353a	527	/** @brief Force or release APB2 peripheral reset.
tushki7	0:60d829a0353a	528	*/
tushki7	0:60d829a0353a	529	#define __TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
tushki7	0:60d829a0353a	530	#define __SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
tushki7	0:60d829a0353a	531	#define __SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
tushki7	0:60d829a0353a	532	#define __SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
tushki7	0:60d829a0353a	533
tushki7	0:60d829a0353a	534	#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
tushki7	0:60d829a0353a	535	#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
tushki7	0:60d829a0353a	536	#define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
tushki7	0:60d829a0353a	537	#define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
tushki7	0:60d829a0353a	538
tushki7	0:60d829a0353a	539	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	540	#define __LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
tushki7	0:60d829a0353a	541	#define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
tushki7	0:60d829a0353a	542	#endif /* STM32F429xx\|\| STM32F439xx */
tushki7	0:60d829a0353a	543
tushki7	0:60d829a0353a	544	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
tushki7	0:60d829a0353a	545	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
tushki7	0:60d829a0353a	546	* power consumption.
tushki7	0:60d829a0353a	547	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
tushki7	0:60d829a0353a	548	* @note By default, all peripheral clocks are enabled during SLEEP mode.
tushki7	0:60d829a0353a	549	*/
tushki7	0:60d829a0353a	550	#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
tushki7	0:60d829a0353a	551	#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
tushki7	0:60d829a0353a	552	#define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
tushki7	0:60d829a0353a	553	#define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
tushki7	0:60d829a0353a	554	#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
tushki7	0:60d829a0353a	555	#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
tushki7	0:60d829a0353a	556	#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
tushki7	0:60d829a0353a	557	#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
tushki7	0:60d829a0353a	558	#define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
tushki7	0:60d829a0353a	559	#define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
tushki7	0:60d829a0353a	560	#define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
tushki7	0:60d829a0353a	561	#define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
tushki7	0:60d829a0353a	562	#define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
tushki7	0:60d829a0353a	563	#define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
tushki7	0:60d829a0353a	564
tushki7	0:60d829a0353a	565	#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
tushki7	0:60d829a0353a	566	#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
tushki7	0:60d829a0353a	567	#define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
tushki7	0:60d829a0353a	568	#define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
tushki7	0:60d829a0353a	569	#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
tushki7	0:60d829a0353a	570	#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
tushki7	0:60d829a0353a	571	#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
tushki7	0:60d829a0353a	572	#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
tushki7	0:60d829a0353a	573	#define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
tushki7	0:60d829a0353a	574	#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
tushki7	0:60d829a0353a	575	#define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
tushki7	0:60d829a0353a	576	#define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
tushki7	0:60d829a0353a	577	#define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
tushki7	0:60d829a0353a	578
tushki7	0:60d829a0353a	579	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
tushki7	0:60d829a0353a	580	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
tushki7	0:60d829a0353a	581	* power consumption.
tushki7	0:60d829a0353a	582	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
tushki7	0:60d829a0353a	583	* @note By default, all peripheral clocks are enabled during SLEEP mode.
tushki7	0:60d829a0353a	584	*/
tushki7	0:60d829a0353a	585	#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
tushki7	0:60d829a0353a	586	#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
tushki7	0:60d829a0353a	587
tushki7	0:60d829a0353a	588	#if defined(STM32F437xx)\|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	589	#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
tushki7	0:60d829a0353a	590	#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
tushki7	0:60d829a0353a	591
tushki7	0:60d829a0353a	592	#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
tushki7	0:60d829a0353a	593	#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
tushki7	0:60d829a0353a	594	#endif /* STM32F437xx \|\| STM32F439xx */
tushki7	0:60d829a0353a	595
tushki7	0:60d829a0353a	596	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
tushki7	0:60d829a0353a	597	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
tushki7	0:60d829a0353a	598	* power consumption.
tushki7	0:60d829a0353a	599	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
tushki7	0:60d829a0353a	600	* @note By default, all peripheral clocks are enabled during SLEEP mode.
tushki7	0:60d829a0353a	601	*/
tushki7	0:60d829a0353a	602	#define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
tushki7	0:60d829a0353a	603	#define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
tushki7	0:60d829a0353a	604
tushki7	0:60d829a0353a	605	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
tushki7	0:60d829a0353a	606	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
tushki7	0:60d829a0353a	607	* power consumption.
tushki7	0:60d829a0353a	608	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
tushki7	0:60d829a0353a	609	* @note By default, all peripheral clocks are enabled during SLEEP mode.
tushki7	0:60d829a0353a	610	*/
tushki7	0:60d829a0353a	611	#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
tushki7	0:60d829a0353a	612	#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
tushki7	0:60d829a0353a	613	#define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
tushki7	0:60d829a0353a	614	#define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
tushki7	0:60d829a0353a	615	#define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
tushki7	0:60d829a0353a	616	#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
tushki7	0:60d829a0353a	617	#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
tushki7	0:60d829a0353a	618	#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
tushki7	0:60d829a0353a	619	#define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
tushki7	0:60d829a0353a	620	#define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
tushki7	0:60d829a0353a	621	#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
tushki7	0:60d829a0353a	622	#define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
tushki7	0:60d829a0353a	623	#define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
tushki7	0:60d829a0353a	624
tushki7	0:60d829a0353a	625	#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
tushki7	0:60d829a0353a	626	#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
tushki7	0:60d829a0353a	627	#define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
tushki7	0:60d829a0353a	628	#define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
tushki7	0:60d829a0353a	629	#define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
tushki7	0:60d829a0353a	630	#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
tushki7	0:60d829a0353a	631	#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
tushki7	0:60d829a0353a	632	#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
tushki7	0:60d829a0353a	633	#define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
tushki7	0:60d829a0353a	634	#define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
tushki7	0:60d829a0353a	635	#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
tushki7	0:60d829a0353a	636	#define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
tushki7	0:60d829a0353a	637	#define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
tushki7	0:60d829a0353a	638
tushki7	0:60d829a0353a	639	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
tushki7	0:60d829a0353a	640	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
tushki7	0:60d829a0353a	641	* power consumption.
tushki7	0:60d829a0353a	642	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
tushki7	0:60d829a0353a	643	* @note By default, all peripheral clocks are enabled during SLEEP mode.
tushki7	0:60d829a0353a	644	*/
tushki7	0:60d829a0353a	645	#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
tushki7	0:60d829a0353a	646	#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
tushki7	0:60d829a0353a	647	#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
tushki7	0:60d829a0353a	648	#define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
tushki7	0:60d829a0353a	649	#define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
tushki7	0:60d829a0353a	650	#define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
tushki7	0:60d829a0353a	651
tushki7	0:60d829a0353a	652	#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
tushki7	0:60d829a0353a	653	#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
tushki7	0:60d829a0353a	654	#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
tushki7	0:60d829a0353a	655	#define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
tushki7	0:60d829a0353a	656	#define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
tushki7	0:60d829a0353a	657	#define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
tushki7	0:60d829a0353a	658
tushki7	0:60d829a0353a	659	#if defined(STM32F429xx)\|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	660	#define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
tushki7	0:60d829a0353a	661
tushki7	0:60d829a0353a	662	#define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
tushki7	0:60d829a0353a	663	#endif /* STM32F429xx \|\| STM32F439xx */
tushki7	0:60d829a0353a	664	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx */
tushki7	0:60d829a0353a	665	/---------------------------------------------------------------------------------------------/
tushki7	0:60d829a0353a	666
tushki7	0:60d829a0353a	667	/----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------/
tushki7	0:60d829a0353a	668	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
tushki7	0:60d829a0353a	669	/** @brief Enables or disables the AHB1 peripheral clock.
tushki7	0:60d829a0353a	670	* @note After reset, the peripheral clock (used for registers read/write access)
tushki7	0:60d829a0353a	671	* is disabled and the application software has to enable this clock before
tushki7	0:60d829a0353a	672	* using it.
tushki7	0:60d829a0353a	673	*/
tushki7	0:60d829a0353a	674	#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOIEN))
tushki7	0:60d829a0353a	675	#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOFEN))
tushki7	0:60d829a0353a	676	#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOGEN))
tushki7	0:60d829a0353a	677	#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_OTGHSEN))
tushki7	0:60d829a0353a	678	#define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_OTGHSULPIEN))
tushki7	0:60d829a0353a	679
tushki7	0:60d829a0353a	680	#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
tushki7	0:60d829a0353a	681	#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
tushki7	0:60d829a0353a	682	#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
tushki7	0:60d829a0353a	683	#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
tushki7	0:60d829a0353a	684	#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
tushki7	0:60d829a0353a	685
tushki7	0:60d829a0353a	686	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
tushki7	0:60d829a0353a	687	/**
tushki7	0:60d829a0353a	688	* @brief Enable ETHERNET clock.
tushki7	0:60d829a0353a	689	*/
tushki7	0:60d829a0353a	690	#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACEN))
tushki7	0:60d829a0353a	691	#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACTXEN))
tushki7	0:60d829a0353a	692	#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACRXEN))
tushki7	0:60d829a0353a	693	#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACPTPEN))
tushki7	0:60d829a0353a	694	#define __ETH_CLK_ENABLE() do { \
tushki7	0:60d829a0353a	695	__ETHMAC_CLK_ENABLE(); \
tushki7	0:60d829a0353a	696	__ETHMACTX_CLK_ENABLE(); \
tushki7	0:60d829a0353a	697	__ETHMACRX_CLK_ENABLE(); \
tushki7	0:60d829a0353a	698	} while(0)
tushki7	0:60d829a0353a	699
tushki7	0:60d829a0353a	700	/**
tushki7	0:60d829a0353a	701	* @brief Disable ETHERNET clock.
tushki7	0:60d829a0353a	702	*/
tushki7	0:60d829a0353a	703	#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
tushki7	0:60d829a0353a	704	#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
tushki7	0:60d829a0353a	705	#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
tushki7	0:60d829a0353a	706	#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
tushki7	0:60d829a0353a	707	#define __ETH_CLK_DISABLE() do { \
tushki7	0:60d829a0353a	708	__ETHMACTX_CLK_DISABLE(); \
tushki7	0:60d829a0353a	709	__ETHMACRX_CLK_DISABLE(); \
tushki7	0:60d829a0353a	710	__ETHMAC_CLK_DISABLE(); \
tushki7	0:60d829a0353a	711	} while(0)
tushki7	0:60d829a0353a	712	#endif /* STM32F407xx \|\| STM32F417xx */
tushki7	0:60d829a0353a	713
tushki7	0:60d829a0353a	714	/** @brief Enable or disable the AHB2 peripheral clock.
tushki7	0:60d829a0353a	715	* @note After reset, the peripheral clock (used for registers read/write access)
tushki7	0:60d829a0353a	716	* is disabled and the application software has to enable this clock before
tushki7	0:60d829a0353a	717	* using it.
tushki7	0:60d829a0353a	718	*/
tushki7	0:60d829a0353a	719	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
tushki7	0:60d829a0353a	720	#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_DCMIEN))
tushki7	0:60d829a0353a	721	#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
tushki7	0:60d829a0353a	722	#endif /* STM32F407xx \|\| STM32F417xx */
tushki7	0:60d829a0353a	723
tushki7	0:60d829a0353a	724	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
tushki7	0:60d829a0353a	725	#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_CRYPEN))
tushki7	0:60d829a0353a	726	#define __HASH_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_HASHEN))
tushki7	0:60d829a0353a	727
tushki7	0:60d829a0353a	728	#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
tushki7	0:60d829a0353a	729	#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
tushki7	0:60d829a0353a	730	#endif /* STM32F415xx \|\| STM32F417xx */
tushki7	0:60d829a0353a	731
tushki7	0:60d829a0353a	732	/** @brief Enables or disables the AHB3 peripheral clock.
tushki7	0:60d829a0353a	733	* @note After reset, the peripheral clock (used for registers read/write access)
tushki7	0:60d829a0353a	734	* is disabled and the application software has to enable this clock before
tushki7	0:60d829a0353a	735	* using it.
tushki7	0:60d829a0353a	736	*/
tushki7	0:60d829a0353a	737	#define __FSMC_CLK_ENABLE() (RCC->AHB3ENR \|= (RCC_AHB3ENR_FSMCEN))
tushki7	0:60d829a0353a	738	#define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
tushki7	0:60d829a0353a	739
tushki7	0:60d829a0353a	740	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
tushki7	0:60d829a0353a	741	* @note After reset, the peripheral clock (used for registers read/write access)
tushki7	0:60d829a0353a	742	* is disabled and the application software has to enable this clock before
tushki7	0:60d829a0353a	743	* using it.
tushki7	0:60d829a0353a	744	*/
tushki7	0:60d829a0353a	745	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
tushki7	0:60d829a0353a	746	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
tushki7	0:60d829a0353a	747	#define __TIM12_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM12EN))
tushki7	0:60d829a0353a	748	#define __TIM13_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM13EN))
tushki7	0:60d829a0353a	749	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
tushki7	0:60d829a0353a	750	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
tushki7	0:60d829a0353a	751	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
tushki7	0:60d829a0353a	752	#define __UART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART4EN))
tushki7	0:60d829a0353a	753	#define __UART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART5EN))
tushki7	0:60d829a0353a	754	#define __CAN1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CAN1EN))
tushki7	0:60d829a0353a	755	#define __CAN2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CAN2EN))
tushki7	0:60d829a0353a	756	#define __DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
tushki7	0:60d829a0353a	757
tushki7	0:60d829a0353a	758	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
tushki7	0:60d829a0353a	759	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
tushki7	0:60d829a0353a	760	#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
tushki7	0:60d829a0353a	761	#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
tushki7	0:60d829a0353a	762	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
tushki7	0:60d829a0353a	763	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
tushki7	0:60d829a0353a	764	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
tushki7	0:60d829a0353a	765	#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
tushki7	0:60d829a0353a	766	#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
tushki7	0:60d829a0353a	767	#define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
tushki7	0:60d829a0353a	768	#define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
tushki7	0:60d829a0353a	769	#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
tushki7	0:60d829a0353a	770
tushki7	0:60d829a0353a	771	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
tushki7	0:60d829a0353a	772	* @note After reset, the peripheral clock (used for registers read/write access)
tushki7	0:60d829a0353a	773	* is disabled and the application software has to enable this clock before
tushki7	0:60d829a0353a	774	* using it.
tushki7	0:60d829a0353a	775	*/
tushki7	0:60d829a0353a	776	#define __TIM8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM8EN))
tushki7	0:60d829a0353a	777	#define __ADC2_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC2EN))
tushki7	0:60d829a0353a	778	#define __ADC3_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC3EN))
tushki7	0:60d829a0353a	779
tushki7	0:60d829a0353a	780	#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
tushki7	0:60d829a0353a	781	#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
tushki7	0:60d829a0353a	782	#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
tushki7	0:60d829a0353a	783
tushki7	0:60d829a0353a	784	/** @brief Force or release AHB1 peripheral reset.
tushki7	0:60d829a0353a	785	*/
tushki7	0:60d829a0353a	786	#define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
tushki7	0:60d829a0353a	787	#define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
tushki7	0:60d829a0353a	788	#define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
tushki7	0:60d829a0353a	789	#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
tushki7	0:60d829a0353a	790	#define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
tushki7	0:60d829a0353a	791
tushki7	0:60d829a0353a	792	#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
tushki7	0:60d829a0353a	793	#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
tushki7	0:60d829a0353a	794	#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
tushki7	0:60d829a0353a	795	#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
tushki7	0:60d829a0353a	796	#define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
tushki7	0:60d829a0353a	797
tushki7	0:60d829a0353a	798	/** @brief Force or release AHB2 peripheral reset.
tushki7	0:60d829a0353a	799	*/
tushki7	0:60d829a0353a	800	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
tushki7	0:60d829a0353a	801	#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
tushki7	0:60d829a0353a	802	#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
tushki7	0:60d829a0353a	803	#endif /* STM32F407xx \|\| STM32F417xx */
tushki7	0:60d829a0353a	804
tushki7	0:60d829a0353a	805	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
tushki7	0:60d829a0353a	806	#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
tushki7	0:60d829a0353a	807	#define __HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
tushki7	0:60d829a0353a	808
tushki7	0:60d829a0353a	809	#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
tushki7	0:60d829a0353a	810	#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
tushki7	0:60d829a0353a	811
tushki7	0:60d829a0353a	812	#endif /* STM32F415xx \|\| STM32F417xx */
tushki7	0:60d829a0353a	813
tushki7	0:60d829a0353a	814	/** @brief Force or release AHB3 peripheral reset
tushki7	0:60d829a0353a	815	*/
tushki7	0:60d829a0353a	816	#define __FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
tushki7	0:60d829a0353a	817	#define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
tushki7	0:60d829a0353a	818
tushki7	0:60d829a0353a	819	/** @brief Force or release APB1 peripheral reset.
tushki7	0:60d829a0353a	820	*/
tushki7	0:60d829a0353a	821	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
tushki7	0:60d829a0353a	822	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
tushki7	0:60d829a0353a	823	#define __TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
tushki7	0:60d829a0353a	824	#define __TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
tushki7	0:60d829a0353a	825	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
tushki7	0:60d829a0353a	826	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
tushki7	0:60d829a0353a	827	#define __UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
tushki7	0:60d829a0353a	828	#define __UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
tushki7	0:60d829a0353a	829	#define __CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
tushki7	0:60d829a0353a	830	#define __CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
tushki7	0:60d829a0353a	831	#define __DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
tushki7	0:60d829a0353a	832
tushki7	0:60d829a0353a	833	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
tushki7	0:60d829a0353a	834	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
tushki7	0:60d829a0353a	835	#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
tushki7	0:60d829a0353a	836	#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
tushki7	0:60d829a0353a	837	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
tushki7	0:60d829a0353a	838	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
tushki7	0:60d829a0353a	839	#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
tushki7	0:60d829a0353a	840	#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
tushki7	0:60d829a0353a	841	#define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
tushki7	0:60d829a0353a	842	#define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
tushki7	0:60d829a0353a	843	#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
tushki7	0:60d829a0353a	844
tushki7	0:60d829a0353a	845	/** @brief Force or release APB2 peripheral reset.
tushki7	0:60d829a0353a	846	*/
tushki7	0:60d829a0353a	847	#define __TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
tushki7	0:60d829a0353a	848	#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
tushki7	0:60d829a0353a	849
tushki7	0:60d829a0353a	850	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
tushki7	0:60d829a0353a	851	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
tushki7	0:60d829a0353a	852	* power consumption.
tushki7	0:60d829a0353a	853	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
tushki7	0:60d829a0353a	854	* @note By default, all peripheral clocks are enabled during SLEEP mode.
tushki7	0:60d829a0353a	855	*/
tushki7	0:60d829a0353a	856	#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
tushki7	0:60d829a0353a	857	#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
tushki7	0:60d829a0353a	858	#define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
tushki7	0:60d829a0353a	859	#define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
tushki7	0:60d829a0353a	860	#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
tushki7	0:60d829a0353a	861	#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
tushki7	0:60d829a0353a	862	#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
tushki7	0:60d829a0353a	863	#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
tushki7	0:60d829a0353a	864	#define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
tushki7	0:60d829a0353a	865	#define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
tushki7	0:60d829a0353a	866
tushki7	0:60d829a0353a	867	#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
tushki7	0:60d829a0353a	868	#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
tushki7	0:60d829a0353a	869	#define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
tushki7	0:60d829a0353a	870	#define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
tushki7	0:60d829a0353a	871	#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
tushki7	0:60d829a0353a	872	#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
tushki7	0:60d829a0353a	873	#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
tushki7	0:60d829a0353a	874	#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
tushki7	0:60d829a0353a	875	#define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
tushki7	0:60d829a0353a	876	#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
tushki7	0:60d829a0353a	877
tushki7	0:60d829a0353a	878	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
tushki7	0:60d829a0353a	879	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
tushki7	0:60d829a0353a	880	* power consumption.
tushki7	0:60d829a0353a	881	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
tushki7	0:60d829a0353a	882	* @note By default, all peripheral clocks are enabled during SLEEP mode.
tushki7	0:60d829a0353a	883	*/
tushki7	0:60d829a0353a	884	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
tushki7	0:60d829a0353a	885	#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
tushki7	0:60d829a0353a	886	#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
tushki7	0:60d829a0353a	887	#endif /* STM32F407xx \|\| STM32F417xx */
tushki7	0:60d829a0353a	888
tushki7	0:60d829a0353a	889	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
tushki7	0:60d829a0353a	890	#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
tushki7	0:60d829a0353a	891	#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
tushki7	0:60d829a0353a	892
tushki7	0:60d829a0353a	893	#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
tushki7	0:60d829a0353a	894	#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
tushki7	0:60d829a0353a	895	#endif /* STM32F415xx \|\| STM32F417xx */
tushki7	0:60d829a0353a	896
tushki7	0:60d829a0353a	897	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
tushki7	0:60d829a0353a	898	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
tushki7	0:60d829a0353a	899	* power consumption.
tushki7	0:60d829a0353a	900	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
tushki7	0:60d829a0353a	901	* @note By default, all peripheral clocks are enabled during SLEEP mode.
tushki7	0:60d829a0353a	902	*/
tushki7	0:60d829a0353a	903	#define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
tushki7	0:60d829a0353a	904	#define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
tushki7	0:60d829a0353a	905
tushki7	0:60d829a0353a	906	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
tushki7	0:60d829a0353a	907	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
tushki7	0:60d829a0353a	908	* power consumption.
tushki7	0:60d829a0353a	909	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
tushki7	0:60d829a0353a	910	* @note By default, all peripheral clocks are enabled during SLEEP mode.
tushki7	0:60d829a0353a	911	*/
tushki7	0:60d829a0353a	912	#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
tushki7	0:60d829a0353a	913	#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
tushki7	0:60d829a0353a	914	#define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
tushki7	0:60d829a0353a	915	#define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
tushki7	0:60d829a0353a	916	#define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
tushki7	0:60d829a0353a	917	#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
tushki7	0:60d829a0353a	918	#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
tushki7	0:60d829a0353a	919	#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
tushki7	0:60d829a0353a	920	#define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
tushki7	0:60d829a0353a	921	#define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
tushki7	0:60d829a0353a	922	#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
tushki7	0:60d829a0353a	923
tushki7	0:60d829a0353a	924	#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
tushki7	0:60d829a0353a	925	#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
tushki7	0:60d829a0353a	926	#define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
tushki7	0:60d829a0353a	927	#define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
tushki7	0:60d829a0353a	928	#define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
tushki7	0:60d829a0353a	929	#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
tushki7	0:60d829a0353a	930	#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
tushki7	0:60d829a0353a	931	#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
tushki7	0:60d829a0353a	932	#define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
tushki7	0:60d829a0353a	933	#define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
tushki7	0:60d829a0353a	934	#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
tushki7	0:60d829a0353a	935
tushki7	0:60d829a0353a	936	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
tushki7	0:60d829a0353a	937	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
tushki7	0:60d829a0353a	938	* power consumption.
tushki7	0:60d829a0353a	939	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
tushki7	0:60d829a0353a	940	* @note By default, all peripheral clocks are enabled during SLEEP mode.
tushki7	0:60d829a0353a	941	*/
tushki7	0:60d829a0353a	942	#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
tushki7	0:60d829a0353a	943	#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
tushki7	0:60d829a0353a	944	#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
tushki7	0:60d829a0353a	945
tushki7	0:60d829a0353a	946	#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
tushki7	0:60d829a0353a	947	#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
tushki7	0:60d829a0353a	948	#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
tushki7	0:60d829a0353a	949	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
tushki7	0:60d829a0353a	950	/---------------------------------------------------------------------------------------------/
tushki7	0:60d829a0353a	951
tushki7	0:60d829a0353a	952	/------------------------------------------ STM32F411xx --------------------------------------/
tushki7	0:60d829a0353a	953	#if defined(STM32F411xE)
tushki7	0:60d829a0353a	954	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
tushki7	0:60d829a0353a	955	*/
tushki7	0:60d829a0353a	956	#define __SPI5_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI5EN))
tushki7	0:60d829a0353a	957	#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
tushki7	0:60d829a0353a	958
tushki7	0:60d829a0353a	959	/** @brief Force or release APB2 peripheral reset.
tushki7	0:60d829a0353a	960	*/
tushki7	0:60d829a0353a	961	#define __SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
tushki7	0:60d829a0353a	962	#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
tushki7	0:60d829a0353a	963
tushki7	0:60d829a0353a	964	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
tushki7	0:60d829a0353a	965	*/
tushki7	0:60d829a0353a	966	#define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
tushki7	0:60d829a0353a	967	#define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
tushki7	0:60d829a0353a	968
tushki7	0:60d829a0353a	969	#endif /* STM32F411xE */
tushki7	0:60d829a0353a	970	/---------------------------------------------------------------------------------------------/
tushki7	0:60d829a0353a	971
tushki7	0:60d829a0353a	972	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
tushki7	0:60d829a0353a	973	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
tushki7	0:60d829a0353a	974
tushki7	0:60d829a0353a	975	/** @brief Macro to configure the Timers clocks prescalers
tushki7	0:60d829a0353a	976	* @note This feature is only available with STM32F429x/439x Devices.
tushki7	0:60d829a0353a	977	* @param __PRESC__ : specifies the Timers clocks prescalers selection
tushki7	0:60d829a0353a	978	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	979	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
tushki7	0:60d829a0353a	980	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
tushki7	0:60d829a0353a	981	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
tushki7	0:60d829a0353a	982	* division by 4 or more.
tushki7	0:60d829a0353a	983	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
tushki7	0:60d829a0353a	984	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
tushki7	0:60d829a0353a	985	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
tushki7	0:60d829a0353a	986	* to division by 8 or more.
tushki7	0:60d829a0353a	987	*/
tushki7	0:60d829a0353a	988	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) DCKCFGR_TIMPRE_BB = (__PRESC__))
tushki7	0:60d829a0353a	989
tushki7	0:60d829a0353a	990	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
tushki7	0:60d829a0353a	991
tushki7	0:60d829a0353a	992	#if defined(STM32F411xE)
tushki7	0:60d829a0353a	993
tushki7	0:60d829a0353a	994	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
tushki7	0:60d829a0353a	995	* @note This macro must be used only when the PLLI2S is disabled.
tushki7	0:60d829a0353a	996	* @note This macro must be used only when the PLLI2S is disabled.
tushki7	0:60d829a0353a	997	* @note PLLI2S clock source is common with the main PLL (configured in
tushki7	0:60d829a0353a	998	* HAL_RCC_ClockConfig() API).
tushki7	0:60d829a0353a	999	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
tushki7	0:60d829a0353a	1000	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
tushki7	0:60d829a0353a	1001	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
tushki7	0:60d829a0353a	1002	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
tushki7	0:60d829a0353a	1003	* of 2 MHz to limit PLLI2S jitter.
tushki7	0:60d829a0353a	1004	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
tushki7	0:60d829a0353a	1005	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
tushki7	0:60d829a0353a	1006	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
tushki7	0:60d829a0353a	1007	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
tushki7	0:60d829a0353a	1008	* @param __PLLI2SR__: specifies the division factor for I2S clock
tushki7	0:60d829a0353a	1009	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
tushki7	0:60d829a0353a	1010	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
tushki7	0:60d829a0353a	1011	* on the I2S clock frequency.
tushki7	0:60d829a0353a	1012	*/
tushki7	0:60d829a0353a	1013	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
tushki7	0:60d829a0353a	1014	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)) \| (__PLLI2SM__))
tushki7	0:60d829a0353a	1015	#endif /* STM32F411xE */
tushki7	0:60d829a0353a	1016
tushki7	0:60d829a0353a	1017
tushki7	0:60d829a0353a	1018	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	1019
tushki7	0:60d829a0353a	1020	/** @brief Macros to Enable or Disable the PLLISAI.
tushki7	0:60d829a0353a	1021	* @note The PLLSAI is only available with STM32F429x/439x Devices.
tushki7	0:60d829a0353a	1022	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
tushki7	0:60d829a0353a	1023	*/
tushki7	0:60d829a0353a	1024	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) CR_PLLSAION_BB = ENABLE)
tushki7	0:60d829a0353a	1025	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) CR_PLLSAION_BB = DISABLE)
tushki7	0:60d829a0353a	1026
tushki7	0:60d829a0353a	1027	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
tushki7	0:60d829a0353a	1028	* @note The PLLSAI is only available with STM32F429x/439x Devices.
tushki7	0:60d829a0353a	1029	* @note This function must be used only when the PLLSAI is disabled.
tushki7	0:60d829a0353a	1030	* @note PLLSAI clock source is common with the main PLL (configured in
tushki7	0:60d829a0353a	1031	* RCC_PLLConfig function )
tushki7	0:60d829a0353a	1032	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
tushki7	0:60d829a0353a	1033	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
tushki7	0:60d829a0353a	1034	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
tushki7	0:60d829a0353a	1035	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
tushki7	0:60d829a0353a	1036	* @param __PLLSAIQ__: specifies the division factor for SAI1 clock
tushki7	0:60d829a0353a	1037	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
tushki7	0:60d829a0353a	1038	* @param __PLLSAIR__: specifies the division factor for LTDC clock
tushki7	0:60d829a0353a	1039	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
tushki7	0:60d829a0353a	1040	*/
tushki7	0:60d829a0353a	1041	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) \| ((__PLLSAIQ__) << 24) \| ((__PLLSAIR__) << 28))
tushki7	0:60d829a0353a	1042
tushki7	0:60d829a0353a	1043	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
tushki7	0:60d829a0353a	1044	* @note This macro must be used only when the PLLI2S is disabled.
tushki7	0:60d829a0353a	1045	* @note PLLI2S clock source is common with the main PLL (configured in
tushki7	0:60d829a0353a	1046	* HAL_RCC_ClockConfig() API)
tushki7	0:60d829a0353a	1047	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
tushki7	0:60d829a0353a	1048	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
tushki7	0:60d829a0353a	1049	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
tushki7	0:60d829a0353a	1050	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
tushki7	0:60d829a0353a	1051	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
tushki7	0:60d829a0353a	1052	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
tushki7	0:60d829a0353a	1053	* @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
tushki7	0:60d829a0353a	1054	* and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
tushki7	0:60d829a0353a	1055	* @param __PLLI2SR__: specifies the division factor for I2S clock
tushki7	0:60d829a0353a	1056	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
tushki7	0:60d829a0353a	1057	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
tushki7	0:60d829a0353a	1058	* on the I2S clock frequency.
tushki7	0:60d829a0353a	1059	*/
tushki7	0:60d829a0353a	1060	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) \| ((__PLLI2SQ__) << 24) \| ((__PLLI2SR__) << 28))
tushki7	0:60d829a0353a	1061
tushki7	0:60d829a0353a	1062	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
tushki7	0:60d829a0353a	1063	* @note The SAI peripheral is only available with STM32F429x/439x Devices.
tushki7	0:60d829a0353a	1064	* @note This function must be called before enabling the PLLI2S.
tushki7	0:60d829a0353a	1065	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
tushki7	0:60d829a0353a	1066	* This parameter must be a number between 1 and 32.
tushki7	0:60d829a0353a	1067	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
tushki7	0:60d829a0353a	1068	*/
tushki7	0:60d829a0353a	1069	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
tushki7	0:60d829a0353a	1070
tushki7	0:60d829a0353a	1071	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
tushki7	0:60d829a0353a	1072	* @note The SAI peripheral is only available with STM32F429x/439x Devices.
tushki7	0:60d829a0353a	1073	* @note This function must be called before enabling the PLLSAI.
tushki7	0:60d829a0353a	1074	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
tushki7	0:60d829a0353a	1075	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
tushki7	0:60d829a0353a	1076	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
tushki7	0:60d829a0353a	1077	*/
tushki7	0:60d829a0353a	1078	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
tushki7	0:60d829a0353a	1079
tushki7	0:60d829a0353a	1080	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
tushki7	0:60d829a0353a	1081	*
tushki7	0:60d829a0353a	1082	* @note The LTDC peripheral is only available with STM32F429x/439x Devices.
tushki7	0:60d829a0353a	1083	* @note This function must be called before enabling the PLLSAI.
tushki7	0:60d829a0353a	1084	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
tushki7	0:60d829a0353a	1085	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
tushki7	0:60d829a0353a	1086	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
tushki7	0:60d829a0353a	1087	*/
tushki7	0:60d829a0353a	1088	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
tushki7	0:60d829a0353a	1089
tushki7	0:60d829a0353a	1090	/** @brief Macro to configure SAI1BlockA clock source selection.
tushki7	0:60d829a0353a	1091	* @note The SAI peripheral is only available with STM32F429x/439x Devices.
tushki7	0:60d829a0353a	1092	* @note This function must be called before enabling PLLSAI, PLLI2S and
tushki7	0:60d829a0353a	1093	* the SAI clock.
tushki7	0:60d829a0353a	1094	* @param __SOURCE__: specifies the SAI Block A clock source.
tushki7	0:60d829a0353a	1095	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	1096	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
tushki7	0:60d829a0353a	1097	* as SAI1 Block A clock.
tushki7	0:60d829a0353a	1098	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
tushki7	0:60d829a0353a	1099	* as SAI1 Block A clock.
tushki7	0:60d829a0353a	1100	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
tushki7	0:60d829a0353a	1101	* used as SAI1 Block A clock.
tushki7	0:60d829a0353a	1102	*/
tushki7	0:60d829a0353a	1103	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
tushki7	0:60d829a0353a	1104
tushki7	0:60d829a0353a	1105	/** @brief Macro to configure SAI1BlockB clock source selection.
tushki7	0:60d829a0353a	1106	* @note The SAI peripheral is only available with STM32F429x/439x Devices.
tushki7	0:60d829a0353a	1107	* @note This function must be called before enabling PLLSAI, PLLI2S and
tushki7	0:60d829a0353a	1108	* the SAI clock.
tushki7	0:60d829a0353a	1109	* @param __SOURCE__: specifies the SAI Block B clock source.
tushki7	0:60d829a0353a	1110	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	1111	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
tushki7	0:60d829a0353a	1112	* as SAI1 Block B clock.
tushki7	0:60d829a0353a	1113	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
tushki7	0:60d829a0353a	1114	* as SAI1 Block B clock.
tushki7	0:60d829a0353a	1115	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
tushki7	0:60d829a0353a	1116	* used as SAI1 Block B clock.
tushki7	0:60d829a0353a	1117	*/
tushki7	0:60d829a0353a	1118	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
tushki7	0:60d829a0353a	1119
tushki7	0:60d829a0353a	1120	/** @brief Enable PLLSAI_RDY interrupt.
tushki7	0:60d829a0353a	1121	*/
tushki7	0:60d829a0353a	1122	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
tushki7	0:60d829a0353a	1123
tushki7	0:60d829a0353a	1124	/** @brief Disable PLLSAI_RDY interrupt.
tushki7	0:60d829a0353a	1125	*/
tushki7	0:60d829a0353a	1126	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
tushki7	0:60d829a0353a	1127
tushki7	0:60d829a0353a	1128	/** @brief Clear the PLLSAI RDY interrupt pending bits.
tushki7	0:60d829a0353a	1129	*/
tushki7	0:60d829a0353a	1130	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
tushki7	0:60d829a0353a	1131
tushki7	0:60d829a0353a	1132	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
tushki7	0:60d829a0353a	1133	* @retval The new state (TRUE or FALSE).
tushki7	0:60d829a0353a	1134	*/
tushki7	0:60d829a0353a	1135	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
tushki7	0:60d829a0353a	1136
tushki7	0:60d829a0353a	1137	/** @brief Check PLLSAI RDY flag is set or not.
tushki7	0:60d829a0353a	1138	* @retval The new state (TRUE or FALSE).
tushki7	0:60d829a0353a	1139	*/
tushki7	0:60d829a0353a	1140	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
tushki7	0:60d829a0353a	1141
tushki7	0:60d829a0353a	1142	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
tushki7	0:60d829a0353a	1143
tushki7	0:60d829a0353a	1144	/* Exported functions --------------------------------------------------------*/
tushki7	0:60d829a0353a	1145	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
tushki7	0:60d829a0353a	1146	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
tushki7	0:60d829a0353a	1147
tushki7	0:60d829a0353a	1148	#if defined(STM32F411xE)
tushki7	0:60d829a0353a	1149	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
tushki7	0:60d829a0353a	1150	#endif /* STM32F411xE */
tushki7	0:60d829a0353a	1151	/**
tushki7	0:60d829a0353a	1152	* @}
tushki7	0:60d829a0353a	1153	*/
tushki7	0:60d829a0353a	1154
tushki7	0:60d829a0353a	1155	/**
tushki7	0:60d829a0353a	1156	* @}
tushki7	0:60d829a0353a	1157	*/
tushki7	0:60d829a0353a	1158
tushki7	0:60d829a0353a	1159	#ifdef __cplusplus
tushki7	0:60d829a0353a	1160	}
tushki7	0:60d829a0353a	1161	#endif
tushki7	0:60d829a0353a	1162
tushki7	0:60d829a0353a	1163	#endif /* __STM32F4xx_HAL_RCC_EX_H */
tushki7	0:60d829a0353a	1164
tushki7	0:60d829a0353a	1165	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	11 Apr 2015
Imports:	100
Forks:	0
Commits:	2
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mbed/TARGET_NUCLEO_F411RE/stm32f4xx_hal_rcc_ex.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

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