FRDM_K64F_LCD - A simple 128x32 graphical LCD program to quicksta…

Users » tushki7 » Code » FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies: C12832

mbed/TARGET_NUCLEO_F411RE/stm32f4xx_hal_eth.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:: tushki7
Date:: Sun Apr 12 15:45:52 2015 +0000
Revision:: 1:eb68c94a8ee5
Parent:: 0:60d829a0353a

A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

User	Revision	Line number	New contents of line
tushki7	0:60d829a0353a	1	/**
tushki7	0:60d829a0353a	2	******************************************************************************
tushki7	0:60d829a0353a	3	* @file stm32f4xx_hal_eth.h
tushki7	0:60d829a0353a	4	* @author MCD Application Team
tushki7	0:60d829a0353a	5	* @version V1.1.0
tushki7	0:60d829a0353a	6	* @date 19-June-2014
tushki7	0:60d829a0353a	7	* @brief Header file of ETH HAL module.
tushki7	0:60d829a0353a	8	******************************************************************************
tushki7	0:60d829a0353a	9	* @attention
tushki7	0:60d829a0353a	10	*
tushki7	0:60d829a0353a	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
tushki7	0:60d829a0353a	12	*
tushki7	0:60d829a0353a	13	* Redistribution and use in source and binary forms, with or without modification,
tushki7	0:60d829a0353a	14	* are permitted provided that the following conditions are met:
tushki7	0:60d829a0353a	15	* 1. Redistributions of source code must retain the above copyright notice,
tushki7	0:60d829a0353a	16	* this list of conditions and the following disclaimer.
tushki7	0:60d829a0353a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
tushki7	0:60d829a0353a	18	* this list of conditions and the following disclaimer in the documentation
tushki7	0:60d829a0353a	19	* and/or other materials provided with the distribution.
tushki7	0:60d829a0353a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
tushki7	0:60d829a0353a	21	* may be used to endorse or promote products derived from this software
tushki7	0:60d829a0353a	22	* without specific prior written permission.
tushki7	0:60d829a0353a	23	*
tushki7	0:60d829a0353a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
tushki7	0:60d829a0353a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
tushki7	0:60d829a0353a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
tushki7	0:60d829a0353a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
tushki7	0:60d829a0353a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
tushki7	0:60d829a0353a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
tushki7	0:60d829a0353a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
tushki7	0:60d829a0353a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
tushki7	0:60d829a0353a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
tushki7	0:60d829a0353a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
tushki7	0:60d829a0353a	34	*
tushki7	0:60d829a0353a	35	******************************************************************************
tushki7	0:60d829a0353a	36	*/
tushki7	0:60d829a0353a	37
tushki7	0:60d829a0353a	38	/* Define to prevent recursive inclusion -------------------------------------*/
tushki7	0:60d829a0353a	39	#ifndef __STM32F4xx_HAL_ETH_H
tushki7	0:60d829a0353a	40	#define __STM32F4xx_HAL_ETH_H
tushki7	0:60d829a0353a	41
tushki7	0:60d829a0353a	42	#ifdef __cplusplus
tushki7	0:60d829a0353a	43	extern "C" {
tushki7	0:60d829a0353a	44	#endif
tushki7	0:60d829a0353a	45
tushki7	0:60d829a0353a	46	#if defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	47	/* Includes ------------------------------------------------------------------*/
tushki7	0:60d829a0353a	48	#include "stm32f4xx_hal_def.h"
tushki7	0:60d829a0353a	49
tushki7	0:60d829a0353a	50	/** @addtogroup STM32F4xx_HAL_Driver
tushki7	0:60d829a0353a	51	* @{
tushki7	0:60d829a0353a	52	*/
tushki7	0:60d829a0353a	53
tushki7	0:60d829a0353a	54	/** @addtogroup ETH
tushki7	0:60d829a0353a	55	* @{
tushki7	0:60d829a0353a	56	*/
tushki7	0:60d829a0353a	57
tushki7	0:60d829a0353a	58	/* Exported types ------------------------------------------------------------*/
tushki7	0:60d829a0353a	59
tushki7	0:60d829a0353a	60	/**
tushki7	0:60d829a0353a	61	* @brief HAL State structures definition
tushki7	0:60d829a0353a	62	*/
tushki7	0:60d829a0353a	63	typedef enum
tushki7	0:60d829a0353a	64	{
tushki7	0:60d829a0353a	65	HAL_ETH_STATE_RESET = 0x00, /!< Peripheral not yet Initialized or disabled /
tushki7	0:60d829a0353a	66	HAL_ETH_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
tushki7	0:60d829a0353a	67	HAL_ETH_STATE_BUSY = 0x02, /!< an internal process is ongoing /
tushki7	0:60d829a0353a	68	HAL_ETH_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
tushki7	0:60d829a0353a	69	HAL_ETH_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
tushki7	0:60d829a0353a	70	HAL_ETH_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
tushki7	0:60d829a0353a	71	HAL_ETH_STATE_BUSY_WR = 0x42, /!< Write process is ongoing /
tushki7	0:60d829a0353a	72	HAL_ETH_STATE_BUSY_RD = 0x82, /!< Read process is ongoing /
tushki7	0:60d829a0353a	73	HAL_ETH_STATE_TIMEOUT = 0x03, /!< Timeout state /
tushki7	0:60d829a0353a	74	HAL_ETH_STATE_ERROR = 0x04 /!< Reception process is ongoing /
tushki7	0:60d829a0353a	75	}HAL_ETH_StateTypeDef;
tushki7	0:60d829a0353a	76
tushki7	0:60d829a0353a	77	/**
tushki7	0:60d829a0353a	78	* @brief ETH Init Structure definition
tushki7	0:60d829a0353a	79	*/
tushki7	0:60d829a0353a	80
tushki7	0:60d829a0353a	81	typedef struct
tushki7	0:60d829a0353a	82	{
tushki7	0:60d829a0353a	83	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
tushki7	0:60d829a0353a	84	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
tushki7	0:60d829a0353a	85	and the mode (half/full-duplex).
tushki7	0:60d829a0353a	86	This parameter can be a value of @ref ETH_AutoNegotiation */
tushki7	0:60d829a0353a	87
tushki7	0:60d829a0353a	88	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
tushki7	0:60d829a0353a	89	This parameter can be a value of @ref ETH_Speed */
tushki7	0:60d829a0353a	90
tushki7	0:60d829a0353a	91	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
tushki7	0:60d829a0353a	92	This parameter can be a value of @ref ETH_Duplex_Mode */
tushki7	0:60d829a0353a	93
tushki7	0:60d829a0353a	94	uint16_t PhyAddress; /*!< Ethernet PHY address.
tushki7	0:60d829a0353a	95	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
tushki7	0:60d829a0353a	96
tushki7	0:60d829a0353a	97	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
tushki7	0:60d829a0353a	98
tushki7	0:60d829a0353a	99	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
tushki7	0:60d829a0353a	100	This parameter can be a value of @ref ETH_Rx_Mode */
tushki7	0:60d829a0353a	101
tushki7	0:60d829a0353a	102	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
tushki7	0:60d829a0353a	103	This parameter can be a value of @ref ETH_Checksum_Mode */
tushki7	0:60d829a0353a	104
tushki7	0:60d829a0353a	105	uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
tushki7	0:60d829a0353a	106	This parameter can be a value of @ref ETH_Media_Interface */
tushki7	0:60d829a0353a	107
tushki7	0:60d829a0353a	108	} ETH_InitTypeDef;
tushki7	0:60d829a0353a	109
tushki7	0:60d829a0353a	110
tushki7	0:60d829a0353a	111	/**
tushki7	0:60d829a0353a	112	* @brief ETH MAC Configuration Structure definition
tushki7	0:60d829a0353a	113	*/
tushki7	0:60d829a0353a	114
tushki7	0:60d829a0353a	115	typedef struct
tushki7	0:60d829a0353a	116	{
tushki7	0:60d829a0353a	117	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
tushki7	0:60d829a0353a	118	When enabled, the MAC allows no more then 2048 bytes to be received.
tushki7	0:60d829a0353a	119	When disabled, the MAC can receive up to 16384 bytes.
tushki7	0:60d829a0353a	120	This parameter can be a value of @ref ETH_watchdog */
tushki7	0:60d829a0353a	121
tushki7	0:60d829a0353a	122	uint32_t Jabber; /*!< Selects or not Jabber timer
tushki7	0:60d829a0353a	123	When enabled, the MAC allows no more then 2048 bytes to be sent.
tushki7	0:60d829a0353a	124	When disabled, the MAC can send up to 16384 bytes.
tushki7	0:60d829a0353a	125	This parameter can be a value of @ref ETH_Jabber */
tushki7	0:60d829a0353a	126
tushki7	0:60d829a0353a	127	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
tushki7	0:60d829a0353a	128	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
tushki7	0:60d829a0353a	129
tushki7	0:60d829a0353a	130	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
tushki7	0:60d829a0353a	131	This parameter can be a value of @ref ETH_Carrier_Sense */
tushki7	0:60d829a0353a	132
tushki7	0:60d829a0353a	133	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
tushki7	0:60d829a0353a	134	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
tushki7	0:60d829a0353a	135	in Half-Duplex mode.
tushki7	0:60d829a0353a	136	This parameter can be a value of @ref ETH_Receive_Own */
tushki7	0:60d829a0353a	137
tushki7	0:60d829a0353a	138	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
tushki7	0:60d829a0353a	139	This parameter can be a value of @ref ETH_Loop_Back_Mode */
tushki7	0:60d829a0353a	140
tushki7	0:60d829a0353a	141	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
tushki7	0:60d829a0353a	142	This parameter can be a value of @ref ETH_Checksum_Offload */
tushki7	0:60d829a0353a	143
tushki7	0:60d829a0353a	144	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
tushki7	0:60d829a0353a	145	when a collision occurs (Half-Duplex mode).
tushki7	0:60d829a0353a	146	This parameter can be a value of @ref ETH_Retry_Transmission */
tushki7	0:60d829a0353a	147
tushki7	0:60d829a0353a	148	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
tushki7	0:60d829a0353a	149	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
tushki7	0:60d829a0353a	150
tushki7	0:60d829a0353a	151	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
tushki7	0:60d829a0353a	152	This parameter can be a value of @ref ETH_Back_Off_Limit */
tushki7	0:60d829a0353a	153
tushki7	0:60d829a0353a	154	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
tushki7	0:60d829a0353a	155	This parameter can be a value of @ref ETH_Deferral_Check */
tushki7	0:60d829a0353a	156
tushki7	0:60d829a0353a	157	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
tushki7	0:60d829a0353a	158	This parameter can be a value of @ref ETH_Receive_All */
tushki7	0:60d829a0353a	159
tushki7	0:60d829a0353a	160	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
tushki7	0:60d829a0353a	161	This parameter can be a value of @ref ETH_Source_Addr_Filter */
tushki7	0:60d829a0353a	162
tushki7	0:60d829a0353a	163	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
tushki7	0:60d829a0353a	164	This parameter can be a value of @ref ETH_Pass_Control_Frames */
tushki7	0:60d829a0353a	165
tushki7	0:60d829a0353a	166	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
tushki7	0:60d829a0353a	167	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
tushki7	0:60d829a0353a	168
tushki7	0:60d829a0353a	169	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
tushki7	0:60d829a0353a	170	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
tushki7	0:60d829a0353a	171
tushki7	0:60d829a0353a	172	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
tushki7	0:60d829a0353a	173	This parameter can be a value of @ref ETH_Promiscuous_Mode */
tushki7	0:60d829a0353a	174
tushki7	0:60d829a0353a	175	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
tushki7	0:60d829a0353a	176	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
tushki7	0:60d829a0353a	177
tushki7	0:60d829a0353a	178	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
tushki7	0:60d829a0353a	179	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
tushki7	0:60d829a0353a	180
tushki7	0:60d829a0353a	181	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
tushki7	0:60d829a0353a	182	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
tushki7	0:60d829a0353a	183
tushki7	0:60d829a0353a	184	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
tushki7	0:60d829a0353a	185	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
tushki7	0:60d829a0353a	186
tushki7	0:60d829a0353a	187	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
tushki7	0:60d829a0353a	188	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
tushki7	0:60d829a0353a	189
tushki7	0:60d829a0353a	190	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
tushki7	0:60d829a0353a	191	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
tushki7	0:60d829a0353a	192
tushki7	0:60d829a0353a	193	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
tushki7	0:60d829a0353a	194	automatic retransmission of PAUSE Frame.
tushki7	0:60d829a0353a	195	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
tushki7	0:60d829a0353a	196
tushki7	0:60d829a0353a	197	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
tushki7	0:60d829a0353a	198	unicast address and unique multicast address).
tushki7	0:60d829a0353a	199	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
tushki7	0:60d829a0353a	200
tushki7	0:60d829a0353a	201	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
tushki7	0:60d829a0353a	202	disable its transmitter for a specified time (Pause Time)
tushki7	0:60d829a0353a	203	This parameter can be a value of @ref ETH_Receive_Flow_Control */
tushki7	0:60d829a0353a	204
tushki7	0:60d829a0353a	205	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
tushki7	0:60d829a0353a	206	or the MAC back-pressure operation (Half-Duplex mode)
tushki7	0:60d829a0353a	207	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
tushki7	0:60d829a0353a	208
tushki7	0:60d829a0353a	209	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
tushki7	0:60d829a0353a	210	comparison and filtering.
tushki7	0:60d829a0353a	211	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
tushki7	0:60d829a0353a	212
tushki7	0:60d829a0353a	213	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
tushki7	0:60d829a0353a	214
tushki7	0:60d829a0353a	215	} ETH_MACInitTypeDef;
tushki7	0:60d829a0353a	216
tushki7	0:60d829a0353a	217
tushki7	0:60d829a0353a	218	/**
tushki7	0:60d829a0353a	219	* @brief ETH DMA Configuration Structure definition
tushki7	0:60d829a0353a	220	*/
tushki7	0:60d829a0353a	221
tushki7	0:60d829a0353a	222	typedef struct
tushki7	0:60d829a0353a	223	{
tushki7	0:60d829a0353a	224	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
tushki7	0:60d829a0353a	225	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
tushki7	0:60d829a0353a	226
tushki7	0:60d829a0353a	227	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
tushki7	0:60d829a0353a	228	This parameter can be a value of @ref ETH_Receive_Store_Forward */
tushki7	0:60d829a0353a	229
tushki7	0:60d829a0353a	230	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
tushki7	0:60d829a0353a	231	This parameter can be a value of @ref ETH_Flush_Received_Frame */
tushki7	0:60d829a0353a	232
tushki7	0:60d829a0353a	233	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
tushki7	0:60d829a0353a	234	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
tushki7	0:60d829a0353a	235
tushki7	0:60d829a0353a	236	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
tushki7	0:60d829a0353a	237	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
tushki7	0:60d829a0353a	238
tushki7	0:60d829a0353a	239	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
tushki7	0:60d829a0353a	240	This parameter can be a value of @ref ETH_Forward_Error_Frames */
tushki7	0:60d829a0353a	241
tushki7	0:60d829a0353a	242	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
tushki7	0:60d829a0353a	243	and length less than 64 bytes) including pad-bytes and CRC)
tushki7	0:60d829a0353a	244	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
tushki7	0:60d829a0353a	245
tushki7	0:60d829a0353a	246	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
tushki7	0:60d829a0353a	247	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
tushki7	0:60d829a0353a	248
tushki7	0:60d829a0353a	249	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
tushki7	0:60d829a0353a	250	frame of Transmit data even before obtaining the status for the first frame.
tushki7	0:60d829a0353a	251	This parameter can be a value of @ref ETH_Second_Frame_Operate */
tushki7	0:60d829a0353a	252
tushki7	0:60d829a0353a	253	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
tushki7	0:60d829a0353a	254	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
tushki7	0:60d829a0353a	255
tushki7	0:60d829a0353a	256	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
tushki7	0:60d829a0353a	257	This parameter can be a value of @ref ETH_Fixed_Burst */
tushki7	0:60d829a0353a	258
tushki7	0:60d829a0353a	259	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
tushki7	0:60d829a0353a	260	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
tushki7	0:60d829a0353a	261
tushki7	0:60d829a0353a	262	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
tushki7	0:60d829a0353a	263	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
tushki7	0:60d829a0353a	264
tushki7	0:60d829a0353a	265	uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
tushki7	0:60d829a0353a	266	This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
tushki7	0:60d829a0353a	267
tushki7	0:60d829a0353a	268	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
tushki7	0:60d829a0353a	269	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
tushki7	0:60d829a0353a	270
tushki7	0:60d829a0353a	271	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
tushki7	0:60d829a0353a	272	This parameter can be a value of @ref ETH_DMA_Arbitration */
tushki7	0:60d829a0353a	273	} ETH_DMAInitTypeDef;
tushki7	0:60d829a0353a	274
tushki7	0:60d829a0353a	275
tushki7	0:60d829a0353a	276	/**
tushki7	0:60d829a0353a	277	* @brief ETH DMA Descriptors data structure definition
tushki7	0:60d829a0353a	278	*/
tushki7	0:60d829a0353a	279
tushki7	0:60d829a0353a	280	typedef struct
tushki7	0:60d829a0353a	281	{
tushki7	0:60d829a0353a	282	__IO uint32_t Status; /!< Status /
tushki7	0:60d829a0353a	283
tushki7	0:60d829a0353a	284	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
tushki7	0:60d829a0353a	285
tushki7	0:60d829a0353a	286	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
tushki7	0:60d829a0353a	287
tushki7	0:60d829a0353a	288	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
tushki7	0:60d829a0353a	289
tushki7	0:60d829a0353a	290	/!< Enhanced ETHERNET DMA PTP Descriptors /
tushki7	0:60d829a0353a	291	uint32_t ExtendedStatus; /!< Extended status for PTP receive descriptor /
tushki7	0:60d829a0353a	292
tushki7	0:60d829a0353a	293	uint32_t Reserved1; /!< Reserved /
tushki7	0:60d829a0353a	294
tushki7	0:60d829a0353a	295	uint32_t TimeStampLow; /!< Time Stamp Low value for transmit and receive /
tushki7	0:60d829a0353a	296
tushki7	0:60d829a0353a	297	uint32_t TimeStampHigh; /!< Time Stamp High value for transmit and receive /
tushki7	0:60d829a0353a	298
tushki7	0:60d829a0353a	299	} ETH_DMADescTypeDef;
tushki7	0:60d829a0353a	300
tushki7	0:60d829a0353a	301
tushki7	0:60d829a0353a	302	/**
tushki7	0:60d829a0353a	303	* @brief Received Frame Informations structure definition
tushki7	0:60d829a0353a	304	*/
tushki7	0:60d829a0353a	305	typedef struct
tushki7	0:60d829a0353a	306	{
tushki7	0:60d829a0353a	307	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
tushki7	0:60d829a0353a	308
tushki7	0:60d829a0353a	309	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
tushki7	0:60d829a0353a	310
tushki7	0:60d829a0353a	311	uint32_t SegCount; /!< Segment count /
tushki7	0:60d829a0353a	312
tushki7	0:60d829a0353a	313	uint32_t length; /!< Frame length /
tushki7	0:60d829a0353a	314
tushki7	0:60d829a0353a	315	uint32_t buffer; /!< Frame buffer /
tushki7	0:60d829a0353a	316
tushki7	0:60d829a0353a	317	} ETH_DMARxFrameInfos;
tushki7	0:60d829a0353a	318
tushki7	0:60d829a0353a	319
tushki7	0:60d829a0353a	320	/**
tushki7	0:60d829a0353a	321	* @brief ETH Handle Structure definition
tushki7	0:60d829a0353a	322	*/
tushki7	0:60d829a0353a	323
tushki7	0:60d829a0353a	324	typedef struct
tushki7	0:60d829a0353a	325	{
tushki7	0:60d829a0353a	326	ETH_TypeDef Instance; /!< Register base address */
tushki7	0:60d829a0353a	327
tushki7	0:60d829a0353a	328	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
tushki7	0:60d829a0353a	329
tushki7	0:60d829a0353a	330	uint32_t LinkStatus; /!< Ethernet link status /
tushki7	0:60d829a0353a	331
tushki7	0:60d829a0353a	332	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
tushki7	0:60d829a0353a	333
tushki7	0:60d829a0353a	334	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
tushki7	0:60d829a0353a	335
tushki7	0:60d829a0353a	336	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
tushki7	0:60d829a0353a	337
tushki7	0:60d829a0353a	338	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
tushki7	0:60d829a0353a	339
tushki7	0:60d829a0353a	340	HAL_LockTypeDef Lock; /!< ETH Lock /
tushki7	0:60d829a0353a	341
tushki7	0:60d829a0353a	342	} ETH_HandleTypeDef;
tushki7	0:60d829a0353a	343
tushki7	0:60d829a0353a	344	/* Exported constants --------------------------------------------------------*/
tushki7	0:60d829a0353a	345
tushki7	0:60d829a0353a	346	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
tushki7	0:60d829a0353a	347
tushki7	0:60d829a0353a	348	/* Delay to wait when writing to some Ethernet registers */
tushki7	0:60d829a0353a	349	#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	350
tushki7	0:60d829a0353a	351
tushki7	0:60d829a0353a	352	/* ETHERNET Errors */
tushki7	0:60d829a0353a	353	#define ETH_SUCCESS ((uint32_t)0)
tushki7	0:60d829a0353a	354	#define ETH_ERROR ((uint32_t)1)
tushki7	0:60d829a0353a	355
tushki7	0:60d829a0353a	356	/** @defgroup ETH_Buffers_setting
tushki7	0:60d829a0353a	357	* @{
tushki7	0:60d829a0353a	358	*/
tushki7	0:60d829a0353a	359	#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC /
tushki7	0:60d829a0353a	360	#define ETH_HEADER ((uint32_t)14) /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
tushki7	0:60d829a0353a	361	#define ETH_CRC ((uint32_t)4) /!< Ethernet CRC /
tushki7	0:60d829a0353a	362	#define ETH_EXTRA ((uint32_t)2) /!< Extra bytes in some cases /
tushki7	0:60d829a0353a	363	#define VLAN_TAG ((uint32_t)4) /!< optional 802.1q VLAN Tag /
tushki7	0:60d829a0353a	364	#define MIN_ETH_PAYLOAD ((uint32_t)46) /!< Minimum Ethernet payload size /
tushki7	0:60d829a0353a	365	#define MAX_ETH_PAYLOAD ((uint32_t)1500) /!< Maximum Ethernet payload size /
tushki7	0:60d829a0353a	366	#define JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /!< Jumbo frame payload size /
tushki7	0:60d829a0353a	367
tushki7	0:60d829a0353a	368	/* Ethernet driver receive buffers are organized in a chained linked-list, when
tushki7	0:60d829a0353a	369	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
tushki7	0:60d829a0353a	370	to the driver receive buffers memory.
tushki7	0:60d829a0353a	371
tushki7	0:60d829a0353a	372	Depending on the size of the received ethernet packet and the size of
tushki7	0:60d829a0353a	373	each ethernet driver receive buffer, the received packet can take one or more
tushki7	0:60d829a0353a	374	ethernet driver receive buffer.
tushki7	0:60d829a0353a	375
tushki7	0:60d829a0353a	376	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
tushki7	0:60d829a0353a	377	and the total count of the driver receive buffers ETH_RXBUFNB.
tushki7	0:60d829a0353a	378
tushki7	0:60d829a0353a	379	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
tushki7	0:60d829a0353a	380	example, they can be reconfigured in the application layer to fit the application
tushki7	0:60d829a0353a	381	needs */
tushki7	0:60d829a0353a	382
tushki7	0:60d829a0353a	383	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
tushki7	0:60d829a0353a	384	packet */
tushki7	0:60d829a0353a	385	#ifndef ETH_RX_BUF_SIZE
tushki7	0:60d829a0353a	386	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
tushki7	0:60d829a0353a	387	#endif
tushki7	0:60d829a0353a	388
tushki7	0:60d829a0353a	389	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
tushki7	0:60d829a0353a	390	#ifndef ETH_RXBUFNB
tushki7	0:60d829a0353a	391	#define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
tushki7	0:60d829a0353a	392	#endif
tushki7	0:60d829a0353a	393
tushki7	0:60d829a0353a	394
tushki7	0:60d829a0353a	395	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
tushki7	0:60d829a0353a	396	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
tushki7	0:60d829a0353a	397	driver transmit buffers memory to the TxFIFO.
tushki7	0:60d829a0353a	398
tushki7	0:60d829a0353a	399	Depending on the size of the Ethernet packet to be transmitted and the size of
tushki7	0:60d829a0353a	400	each ethernet driver transmit buffer, the packet to be transmitted can take
tushki7	0:60d829a0353a	401	one or more ethernet driver transmit buffer.
tushki7	0:60d829a0353a	402
tushki7	0:60d829a0353a	403	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
tushki7	0:60d829a0353a	404	and the total count of the driver transmit buffers ETH_TXBUFNB.
tushki7	0:60d829a0353a	405
tushki7	0:60d829a0353a	406	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
tushki7	0:60d829a0353a	407	example, they can be reconfigured in the application layer to fit the application
tushki7	0:60d829a0353a	408	needs */
tushki7	0:60d829a0353a	409
tushki7	0:60d829a0353a	410	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
tushki7	0:60d829a0353a	411	packet */
tushki7	0:60d829a0353a	412	#ifndef ETH_TX_BUF_SIZE
tushki7	0:60d829a0353a	413	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
tushki7	0:60d829a0353a	414	#endif
tushki7	0:60d829a0353a	415
tushki7	0:60d829a0353a	416	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
tushki7	0:60d829a0353a	417	#ifndef ETH_TXBUFNB
tushki7	0:60d829a0353a	418	#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
tushki7	0:60d829a0353a	419	#endif
tushki7	0:60d829a0353a	420
tushki7	0:60d829a0353a	421
tushki7	0:60d829a0353a	422	/*
tushki7	0:60d829a0353a	423	DMA Tx Desciptor
tushki7	0:60d829a0353a	424	-----------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	425	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
tushki7	0:60d829a0353a	426	-----------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	427	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
tushki7	0:60d829a0353a	428	-----------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	429	TDES2 \| Buffer1 Address [31:0] \|
tushki7	0:60d829a0353a	430	-----------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	431	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
tushki7	0:60d829a0353a	432	-----------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	433	*/
tushki7	0:60d829a0353a	434
tushki7	0:60d829a0353a	435	/**
tushki7	0:60d829a0353a	436	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
tushki7	0:60d829a0353a	437	*/
tushki7	0:60d829a0353a	438	#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
tushki7	0:60d829a0353a	439	#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /!< Interrupt on Completion /
tushki7	0:60d829a0353a	440	#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /!< Last Segment /
tushki7	0:60d829a0353a	441	#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /!< First Segment /
tushki7	0:60d829a0353a	442	#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /!< Disable CRC /
tushki7	0:60d829a0353a	443	#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /!< Disable Padding /
tushki7	0:60d829a0353a	444	#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /!< Transmit Time Stamp Enable /
tushki7	0:60d829a0353a	445	#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /!< Checksum Insertion Control: 4 cases /
tushki7	0:60d829a0353a	446	#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /!< Do Nothing: Checksum Engine is bypassed /
tushki7	0:60d829a0353a	447	#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /!< IPV4 header Checksum Insertion /
tushki7	0:60d829a0353a	448	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
tushki7	0:60d829a0353a	449	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
tushki7	0:60d829a0353a	450	#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /!< Transmit End of Ring /
tushki7	0:60d829a0353a	451	#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /!< Second Address Chained /
tushki7	0:60d829a0353a	452	#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /!< Tx Time Stamp Status /
tushki7	0:60d829a0353a	453	#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /!< IP Header Error /
tushki7	0:60d829a0353a	454	#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
tushki7	0:60d829a0353a	455	#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /!< Jabber Timeout /
tushki7	0:60d829a0353a	456	#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
tushki7	0:60d829a0353a	457	#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /!< Payload Checksum Error /
tushki7	0:60d829a0353a	458	#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /!< Loss of Carrier: carrier lost during transmission /
tushki7	0:60d829a0353a	459	#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /!< No Carrier: no carrier signal from the transceiver /
tushki7	0:60d829a0353a	460	#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /!< Late Collision: transmission aborted due to collision /
tushki7	0:60d829a0353a	461	#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /!< Excessive Collision: transmission aborted after 16 collisions /
tushki7	0:60d829a0353a	462	#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /!< VLAN Frame /
tushki7	0:60d829a0353a	463	#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /!< Collision Count /
tushki7	0:60d829a0353a	464	#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /!< Excessive Deferral /
tushki7	0:60d829a0353a	465	#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /!< Underflow Error: late data arrival from the memory /
tushki7	0:60d829a0353a	466	#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /!< Deferred Bit /
tushki7	0:60d829a0353a	467
tushki7	0:60d829a0353a	468	/**
tushki7	0:60d829a0353a	469	* @brief Bit definition of TDES1 register
tushki7	0:60d829a0353a	470	*/
tushki7	0:60d829a0353a	471	#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /!< Transmit Buffer2 Size /
tushki7	0:60d829a0353a	472	#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /!< Transmit Buffer1 Size /
tushki7	0:60d829a0353a	473
tushki7	0:60d829a0353a	474	/**
tushki7	0:60d829a0353a	475	* @brief Bit definition of TDES2 register
tushki7	0:60d829a0353a	476	*/
tushki7	0:60d829a0353a	477	#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
tushki7	0:60d829a0353a	478
tushki7	0:60d829a0353a	479	/**
tushki7	0:60d829a0353a	480	* @brief Bit definition of TDES3 register
tushki7	0:60d829a0353a	481	*/
tushki7	0:60d829a0353a	482	#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
tushki7	0:60d829a0353a	483
tushki7	0:60d829a0353a	484	/*---------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	485	TDES6 \| Transmit Time Stamp Low [31:0] \|
tushki7	0:60d829a0353a	486	-----------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	487	TDES7 \| Transmit Time Stamp High [31:0] \|
tushki7	0:60d829a0353a	488	----------------------------------------------------------------------------------------------*/
tushki7	0:60d829a0353a	489
tushki7	0:60d829a0353a	490	/* Bit definition of TDES6 register */
tushki7	0:60d829a0353a	491	#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
tushki7	0:60d829a0353a	492
tushki7	0:60d829a0353a	493	/* Bit definition of TDES7 register */
tushki7	0:60d829a0353a	494	#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
tushki7	0:60d829a0353a	495
tushki7	0:60d829a0353a	496	/**
tushki7	0:60d829a0353a	497	* @}
tushki7	0:60d829a0353a	498	*/
tushki7	0:60d829a0353a	499
tushki7	0:60d829a0353a	500
tushki7	0:60d829a0353a	501	/** @defgroup ETH_DMA_Rx_descriptor
tushki7	0:60d829a0353a	502	* @{
tushki7	0:60d829a0353a	503	*/
tushki7	0:60d829a0353a	504
tushki7	0:60d829a0353a	505	/*
tushki7	0:60d829a0353a	506	DMA Rx Descriptor
tushki7	0:60d829a0353a	507	--------------------------------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	508	RDES0 \| OWN(31) \| Status [30:0] \|
tushki7	0:60d829a0353a	509	---------------------------------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	510	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
tushki7	0:60d829a0353a	511	---------------------------------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	512	RDES2 \| Buffer1 Address [31:0] \|
tushki7	0:60d829a0353a	513	---------------------------------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	514	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
tushki7	0:60d829a0353a	515	---------------------------------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	516	*/
tushki7	0:60d829a0353a	517
tushki7	0:60d829a0353a	518	/**
tushki7	0:60d829a0353a	519	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
tushki7	0:60d829a0353a	520	*/
tushki7	0:60d829a0353a	521	#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
tushki7	0:60d829a0353a	522	#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /!< DA Filter Fail for the rx frame /
tushki7	0:60d829a0353a	523	#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /!< Receive descriptor frame length /
tushki7	0:60d829a0353a	524	#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
tushki7	0:60d829a0353a	525	#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /!< Descriptor error: no more descriptors for receive frame /
tushki7	0:60d829a0353a	526	#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /!< SA Filter Fail for the received frame /
tushki7	0:60d829a0353a	527	#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /!< Frame size not matching with length field /
tushki7	0:60d829a0353a	528	#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /!< Overflow Error: Frame was damaged due to buffer overflow /
tushki7	0:60d829a0353a	529	#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /!< VLAN Tag: received frame is a VLAN frame /
tushki7	0:60d829a0353a	530	#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /!< First descriptor of the frame /
tushki7	0:60d829a0353a	531	#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /!< Last descriptor of the frame /
tushki7	0:60d829a0353a	532	#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /!< IPC Checksum Error: Rx Ipv4 header checksum error /
tushki7	0:60d829a0353a	533	#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /!< Late collision occurred during reception /
tushki7	0:60d829a0353a	534	#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /!< Frame type - Ethernet, otherwise 802.3 /
tushki7	0:60d829a0353a	535	#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /!< Receive Watchdog Timeout: watchdog timer expired during reception /
tushki7	0:60d829a0353a	536	#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /!< Receive error: error reported by MII interface /
tushki7	0:60d829a0353a	537	#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /!< Dribble bit error: frame contains non int multiple of 8 bits /
tushki7	0:60d829a0353a	538	#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /!< CRC error /
tushki7	0:60d829a0353a	539	#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
tushki7	0:60d829a0353a	540
tushki7	0:60d829a0353a	541	/**
tushki7	0:60d829a0353a	542	* @brief Bit definition of RDES1 register
tushki7	0:60d829a0353a	543	*/
tushki7	0:60d829a0353a	544	#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /!< Disable Interrupt on Completion /
tushki7	0:60d829a0353a	545	#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /!< Receive Buffer2 Size /
tushki7	0:60d829a0353a	546	#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /!< Receive End of Ring /
tushki7	0:60d829a0353a	547	#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /!< Second Address Chained /
tushki7	0:60d829a0353a	548	#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /!< Receive Buffer1 Size /
tushki7	0:60d829a0353a	549
tushki7	0:60d829a0353a	550	/**
tushki7	0:60d829a0353a	551	* @brief Bit definition of RDES2 register
tushki7	0:60d829a0353a	552	*/
tushki7	0:60d829a0353a	553	#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
tushki7	0:60d829a0353a	554
tushki7	0:60d829a0353a	555	/**
tushki7	0:60d829a0353a	556	* @brief Bit definition of RDES3 register
tushki7	0:60d829a0353a	557	*/
tushki7	0:60d829a0353a	558	#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
tushki7	0:60d829a0353a	559
tushki7	0:60d829a0353a	560	/*---------------------------------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	561	RDES4 \| Reserved[31:15] \| Extended Status [14:0] \|
tushki7	0:60d829a0353a	562	---------------------------------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	563	RDES5 \| Reserved[31:0] \|
tushki7	0:60d829a0353a	564	---------------------------------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	565	RDES6 \| Receive Time Stamp Low [31:0] \|
tushki7	0:60d829a0353a	566	---------------------------------------------------------------------------------------------------------------------
tushki7	0:60d829a0353a	567	RDES7 \| Receive Time Stamp High [31:0] \|
tushki7	0:60d829a0353a	568	--------------------------------------------------------------------------------------------------------------------*/
tushki7	0:60d829a0353a	569
tushki7	0:60d829a0353a	570	/* Bit definition of RDES4 register */
tushki7	0:60d829a0353a	571	#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
tushki7	0:60d829a0353a	572	#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
tushki7	0:60d829a0353a	573	#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
tushki7	0:60d829a0353a	574	#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
tushki7	0:60d829a0353a	575	#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
tushki7	0:60d829a0353a	576	#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
tushki7	0:60d829a0353a	577	#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
tushki7	0:60d829a0353a	578	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
tushki7	0:60d829a0353a	579	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
tushki7	0:60d829a0353a	580	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
tushki7	0:60d829a0353a	581	#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
tushki7	0:60d829a0353a	582	#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
tushki7	0:60d829a0353a	583	#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
tushki7	0:60d829a0353a	584	#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
tushki7	0:60d829a0353a	585	#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
tushki7	0:60d829a0353a	586	#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
tushki7	0:60d829a0353a	587	#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
tushki7	0:60d829a0353a	588	#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
tushki7	0:60d829a0353a	589	#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
tushki7	0:60d829a0353a	590
tushki7	0:60d829a0353a	591	/* Bit definition of RDES6 register */
tushki7	0:60d829a0353a	592	#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
tushki7	0:60d829a0353a	593
tushki7	0:60d829a0353a	594	/* Bit definition of RDES7 register */
tushki7	0:60d829a0353a	595	#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
tushki7	0:60d829a0353a	596
tushki7	0:60d829a0353a	597
tushki7	0:60d829a0353a	598	/** @defgroup ETH_AutoNegotiation
tushki7	0:60d829a0353a	599	* @{
tushki7	0:60d829a0353a	600	*/
tushki7	0:60d829a0353a	601	#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	602	#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	603	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
tushki7	0:60d829a0353a	604	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
tushki7	0:60d829a0353a	605	/**
tushki7	0:60d829a0353a	606	* @}
tushki7	0:60d829a0353a	607	*/
tushki7	0:60d829a0353a	608	/** @defgroup ETH_Speed
tushki7	0:60d829a0353a	609	* @{
tushki7	0:60d829a0353a	610	*/
tushki7	0:60d829a0353a	611	#define ETH_SPEED_10M ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	612	#define ETH_SPEED_100M ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	613	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
tushki7	0:60d829a0353a	614	((SPEED) == ETH_SPEED_100M))
tushki7	0:60d829a0353a	615	/**
tushki7	0:60d829a0353a	616	* @}
tushki7	0:60d829a0353a	617	*/
tushki7	0:60d829a0353a	618	/** @defgroup ETH_Duplex_Mode
tushki7	0:60d829a0353a	619	* @{
tushki7	0:60d829a0353a	620	*/
tushki7	0:60d829a0353a	621	#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	622	#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	623	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
tushki7	0:60d829a0353a	624	((MODE) == ETH_MODE_HALFDUPLEX))
tushki7	0:60d829a0353a	625	/**
tushki7	0:60d829a0353a	626	* @}
tushki7	0:60d829a0353a	627	*/
tushki7	0:60d829a0353a	628	/** @defgroup ETH_Rx_Mode
tushki7	0:60d829a0353a	629	* @{
tushki7	0:60d829a0353a	630	*/
tushki7	0:60d829a0353a	631	#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	632	#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	633	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
tushki7	0:60d829a0353a	634	((MODE) == ETH_RXINTERRUPT_MODE))
tushki7	0:60d829a0353a	635	/**
tushki7	0:60d829a0353a	636	* @}
tushki7	0:60d829a0353a	637	*/
tushki7	0:60d829a0353a	638
tushki7	0:60d829a0353a	639	/** @defgroup ETH_Checksum_Mode
tushki7	0:60d829a0353a	640	* @{
tushki7	0:60d829a0353a	641	*/
tushki7	0:60d829a0353a	642	#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	643	#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	644	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
tushki7	0:60d829a0353a	645	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
tushki7	0:60d829a0353a	646	/**
tushki7	0:60d829a0353a	647	* @}
tushki7	0:60d829a0353a	648	*/
tushki7	0:60d829a0353a	649
tushki7	0:60d829a0353a	650	/** @defgroup ETH_Media_Interface
tushki7	0:60d829a0353a	651	* @{
tushki7	0:60d829a0353a	652	*/
tushki7	0:60d829a0353a	653	#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	654	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
tushki7	0:60d829a0353a	655	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
tushki7	0:60d829a0353a	656	((MODE) == ETH_MEDIA_INTERFACE_RMII))
tushki7	0:60d829a0353a	657
tushki7	0:60d829a0353a	658	/**
tushki7	0:60d829a0353a	659	* @}
tushki7	0:60d829a0353a	660	*/
tushki7	0:60d829a0353a	661
tushki7	0:60d829a0353a	662	/** @defgroup ETH_watchdog
tushki7	0:60d829a0353a	663	* @{
tushki7	0:60d829a0353a	664	*/
tushki7	0:60d829a0353a	665	#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	666	#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
tushki7	0:60d829a0353a	667	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
tushki7	0:60d829a0353a	668	((CMD) == ETH_WATCHDOG_DISABLE))
tushki7	0:60d829a0353a	669
tushki7	0:60d829a0353a	670	/**
tushki7	0:60d829a0353a	671	* @}
tushki7	0:60d829a0353a	672	*/
tushki7	0:60d829a0353a	673
tushki7	0:60d829a0353a	674	/** @defgroup ETH_Jabber
tushki7	0:60d829a0353a	675	* @{
tushki7	0:60d829a0353a	676	*/
tushki7	0:60d829a0353a	677	#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	678	#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
tushki7	0:60d829a0353a	679	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
tushki7	0:60d829a0353a	680	((CMD) == ETH_JABBER_DISABLE))
tushki7	0:60d829a0353a	681
tushki7	0:60d829a0353a	682	/**
tushki7	0:60d829a0353a	683	* @}
tushki7	0:60d829a0353a	684	*/
tushki7	0:60d829a0353a	685
tushki7	0:60d829a0353a	686	/** @defgroup ETH_Inter_Frame_Gap
tushki7	0:60d829a0353a	687	* @{
tushki7	0:60d829a0353a	688	*/
tushki7	0:60d829a0353a	689	#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /!< minimum IFG between frames during transmission is 96Bit /
tushki7	0:60d829a0353a	690	#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /!< minimum IFG between frames during transmission is 88Bit /
tushki7	0:60d829a0353a	691	#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /!< minimum IFG between frames during transmission is 80Bit /
tushki7	0:60d829a0353a	692	#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /!< minimum IFG between frames during transmission is 72Bit /
tushki7	0:60d829a0353a	693	#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /!< minimum IFG between frames during transmission is 64Bit /
tushki7	0:60d829a0353a	694	#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /!< minimum IFG between frames during transmission is 56Bit /
tushki7	0:60d829a0353a	695	#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /!< minimum IFG between frames during transmission is 48Bit /
tushki7	0:60d829a0353a	696	#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /!< minimum IFG between frames during transmission is 40Bit /
tushki7	0:60d829a0353a	697	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
tushki7	0:60d829a0353a	698	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
tushki7	0:60d829a0353a	699	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
tushki7	0:60d829a0353a	700	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
tushki7	0:60d829a0353a	701	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
tushki7	0:60d829a0353a	702	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
tushki7	0:60d829a0353a	703	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
tushki7	0:60d829a0353a	704	((GAP) == ETH_INTERFRAMEGAP_40BIT))
tushki7	0:60d829a0353a	705
tushki7	0:60d829a0353a	706	/**
tushki7	0:60d829a0353a	707	* @}
tushki7	0:60d829a0353a	708	*/
tushki7	0:60d829a0353a	709
tushki7	0:60d829a0353a	710	/** @defgroup ETH_Carrier_Sense
tushki7	0:60d829a0353a	711	* @{
tushki7	0:60d829a0353a	712	*/
tushki7	0:60d829a0353a	713	#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	714	#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	715	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
tushki7	0:60d829a0353a	716	((CMD) == ETH_CARRIERSENCE_DISABLE))
tushki7	0:60d829a0353a	717
tushki7	0:60d829a0353a	718	/**
tushki7	0:60d829a0353a	719	* @}
tushki7	0:60d829a0353a	720	*/
tushki7	0:60d829a0353a	721
tushki7	0:60d829a0353a	722	/** @defgroup ETH_Receive_Own
tushki7	0:60d829a0353a	723	* @{
tushki7	0:60d829a0353a	724	*/
tushki7	0:60d829a0353a	725	#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	726	#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	727	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
tushki7	0:60d829a0353a	728	((CMD) == ETH_RECEIVEOWN_DISABLE))
tushki7	0:60d829a0353a	729
tushki7	0:60d829a0353a	730	/**
tushki7	0:60d829a0353a	731	* @}
tushki7	0:60d829a0353a	732	*/
tushki7	0:60d829a0353a	733
tushki7	0:60d829a0353a	734	/** @defgroup ETH_Loop_Back_Mode
tushki7	0:60d829a0353a	735	* @{
tushki7	0:60d829a0353a	736	*/
tushki7	0:60d829a0353a	737	#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	738	#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	739	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
tushki7	0:60d829a0353a	740	((CMD) == ETH_LOOPBACKMODE_DISABLE))
tushki7	0:60d829a0353a	741
tushki7	0:60d829a0353a	742	/**
tushki7	0:60d829a0353a	743	* @}
tushki7	0:60d829a0353a	744	*/
tushki7	0:60d829a0353a	745
tushki7	0:60d829a0353a	746	/** @defgroup ETH_Checksum_Offload
tushki7	0:60d829a0353a	747	* @{
tushki7	0:60d829a0353a	748	*/
tushki7	0:60d829a0353a	749	#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	750	#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	751	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
tushki7	0:60d829a0353a	752	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
tushki7	0:60d829a0353a	753
tushki7	0:60d829a0353a	754	/**
tushki7	0:60d829a0353a	755	* @}
tushki7	0:60d829a0353a	756	*/
tushki7	0:60d829a0353a	757
tushki7	0:60d829a0353a	758	/** @defgroup ETH_Retry_Transmission
tushki7	0:60d829a0353a	759	* @{
tushki7	0:60d829a0353a	760	*/
tushki7	0:60d829a0353a	761	#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	762	#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	763	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
tushki7	0:60d829a0353a	764	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
tushki7	0:60d829a0353a	765
tushki7	0:60d829a0353a	766	/**
tushki7	0:60d829a0353a	767	* @}
tushki7	0:60d829a0353a	768	*/
tushki7	0:60d829a0353a	769
tushki7	0:60d829a0353a	770	/** @defgroup ETH_Automatic_Pad_CRC_Strip
tushki7	0:60d829a0353a	771	* @{
tushki7	0:60d829a0353a	772	*/
tushki7	0:60d829a0353a	773	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	774	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	775	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
tushki7	0:60d829a0353a	776	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
tushki7	0:60d829a0353a	777
tushki7	0:60d829a0353a	778	/**
tushki7	0:60d829a0353a	779	* @}
tushki7	0:60d829a0353a	780	*/
tushki7	0:60d829a0353a	781
tushki7	0:60d829a0353a	782	/** @defgroup ETH_Back_Off_Limit
tushki7	0:60d829a0353a	783	* @{
tushki7	0:60d829a0353a	784	*/
tushki7	0:60d829a0353a	785	#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	786	#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	787	#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	788	#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
tushki7	0:60d829a0353a	789	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
tushki7	0:60d829a0353a	790	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
tushki7	0:60d829a0353a	791	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
tushki7	0:60d829a0353a	792	((LIMIT) == ETH_BACKOFFLIMIT_1))
tushki7	0:60d829a0353a	793
tushki7	0:60d829a0353a	794	/**
tushki7	0:60d829a0353a	795	* @}
tushki7	0:60d829a0353a	796	*/
tushki7	0:60d829a0353a	797
tushki7	0:60d829a0353a	798	/** @defgroup ETH_Deferral_Check
tushki7	0:60d829a0353a	799	* @{
tushki7	0:60d829a0353a	800	*/
tushki7	0:60d829a0353a	801	#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	802	#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	803	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
tushki7	0:60d829a0353a	804	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
tushki7	0:60d829a0353a	805
tushki7	0:60d829a0353a	806	/**
tushki7	0:60d829a0353a	807	* @}
tushki7	0:60d829a0353a	808	*/
tushki7	0:60d829a0353a	809
tushki7	0:60d829a0353a	810	/** @defgroup ETH_Receive_All
tushki7	0:60d829a0353a	811	* @{
tushki7	0:60d829a0353a	812	*/
tushki7	0:60d829a0353a	813	#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
tushki7	0:60d829a0353a	814	#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	815	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
tushki7	0:60d829a0353a	816	((CMD) == ETH_RECEIVEAll_DISABLE))
tushki7	0:60d829a0353a	817
tushki7	0:60d829a0353a	818	/**
tushki7	0:60d829a0353a	819	* @}
tushki7	0:60d829a0353a	820	*/
tushki7	0:60d829a0353a	821
tushki7	0:60d829a0353a	822	/** @defgroup ETH_Source_Addr_Filter
tushki7	0:60d829a0353a	823	* @{
tushki7	0:60d829a0353a	824	*/
tushki7	0:60d829a0353a	825	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	826	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
tushki7	0:60d829a0353a	827	#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	828	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
tushki7	0:60d829a0353a	829	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
tushki7	0:60d829a0353a	830	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
tushki7	0:60d829a0353a	831
tushki7	0:60d829a0353a	832	/**
tushki7	0:60d829a0353a	833	* @}
tushki7	0:60d829a0353a	834	*/
tushki7	0:60d829a0353a	835
tushki7	0:60d829a0353a	836	/** @defgroup ETH_Pass_Control_Frames
tushki7	0:60d829a0353a	837	* @{
tushki7	0:60d829a0353a	838	*/
tushki7	0:60d829a0353a	839	#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /!< MAC filters all control frames from reaching the application /
tushki7	0:60d829a0353a	840	#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /!< MAC forwards all control frames to application even if they fail the Address Filter /
tushki7	0:60d829a0353a	841	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /!< MAC forwards control frames that pass the Address Filter. /
tushki7	0:60d829a0353a	842	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
tushki7	0:60d829a0353a	843	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
tushki7	0:60d829a0353a	844	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
tushki7	0:60d829a0353a	845
tushki7	0:60d829a0353a	846	/**
tushki7	0:60d829a0353a	847	* @}
tushki7	0:60d829a0353a	848	*/
tushki7	0:60d829a0353a	849
tushki7	0:60d829a0353a	850	/** @defgroup ETH_Broadcast_Frames_Reception
tushki7	0:60d829a0353a	851	* @{
tushki7	0:60d829a0353a	852	*/
tushki7	0:60d829a0353a	853	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	854	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	855	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
tushki7	0:60d829a0353a	856	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
tushki7	0:60d829a0353a	857
tushki7	0:60d829a0353a	858	/**
tushki7	0:60d829a0353a	859	* @}
tushki7	0:60d829a0353a	860	*/
tushki7	0:60d829a0353a	861
tushki7	0:60d829a0353a	862	/** @defgroup ETH_Destination_Addr_Filter
tushki7	0:60d829a0353a	863	* @{
tushki7	0:60d829a0353a	864	*/
tushki7	0:60d829a0353a	865	#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	866	#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	867	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
tushki7	0:60d829a0353a	868	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
tushki7	0:60d829a0353a	869
tushki7	0:60d829a0353a	870	/**
tushki7	0:60d829a0353a	871	* @}
tushki7	0:60d829a0353a	872	*/
tushki7	0:60d829a0353a	873
tushki7	0:60d829a0353a	874	/** @defgroup ETH_Promiscuous_Mode
tushki7	0:60d829a0353a	875	* @{
tushki7	0:60d829a0353a	876	*/
tushki7	0:60d829a0353a	877	#define ETH_PROMISCIOUSMODE_ENABLE ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	878	#define ETH_PROMISCIOUSMODE_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	879	#define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PROMISCIOUSMODE_ENABLE) \|\| \
tushki7	0:60d829a0353a	880	((CMD) == ETH_PROMISCIOUSMODE_DISABLE))
tushki7	0:60d829a0353a	881
tushki7	0:60d829a0353a	882	/**
tushki7	0:60d829a0353a	883	* @}
tushki7	0:60d829a0353a	884	*/
tushki7	0:60d829a0353a	885
tushki7	0:60d829a0353a	886	/** @defgroup ETH_Multicast_Frames_Filter
tushki7	0:60d829a0353a	887	* @{
tushki7	0:60d829a0353a	888	*/
tushki7	0:60d829a0353a	889	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
tushki7	0:60d829a0353a	890	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	891	#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	892	#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	893	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
tushki7	0:60d829a0353a	894	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
tushki7	0:60d829a0353a	895	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
tushki7	0:60d829a0353a	896	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
tushki7	0:60d829a0353a	897	/**
tushki7	0:60d829a0353a	898	* @}
tushki7	0:60d829a0353a	899	*/
tushki7	0:60d829a0353a	900
tushki7	0:60d829a0353a	901	/** @defgroup ETH_Unicast_Frames_Filter
tushki7	0:60d829a0353a	902	* @{
tushki7	0:60d829a0353a	903	*/
tushki7	0:60d829a0353a	904	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
tushki7	0:60d829a0353a	905	#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	906	#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	907	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
tushki7	0:60d829a0353a	908	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
tushki7	0:60d829a0353a	909	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
tushki7	0:60d829a0353a	910	/**
tushki7	0:60d829a0353a	911	* @}
tushki7	0:60d829a0353a	912	*/
tushki7	0:60d829a0353a	913
tushki7	0:60d829a0353a	914	/** @defgroup ETH_Pause_Time
tushki7	0:60d829a0353a	915	* @{
tushki7	0:60d829a0353a	916	*/
tushki7	0:60d829a0353a	917	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
tushki7	0:60d829a0353a	918
tushki7	0:60d829a0353a	919	/**
tushki7	0:60d829a0353a	920	* @}
tushki7	0:60d829a0353a	921	*/
tushki7	0:60d829a0353a	922
tushki7	0:60d829a0353a	923	/** @defgroup ETH_Zero_Quanta_Pause
tushki7	0:60d829a0353a	924	* @{
tushki7	0:60d829a0353a	925	*/
tushki7	0:60d829a0353a	926	#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	927	#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	928	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
tushki7	0:60d829a0353a	929	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
tushki7	0:60d829a0353a	930	/**
tushki7	0:60d829a0353a	931	* @}
tushki7	0:60d829a0353a	932	*/
tushki7	0:60d829a0353a	933
tushki7	0:60d829a0353a	934	/** @defgroup ETH_Pause_Low_Threshold
tushki7	0:60d829a0353a	935	* @{
tushki7	0:60d829a0353a	936	*/
tushki7	0:60d829a0353a	937	#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /!< Pause time minus 4 slot times /
tushki7	0:60d829a0353a	938	#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /!< Pause time minus 28 slot times /
tushki7	0:60d829a0353a	939	#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /!< Pause time minus 144 slot times /
tushki7	0:60d829a0353a	940	#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /!< Pause time minus 256 slot times /
tushki7	0:60d829a0353a	941	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
tushki7	0:60d829a0353a	942	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
tushki7	0:60d829a0353a	943	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
tushki7	0:60d829a0353a	944	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
tushki7	0:60d829a0353a	945	/**
tushki7	0:60d829a0353a	946	* @}
tushki7	0:60d829a0353a	947	*/
tushki7	0:60d829a0353a	948
tushki7	0:60d829a0353a	949	/** @defgroup ETH_Unicast_Pause_Frame_Detect
tushki7	0:60d829a0353a	950	* @{
tushki7	0:60d829a0353a	951	*/
tushki7	0:60d829a0353a	952	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	953	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	954	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
tushki7	0:60d829a0353a	955	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
tushki7	0:60d829a0353a	956	/**
tushki7	0:60d829a0353a	957	* @}
tushki7	0:60d829a0353a	958	*/
tushki7	0:60d829a0353a	959
tushki7	0:60d829a0353a	960	/** @defgroup ETH_Receive_Flow_Control
tushki7	0:60d829a0353a	961	* @{
tushki7	0:60d829a0353a	962	*/
tushki7	0:60d829a0353a	963	#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	964	#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	965	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
tushki7	0:60d829a0353a	966	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
tushki7	0:60d829a0353a	967	/**
tushki7	0:60d829a0353a	968	* @}
tushki7	0:60d829a0353a	969	*/
tushki7	0:60d829a0353a	970
tushki7	0:60d829a0353a	971	/** @defgroup ETH_Transmit_Flow_Control
tushki7	0:60d829a0353a	972	* @{
tushki7	0:60d829a0353a	973	*/
tushki7	0:60d829a0353a	974	#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	975	#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	976	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
tushki7	0:60d829a0353a	977	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
tushki7	0:60d829a0353a	978	/**
tushki7	0:60d829a0353a	979	* @}
tushki7	0:60d829a0353a	980	*/
tushki7	0:60d829a0353a	981
tushki7	0:60d829a0353a	982	/** @defgroup ETH_VLAN_Tag_Comparison
tushki7	0:60d829a0353a	983	* @{
tushki7	0:60d829a0353a	984	*/
tushki7	0:60d829a0353a	985	#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	986	#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	987	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
tushki7	0:60d829a0353a	988	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
tushki7	0:60d829a0353a	989	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
tushki7	0:60d829a0353a	990
tushki7	0:60d829a0353a	991	/**
tushki7	0:60d829a0353a	992	* @}
tushki7	0:60d829a0353a	993	*/
tushki7	0:60d829a0353a	994
tushki7	0:60d829a0353a	995	/** @defgroup ETH_MAC_addresses
tushki7	0:60d829a0353a	996	* @{
tushki7	0:60d829a0353a	997	*/
tushki7	0:60d829a0353a	998	#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	999	#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	1000	#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	1001	#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
tushki7	0:60d829a0353a	1002	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
tushki7	0:60d829a0353a	1003	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
tushki7	0:60d829a0353a	1004	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
tushki7	0:60d829a0353a	1005	((ADDRESS) == ETH_MAC_ADDRESS3))
tushki7	0:60d829a0353a	1006	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
tushki7	0:60d829a0353a	1007	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
tushki7	0:60d829a0353a	1008	((ADDRESS) == ETH_MAC_ADDRESS3))
tushki7	0:60d829a0353a	1009	/**
tushki7	0:60d829a0353a	1010	* @}
tushki7	0:60d829a0353a	1011	*/
tushki7	0:60d829a0353a	1012
tushki7	0:60d829a0353a	1013	/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
tushki7	0:60d829a0353a	1014	* @{
tushki7	0:60d829a0353a	1015	*/
tushki7	0:60d829a0353a	1016	#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	1017	#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	1018	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
tushki7	0:60d829a0353a	1019	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
tushki7	0:60d829a0353a	1020	/**
tushki7	0:60d829a0353a	1021	* @}
tushki7	0:60d829a0353a	1022	*/
tushki7	0:60d829a0353a	1023
tushki7	0:60d829a0353a	1024	/** @defgroup ETH_MAC_addresses_filter_Mask_bytes
tushki7	0:60d829a0353a	1025	* @{
tushki7	0:60d829a0353a	1026	*/
tushki7	0:60d829a0353a	1027	#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /!< Mask MAC Address high reg bits [15:8] /
tushki7	0:60d829a0353a	1028	#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /!< Mask MAC Address high reg bits [7:0] /
tushki7	0:60d829a0353a	1029	#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /!< Mask MAC Address low reg bits [31:24] /
tushki7	0:60d829a0353a	1030	#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /!< Mask MAC Address low reg bits [23:16] /
tushki7	0:60d829a0353a	1031	#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /!< Mask MAC Address low reg bits [15:8] /
tushki7	0:60d829a0353a	1032	#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /!< Mask MAC Address low reg bits [70] /
tushki7	0:60d829a0353a	1033	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
tushki7	0:60d829a0353a	1034	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
tushki7	0:60d829a0353a	1035	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
tushki7	0:60d829a0353a	1036	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
tushki7	0:60d829a0353a	1037	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
tushki7	0:60d829a0353a	1038	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
tushki7	0:60d829a0353a	1039
tushki7	0:60d829a0353a	1040	/**
tushki7	0:60d829a0353a	1041	* @}
tushki7	0:60d829a0353a	1042	*/
tushki7	0:60d829a0353a	1043
tushki7	0:60d829a0353a	1044	/** @defgroup ETH_MAC_Debug_flags
tushki7	0:60d829a0353a	1045	* @{
tushki7	0:60d829a0353a	1046	*/
tushki7	0:60d829a0353a	1047	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
tushki7	0:60d829a0353a	1048
tushki7	0:60d829a0353a	1049	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
tushki7	0:60d829a0353a	1050
tushki7	0:60d829a0353a	1051	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
tushki7	0:60d829a0353a	1052
tushki7	0:60d829a0353a	1053	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
tushki7	0:60d829a0353a	1054	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
tushki7	0:60d829a0353a	1055	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
tushki7	0:60d829a0353a	1056	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
tushki7	0:60d829a0353a	1057
tushki7	0:60d829a0353a	1058	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
tushki7	0:60d829a0353a	1059
tushki7	0:60d829a0353a	1060	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
tushki7	0:60d829a0353a	1061	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
tushki7	0:60d829a0353a	1062	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
tushki7	0:60d829a0353a	1063	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
tushki7	0:60d829a0353a	1064
tushki7	0:60d829a0353a	1065	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
tushki7	0:60d829a0353a	1066
tushki7	0:60d829a0353a	1067	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
tushki7	0:60d829a0353a	1068	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
tushki7	0:60d829a0353a	1069	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
tushki7	0:60d829a0353a	1070	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
tushki7	0:60d829a0353a	1071
tushki7	0:60d829a0353a	1072	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
tushki7	0:60d829a0353a	1073	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
tushki7	0:60d829a0353a	1074	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
tushki7	0:60d829a0353a	1075	#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
tushki7	0:60d829a0353a	1076
tushki7	0:60d829a0353a	1077	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
tushki7	0:60d829a0353a	1078
tushki7	0:60d829a0353a	1079	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
tushki7	0:60d829a0353a	1080	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
tushki7	0:60d829a0353a	1081	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
tushki7	0:60d829a0353a	1082	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
tushki7	0:60d829a0353a	1083
tushki7	0:60d829a0353a	1084	#define ETH_MAC_MII_RECEIVE_PROTOCOL_AVTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
tushki7	0:60d829a0353a	1085
tushki7	0:60d829a0353a	1086	/**
tushki7	0:60d829a0353a	1087	* @}
tushki7	0:60d829a0353a	1088	*/
tushki7	0:60d829a0353a	1089
tushki7	0:60d829a0353a	1090	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
tushki7	0:60d829a0353a	1091	* @{
tushki7	0:60d829a0353a	1092	*/
tushki7	0:60d829a0353a	1093	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	1094	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
tushki7	0:60d829a0353a	1095	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
tushki7	0:60d829a0353a	1096	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
tushki7	0:60d829a0353a	1097	/**
tushki7	0:60d829a0353a	1098	* @}
tushki7	0:60d829a0353a	1099	*/
tushki7	0:60d829a0353a	1100
tushki7	0:60d829a0353a	1101	/** @defgroup ETH_Receive_Store_Forward
tushki7	0:60d829a0353a	1102	* @{
tushki7	0:60d829a0353a	1103	*/
tushki7	0:60d829a0353a	1104	#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
tushki7	0:60d829a0353a	1105	#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	1106	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
tushki7	0:60d829a0353a	1107	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
tushki7	0:60d829a0353a	1108	/**
tushki7	0:60d829a0353a	1109	* @}
tushki7	0:60d829a0353a	1110	*/
tushki7	0:60d829a0353a	1111
tushki7	0:60d829a0353a	1112	/** @defgroup ETH_Flush_Received_Frame
tushki7	0:60d829a0353a	1113	* @{
tushki7	0:60d829a0353a	1114	*/
tushki7	0:60d829a0353a	1115	#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	1116	#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
tushki7	0:60d829a0353a	1117	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
tushki7	0:60d829a0353a	1118	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
tushki7	0:60d829a0353a	1119	/**
tushki7	0:60d829a0353a	1120	* @}
tushki7	0:60d829a0353a	1121	*/
tushki7	0:60d829a0353a	1122
tushki7	0:60d829a0353a	1123	/** @defgroup ETH_Transmit_Store_Forward
tushki7	0:60d829a0353a	1124	* @{
tushki7	0:60d829a0353a	1125	*/
tushki7	0:60d829a0353a	1126	#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
tushki7	0:60d829a0353a	1127	#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	1128	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
tushki7	0:60d829a0353a	1129	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
tushki7	0:60d829a0353a	1130	/**
tushki7	0:60d829a0353a	1131	* @}
tushki7	0:60d829a0353a	1132	*/
tushki7	0:60d829a0353a	1133
tushki7	0:60d829a0353a	1134	/** @defgroup ETH_Transmit_Threshold_Control
tushki7	0:60d829a0353a	1135	* @{
tushki7	0:60d829a0353a	1136	*/
tushki7	0:60d829a0353a	1137	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
tushki7	0:60d829a0353a	1138	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
tushki7	0:60d829a0353a	1139	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
tushki7	0:60d829a0353a	1140	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
tushki7	0:60d829a0353a	1141	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
tushki7	0:60d829a0353a	1142	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
tushki7	0:60d829a0353a	1143	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
tushki7	0:60d829a0353a	1144	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
tushki7	0:60d829a0353a	1145	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
tushki7	0:60d829a0353a	1146	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
tushki7	0:60d829a0353a	1147	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
tushki7	0:60d829a0353a	1148	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
tushki7	0:60d829a0353a	1149	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
tushki7	0:60d829a0353a	1150	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
tushki7	0:60d829a0353a	1151	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
tushki7	0:60d829a0353a	1152	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
tushki7	0:60d829a0353a	1153	/**
tushki7	0:60d829a0353a	1154	* @}
tushki7	0:60d829a0353a	1155	*/
tushki7	0:60d829a0353a	1156
tushki7	0:60d829a0353a	1157	/** @defgroup ETH_Forward_Error_Frames
tushki7	0:60d829a0353a	1158	* @{
tushki7	0:60d829a0353a	1159	*/
tushki7	0:60d829a0353a	1160	#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	1161	#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	1162	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
tushki7	0:60d829a0353a	1163	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
tushki7	0:60d829a0353a	1164	/**
tushki7	0:60d829a0353a	1165	* @}
tushki7	0:60d829a0353a	1166	*/
tushki7	0:60d829a0353a	1167
tushki7	0:60d829a0353a	1168	/** @defgroup ETH_Forward_Undersized_Good_Frames
tushki7	0:60d829a0353a	1169	* @{
tushki7	0:60d829a0353a	1170	*/
tushki7	0:60d829a0353a	1171	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	1172	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	1173	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
tushki7	0:60d829a0353a	1174	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
tushki7	0:60d829a0353a	1175
tushki7	0:60d829a0353a	1176	/**
tushki7	0:60d829a0353a	1177	* @}
tushki7	0:60d829a0353a	1178	*/
tushki7	0:60d829a0353a	1179
tushki7	0:60d829a0353a	1180	/** @defgroup ETH_Receive_Threshold_Control
tushki7	0:60d829a0353a	1181	* @{
tushki7	0:60d829a0353a	1182	*/
tushki7	0:60d829a0353a	1183	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Receive FIFO is 64 Bytes /
tushki7	0:60d829a0353a	1184	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /!< threshold level of the MTL Receive FIFO is 32 Bytes /
tushki7	0:60d829a0353a	1185	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /!< threshold level of the MTL Receive FIFO is 96 Bytes /
tushki7	0:60d829a0353a	1186	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /!< threshold level of the MTL Receive FIFO is 128 Bytes /
tushki7	0:60d829a0353a	1187	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
tushki7	0:60d829a0353a	1188	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
tushki7	0:60d829a0353a	1189	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
tushki7	0:60d829a0353a	1190	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
tushki7	0:60d829a0353a	1191	/**
tushki7	0:60d829a0353a	1192	* @}
tushki7	0:60d829a0353a	1193	*/
tushki7	0:60d829a0353a	1194
tushki7	0:60d829a0353a	1195	/** @defgroup ETH_Second_Frame_Operate
tushki7	0:60d829a0353a	1196	* @{
tushki7	0:60d829a0353a	1197	*/
tushki7	0:60d829a0353a	1198	#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	1199	#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	1200	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
tushki7	0:60d829a0353a	1201	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
tushki7	0:60d829a0353a	1202
tushki7	0:60d829a0353a	1203	/**
tushki7	0:60d829a0353a	1204	* @}
tushki7	0:60d829a0353a	1205	*/
tushki7	0:60d829a0353a	1206
tushki7	0:60d829a0353a	1207	/** @defgroup ETH_Address_Aligned_Beats
tushki7	0:60d829a0353a	1208	* @{
tushki7	0:60d829a0353a	1209	*/
tushki7	0:60d829a0353a	1210	#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
tushki7	0:60d829a0353a	1211	#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	1212	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
tushki7	0:60d829a0353a	1213	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
tushki7	0:60d829a0353a	1214
tushki7	0:60d829a0353a	1215	/**
tushki7	0:60d829a0353a	1216	* @}
tushki7	0:60d829a0353a	1217	*/
tushki7	0:60d829a0353a	1218
tushki7	0:60d829a0353a	1219	/** @defgroup ETH_Fixed_Burst
tushki7	0:60d829a0353a	1220	* @{
tushki7	0:60d829a0353a	1221	*/
tushki7	0:60d829a0353a	1222	#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
tushki7	0:60d829a0353a	1223	#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	1224	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
tushki7	0:60d829a0353a	1225	((CMD) == ETH_FIXEDBURST_DISABLE))
tushki7	0:60d829a0353a	1226
tushki7	0:60d829a0353a	1227	/**
tushki7	0:60d829a0353a	1228	* @}
tushki7	0:60d829a0353a	1229	*/
tushki7	0:60d829a0353a	1230
tushki7	0:60d829a0353a	1231	/** @defgroup ETH_Rx_DMA_Burst_Length
tushki7	0:60d829a0353a	1232	* @{
tushki7	0:60d829a0353a	1233	*/
tushki7	0:60d829a0353a	1234	#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
tushki7	0:60d829a0353a	1235	#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
tushki7	0:60d829a0353a	1236	#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
tushki7	0:60d829a0353a	1237	#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
tushki7	0:60d829a0353a	1238	#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
tushki7	0:60d829a0353a	1239	#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
tushki7	0:60d829a0353a	1240	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
tushki7	0:60d829a0353a	1241	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
tushki7	0:60d829a0353a	1242	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
tushki7	0:60d829a0353a	1243	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
tushki7	0:60d829a0353a	1244	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
tushki7	0:60d829a0353a	1245	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
tushki7	0:60d829a0353a	1246
tushki7	0:60d829a0353a	1247	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
tushki7	0:60d829a0353a	1248	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
tushki7	0:60d829a0353a	1249	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
tushki7	0:60d829a0353a	1250	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
tushki7	0:60d829a0353a	1251	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
tushki7	0:60d829a0353a	1252	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
tushki7	0:60d829a0353a	1253	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
tushki7	0:60d829a0353a	1254	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
tushki7	0:60d829a0353a	1255	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
tushki7	0:60d829a0353a	1256	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
tushki7	0:60d829a0353a	1257	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
tushki7	0:60d829a0353a	1258	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
tushki7	0:60d829a0353a	1259
tushki7	0:60d829a0353a	1260	/**
tushki7	0:60d829a0353a	1261	* @}
tushki7	0:60d829a0353a	1262	*/
tushki7	0:60d829a0353a	1263
tushki7	0:60d829a0353a	1264	/** @defgroup ETH_Tx_DMA_Burst_Length
tushki7	0:60d829a0353a	1265	* @{
tushki7	0:60d829a0353a	1266	*/
tushki7	0:60d829a0353a	1267	#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
tushki7	0:60d829a0353a	1268	#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
tushki7	0:60d829a0353a	1269	#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
tushki7	0:60d829a0353a	1270	#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
tushki7	0:60d829a0353a	1271	#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
tushki7	0:60d829a0353a	1272	#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
tushki7	0:60d829a0353a	1273	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
tushki7	0:60d829a0353a	1274	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
tushki7	0:60d829a0353a	1275	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
tushki7	0:60d829a0353a	1276	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
tushki7	0:60d829a0353a	1277	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
tushki7	0:60d829a0353a	1278	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
tushki7	0:60d829a0353a	1279
tushki7	0:60d829a0353a	1280	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
tushki7	0:60d829a0353a	1281	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
tushki7	0:60d829a0353a	1282	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
tushki7	0:60d829a0353a	1283	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
tushki7	0:60d829a0353a	1284	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
tushki7	0:60d829a0353a	1285	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
tushki7	0:60d829a0353a	1286	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
tushki7	0:60d829a0353a	1287	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
tushki7	0:60d829a0353a	1288	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
tushki7	0:60d829a0353a	1289	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
tushki7	0:60d829a0353a	1290	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
tushki7	0:60d829a0353a	1291	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
tushki7	0:60d829a0353a	1292
tushki7	0:60d829a0353a	1293	/** @defgroup ETH_DMA_Enhanced_descriptor_format
tushki7	0:60d829a0353a	1294	* @{
tushki7	0:60d829a0353a	1295	*/
tushki7	0:60d829a0353a	1296	#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	1297	#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	1298
tushki7	0:60d829a0353a	1299	#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) \|\| \
tushki7	0:60d829a0353a	1300	((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
tushki7	0:60d829a0353a	1301
tushki7	0:60d829a0353a	1302	/**
tushki7	0:60d829a0353a	1303	* @}
tushki7	0:60d829a0353a	1304	*/
tushki7	0:60d829a0353a	1305
tushki7	0:60d829a0353a	1306	/**
tushki7	0:60d829a0353a	1307	* @brief ETH DMA Descriptor SkipLength
tushki7	0:60d829a0353a	1308	*/
tushki7	0:60d829a0353a	1309	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
tushki7	0:60d829a0353a	1310
tushki7	0:60d829a0353a	1311
tushki7	0:60d829a0353a	1312	/** @defgroup ETH_DMA_Arbitration
tushki7	0:60d829a0353a	1313	* @{
tushki7	0:60d829a0353a	1314	*/
tushki7	0:60d829a0353a	1315	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	1316	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	1317	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	1318	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
tushki7	0:60d829a0353a	1319	#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	1320	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
tushki7	0:60d829a0353a	1321	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
tushki7	0:60d829a0353a	1322	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
tushki7	0:60d829a0353a	1323	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
tushki7	0:60d829a0353a	1324	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
tushki7	0:60d829a0353a	1325	/**
tushki7	0:60d829a0353a	1326	* @}
tushki7	0:60d829a0353a	1327	*/
tushki7	0:60d829a0353a	1328
tushki7	0:60d829a0353a	1329	/** @defgroup ETH_DMA_Tx_descriptor_flags
tushki7	0:60d829a0353a	1330	* @{
tushki7	0:60d829a0353a	1331	*/
tushki7	0:60d829a0353a	1332	#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) \|\| \
tushki7	0:60d829a0353a	1333	((FLAG) == ETH_DMATXDESC_IC) \|\| \
tushki7	0:60d829a0353a	1334	((FLAG) == ETH_DMATXDESC_LS) \|\| \
tushki7	0:60d829a0353a	1335	((FLAG) == ETH_DMATXDESC_FS) \|\| \
tushki7	0:60d829a0353a	1336	((FLAG) == ETH_DMATXDESC_DC) \|\| \
tushki7	0:60d829a0353a	1337	((FLAG) == ETH_DMATXDESC_DP) \|\| \
tushki7	0:60d829a0353a	1338	((FLAG) == ETH_DMATXDESC_TTSE) \|\| \
tushki7	0:60d829a0353a	1339	((FLAG) == ETH_DMATXDESC_TER) \|\| \
tushki7	0:60d829a0353a	1340	((FLAG) == ETH_DMATXDESC_TCH) \|\| \
tushki7	0:60d829a0353a	1341	((FLAG) == ETH_DMATXDESC_TTSS) \|\| \
tushki7	0:60d829a0353a	1342	((FLAG) == ETH_DMATXDESC_IHE) \|\| \
tushki7	0:60d829a0353a	1343	((FLAG) == ETH_DMATXDESC_ES) \|\| \
tushki7	0:60d829a0353a	1344	((FLAG) == ETH_DMATXDESC_JT) \|\| \
tushki7	0:60d829a0353a	1345	((FLAG) == ETH_DMATXDESC_FF) \|\| \
tushki7	0:60d829a0353a	1346	((FLAG) == ETH_DMATXDESC_PCE) \|\| \
tushki7	0:60d829a0353a	1347	((FLAG) == ETH_DMATXDESC_LCA) \|\| \
tushki7	0:60d829a0353a	1348	((FLAG) == ETH_DMATXDESC_NC) \|\| \
tushki7	0:60d829a0353a	1349	((FLAG) == ETH_DMATXDESC_LCO) \|\| \
tushki7	0:60d829a0353a	1350	((FLAG) == ETH_DMATXDESC_EC) \|\| \
tushki7	0:60d829a0353a	1351	((FLAG) == ETH_DMATXDESC_VF) \|\| \
tushki7	0:60d829a0353a	1352	((FLAG) == ETH_DMATXDESC_CC) \|\| \
tushki7	0:60d829a0353a	1353	((FLAG) == ETH_DMATXDESC_ED) \|\| \
tushki7	0:60d829a0353a	1354	((FLAG) == ETH_DMATXDESC_UF) \|\| \
tushki7	0:60d829a0353a	1355	((FLAG) == ETH_DMATXDESC_DB))
tushki7	0:60d829a0353a	1356
tushki7	0:60d829a0353a	1357	/**
tushki7	0:60d829a0353a	1358	* @}
tushki7	0:60d829a0353a	1359	*/
tushki7	0:60d829a0353a	1360
tushki7	0:60d829a0353a	1361	/** @defgroup ETH_DMA_Tx_descriptor_segment
tushki7	0:60d829a0353a	1362	* @{
tushki7	0:60d829a0353a	1363	*/
tushki7	0:60d829a0353a	1364	#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /!< Last Segment /
tushki7	0:60d829a0353a	1365	#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /!< First Segment /
tushki7	0:60d829a0353a	1366	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
tushki7	0:60d829a0353a	1367	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
tushki7	0:60d829a0353a	1368
tushki7	0:60d829a0353a	1369	/**
tushki7	0:60d829a0353a	1370	* @}
tushki7	0:60d829a0353a	1371	*/
tushki7	0:60d829a0353a	1372
tushki7	0:60d829a0353a	1373	/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
tushki7	0:60d829a0353a	1374	* @{
tushki7	0:60d829a0353a	1375	*/
tushki7	0:60d829a0353a	1376	#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /!< Checksum engine bypass /
tushki7	0:60d829a0353a	1377	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /!< IPv4 header checksum insertion /
tushki7	0:60d829a0353a	1378	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
tushki7	0:60d829a0353a	1379	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
tushki7	0:60d829a0353a	1380	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
tushki7	0:60d829a0353a	1381	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
tushki7	0:60d829a0353a	1382	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
tushki7	0:60d829a0353a	1383	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
tushki7	0:60d829a0353a	1384	/**
tushki7	0:60d829a0353a	1385	* @brief ETH DMA Tx Desciptor buffer size
tushki7	0:60d829a0353a	1386	*/
tushki7	0:60d829a0353a	1387	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
tushki7	0:60d829a0353a	1388
tushki7	0:60d829a0353a	1389	/**
tushki7	0:60d829a0353a	1390	* @}
tushki7	0:60d829a0353a	1391	*/
tushki7	0:60d829a0353a	1392
tushki7	0:60d829a0353a	1393	/** @defgroup ETH_DMA_Rx_descriptor_flags
tushki7	0:60d829a0353a	1394	* @{
tushki7	0:60d829a0353a	1395	*/
tushki7	0:60d829a0353a	1396	#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) \|\| \
tushki7	0:60d829a0353a	1397	((FLAG) == ETH_DMARXDESC_AFM) \|\| \
tushki7	0:60d829a0353a	1398	((FLAG) == ETH_DMARXDESC_ES) \|\| \
tushki7	0:60d829a0353a	1399	((FLAG) == ETH_DMARXDESC_DE) \|\| \
tushki7	0:60d829a0353a	1400	((FLAG) == ETH_DMARXDESC_SAF) \|\| \
tushki7	0:60d829a0353a	1401	((FLAG) == ETH_DMARXDESC_LE) \|\| \
tushki7	0:60d829a0353a	1402	((FLAG) == ETH_DMARXDESC_OE) \|\| \
tushki7	0:60d829a0353a	1403	((FLAG) == ETH_DMARXDESC_VLAN) \|\| \
tushki7	0:60d829a0353a	1404	((FLAG) == ETH_DMARXDESC_FS) \|\| \
tushki7	0:60d829a0353a	1405	((FLAG) == ETH_DMARXDESC_LS) \|\| \
tushki7	0:60d829a0353a	1406	((FLAG) == ETH_DMARXDESC_IPV4HCE) \|\| \
tushki7	0:60d829a0353a	1407	((FLAG) == ETH_DMARXDESC_LC) \|\| \
tushki7	0:60d829a0353a	1408	((FLAG) == ETH_DMARXDESC_FT) \|\| \
tushki7	0:60d829a0353a	1409	((FLAG) == ETH_DMARXDESC_RWT) \|\| \
tushki7	0:60d829a0353a	1410	((FLAG) == ETH_DMARXDESC_RE) \|\| \
tushki7	0:60d829a0353a	1411	((FLAG) == ETH_DMARXDESC_DBE) \|\| \
tushki7	0:60d829a0353a	1412	((FLAG) == ETH_DMARXDESC_CE) \|\| \
tushki7	0:60d829a0353a	1413	((FLAG) == ETH_DMARXDESC_MAMPCE))
tushki7	0:60d829a0353a	1414
tushki7	0:60d829a0353a	1415	/* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
tushki7	0:60d829a0353a	1416	#define IS_ETH_DMAPTPRXDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRXDESC_PTPV) \|\| \
tushki7	0:60d829a0353a	1417	((FLAG) == ETH_DMAPTPRXDESC_PTPFT) \|\| \
tushki7	0:60d829a0353a	1418	((FLAG) == ETH_DMAPTPRXDESC_PTPMT) \|\| \
tushki7	0:60d829a0353a	1419	((FLAG) == ETH_DMAPTPRXDESC_IPV6PR) \|\| \
tushki7	0:60d829a0353a	1420	((FLAG) == ETH_DMAPTPRXDESC_IPV4PR) \|\| \
tushki7	0:60d829a0353a	1421	((FLAG) == ETH_DMAPTPRXDESC_IPCB) \|\| \
tushki7	0:60d829a0353a	1422	((FLAG) == ETH_DMAPTPRXDESC_IPPE) \|\| \
tushki7	0:60d829a0353a	1423	((FLAG) == ETH_DMAPTPRXDESC_IPHE) \|\| \
tushki7	0:60d829a0353a	1424	((FLAG) == ETH_DMAPTPRXDESC_IPPT))
tushki7	0:60d829a0353a	1425
tushki7	0:60d829a0353a	1426	/**
tushki7	0:60d829a0353a	1427	* @}
tushki7	0:60d829a0353a	1428	*/
tushki7	0:60d829a0353a	1429
tushki7	0:60d829a0353a	1430	/** @defgroup ETH_DMA_Rx_descriptor_buffers_
tushki7	0:60d829a0353a	1431	* @{
tushki7	0:60d829a0353a	1432	*/
tushki7	0:60d829a0353a	1433	#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /!< DMA Rx Desc Buffer1 /
tushki7	0:60d829a0353a	1434	#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /!< DMA Rx Desc Buffer2 /
tushki7	0:60d829a0353a	1435	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
tushki7	0:60d829a0353a	1436	((BUFFER) == ETH_DMARXDESC_BUFFER2))
tushki7	0:60d829a0353a	1437
tushki7	0:60d829a0353a	1438
tushki7	0:60d829a0353a	1439	/* ETHERNET DMA Tx descriptors Collision Count Shift */
tushki7	0:60d829a0353a	1440	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
tushki7	0:60d829a0353a	1441
tushki7	0:60d829a0353a	1442	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
tushki7	0:60d829a0353a	1443	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
tushki7	0:60d829a0353a	1444
tushki7	0:60d829a0353a	1445	/* ETHERNET DMA Rx descriptors Frame Length Shift */
tushki7	0:60d829a0353a	1446	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
tushki7	0:60d829a0353a	1447
tushki7	0:60d829a0353a	1448	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
tushki7	0:60d829a0353a	1449	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
tushki7	0:60d829a0353a	1450
tushki7	0:60d829a0353a	1451	/* ETHERNET DMA Rx descriptors Frame length Shift */
tushki7	0:60d829a0353a	1452	#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
tushki7	0:60d829a0353a	1453
tushki7	0:60d829a0353a	1454	/**
tushki7	0:60d829a0353a	1455	* @}
tushki7	0:60d829a0353a	1456	*/
tushki7	0:60d829a0353a	1457
tushki7	0:60d829a0353a	1458	/** @defgroup ETH_PMT_Flags
tushki7	0:60d829a0353a	1459	* @{
tushki7	0:60d829a0353a	1460	*/
tushki7	0:60d829a0353a	1461	#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /!< Wake-Up Frame Filter Register Pointer Reset /
tushki7	0:60d829a0353a	1462	#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /!< Wake-Up Frame Received /
tushki7	0:60d829a0353a	1463	#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /!< Magic Packet Received /
tushki7	0:60d829a0353a	1464	#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) \|\| \
tushki7	0:60d829a0353a	1465	((FLAG) == ETH_PMT_FLAG_MPR))
tushki7	0:60d829a0353a	1466	/**
tushki7	0:60d829a0353a	1467	* @}
tushki7	0:60d829a0353a	1468	*/
tushki7	0:60d829a0353a	1469
tushki7	0:60d829a0353a	1470	/** @defgroup ETH_MMC_Tx_Interrupts
tushki7	0:60d829a0353a	1471	* @{
tushki7	0:60d829a0353a	1472	*/
tushki7	0:60d829a0353a	1473	#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /!< When Tx good frame counter reaches half the maximum value /
tushki7	0:60d829a0353a	1474	#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /!< When Tx good multi col counter reaches half the maximum value /
tushki7	0:60d829a0353a	1475	#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /!< When Tx good single col counter reaches half the maximum value /
tushki7	0:60d829a0353a	1476
tushki7	0:60d829a0353a	1477	/**
tushki7	0:60d829a0353a	1478	* @}
tushki7	0:60d829a0353a	1479	*/
tushki7	0:60d829a0353a	1480
tushki7	0:60d829a0353a	1481	/** @defgroup ETH_MMC_Rx_Interrupts
tushki7	0:60d829a0353a	1482	* @{
tushki7	0:60d829a0353a	1483	*/
tushki7	0:60d829a0353a	1484	#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /!< When Rx good unicast frames counter reaches half the maximum value /
tushki7	0:60d829a0353a	1485	#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /!< When Rx alignment error counter reaches half the maximum value /
tushki7	0:60d829a0353a	1486	#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /!< When Rx crc error counter reaches half the maximum value /
tushki7	0:60d829a0353a	1487	#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) \|\| (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
tushki7	0:60d829a0353a	1488	((IT) != 0x00))
tushki7	0:60d829a0353a	1489	#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) \|\| ((IT) == ETH_MMC_IT_TGFMSC) \|\| \
tushki7	0:60d829a0353a	1490	((IT) == ETH_MMC_IT_TGFSC) \|\| ((IT) == ETH_MMC_IT_RGUF) \|\| \
tushki7	0:60d829a0353a	1491	((IT) == ETH_MMC_IT_RFAE) \|\| ((IT) == ETH_MMC_IT_RFCE))
tushki7	0:60d829a0353a	1492	/**
tushki7	0:60d829a0353a	1493	* @}
tushki7	0:60d829a0353a	1494	*/
tushki7	0:60d829a0353a	1495
tushki7	0:60d829a0353a	1496	/** @defgroup ETH_MMC_Registers
tushki7	0:60d829a0353a	1497	* @{
tushki7	0:60d829a0353a	1498	*/
tushki7	0:60d829a0353a	1499	#define ETH_MMCCR ((uint32_t)0x00000100) /!< MMC CR register /
tushki7	0:60d829a0353a	1500	#define ETH_MMCRIR ((uint32_t)0x00000104) /!< MMC RIR register /
tushki7	0:60d829a0353a	1501	#define ETH_MMCTIR ((uint32_t)0x00000108) /!< MMC TIR register /
tushki7	0:60d829a0353a	1502	#define ETH_MMCRIMR ((uint32_t)0x0000010C) /!< MMC RIMR register /
tushki7	0:60d829a0353a	1503	#define ETH_MMCTIMR ((uint32_t)0x00000110) /!< MMC TIMR register /
tushki7	0:60d829a0353a	1504	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /!< MMC TGFSCCR register /
tushki7	0:60d829a0353a	1505	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /!< MMC TGFMSCCR register /
tushki7	0:60d829a0353a	1506	#define ETH_MMCTGFCR ((uint32_t)0x00000168) /!< MMC TGFCR register /
tushki7	0:60d829a0353a	1507	#define ETH_MMCRFCECR ((uint32_t)0x00000194) /!< MMC RFCECR register /
tushki7	0:60d829a0353a	1508	#define ETH_MMCRFAECR ((uint32_t)0x00000198) /!< MMC RFAECR register /
tushki7	0:60d829a0353a	1509	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /!< MMC RGUFCR register /
tushki7	0:60d829a0353a	1510
tushki7	0:60d829a0353a	1511	/**
tushki7	0:60d829a0353a	1512	* @brief ETH MMC registers
tushki7	0:60d829a0353a	1513	*/
tushki7	0:60d829a0353a	1514	#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) \|\| ((REG) == ETH_MMCRIR) \|\| \
tushki7	0:60d829a0353a	1515	((REG) == ETH_MMCTIR) \|\| ((REG) == ETH_MMCRIMR) \|\| \
tushki7	0:60d829a0353a	1516	((REG) == ETH_MMCTIMR) \|\| ((REG) == ETH_MMCTGFSCCR) \|\| \
tushki7	0:60d829a0353a	1517	((REG) == ETH_MMCTGFMSCCR) \|\| ((REG) == ETH_MMCTGFCR) \|\| \
tushki7	0:60d829a0353a	1518	((REG) == ETH_MMCRFCECR) \|\| ((REG) == ETH_MMCRFAECR) \|\| \
tushki7	0:60d829a0353a	1519	((REG) == ETH_MMCRGUFCR))
tushki7	0:60d829a0353a	1520	/**
tushki7	0:60d829a0353a	1521	* @}
tushki7	0:60d829a0353a	1522	*/
tushki7	0:60d829a0353a	1523
tushki7	0:60d829a0353a	1524	/** @defgroup ETH_MAC_Flags
tushki7	0:60d829a0353a	1525	* @{
tushki7	0:60d829a0353a	1526	*/
tushki7	0:60d829a0353a	1527	#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /!< Time stamp trigger flag (on MAC) /
tushki7	0:60d829a0353a	1528	#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /!< MMC transmit flag /
tushki7	0:60d829a0353a	1529	#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /!< MMC receive flag /
tushki7	0:60d829a0353a	1530	#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /!< MMC flag (on MAC) /
tushki7	0:60d829a0353a	1531	#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /!< PMT flag (on MAC) /
tushki7	0:60d829a0353a	1532	#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) \|\| ((FLAG) == ETH_MAC_FLAG_MMCT) \|\| \
tushki7	0:60d829a0353a	1533	((FLAG) == ETH_MAC_FLAG_MMCR) \|\| ((FLAG) == ETH_MAC_FLAG_MMC) \|\| \
tushki7	0:60d829a0353a	1534	((FLAG) == ETH_MAC_FLAG_PMT))
tushki7	0:60d829a0353a	1535	/**
tushki7	0:60d829a0353a	1536	* @}
tushki7	0:60d829a0353a	1537	*/
tushki7	0:60d829a0353a	1538
tushki7	0:60d829a0353a	1539	/** @defgroup ETH_DMA_Flags
tushki7	0:60d829a0353a	1540	* @{
tushki7	0:60d829a0353a	1541	*/
tushki7	0:60d829a0353a	1542	#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
tushki7	0:60d829a0353a	1543	#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
tushki7	0:60d829a0353a	1544	#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
tushki7	0:60d829a0353a	1545	#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /!< Error bits 0-Rx DMA, 1-Tx DMA /
tushki7	0:60d829a0353a	1546	#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /!< Error bits 0-write trnsf, 1-read transfr /
tushki7	0:60d829a0353a	1547	#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /!< Error bits 0-data buffer, 1-desc. access /
tushki7	0:60d829a0353a	1548	#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary flag /
tushki7	0:60d829a0353a	1549	#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary flag /
tushki7	0:60d829a0353a	1550	#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /!< Early receive flag /
tushki7	0:60d829a0353a	1551	#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /!< Fatal bus error flag /
tushki7	0:60d829a0353a	1552	#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /!< Early transmit flag /
tushki7	0:60d829a0353a	1553	#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout flag /
tushki7	0:60d829a0353a	1554	#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /!< Receive process stopped flag /
tushki7	0:60d829a0353a	1555	#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable flag /
tushki7	0:60d829a0353a	1556	#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /!< Receive flag /
tushki7	0:60d829a0353a	1557	#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /!< Underflow flag /
tushki7	0:60d829a0353a	1558	#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /!< Overflow flag /
tushki7	0:60d829a0353a	1559	#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout flag /
tushki7	0:60d829a0353a	1560	#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable flag /
tushki7	0:60d829a0353a	1561	#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /!< Transmit process stopped flag /
tushki7	0:60d829a0353a	1562	#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /!< Transmit flag /
tushki7	0:60d829a0353a	1563
tushki7	0:60d829a0353a	1564	#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
tushki7	0:60d829a0353a	1565	#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) \|\| ((FLAG) == ETH_DMA_FLAG_PMT) \|\| \
tushki7	0:60d829a0353a	1566	((FLAG) == ETH_DMA_FLAG_MMC) \|\| ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) \|\| \
tushki7	0:60d829a0353a	1567	((FLAG) == ETH_DMA_FLAG_READWRITEERROR) \|\| ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) \|\| \
tushki7	0:60d829a0353a	1568	((FLAG) == ETH_DMA_FLAG_NIS) \|\| ((FLAG) == ETH_DMA_FLAG_AIS) \|\| \
tushki7	0:60d829a0353a	1569	((FLAG) == ETH_DMA_FLAG_ER) \|\| ((FLAG) == ETH_DMA_FLAG_FBE) \|\| \
tushki7	0:60d829a0353a	1570	((FLAG) == ETH_DMA_FLAG_ET) \|\| ((FLAG) == ETH_DMA_FLAG_RWT) \|\| \
tushki7	0:60d829a0353a	1571	((FLAG) == ETH_DMA_FLAG_RPS) \|\| ((FLAG) == ETH_DMA_FLAG_RBU) \|\| \
tushki7	0:60d829a0353a	1572	((FLAG) == ETH_DMA_FLAG_R) \|\| ((FLAG) == ETH_DMA_FLAG_TU) \|\| \
tushki7	0:60d829a0353a	1573	((FLAG) == ETH_DMA_FLAG_RO) \|\| ((FLAG) == ETH_DMA_FLAG_TJT) \|\| \
tushki7	0:60d829a0353a	1574	((FLAG) == ETH_DMA_FLAG_TBU) \|\| ((FLAG) == ETH_DMA_FLAG_TPS) \|\| \
tushki7	0:60d829a0353a	1575	((FLAG) == ETH_DMA_FLAG_T))
tushki7	0:60d829a0353a	1576	/**
tushki7	0:60d829a0353a	1577	* @}
tushki7	0:60d829a0353a	1578	*/
tushki7	0:60d829a0353a	1579
tushki7	0:60d829a0353a	1580	/** @defgroup ETH_MAC_Interrupts
tushki7	0:60d829a0353a	1581	* @{
tushki7	0:60d829a0353a	1582	*/
tushki7	0:60d829a0353a	1583	#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /!< Time stamp trigger interrupt (on MAC) /
tushki7	0:60d829a0353a	1584	#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /!< MMC transmit interrupt /
tushki7	0:60d829a0353a	1585	#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /!< MMC receive interrupt /
tushki7	0:60d829a0353a	1586	#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /!< MMC interrupt (on MAC) /
tushki7	0:60d829a0353a	1587	#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /!< PMT interrupt (on MAC) /
tushki7	0:60d829a0353a	1588	#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
tushki7	0:60d829a0353a	1589	#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) \|\| ((IT) == ETH_MAC_IT_MMCT) \|\| \
tushki7	0:60d829a0353a	1590	((IT) == ETH_MAC_IT_MMCR) \|\| ((IT) == ETH_MAC_IT_MMC) \|\| \
tushki7	0:60d829a0353a	1591	((IT) == ETH_MAC_IT_PMT))
tushki7	0:60d829a0353a	1592	/**
tushki7	0:60d829a0353a	1593	* @}
tushki7	0:60d829a0353a	1594	*/
tushki7	0:60d829a0353a	1595
tushki7	0:60d829a0353a	1596	/** @defgroup ETH_DMA_Interrupts
tushki7	0:60d829a0353a	1597	* @{
tushki7	0:60d829a0353a	1598	*/
tushki7	0:60d829a0353a	1599	#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
tushki7	0:60d829a0353a	1600	#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
tushki7	0:60d829a0353a	1601	#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
tushki7	0:60d829a0353a	1602	#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary /
tushki7	0:60d829a0353a	1603	#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary /
tushki7	0:60d829a0353a	1604	#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /!< Early receive interrupt /
tushki7	0:60d829a0353a	1605	#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /!< Fatal bus error interrupt /
tushki7	0:60d829a0353a	1606	#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /!< Early transmit interrupt /
tushki7	0:60d829a0353a	1607	#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout interrupt /
tushki7	0:60d829a0353a	1608	#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /!< Receive process stopped interrupt /
tushki7	0:60d829a0353a	1609	#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable interrupt /
tushki7	0:60d829a0353a	1610	#define ETH_DMA_IT_R ((uint32_t)0x00000040) /!< Receive interrupt /
tushki7	0:60d829a0353a	1611	#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /!< Underflow interrupt /
tushki7	0:60d829a0353a	1612	#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /!< Overflow interrupt /
tushki7	0:60d829a0353a	1613	#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout interrupt /
tushki7	0:60d829a0353a	1614	#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable interrupt /
tushki7	0:60d829a0353a	1615	#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /!< Transmit process stopped interrupt /
tushki7	0:60d829a0353a	1616	#define ETH_DMA_IT_T ((uint32_t)0x00000001) /!< Transmit interrupt /
tushki7	0:60d829a0353a	1617
tushki7	0:60d829a0353a	1618	#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
tushki7	0:60d829a0353a	1619	#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) \|\| ((IT) == ETH_DMA_IT_PMT) \|\| \
tushki7	0:60d829a0353a	1620	((IT) == ETH_DMA_IT_MMC) \|\| ((IT) == ETH_DMA_IT_NIS) \|\| \
tushki7	0:60d829a0353a	1621	((IT) == ETH_DMA_IT_AIS) \|\| ((IT) == ETH_DMA_IT_ER) \|\| \
tushki7	0:60d829a0353a	1622	((IT) == ETH_DMA_IT_FBE) \|\| ((IT) == ETH_DMA_IT_ET) \|\| \
tushki7	0:60d829a0353a	1623	((IT) == ETH_DMA_IT_RWT) \|\| ((IT) == ETH_DMA_IT_RPS) \|\| \
tushki7	0:60d829a0353a	1624	((IT) == ETH_DMA_IT_RBU) \|\| ((IT) == ETH_DMA_IT_R) \|\| \
tushki7	0:60d829a0353a	1625	((IT) == ETH_DMA_IT_TU) \|\| ((IT) == ETH_DMA_IT_RO) \|\| \
tushki7	0:60d829a0353a	1626	((IT) == ETH_DMA_IT_TJT) \|\| ((IT) == ETH_DMA_IT_TBU) \|\| \
tushki7	0:60d829a0353a	1627	((IT) == ETH_DMA_IT_TPS) \|\| ((IT) == ETH_DMA_IT_T))
tushki7	0:60d829a0353a	1628
tushki7	0:60d829a0353a	1629	/**
tushki7	0:60d829a0353a	1630	* @}
tushki7	0:60d829a0353a	1631	*/
tushki7	0:60d829a0353a	1632
tushki7	0:60d829a0353a	1633	/** @defgroup ETH_DMA_transmit_process_state_
tushki7	0:60d829a0353a	1634	* @{
tushki7	0:60d829a0353a	1635	*/
tushki7	0:60d829a0353a	1636	#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Tx Command issued /
tushki7	0:60d829a0353a	1637	#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /!< Running - fetching the Tx descriptor /
tushki7	0:60d829a0353a	1638	#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /!< Running - waiting for status /
tushki7	0:60d829a0353a	1639	#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /!< Running - reading the data from host memory /
tushki7	0:60d829a0353a	1640	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /!< Suspended - Tx Descriptor unavailable /
tushki7	0:60d829a0353a	1641	#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /!< Running - closing Rx descriptor /
tushki7	0:60d829a0353a	1642
tushki7	0:60d829a0353a	1643	/**
tushki7	0:60d829a0353a	1644	* @}
tushki7	0:60d829a0353a	1645	*/
tushki7	0:60d829a0353a	1646
tushki7	0:60d829a0353a	1647
tushki7	0:60d829a0353a	1648	/** @defgroup ETH_DMA_receive_process_state_
tushki7	0:60d829a0353a	1649	* @{
tushki7	0:60d829a0353a	1650	*/
tushki7	0:60d829a0353a	1651	#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Rx Command issued /
tushki7	0:60d829a0353a	1652	#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /!< Running - fetching the Rx descriptor /
tushki7	0:60d829a0353a	1653	#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /!< Running - waiting for packet /
tushki7	0:60d829a0353a	1654	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /!< Suspended - Rx Descriptor unavailable /
tushki7	0:60d829a0353a	1655	#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /!< Running - closing descriptor /
tushki7	0:60d829a0353a	1656	#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /!< Running - queuing the receive frame into host memory /
tushki7	0:60d829a0353a	1657
tushki7	0:60d829a0353a	1658	/**
tushki7	0:60d829a0353a	1659	* @}
tushki7	0:60d829a0353a	1660	*/
tushki7	0:60d829a0353a	1661
tushki7	0:60d829a0353a	1662	/** @defgroup ETH_DMA_overflow_
tushki7	0:60d829a0353a	1663	* @{
tushki7	0:60d829a0353a	1664	*/
tushki7	0:60d829a0353a	1665	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /!< Overflow bit for FIFO overflow counter /
tushki7	0:60d829a0353a	1666	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /!< Overflow bit for missed frame counter /
tushki7	0:60d829a0353a	1667	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
tushki7	0:60d829a0353a	1668	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
tushki7	0:60d829a0353a	1669	/**
tushki7	0:60d829a0353a	1670	* @}
tushki7	0:60d829a0353a	1671	*/
tushki7	0:60d829a0353a	1672
tushki7	0:60d829a0353a	1673	/* ETHERNET MAC address offsets */
tushki7	0:60d829a0353a	1674	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
tushki7	0:60d829a0353a	1675	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
tushki7	0:60d829a0353a	1676
tushki7	0:60d829a0353a	1677	/* ETHERNET MACMIIAR register Mask */
tushki7	0:60d829a0353a	1678	#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
tushki7	0:60d829a0353a	1679
tushki7	0:60d829a0353a	1680	/* ETHERNET MACCR register Mask */
tushki7	0:60d829a0353a	1681	#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
tushki7	0:60d829a0353a	1682
tushki7	0:60d829a0353a	1683	/* ETHERNET MACFCR register Mask */
tushki7	0:60d829a0353a	1684	#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
tushki7	0:60d829a0353a	1685
tushki7	0:60d829a0353a	1686
tushki7	0:60d829a0353a	1687	/* ETHERNET DMAOMR register Mask */
tushki7	0:60d829a0353a	1688	#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
tushki7	0:60d829a0353a	1689
tushki7	0:60d829a0353a	1690
tushki7	0:60d829a0353a	1691	/* ETHERNET Remote Wake-up frame register length */
tushki7	0:60d829a0353a	1692	#define ETH_WAKEUP_REGISTER_LENGTH 8
tushki7	0:60d829a0353a	1693
tushki7	0:60d829a0353a	1694	/* ETHERNET Missed frames counter Shift */
tushki7	0:60d829a0353a	1695	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
tushki7	0:60d829a0353a	1696
tushki7	0:60d829a0353a	1697	/**
tushki7	0:60d829a0353a	1698	* @}
tushki7	0:60d829a0353a	1699	*/
tushki7	0:60d829a0353a	1700
tushki7	0:60d829a0353a	1701	/* Exported macro ------------------------------------------------------------*/
tushki7	0:60d829a0353a	1702
tushki7	0:60d829a0353a	1703	/** @brief Reset ETH handle state
tushki7	0:60d829a0353a	1704	* @param __HANDLE__: specifies the ETH handle.
tushki7	0:60d829a0353a	1705	* @retval None
tushki7	0:60d829a0353a	1706	*/
tushki7	0:60d829a0353a	1707	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
tushki7	0:60d829a0353a	1708
tushki7	0:60d829a0353a	1709	/**
tushki7	0:60d829a0353a	1710	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
tushki7	0:60d829a0353a	1711	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1712	* @param __FLAG__: specifies the flag to check.
tushki7	0:60d829a0353a	1713	* @retval the ETH_DMATxDescFlag (SET or RESET).
tushki7	0:60d829a0353a	1714	*/
tushki7	0:60d829a0353a	1715	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
tushki7	0:60d829a0353a	1716
tushki7	0:60d829a0353a	1717	/**
tushki7	0:60d829a0353a	1718	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
tushki7	0:60d829a0353a	1719	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1720	* @param __FLAG__: specifies the flag to check.
tushki7	0:60d829a0353a	1721	* @retval the ETH_DMATxDescFlag (SET or RESET).
tushki7	0:60d829a0353a	1722	*/
tushki7	0:60d829a0353a	1723	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
tushki7	0:60d829a0353a	1724
tushki7	0:60d829a0353a	1725	/**
tushki7	0:60d829a0353a	1726	* @brief Enables the specified DMA Rx Desc receive interrupt.
tushki7	0:60d829a0353a	1727	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1728	* @retval None
tushki7	0:60d829a0353a	1729	*/
tushki7	0:60d829a0353a	1730	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
tushki7	0:60d829a0353a	1731
tushki7	0:60d829a0353a	1732	/**
tushki7	0:60d829a0353a	1733	* @brief Disables the specified DMA Rx Desc receive interrupt.
tushki7	0:60d829a0353a	1734	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1735	* @retval None
tushki7	0:60d829a0353a	1736	*/
tushki7	0:60d829a0353a	1737	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
tushki7	0:60d829a0353a	1738
tushki7	0:60d829a0353a	1739	/**
tushki7	0:60d829a0353a	1740	* @brief Set the specified DMA Rx Desc Own bit.
tushki7	0:60d829a0353a	1741	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1742	* @retval None
tushki7	0:60d829a0353a	1743	*/
tushki7	0:60d829a0353a	1744	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
tushki7	0:60d829a0353a	1745
tushki7	0:60d829a0353a	1746	/**
tushki7	0:60d829a0353a	1747	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
tushki7	0:60d829a0353a	1748	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1749	* @retval The Transmit descriptor collision counter value.
tushki7	0:60d829a0353a	1750	*/
tushki7	0:60d829a0353a	1751	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
tushki7	0:60d829a0353a	1752
tushki7	0:60d829a0353a	1753	/**
tushki7	0:60d829a0353a	1754	* @brief Set the specified DMA Tx Desc Own bit.
tushki7	0:60d829a0353a	1755	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1756	* @retval None
tushki7	0:60d829a0353a	1757	*/
tushki7	0:60d829a0353a	1758	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
tushki7	0:60d829a0353a	1759
tushki7	0:60d829a0353a	1760	/**
tushki7	0:60d829a0353a	1761	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
tushki7	0:60d829a0353a	1762	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1763	* @retval None
tushki7	0:60d829a0353a	1764	*/
tushki7	0:60d829a0353a	1765	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
tushki7	0:60d829a0353a	1766
tushki7	0:60d829a0353a	1767	/**
tushki7	0:60d829a0353a	1768	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
tushki7	0:60d829a0353a	1769	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1770	* @retval None
tushki7	0:60d829a0353a	1771	*/
tushki7	0:60d829a0353a	1772	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
tushki7	0:60d829a0353a	1773
tushki7	0:60d829a0353a	1774	/**
tushki7	0:60d829a0353a	1775	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
tushki7	0:60d829a0353a	1776	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1777	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
tushki7	0:60d829a0353a	1778	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	1779	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
tushki7	0:60d829a0353a	1780	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
tushki7	0:60d829a0353a	1781	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
tushki7	0:60d829a0353a	1782	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
tushki7	0:60d829a0353a	1783	* @retval None
tushki7	0:60d829a0353a	1784	*/
tushki7	0:60d829a0353a	1785	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
tushki7	0:60d829a0353a	1786
tushki7	0:60d829a0353a	1787	/**
tushki7	0:60d829a0353a	1788	* @brief Enables the DMA Tx Desc CRC.
tushki7	0:60d829a0353a	1789	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1790	* @retval None
tushki7	0:60d829a0353a	1791	*/
tushki7	0:60d829a0353a	1792	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
tushki7	0:60d829a0353a	1793
tushki7	0:60d829a0353a	1794	/**
tushki7	0:60d829a0353a	1795	* @brief Disables the DMA Tx Desc CRC.
tushki7	0:60d829a0353a	1796	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1797	* @retval None
tushki7	0:60d829a0353a	1798	*/
tushki7	0:60d829a0353a	1799	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
tushki7	0:60d829a0353a	1800
tushki7	0:60d829a0353a	1801	/**
tushki7	0:60d829a0353a	1802	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
tushki7	0:60d829a0353a	1803	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1804	* @retval None
tushki7	0:60d829a0353a	1805	*/
tushki7	0:60d829a0353a	1806	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
tushki7	0:60d829a0353a	1807
tushki7	0:60d829a0353a	1808	/**
tushki7	0:60d829a0353a	1809	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
tushki7	0:60d829a0353a	1810	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1811	* @retval None
tushki7	0:60d829a0353a	1812	*/
tushki7	0:60d829a0353a	1813	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
tushki7	0:60d829a0353a	1814
tushki7	0:60d829a0353a	1815	/**
tushki7	0:60d829a0353a	1816	* @brief Enables the specified ETHERNET MAC interrupts.
tushki7	0:60d829a0353a	1817	* @param __HANDLE__ : ETH Handle
tushki7	0:60d829a0353a	1818	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
tushki7	0:60d829a0353a	1819	* enabled or disabled.
tushki7	0:60d829a0353a	1820	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1821	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
tushki7	0:60d829a0353a	1822	* @arg ETH_MAC_IT_PMT : PMT interrupt
tushki7	0:60d829a0353a	1823	* @retval None
tushki7	0:60d829a0353a	1824	*/
tushki7	0:60d829a0353a	1825	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
tushki7	0:60d829a0353a	1826
tushki7	0:60d829a0353a	1827	/**
tushki7	0:60d829a0353a	1828	* @brief Disables the specified ETHERNET MAC interrupts.
tushki7	0:60d829a0353a	1829	* @param __HANDLE__ : ETH Handle
tushki7	0:60d829a0353a	1830	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
tushki7	0:60d829a0353a	1831	* enabled or disabled.
tushki7	0:60d829a0353a	1832	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1833	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
tushki7	0:60d829a0353a	1834	* @arg ETH_MAC_IT_PMT : PMT interrupt
tushki7	0:60d829a0353a	1835	* @retval None
tushki7	0:60d829a0353a	1836	*/
tushki7	0:60d829a0353a	1837	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
tushki7	0:60d829a0353a	1838
tushki7	0:60d829a0353a	1839	/**
tushki7	0:60d829a0353a	1840	* @brief Initiate a Pause Control Frame (Full-duplex only).
tushki7	0:60d829a0353a	1841	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1842	* @retval None
tushki7	0:60d829a0353a	1843	*/
tushki7	0:60d829a0353a	1844	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
tushki7	0:60d829a0353a	1845
tushki7	0:60d829a0353a	1846	/**
tushki7	0:60d829a0353a	1847	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
tushki7	0:60d829a0353a	1848	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1849	* @retval The new state of flow control busy status bit (SET or RESET).
tushki7	0:60d829a0353a	1850	*/
tushki7	0:60d829a0353a	1851	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
tushki7	0:60d829a0353a	1852
tushki7	0:60d829a0353a	1853	/**
tushki7	0:60d829a0353a	1854	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
tushki7	0:60d829a0353a	1855	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1856	* @retval None
tushki7	0:60d829a0353a	1857	*/
tushki7	0:60d829a0353a	1858	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
tushki7	0:60d829a0353a	1859
tushki7	0:60d829a0353a	1860	/**
tushki7	0:60d829a0353a	1861	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
tushki7	0:60d829a0353a	1862	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1863	* @retval None
tushki7	0:60d829a0353a	1864	*/
tushki7	0:60d829a0353a	1865	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
tushki7	0:60d829a0353a	1866
tushki7	0:60d829a0353a	1867	/**
tushki7	0:60d829a0353a	1868	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
tushki7	0:60d829a0353a	1869	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1870	* @param __FLAG__: specifies the flag to check.
tushki7	0:60d829a0353a	1871	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	1872	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
tushki7	0:60d829a0353a	1873	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
tushki7	0:60d829a0353a	1874	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
tushki7	0:60d829a0353a	1875	* @arg ETH_MAC_FLAG_MMC : MMC flag
tushki7	0:60d829a0353a	1876	* @arg ETH_MAC_FLAG_PMT : PMT flag
tushki7	0:60d829a0353a	1877	* @retval The state of ETHERNET MAC flag.
tushki7	0:60d829a0353a	1878	*/
tushki7	0:60d829a0353a	1879	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
tushki7	0:60d829a0353a	1880
tushki7	0:60d829a0353a	1881	/**
tushki7	0:60d829a0353a	1882	* @brief Enables the specified ETHERNET DMA interrupts.
tushki7	0:60d829a0353a	1883	* @param __HANDLE__ : ETH Handle
tushki7	0:60d829a0353a	1884	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
tushki7	0:60d829a0353a	1885	* enabled @defgroup ETH_DMA_Interrupts
tushki7	0:60d829a0353a	1886	* @retval None
tushki7	0:60d829a0353a	1887	*/
tushki7	0:60d829a0353a	1888	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
tushki7	0:60d829a0353a	1889
tushki7	0:60d829a0353a	1890	/**
tushki7	0:60d829a0353a	1891	* @brief Disables the specified ETHERNET DMA interrupts.
tushki7	0:60d829a0353a	1892	* @param __HANDLE__ : ETH Handle
tushki7	0:60d829a0353a	1893	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
tushki7	0:60d829a0353a	1894	* disabled. @defgroup ETH_DMA_Interrupts
tushki7	0:60d829a0353a	1895	* @retval None
tushki7	0:60d829a0353a	1896	*/
tushki7	0:60d829a0353a	1897	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
tushki7	0:60d829a0353a	1898
tushki7	0:60d829a0353a	1899	/**
tushki7	0:60d829a0353a	1900	* @brief Clears the ETHERNET DMA IT pending bit.
tushki7	0:60d829a0353a	1901	* @param __HANDLE__ : ETH Handle
tushki7	0:60d829a0353a	1902	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @defgroup ETH_DMA_Interrupts
tushki7	0:60d829a0353a	1903	* @retval None
tushki7	0:60d829a0353a	1904	*/
tushki7	0:60d829a0353a	1905	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
tushki7	0:60d829a0353a	1906
tushki7	0:60d829a0353a	1907	/**
tushki7	0:60d829a0353a	1908	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
tushki7	0:60d829a0353a	1909	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1910	* @param __FLAG__: specifies the flag to check. @defgroup ETH_DMA_Flags
tushki7	0:60d829a0353a	1911	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
tushki7	0:60d829a0353a	1912	*/
tushki7	0:60d829a0353a	1913	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
tushki7	0:60d829a0353a	1914
tushki7	0:60d829a0353a	1915	/**
tushki7	0:60d829a0353a	1916	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
tushki7	0:60d829a0353a	1917	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1918	* @param __FLAG__: specifies the flag to clear. @defgroup ETH_DMA_Flags
tushki7	0:60d829a0353a	1919	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
tushki7	0:60d829a0353a	1920	*/
tushki7	0:60d829a0353a	1921	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
tushki7	0:60d829a0353a	1922
tushki7	0:60d829a0353a	1923	/**
tushki7	0:60d829a0353a	1924	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
tushki7	0:60d829a0353a	1925	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1926	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
tushki7	0:60d829a0353a	1927	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	1928	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
tushki7	0:60d829a0353a	1929	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
tushki7	0:60d829a0353a	1930	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
tushki7	0:60d829a0353a	1931	*/
tushki7	0:60d829a0353a	1932	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
tushki7	0:60d829a0353a	1933
tushki7	0:60d829a0353a	1934	/**
tushki7	0:60d829a0353a	1935	* @brief Set the DMA Receive status watchdog timer register value
tushki7	0:60d829a0353a	1936	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1937	* @param __VALUE__: DMA Receive status watchdog timer register value
tushki7	0:60d829a0353a	1938	* @retval None
tushki7	0:60d829a0353a	1939	*/
tushki7	0:60d829a0353a	1940	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
tushki7	0:60d829a0353a	1941
tushki7	0:60d829a0353a	1942	/**
tushki7	0:60d829a0353a	1943	* @brief Enables any unicast packet filtered by the MAC address
tushki7	0:60d829a0353a	1944	* recognition to be a wake-up frame.
tushki7	0:60d829a0353a	1945	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	1946	* @retval None
tushki7	0:60d829a0353a	1947	*/
tushki7	0:60d829a0353a	1948	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
tushki7	0:60d829a0353a	1949
tushki7	0:60d829a0353a	1950	/**
tushki7	0:60d829a0353a	1951	* @brief Disables any unicast packet filtered by the MAC address
tushki7	0:60d829a0353a	1952	* recognition to be a wake-up frame.
tushki7	0:60d829a0353a	1953	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	1954	* @retval None
tushki7	0:60d829a0353a	1955	*/
tushki7	0:60d829a0353a	1956	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
tushki7	0:60d829a0353a	1957
tushki7	0:60d829a0353a	1958	/**
tushki7	0:60d829a0353a	1959	* @brief Enables the MAC Wake-Up Frame Detection.
tushki7	0:60d829a0353a	1960	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	1961	* @retval None
tushki7	0:60d829a0353a	1962	*/
tushki7	0:60d829a0353a	1963	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
tushki7	0:60d829a0353a	1964
tushki7	0:60d829a0353a	1965	/**
tushki7	0:60d829a0353a	1966	* @brief Disables the MAC Wake-Up Frame Detection.
tushki7	0:60d829a0353a	1967	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	1968	* @retval None
tushki7	0:60d829a0353a	1969	*/
tushki7	0:60d829a0353a	1970	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
tushki7	0:60d829a0353a	1971
tushki7	0:60d829a0353a	1972	/**
tushki7	0:60d829a0353a	1973	* @brief Enables the MAC Magic Packet Detection.
tushki7	0:60d829a0353a	1974	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	1975	* @retval None
tushki7	0:60d829a0353a	1976	*/
tushki7	0:60d829a0353a	1977	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
tushki7	0:60d829a0353a	1978
tushki7	0:60d829a0353a	1979	/**
tushki7	0:60d829a0353a	1980	* @brief Disables the MAC Magic Packet Detection.
tushki7	0:60d829a0353a	1981	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	1982	* @retval None
tushki7	0:60d829a0353a	1983	*/
tushki7	0:60d829a0353a	1984	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
tushki7	0:60d829a0353a	1985
tushki7	0:60d829a0353a	1986	/**
tushki7	0:60d829a0353a	1987	* @brief Enables the MAC Power Down.
tushki7	0:60d829a0353a	1988	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1989	* @retval None
tushki7	0:60d829a0353a	1990	*/
tushki7	0:60d829a0353a	1991	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
tushki7	0:60d829a0353a	1992
tushki7	0:60d829a0353a	1993	/**
tushki7	0:60d829a0353a	1994	* @brief Disables the MAC Power Down.
tushki7	0:60d829a0353a	1995	* @param __HANDLE__: ETH Handle
tushki7	0:60d829a0353a	1996	* @retval None
tushki7	0:60d829a0353a	1997	*/
tushki7	0:60d829a0353a	1998	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
tushki7	0:60d829a0353a	1999
tushki7	0:60d829a0353a	2000	/**
tushki7	0:60d829a0353a	2001	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
tushki7	0:60d829a0353a	2002	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2003	* @param __FLAG__: specifies the flag to check.
tushki7	0:60d829a0353a	2004	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	2005	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
tushki7	0:60d829a0353a	2006	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
tushki7	0:60d829a0353a	2007	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
tushki7	0:60d829a0353a	2008	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
tushki7	0:60d829a0353a	2009	*/
tushki7	0:60d829a0353a	2010	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
tushki7	0:60d829a0353a	2011
tushki7	0:60d829a0353a	2012	/**
tushki7	0:60d829a0353a	2013	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
tushki7	0:60d829a0353a	2014	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2015	* @retval None
tushki7	0:60d829a0353a	2016	*/
tushki7	0:60d829a0353a	2017	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
tushki7	0:60d829a0353a	2018
tushki7	0:60d829a0353a	2019	/**
tushki7	0:60d829a0353a	2020	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
tushki7	0:60d829a0353a	2021	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2022	* @retval None
tushki7	0:60d829a0353a	2023	*/
tushki7	0:60d829a0353a	2024	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
tushki7	0:60d829a0353a	2025	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
tushki7	0:60d829a0353a	2026
tushki7	0:60d829a0353a	2027	/**
tushki7	0:60d829a0353a	2028	* @brief Enables the MMC Counter Freeze.
tushki7	0:60d829a0353a	2029	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2030	* @retval None
tushki7	0:60d829a0353a	2031	*/
tushki7	0:60d829a0353a	2032	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
tushki7	0:60d829a0353a	2033
tushki7	0:60d829a0353a	2034	/**
tushki7	0:60d829a0353a	2035	* @brief Disables the MMC Counter Freeze.
tushki7	0:60d829a0353a	2036	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2037	* @retval None
tushki7	0:60d829a0353a	2038	*/
tushki7	0:60d829a0353a	2039	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
tushki7	0:60d829a0353a	2040
tushki7	0:60d829a0353a	2041	/**
tushki7	0:60d829a0353a	2042	* @brief Enables the MMC Reset On Read.
tushki7	0:60d829a0353a	2043	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2044	* @retval None
tushki7	0:60d829a0353a	2045	*/
tushki7	0:60d829a0353a	2046	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
tushki7	0:60d829a0353a	2047
tushki7	0:60d829a0353a	2048	/**
tushki7	0:60d829a0353a	2049	* @brief Disables the MMC Reset On Read.
tushki7	0:60d829a0353a	2050	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2051	* @retval None
tushki7	0:60d829a0353a	2052	*/
tushki7	0:60d829a0353a	2053	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
tushki7	0:60d829a0353a	2054
tushki7	0:60d829a0353a	2055	/**
tushki7	0:60d829a0353a	2056	* @brief Enables the MMC Counter Stop Rollover.
tushki7	0:60d829a0353a	2057	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2058	* @retval None
tushki7	0:60d829a0353a	2059	*/
tushki7	0:60d829a0353a	2060	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
tushki7	0:60d829a0353a	2061
tushki7	0:60d829a0353a	2062	/**
tushki7	0:60d829a0353a	2063	* @brief Disables the MMC Counter Stop Rollover.
tushki7	0:60d829a0353a	2064	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2065	* @retval None
tushki7	0:60d829a0353a	2066	*/
tushki7	0:60d829a0353a	2067	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
tushki7	0:60d829a0353a	2068
tushki7	0:60d829a0353a	2069	/**
tushki7	0:60d829a0353a	2070	* @brief Resets the MMC Counters.
tushki7	0:60d829a0353a	2071	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2072	* @retval None
tushki7	0:60d829a0353a	2073	*/
tushki7	0:60d829a0353a	2074	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
tushki7	0:60d829a0353a	2075
tushki7	0:60d829a0353a	2076	/**
tushki7	0:60d829a0353a	2077	* @brief Enables the specified ETHERNET MMC Rx interrupts.
tushki7	0:60d829a0353a	2078	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2079	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
tushki7	0:60d829a0353a	2080	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	2081	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
tushki7	0:60d829a0353a	2082	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
tushki7	0:60d829a0353a	2083	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
tushki7	0:60d829a0353a	2084	* @retval None
tushki7	0:60d829a0353a	2085	*/
tushki7	0:60d829a0353a	2086	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
tushki7	0:60d829a0353a	2087	/**
tushki7	0:60d829a0353a	2088	* @brief Disables the specified ETHERNET MMC Rx interrupts.
tushki7	0:60d829a0353a	2089	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2090	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
tushki7	0:60d829a0353a	2091	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	2092	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
tushki7	0:60d829a0353a	2093	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
tushki7	0:60d829a0353a	2094	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
tushki7	0:60d829a0353a	2095	* @retval None
tushki7	0:60d829a0353a	2096	*/
tushki7	0:60d829a0353a	2097	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFF)
tushki7	0:60d829a0353a	2098	/**
tushki7	0:60d829a0353a	2099	* @brief Enables the specified ETHERNET MMC Tx interrupts.
tushki7	0:60d829a0353a	2100	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2101	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
tushki7	0:60d829a0353a	2102	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	2103	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
tushki7	0:60d829a0353a	2104	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
tushki7	0:60d829a0353a	2105	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
tushki7	0:60d829a0353a	2106	* @retval None
tushki7	0:60d829a0353a	2107	*/
tushki7	0:60d829a0353a	2108	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
tushki7	0:60d829a0353a	2109
tushki7	0:60d829a0353a	2110	/**
tushki7	0:60d829a0353a	2111	* @brief Disables the specified ETHERNET MMC Tx interrupts.
tushki7	0:60d829a0353a	2112	* @param __HANDLE__: ETH Handle.
tushki7	0:60d829a0353a	2113	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
tushki7	0:60d829a0353a	2114	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	2115	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
tushki7	0:60d829a0353a	2116	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
tushki7	0:60d829a0353a	2117	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
tushki7	0:60d829a0353a	2118	* @retval None
tushki7	0:60d829a0353a	2119	*/
tushki7	0:60d829a0353a	2120	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
tushki7	0:60d829a0353a	2121
tushki7	0:60d829a0353a	2122	/** @defgroup ETH_EXTI_LINE_WAKEUP
tushki7	0:60d829a0353a	2123	* @{
tushki7	0:60d829a0353a	2124	*/
tushki7	0:60d829a0353a	2125	#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /!< External interrupt line 19 Connected to the ETH EXTI Line /
tushki7	0:60d829a0353a	2126
tushki7	0:60d829a0353a	2127	/**
tushki7	0:60d829a0353a	2128	* @}
tushki7	0:60d829a0353a	2129	*/
tushki7	0:60d829a0353a	2130
tushki7	0:60d829a0353a	2131	/**
tushki7	0:60d829a0353a	2132	* @brief Enables the ETH External interrupt line.
tushki7	0:60d829a0353a	2133	* @param None
tushki7	0:60d829a0353a	2134	* @retval None
tushki7	0:60d829a0353a	2135	*/
tushki7	0:60d829a0353a	2136	#define __HAL_ETH_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
tushki7	0:60d829a0353a	2137
tushki7	0:60d829a0353a	2138	/**
tushki7	0:60d829a0353a	2139	* @brief Disables the ETH External interrupt line.
tushki7	0:60d829a0353a	2140	* @param None
tushki7	0:60d829a0353a	2141	* @retval None
tushki7	0:60d829a0353a	2142	*/
tushki7	0:60d829a0353a	2143	#define __HAL_ETH_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
tushki7	0:60d829a0353a	2144
tushki7	0:60d829a0353a	2145	/**
tushki7	0:60d829a0353a	2146	* @brief Get flag of the ETH External interrupt line.
tushki7	0:60d829a0353a	2147	* @param None
tushki7	0:60d829a0353a	2148	* @retval None
tushki7	0:60d829a0353a	2149	*/
tushki7	0:60d829a0353a	2150	#define __HAL_ETH_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
tushki7	0:60d829a0353a	2151
tushki7	0:60d829a0353a	2152	/**
tushki7	0:60d829a0353a	2153	* @brief Clear flag of the ETH External interrupt line.
tushki7	0:60d829a0353a	2154	* @param None
tushki7	0:60d829a0353a	2155	* @retval None
tushki7	0:60d829a0353a	2156	*/
tushki7	0:60d829a0353a	2157	#define __HAL_ETH_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
tushki7	0:60d829a0353a	2158
tushki7	0:60d829a0353a	2159	/**
tushki7	0:60d829a0353a	2160	* @brief Sets rising edge trigger to the ETH External interrupt line.
tushki7	0:60d829a0353a	2161	* @param None
tushki7	0:60d829a0353a	2162	* @retval None
tushki7	0:60d829a0353a	2163	*/
tushki7	0:60d829a0353a	2164	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
tushki7	0:60d829a0353a	2165	EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
tushki7	0:60d829a0353a	2166
tushki7	0:60d829a0353a	2167	/**
tushki7	0:60d829a0353a	2168	* @brief Sets falling edge trigger to the ETH External interrupt line.
tushki7	0:60d829a0353a	2169	* @param None
tushki7	0:60d829a0353a	2170	* @retval None
tushki7	0:60d829a0353a	2171	*/
tushki7	0:60d829a0353a	2172	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP);\
tushki7	0:60d829a0353a	2173	EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
tushki7	0:60d829a0353a	2174
tushki7	0:60d829a0353a	2175	/**
tushki7	0:60d829a0353a	2176	* @brief Sets rising/falling edge trigger to the ETH External interrupt line.
tushki7	0:60d829a0353a	2177	* @param None
tushki7	0:60d829a0353a	2178	* @retval None
tushki7	0:60d829a0353a	2179	*/
tushki7	0:60d829a0353a	2180	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
tushki7	0:60d829a0353a	2181	EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
tushki7	0:60d829a0353a	2182	EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP;\
tushki7	0:60d829a0353a	2183	EXTI->FTSR \|= ETH_EXTI_LINE_WAKEUP
tushki7	0:60d829a0353a	2184
tushki7	0:60d829a0353a	2185	/* Exported functions --------------------------------------------------------*/
tushki7	0:60d829a0353a	2186
tushki7	0:60d829a0353a	2187	/* Initialization and de-initialization functions ****************************/
tushki7	0:60d829a0353a	2188	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2189	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2190	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2191	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2192	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
tushki7	0:60d829a0353a	2193	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
tushki7	0:60d829a0353a	2194
tushki7	0:60d829a0353a	2195	/* IO operation functions ****************************************************/
tushki7	0:60d829a0353a	2196	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
tushki7	0:60d829a0353a	2197	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2198
tushki7	0:60d829a0353a	2199	/* Non-Blocking mode: Interrupt */
tushki7	0:60d829a0353a	2200	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2201	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2202
tushki7	0:60d829a0353a	2203	/* Callback in non blocking modes (Interrupt) */
tushki7	0:60d829a0353a	2204	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2205	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2206	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2207
tushki7	0:60d829a0353a	2208	/* Cmmunication with PHY functions*/
tushki7	0:60d829a0353a	2209	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
tushki7	0:60d829a0353a	2210	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
tushki7	0:60d829a0353a	2211
tushki7	0:60d829a0353a	2212	/* Peripheral Control functions **********************************************/
tushki7	0:60d829a0353a	2213	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2214	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2215
tushki7	0:60d829a0353a	2216	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
tushki7	0:60d829a0353a	2217	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
tushki7	0:60d829a0353a	2218
tushki7	0:60d829a0353a	2219	/* Peripheral State functions ************************************************/
tushki7	0:60d829a0353a	2220	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
tushki7	0:60d829a0353a	2221
tushki7	0:60d829a0353a	2222	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
tushki7	0:60d829a0353a	2223	/**
tushki7	0:60d829a0353a	2224	* @}
tushki7	0:60d829a0353a	2225	*/
tushki7	0:60d829a0353a	2226
tushki7	0:60d829a0353a	2227	/**
tushki7	0:60d829a0353a	2228	* @}
tushki7	0:60d829a0353a	2229	*/
tushki7	0:60d829a0353a	2230
tushki7	0:60d829a0353a	2231	#ifdef __cplusplus
tushki7	0:60d829a0353a	2232	}
tushki7	0:60d829a0353a	2233	#endif
tushki7	0:60d829a0353a	2234
tushki7	0:60d829a0353a	2235	#endif /* __STM32F4xx_HAL_ETH_H */
tushki7	0:60d829a0353a	2236
tushki7	0:60d829a0353a	2237
tushki7	0:60d829a0353a	2238
tushki7	0:60d829a0353a	2239	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	11 Apr 2015
Imports:	100
Forks:	0
Commits:	2
Dependents:	0
Dependencies:	1
Followers:	2

mbed/TARGET_NUCLEO_F411RE/stm32f4xx_hal_eth.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

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