Tushar Sachdeva
A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.
mbed/TARGET_NUCLEO_F302R8/stm32f3xx_hal_dma.h@1:eb68c94a8ee5, 2015-04-12 (annotated)
- Committer:
- tushki7
- Date:
- Sun Apr 12 15:45:52 2015 +0000
- Revision:
- 1:eb68c94a8ee5
- Parent:
- 0:60d829a0353a
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| tushki7 | 0:60d829a0353a | 1 | /** |
| tushki7 | 0:60d829a0353a | 2 | ****************************************************************************** |
| tushki7 | 0:60d829a0353a | 3 | * @file stm32f3xx_hal_dma.h |
| tushki7 | 0:60d829a0353a | 4 | * @author MCD Application Team |
| tushki7 | 0:60d829a0353a | 5 | * @version V1.1.0 |
| tushki7 | 0:60d829a0353a | 6 | * @date 12-Sept-2014 |
| tushki7 | 0:60d829a0353a | 7 | * @brief Header file of DMA HAL module. |
| tushki7 | 0:60d829a0353a | 8 | ****************************************************************************** |
| tushki7 | 0:60d829a0353a | 9 | * @attention |
| tushki7 | 0:60d829a0353a | 10 | * |
| tushki7 | 0:60d829a0353a | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| tushki7 | 0:60d829a0353a | 12 | * |
| tushki7 | 0:60d829a0353a | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| tushki7 | 0:60d829a0353a | 14 | * are permitted provided that the following conditions are met: |
| tushki7 | 0:60d829a0353a | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| tushki7 | 0:60d829a0353a | 16 | * this list of conditions and the following disclaimer. |
| tushki7 | 0:60d829a0353a | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| tushki7 | 0:60d829a0353a | 18 | * this list of conditions and the following disclaimer in the documentation |
| tushki7 | 0:60d829a0353a | 19 | * and/or other materials provided with the distribution. |
| tushki7 | 0:60d829a0353a | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| tushki7 | 0:60d829a0353a | 21 | * may be used to endorse or promote products derived from this software |
| tushki7 | 0:60d829a0353a | 22 | * without specific prior written permission. |
| tushki7 | 0:60d829a0353a | 23 | * |
| tushki7 | 0:60d829a0353a | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| tushki7 | 0:60d829a0353a | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| tushki7 | 0:60d829a0353a | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| tushki7 | 0:60d829a0353a | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| tushki7 | 0:60d829a0353a | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| tushki7 | 0:60d829a0353a | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| tushki7 | 0:60d829a0353a | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| tushki7 | 0:60d829a0353a | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| tushki7 | 0:60d829a0353a | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| tushki7 | 0:60d829a0353a | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| tushki7 | 0:60d829a0353a | 34 | * |
| tushki7 | 0:60d829a0353a | 35 | ****************************************************************************** |
| tushki7 | 0:60d829a0353a | 36 | */ |
| tushki7 | 0:60d829a0353a | 37 | |
| tushki7 | 0:60d829a0353a | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| tushki7 | 0:60d829a0353a | 39 | #ifndef __STM32F3xx_HAL_DMA_H |
| tushki7 | 0:60d829a0353a | 40 | #define __STM32F3xx_HAL_DMA_H |
| tushki7 | 0:60d829a0353a | 41 | |
| tushki7 | 0:60d829a0353a | 42 | #ifdef __cplusplus |
| tushki7 | 0:60d829a0353a | 43 | extern "C" { |
| tushki7 | 0:60d829a0353a | 44 | #endif |
| tushki7 | 0:60d829a0353a | 45 | |
| tushki7 | 0:60d829a0353a | 46 | /* Includes ------------------------------------------------------------------*/ |
| tushki7 | 0:60d829a0353a | 47 | #include "stm32f3xx_hal_def.h" |
| tushki7 | 0:60d829a0353a | 48 | |
| tushki7 | 0:60d829a0353a | 49 | /** @addtogroup STM32F3xx_HAL_Driver |
| tushki7 | 0:60d829a0353a | 50 | * @{ |
| tushki7 | 0:60d829a0353a | 51 | */ |
| tushki7 | 0:60d829a0353a | 52 | |
| tushki7 | 0:60d829a0353a | 53 | /** @addtogroup DMA DMA HAL module driver |
| tushki7 | 0:60d829a0353a | 54 | * @{ |
| tushki7 | 0:60d829a0353a | 55 | */ |
| tushki7 | 0:60d829a0353a | 56 | |
| tushki7 | 0:60d829a0353a | 57 | /* Exported types ------------------------------------------------------------*/ |
| tushki7 | 0:60d829a0353a | 58 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| tushki7 | 0:60d829a0353a | 59 | * @{ |
| tushki7 | 0:60d829a0353a | 60 | */ |
| tushki7 | 0:60d829a0353a | 61 | |
| tushki7 | 0:60d829a0353a | 62 | /** |
| tushki7 | 0:60d829a0353a | 63 | * @brief DMA Configuration Structure definition |
| tushki7 | 0:60d829a0353a | 64 | */ |
| tushki7 | 0:60d829a0353a | 65 | typedef struct |
| tushki7 | 0:60d829a0353a | 66 | { |
| tushki7 | 0:60d829a0353a | 67 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| tushki7 | 0:60d829a0353a | 68 | from memory to memory or from peripheral to memory. |
| tushki7 | 0:60d829a0353a | 69 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| tushki7 | 0:60d829a0353a | 70 | |
| tushki7 | 0:60d829a0353a | 71 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| tushki7 | 0:60d829a0353a | 72 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| tushki7 | 0:60d829a0353a | 73 | |
| tushki7 | 0:60d829a0353a | 74 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| tushki7 | 0:60d829a0353a | 75 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| tushki7 | 0:60d829a0353a | 76 | |
| tushki7 | 0:60d829a0353a | 77 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| tushki7 | 0:60d829a0353a | 78 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| tushki7 | 0:60d829a0353a | 79 | |
| tushki7 | 0:60d829a0353a | 80 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| tushki7 | 0:60d829a0353a | 81 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| tushki7 | 0:60d829a0353a | 82 | |
| tushki7 | 0:60d829a0353a | 83 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. |
| tushki7 | 0:60d829a0353a | 84 | This parameter can be a value of @ref DMA_mode |
| tushki7 | 0:60d829a0353a | 85 | @note The circular buffer mode cannot be used if the memory-to-memory |
| tushki7 | 0:60d829a0353a | 86 | data transfer is configured on the selected Channel */ |
| tushki7 | 0:60d829a0353a | 87 | |
| tushki7 | 0:60d829a0353a | 88 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. |
| tushki7 | 0:60d829a0353a | 89 | This parameter can be a value of @ref DMA_Priority_level */ |
| tushki7 | 0:60d829a0353a | 90 | |
| tushki7 | 0:60d829a0353a | 91 | } DMA_InitTypeDef; |
| tushki7 | 0:60d829a0353a | 92 | |
| tushki7 | 0:60d829a0353a | 93 | /** |
| tushki7 | 0:60d829a0353a | 94 | * @brief DMA Configuration enumeration values definition |
| tushki7 | 0:60d829a0353a | 95 | */ |
| tushki7 | 0:60d829a0353a | 96 | typedef enum |
| tushki7 | 0:60d829a0353a | 97 | { |
| tushki7 | 0:60d829a0353a | 98 | DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ |
| tushki7 | 0:60d829a0353a | 99 | DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ |
| tushki7 | 0:60d829a0353a | 100 | |
| tushki7 | 0:60d829a0353a | 101 | } DMA_ControlTypeDef; |
| tushki7 | 0:60d829a0353a | 102 | |
| tushki7 | 0:60d829a0353a | 103 | /** |
| tushki7 | 0:60d829a0353a | 104 | * @brief HAL DMA State structures definition |
| tushki7 | 0:60d829a0353a | 105 | */ |
| tushki7 | 0:60d829a0353a | 106 | typedef enum |
| tushki7 | 0:60d829a0353a | 107 | { |
| tushki7 | 0:60d829a0353a | 108 | HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ |
| tushki7 | 0:60d829a0353a | 109 | HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */ |
| tushki7 | 0:60d829a0353a | 110 | HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */ |
| tushki7 | 0:60d829a0353a | 111 | HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ |
| tushki7 | 0:60d829a0353a | 112 | HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ |
| tushki7 | 0:60d829a0353a | 113 | HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ |
| tushki7 | 0:60d829a0353a | 114 | |
| tushki7 | 0:60d829a0353a | 115 | }HAL_DMA_StateTypeDef; |
| tushki7 | 0:60d829a0353a | 116 | |
| tushki7 | 0:60d829a0353a | 117 | /** |
| tushki7 | 0:60d829a0353a | 118 | * @brief HAL DMA Error Code structure definition |
| tushki7 | 0:60d829a0353a | 119 | */ |
| tushki7 | 0:60d829a0353a | 120 | typedef enum |
| tushki7 | 0:60d829a0353a | 121 | { |
| tushki7 | 0:60d829a0353a | 122 | HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ |
| tushki7 | 0:60d829a0353a | 123 | HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ |
| tushki7 | 0:60d829a0353a | 124 | |
| tushki7 | 0:60d829a0353a | 125 | }HAL_DMA_LevelCompleteTypeDef; |
| tushki7 | 0:60d829a0353a | 126 | |
| tushki7 | 0:60d829a0353a | 127 | |
| tushki7 | 0:60d829a0353a | 128 | /** |
| tushki7 | 0:60d829a0353a | 129 | * @brief DMA handle Structure definition |
| tushki7 | 0:60d829a0353a | 130 | */ |
| tushki7 | 0:60d829a0353a | 131 | typedef struct __DMA_HandleTypeDef |
| tushki7 | 0:60d829a0353a | 132 | { |
| tushki7 | 0:60d829a0353a | 133 | DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
| tushki7 | 0:60d829a0353a | 134 | |
| tushki7 | 0:60d829a0353a | 135 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| tushki7 | 0:60d829a0353a | 136 | |
| tushki7 | 0:60d829a0353a | 137 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| tushki7 | 0:60d829a0353a | 138 | |
| tushki7 | 0:60d829a0353a | 139 | HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| tushki7 | 0:60d829a0353a | 140 | |
| tushki7 | 0:60d829a0353a | 141 | void *Parent; /*!< Parent object state */ |
| tushki7 | 0:60d829a0353a | 142 | |
| tushki7 | 0:60d829a0353a | 143 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| tushki7 | 0:60d829a0353a | 144 | |
| tushki7 | 0:60d829a0353a | 145 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| tushki7 | 0:60d829a0353a | 146 | |
| tushki7 | 0:60d829a0353a | 147 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| tushki7 | 0:60d829a0353a | 148 | |
| tushki7 | 0:60d829a0353a | 149 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| tushki7 | 0:60d829a0353a | 150 | |
| tushki7 | 0:60d829a0353a | 151 | } DMA_HandleTypeDef; |
| tushki7 | 0:60d829a0353a | 152 | /** |
| tushki7 | 0:60d829a0353a | 153 | * @} |
| tushki7 | 0:60d829a0353a | 154 | */ |
| tushki7 | 0:60d829a0353a | 155 | |
| tushki7 | 0:60d829a0353a | 156 | /* Exported constants --------------------------------------------------------*/ |
| tushki7 | 0:60d829a0353a | 157 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| tushki7 | 0:60d829a0353a | 158 | * @{ |
| tushki7 | 0:60d829a0353a | 159 | */ |
| tushki7 | 0:60d829a0353a | 160 | |
| tushki7 | 0:60d829a0353a | 161 | /** @defgroup DMA_Error_Code DMA Error Code |
| tushki7 | 0:60d829a0353a | 162 | * @{ |
| tushki7 | 0:60d829a0353a | 163 | */ |
| tushki7 | 0:60d829a0353a | 164 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| tushki7 | 0:60d829a0353a | 165 | #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ |
| tushki7 | 0:60d829a0353a | 166 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ |
| tushki7 | 0:60d829a0353a | 167 | /** |
| tushki7 | 0:60d829a0353a | 168 | * @} |
| tushki7 | 0:60d829a0353a | 169 | */ |
| tushki7 | 0:60d829a0353a | 170 | |
| tushki7 | 0:60d829a0353a | 171 | |
| tushki7 | 0:60d829a0353a | 172 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
| tushki7 | 0:60d829a0353a | 173 | * @{ |
| tushki7 | 0:60d829a0353a | 174 | */ |
| tushki7 | 0:60d829a0353a | 175 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ |
| tushki7 | 0:60d829a0353a | 176 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
| tushki7 | 0:60d829a0353a | 177 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ |
| tushki7 | 0:60d829a0353a | 178 | |
| tushki7 | 0:60d829a0353a | 179 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| tushki7 | 0:60d829a0353a | 180 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| tushki7 | 0:60d829a0353a | 181 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| tushki7 | 0:60d829a0353a | 182 | /** |
| tushki7 | 0:60d829a0353a | 183 | * @} |
| tushki7 | 0:60d829a0353a | 184 | */ |
| tushki7 | 0:60d829a0353a | 185 | |
| tushki7 | 0:60d829a0353a | 186 | /** @defgroup DMA_Data_buffer_size DMA Data buffer size |
| tushki7 | 0:60d829a0353a | 187 | * @{ |
| tushki7 | 0:60d829a0353a | 188 | */ |
| tushki7 | 0:60d829a0353a | 189 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| tushki7 | 0:60d829a0353a | 190 | /** |
| tushki7 | 0:60d829a0353a | 191 | * @} |
| tushki7 | 0:60d829a0353a | 192 | */ |
| tushki7 | 0:60d829a0353a | 193 | |
| tushki7 | 0:60d829a0353a | 194 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
| tushki7 | 0:60d829a0353a | 195 | * @{ |
| tushki7 | 0:60d829a0353a | 196 | */ |
| tushki7 | 0:60d829a0353a | 197 | #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
| tushki7 | 0:60d829a0353a | 198 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ |
| tushki7 | 0:60d829a0353a | 199 | |
| tushki7 | 0:60d829a0353a | 200 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| tushki7 | 0:60d829a0353a | 201 | ((STATE) == DMA_PINC_DISABLE)) |
| tushki7 | 0:60d829a0353a | 202 | /** |
| tushki7 | 0:60d829a0353a | 203 | * @} |
| tushki7 | 0:60d829a0353a | 204 | */ |
| tushki7 | 0:60d829a0353a | 205 | |
| tushki7 | 0:60d829a0353a | 206 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
| tushki7 | 0:60d829a0353a | 207 | * @{ |
| tushki7 | 0:60d829a0353a | 208 | */ |
| tushki7 | 0:60d829a0353a | 209 | #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
| tushki7 | 0:60d829a0353a | 210 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ |
| tushki7 | 0:60d829a0353a | 211 | |
| tushki7 | 0:60d829a0353a | 212 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| tushki7 | 0:60d829a0353a | 213 | ((STATE) == DMA_MINC_DISABLE)) |
| tushki7 | 0:60d829a0353a | 214 | /** |
| tushki7 | 0:60d829a0353a | 215 | * @} |
| tushki7 | 0:60d829a0353a | 216 | */ |
| tushki7 | 0:60d829a0353a | 217 | |
| tushki7 | 0:60d829a0353a | 218 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
| tushki7 | 0:60d829a0353a | 219 | * @{ |
| tushki7 | 0:60d829a0353a | 220 | */ |
| tushki7 | 0:60d829a0353a | 221 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ |
| tushki7 | 0:60d829a0353a | 222 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ |
| tushki7 | 0:60d829a0353a | 223 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ |
| tushki7 | 0:60d829a0353a | 224 | |
| tushki7 | 0:60d829a0353a | 225 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| tushki7 | 0:60d829a0353a | 226 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| tushki7 | 0:60d829a0353a | 227 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| tushki7 | 0:60d829a0353a | 228 | /** |
| tushki7 | 0:60d829a0353a | 229 | * @} |
| tushki7 | 0:60d829a0353a | 230 | */ |
| tushki7 | 0:60d829a0353a | 231 | |
| tushki7 | 0:60d829a0353a | 232 | |
| tushki7 | 0:60d829a0353a | 233 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
| tushki7 | 0:60d829a0353a | 234 | * @{ |
| tushki7 | 0:60d829a0353a | 235 | */ |
| tushki7 | 0:60d829a0353a | 236 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ |
| tushki7 | 0:60d829a0353a | 237 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ |
| tushki7 | 0:60d829a0353a | 238 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ |
| tushki7 | 0:60d829a0353a | 239 | |
| tushki7 | 0:60d829a0353a | 240 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| tushki7 | 0:60d829a0353a | 241 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| tushki7 | 0:60d829a0353a | 242 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| tushki7 | 0:60d829a0353a | 243 | /** |
| tushki7 | 0:60d829a0353a | 244 | * @} |
| tushki7 | 0:60d829a0353a | 245 | */ |
| tushki7 | 0:60d829a0353a | 246 | |
| tushki7 | 0:60d829a0353a | 247 | /** @defgroup DMA_mode DMA mode |
| tushki7 | 0:60d829a0353a | 248 | * @{ |
| tushki7 | 0:60d829a0353a | 249 | */ |
| tushki7 | 0:60d829a0353a | 250 | #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */ |
| tushki7 | 0:60d829a0353a | 251 | #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ |
| tushki7 | 0:60d829a0353a | 252 | |
| tushki7 | 0:60d829a0353a | 253 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| tushki7 | 0:60d829a0353a | 254 | ((MODE) == DMA_CIRCULAR)) |
| tushki7 | 0:60d829a0353a | 255 | /** |
| tushki7 | 0:60d829a0353a | 256 | * @} |
| tushki7 | 0:60d829a0353a | 257 | */ |
| tushki7 | 0:60d829a0353a | 258 | |
| tushki7 | 0:60d829a0353a | 259 | /** @defgroup DMA_Priority_level DMA Priority level |
| tushki7 | 0:60d829a0353a | 260 | * @{ |
| tushki7 | 0:60d829a0353a | 261 | */ |
| tushki7 | 0:60d829a0353a | 262 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ |
| tushki7 | 0:60d829a0353a | 263 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
| tushki7 | 0:60d829a0353a | 264 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
| tushki7 | 0:60d829a0353a | 265 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
| tushki7 | 0:60d829a0353a | 266 | |
| tushki7 | 0:60d829a0353a | 267 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| tushki7 | 0:60d829a0353a | 268 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| tushki7 | 0:60d829a0353a | 269 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| tushki7 | 0:60d829a0353a | 270 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| tushki7 | 0:60d829a0353a | 271 | /** |
| tushki7 | 0:60d829a0353a | 272 | * @} |
| tushki7 | 0:60d829a0353a | 273 | */ |
| tushki7 | 0:60d829a0353a | 274 | |
| tushki7 | 0:60d829a0353a | 275 | |
| tushki7 | 0:60d829a0353a | 276 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
| tushki7 | 0:60d829a0353a | 277 | * @{ |
| tushki7 | 0:60d829a0353a | 278 | */ |
| tushki7 | 0:60d829a0353a | 279 | |
| tushki7 | 0:60d829a0353a | 280 | #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
| tushki7 | 0:60d829a0353a | 281 | #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
| tushki7 | 0:60d829a0353a | 282 | #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
| tushki7 | 0:60d829a0353a | 283 | |
| tushki7 | 0:60d829a0353a | 284 | /** |
| tushki7 | 0:60d829a0353a | 285 | * @} |
| tushki7 | 0:60d829a0353a | 286 | */ |
| tushki7 | 0:60d829a0353a | 287 | |
| tushki7 | 0:60d829a0353a | 288 | /** @defgroup DMA_flag_definitions DMA flag definitions |
| tushki7 | 0:60d829a0353a | 289 | * @{ |
| tushki7 | 0:60d829a0353a | 290 | */ |
| tushki7 | 0:60d829a0353a | 291 | |
| tushki7 | 0:60d829a0353a | 292 | #define DMA_FLAG_GL1 ((uint32_t)0x00000001) |
| tushki7 | 0:60d829a0353a | 293 | #define DMA_FLAG_TC1 ((uint32_t)0x00000002) |
| tushki7 | 0:60d829a0353a | 294 | #define DMA_FLAG_HT1 ((uint32_t)0x00000004) |
| tushki7 | 0:60d829a0353a | 295 | #define DMA_FLAG_TE1 ((uint32_t)0x00000008) |
| tushki7 | 0:60d829a0353a | 296 | #define DMA_FLAG_GL2 ((uint32_t)0x00000010) |
| tushki7 | 0:60d829a0353a | 297 | #define DMA_FLAG_TC2 ((uint32_t)0x00000020) |
| tushki7 | 0:60d829a0353a | 298 | #define DMA_FLAG_HT2 ((uint32_t)0x00000040) |
| tushki7 | 0:60d829a0353a | 299 | #define DMA_FLAG_TE2 ((uint32_t)0x00000080) |
| tushki7 | 0:60d829a0353a | 300 | #define DMA_FLAG_GL3 ((uint32_t)0x00000100) |
| tushki7 | 0:60d829a0353a | 301 | #define DMA_FLAG_TC3 ((uint32_t)0x00000200) |
| tushki7 | 0:60d829a0353a | 302 | #define DMA_FLAG_HT3 ((uint32_t)0x00000400) |
| tushki7 | 0:60d829a0353a | 303 | #define DMA_FLAG_TE3 ((uint32_t)0x00000800) |
| tushki7 | 0:60d829a0353a | 304 | #define DMA_FLAG_GL4 ((uint32_t)0x00001000) |
| tushki7 | 0:60d829a0353a | 305 | #define DMA_FLAG_TC4 ((uint32_t)0x00002000) |
| tushki7 | 0:60d829a0353a | 306 | #define DMA_FLAG_HT4 ((uint32_t)0x00004000) |
| tushki7 | 0:60d829a0353a | 307 | #define DMA_FLAG_TE4 ((uint32_t)0x00008000) |
| tushki7 | 0:60d829a0353a | 308 | #define DMA_FLAG_GL5 ((uint32_t)0x00010000) |
| tushki7 | 0:60d829a0353a | 309 | #define DMA_FLAG_TC5 ((uint32_t)0x00020000) |
| tushki7 | 0:60d829a0353a | 310 | #define DMA_FLAG_HT5 ((uint32_t)0x00040000) |
| tushki7 | 0:60d829a0353a | 311 | #define DMA_FLAG_TE5 ((uint32_t)0x00080000) |
| tushki7 | 0:60d829a0353a | 312 | #define DMA_FLAG_GL6 ((uint32_t)0x00100000) |
| tushki7 | 0:60d829a0353a | 313 | #define DMA_FLAG_TC6 ((uint32_t)0x00200000) |
| tushki7 | 0:60d829a0353a | 314 | #define DMA_FLAG_HT6 ((uint32_t)0x00400000) |
| tushki7 | 0:60d829a0353a | 315 | #define DMA_FLAG_TE6 ((uint32_t)0x00800000) |
| tushki7 | 0:60d829a0353a | 316 | #define DMA_FLAG_GL7 ((uint32_t)0x01000000) |
| tushki7 | 0:60d829a0353a | 317 | #define DMA_FLAG_TC7 ((uint32_t)0x02000000) |
| tushki7 | 0:60d829a0353a | 318 | #define DMA_FLAG_HT7 ((uint32_t)0x04000000) |
| tushki7 | 0:60d829a0353a | 319 | #define DMA_FLAG_TE7 ((uint32_t)0x08000000) |
| tushki7 | 0:60d829a0353a | 320 | |
| tushki7 | 0:60d829a0353a | 321 | |
| tushki7 | 0:60d829a0353a | 322 | /** |
| tushki7 | 0:60d829a0353a | 323 | * @} |
| tushki7 | 0:60d829a0353a | 324 | */ |
| tushki7 | 0:60d829a0353a | 325 | |
| tushki7 | 0:60d829a0353a | 326 | /** |
| tushki7 | 0:60d829a0353a | 327 | * @} |
| tushki7 | 0:60d829a0353a | 328 | */ |
| tushki7 | 0:60d829a0353a | 329 | |
| tushki7 | 0:60d829a0353a | 330 | /* Exported macros -----------------------------------------------------------*/ |
| tushki7 | 0:60d829a0353a | 331 | /** @defgroup DMA_Exported_Macros DMA Exported Macros |
| tushki7 | 0:60d829a0353a | 332 | * @{ |
| tushki7 | 0:60d829a0353a | 333 | */ |
| tushki7 | 0:60d829a0353a | 334 | |
| tushki7 | 0:60d829a0353a | 335 | /** @brief Reset DMA handle state |
| tushki7 | 0:60d829a0353a | 336 | * @param __HANDLE__: DMA handle. |
| tushki7 | 0:60d829a0353a | 337 | * @retval None |
| tushki7 | 0:60d829a0353a | 338 | */ |
| tushki7 | 0:60d829a0353a | 339 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| tushki7 | 0:60d829a0353a | 340 | |
| tushki7 | 0:60d829a0353a | 341 | /** |
| tushki7 | 0:60d829a0353a | 342 | * @brief Enable the specified DMA Channel. |
| tushki7 | 0:60d829a0353a | 343 | * @param __HANDLE__: DMA handle |
| tushki7 | 0:60d829a0353a | 344 | * @retval None. |
| tushki7 | 0:60d829a0353a | 345 | */ |
| tushki7 | 0:60d829a0353a | 346 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) |
| tushki7 | 0:60d829a0353a | 347 | |
| tushki7 | 0:60d829a0353a | 348 | /** |
| tushki7 | 0:60d829a0353a | 349 | * @brief Disable the specified DMA Channel. |
| tushki7 | 0:60d829a0353a | 350 | * @param __HANDLE__: DMA handle |
| tushki7 | 0:60d829a0353a | 351 | * @retval None. |
| tushki7 | 0:60d829a0353a | 352 | */ |
| tushki7 | 0:60d829a0353a | 353 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) |
| tushki7 | 0:60d829a0353a | 354 | |
| tushki7 | 0:60d829a0353a | 355 | |
| tushki7 | 0:60d829a0353a | 356 | /* Interrupt & Flag management */ |
| tushki7 | 0:60d829a0353a | 357 | |
| tushki7 | 0:60d829a0353a | 358 | /** |
| tushki7 | 0:60d829a0353a | 359 | * @brief Enables the specified DMA Channel interrupts. |
| tushki7 | 0:60d829a0353a | 360 | * @param __HANDLE__: DMA handle |
| tushki7 | 0:60d829a0353a | 361 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| tushki7 | 0:60d829a0353a | 362 | * This parameter can be any combination of the following values: |
| tushki7 | 0:60d829a0353a | 363 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| tushki7 | 0:60d829a0353a | 364 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| tushki7 | 0:60d829a0353a | 365 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| tushki7 | 0:60d829a0353a | 366 | * @retval None |
| tushki7 | 0:60d829a0353a | 367 | */ |
| tushki7 | 0:60d829a0353a | 368 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) |
| tushki7 | 0:60d829a0353a | 369 | |
| tushki7 | 0:60d829a0353a | 370 | /** |
| tushki7 | 0:60d829a0353a | 371 | * @brief Disables the specified DMA Channel interrupts. |
| tushki7 | 0:60d829a0353a | 372 | * @param __HANDLE__: DMA handle |
| tushki7 | 0:60d829a0353a | 373 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| tushki7 | 0:60d829a0353a | 374 | * This parameter can be any combination of the following values: |
| tushki7 | 0:60d829a0353a | 375 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| tushki7 | 0:60d829a0353a | 376 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| tushki7 | 0:60d829a0353a | 377 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| tushki7 | 0:60d829a0353a | 378 | * @retval None |
| tushki7 | 0:60d829a0353a | 379 | */ |
| tushki7 | 0:60d829a0353a | 380 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) |
| tushki7 | 0:60d829a0353a | 381 | |
| tushki7 | 0:60d829a0353a | 382 | /** |
| tushki7 | 0:60d829a0353a | 383 | * @brief Checks whether the specified DMA Channel interrupt has occurred or not. |
| tushki7 | 0:60d829a0353a | 384 | * @param __HANDLE__: DMA handle |
| tushki7 | 0:60d829a0353a | 385 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| tushki7 | 0:60d829a0353a | 386 | * This parameter can be one of the following values: |
| tushki7 | 0:60d829a0353a | 387 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| tushki7 | 0:60d829a0353a | 388 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| tushki7 | 0:60d829a0353a | 389 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| tushki7 | 0:60d829a0353a | 390 | * @retval The state of DMA_IT (SET or RESET). |
| tushki7 | 0:60d829a0353a | 391 | */ |
| tushki7 | 0:60d829a0353a | 392 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| tushki7 | 0:60d829a0353a | 393 | |
| tushki7 | 0:60d829a0353a | 394 | /** |
| tushki7 | 0:60d829a0353a | 395 | * @} |
| tushki7 | 0:60d829a0353a | 396 | */ |
| tushki7 | 0:60d829a0353a | 397 | |
| tushki7 | 0:60d829a0353a | 398 | /* Include DMA HAL Extended module */ |
| tushki7 | 0:60d829a0353a | 399 | #include "stm32f3xx_hal_dma_ex.h" |
| tushki7 | 0:60d829a0353a | 400 | |
| tushki7 | 0:60d829a0353a | 401 | /* Exported functions --------------------------------------------------------*/ |
| tushki7 | 0:60d829a0353a | 402 | /** @addtogroup DMA_Exported_Functions DMA Exported Functions |
| tushki7 | 0:60d829a0353a | 403 | * @{ |
| tushki7 | 0:60d829a0353a | 404 | */ |
| tushki7 | 0:60d829a0353a | 405 | |
| tushki7 | 0:60d829a0353a | 406 | /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
| tushki7 | 0:60d829a0353a | 407 | * @{ |
| tushki7 | 0:60d829a0353a | 408 | */ |
| tushki7 | 0:60d829a0353a | 409 | /* Initialization and de-initialization functions *****************************/ |
| tushki7 | 0:60d829a0353a | 410 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| tushki7 | 0:60d829a0353a | 411 | HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
| tushki7 | 0:60d829a0353a | 412 | |
| tushki7 | 0:60d829a0353a | 413 | /** |
| tushki7 | 0:60d829a0353a | 414 | * @} |
| tushki7 | 0:60d829a0353a | 415 | */ |
| tushki7 | 0:60d829a0353a | 416 | |
| tushki7 | 0:60d829a0353a | 417 | /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions |
| tushki7 | 0:60d829a0353a | 418 | * @{ |
| tushki7 | 0:60d829a0353a | 419 | */ |
| tushki7 | 0:60d829a0353a | 420 | /* IO operation functions *****************************************************/ |
| tushki7 | 0:60d829a0353a | 421 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| tushki7 | 0:60d829a0353a | 422 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| tushki7 | 0:60d829a0353a | 423 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| tushki7 | 0:60d829a0353a | 424 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| tushki7 | 0:60d829a0353a | 425 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| tushki7 | 0:60d829a0353a | 426 | |
| tushki7 | 0:60d829a0353a | 427 | /** |
| tushki7 | 0:60d829a0353a | 428 | * @} |
| tushki7 | 0:60d829a0353a | 429 | */ |
| tushki7 | 0:60d829a0353a | 430 | |
| tushki7 | 0:60d829a0353a | 431 | /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions |
| tushki7 | 0:60d829a0353a | 432 | * @{ |
| tushki7 | 0:60d829a0353a | 433 | */ |
| tushki7 | 0:60d829a0353a | 434 | /* Peripheral State and Error functions ***************************************/ |
| tushki7 | 0:60d829a0353a | 435 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| tushki7 | 0:60d829a0353a | 436 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| tushki7 | 0:60d829a0353a | 437 | |
| tushki7 | 0:60d829a0353a | 438 | /** |
| tushki7 | 0:60d829a0353a | 439 | * @} |
| tushki7 | 0:60d829a0353a | 440 | */ |
| tushki7 | 0:60d829a0353a | 441 | |
| tushki7 | 0:60d829a0353a | 442 | /** |
| tushki7 | 0:60d829a0353a | 443 | * @} |
| tushki7 | 0:60d829a0353a | 444 | */ |
| tushki7 | 0:60d829a0353a | 445 | |
| tushki7 | 0:60d829a0353a | 446 | /** |
| tushki7 | 0:60d829a0353a | 447 | * @} |
| tushki7 | 0:60d829a0353a | 448 | */ |
| tushki7 | 0:60d829a0353a | 449 | |
| tushki7 | 0:60d829a0353a | 450 | /** |
| tushki7 | 0:60d829a0353a | 451 | * @} |
| tushki7 | 0:60d829a0353a | 452 | */ |
| tushki7 | 0:60d829a0353a | 453 | |
| tushki7 | 0:60d829a0353a | 454 | #ifdef __cplusplus |
| tushki7 | 0:60d829a0353a | 455 | } |
| tushki7 | 0:60d829a0353a | 456 | #endif |
| tushki7 | 0:60d829a0353a | 457 | |
| tushki7 | 0:60d829a0353a | 458 | #endif /* __STM32F3xx_HAL_DMA_H */ |
| tushki7 | 0:60d829a0353a | 459 | |
| tushki7 | 0:60d829a0353a | 460 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |