FRDM_K64F_LCD - A simple 128x32 graphical LCD program to quicksta…

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A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies: C12832

mbed/TARGET_NUCLEO_F070RB/stm32f0xx_hal_tim.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:: tushki7
Date:: Sun Apr 12 15:45:52 2015 +0000
Revision:: 1:eb68c94a8ee5
Parent:: 0:60d829a0353a

A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

User	Revision	Line number	New contents of line
tushki7	0:60d829a0353a	1	/**
tushki7	0:60d829a0353a	2	******************************************************************************
tushki7	0:60d829a0353a	3	* @file stm32f0xx_hal_tim.h
tushki7	0:60d829a0353a	4	* @author MCD Application Team
tushki7	0:60d829a0353a	5	* @version V1.2.0
tushki7	0:60d829a0353a	6	* @date 11-December-2014
tushki7	0:60d829a0353a	7	* @brief Header file of TIM HAL module.
tushki7	0:60d829a0353a	8	******************************************************************************
tushki7	0:60d829a0353a	9	* @attention
tushki7	0:60d829a0353a	10	*
tushki7	0:60d829a0353a	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
tushki7	0:60d829a0353a	12	*
tushki7	0:60d829a0353a	13	* Redistribution and use in source and binary forms, with or without modification,
tushki7	0:60d829a0353a	14	* are permitted provided that the following conditions are met:
tushki7	0:60d829a0353a	15	* 1. Redistributions of source code must retain the above copyright notice,
tushki7	0:60d829a0353a	16	* this list of conditions and the following disclaimer.
tushki7	0:60d829a0353a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
tushki7	0:60d829a0353a	18	* this list of conditions and the following disclaimer in the documentation
tushki7	0:60d829a0353a	19	* and/or other materials provided with the distribution.
tushki7	0:60d829a0353a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
tushki7	0:60d829a0353a	21	* may be used to endorse or promote products derived from this software
tushki7	0:60d829a0353a	22	* without specific prior written permission.
tushki7	0:60d829a0353a	23	*
tushki7	0:60d829a0353a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
tushki7	0:60d829a0353a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
tushki7	0:60d829a0353a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
tushki7	0:60d829a0353a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
tushki7	0:60d829a0353a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
tushki7	0:60d829a0353a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
tushki7	0:60d829a0353a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
tushki7	0:60d829a0353a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
tushki7	0:60d829a0353a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
tushki7	0:60d829a0353a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
tushki7	0:60d829a0353a	34	*
tushki7	0:60d829a0353a	35	******************************************************************************
tushki7	0:60d829a0353a	36	*/
tushki7	0:60d829a0353a	37
tushki7	0:60d829a0353a	38	/* Define to prevent recursive inclusion -------------------------------------*/
tushki7	0:60d829a0353a	39	#ifndef __STM32F0xx_HAL_TIM_H
tushki7	0:60d829a0353a	40	#define __STM32F0xx_HAL_TIM_H
tushki7	0:60d829a0353a	41
tushki7	0:60d829a0353a	42	#ifdef __cplusplus
tushki7	0:60d829a0353a	43	extern "C" {
tushki7	0:60d829a0353a	44	#endif
tushki7	0:60d829a0353a	45
tushki7	0:60d829a0353a	46	/* Includes ------------------------------------------------------------------*/
tushki7	0:60d829a0353a	47	#include "stm32f0xx_hal_def.h"
tushki7	0:60d829a0353a	48
tushki7	0:60d829a0353a	49	/** @addtogroup STM32F0xx_HAL_Driver
tushki7	0:60d829a0353a	50	* @{
tushki7	0:60d829a0353a	51	*/
tushki7	0:60d829a0353a	52
tushki7	0:60d829a0353a	53	/** @addtogroup TIM
tushki7	0:60d829a0353a	54	* @{
tushki7	0:60d829a0353a	55	*/
tushki7	0:60d829a0353a	56
tushki7	0:60d829a0353a	57	/* Exported types ------------------------------------------------------------*/
tushki7	0:60d829a0353a	58	/** @defgroup TIM_Exported_Types TIM Exported Types
tushki7	0:60d829a0353a	59	* @{
tushki7	0:60d829a0353a	60	*/
tushki7	0:60d829a0353a	61
tushki7	0:60d829a0353a	62	/**
tushki7	0:60d829a0353a	63	* @brief TIM Time base Configuration Structure definition
tushki7	0:60d829a0353a	64	*/
tushki7	0:60d829a0353a	65	typedef struct
tushki7	0:60d829a0353a	66	{
tushki7	0:60d829a0353a	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
tushki7	0:60d829a0353a	68	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
tushki7	0:60d829a0353a	69
tushki7	0:60d829a0353a	70	uint32_t CounterMode; /*!< Specifies the counter mode.
tushki7	0:60d829a0353a	71	This parameter can be a value of @ref TIM_Counter_Mode */
tushki7	0:60d829a0353a	72
tushki7	0:60d829a0353a	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
tushki7	0:60d829a0353a	74	Auto-Reload Register at the next update event.
tushki7	0:60d829a0353a	75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
tushki7	0:60d829a0353a	76
tushki7	0:60d829a0353a	77	uint32_t ClockDivision; /*!< Specifies the clock division.
tushki7	0:60d829a0353a	78	This parameter can be a value of @ref TIM_ClockDivision */
tushki7	0:60d829a0353a	79
tushki7	0:60d829a0353a	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
tushki7	0:60d829a0353a	81	reaches zero, an update event is generated and counting restarts
tushki7	0:60d829a0353a	82	from the RCR value (N).
tushki7	0:60d829a0353a	83	This means in PWM mode that (N+1) corresponds to:
tushki7	0:60d829a0353a	84	- the number of PWM periods in edge-aligned mode
tushki7	0:60d829a0353a	85	- the number of half PWM period in center-aligned mode
tushki7	0:60d829a0353a	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
tushki7	0:60d829a0353a	87	@note This parameter is valid only for TIM1 and TIM8. */
tushki7	0:60d829a0353a	88	} TIM_Base_InitTypeDef;
tushki7	0:60d829a0353a	89
tushki7	0:60d829a0353a	90	/**
tushki7	0:60d829a0353a	91	* @brief TIM Output Compare Configuration Structure definition
tushki7	0:60d829a0353a	92	*/
tushki7	0:60d829a0353a	93	typedef struct
tushki7	0:60d829a0353a	94	{
tushki7	0:60d829a0353a	95	uint32_t OCMode; /*!< Specifies the TIM mode.
tushki7	0:60d829a0353a	96	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
tushki7	0:60d829a0353a	97
tushki7	0:60d829a0353a	98	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
tushki7	0:60d829a0353a	99	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
tushki7	0:60d829a0353a	100
tushki7	0:60d829a0353a	101	uint32_t OCPolarity; /*!< Specifies the output polarity.
tushki7	0:60d829a0353a	102	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
tushki7	0:60d829a0353a	103
tushki7	0:60d829a0353a	104	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
tushki7	0:60d829a0353a	105	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
tushki7	0:60d829a0353a	106	@note This parameter is valid only for TIM1 and TIM8. */
tushki7	0:60d829a0353a	107
tushki7	0:60d829a0353a	108	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
tushki7	0:60d829a0353a	109	This parameter can be a value of @ref TIM_Output_Fast_State
tushki7	0:60d829a0353a	110	@note This parameter is valid only in PWM1 and PWM2 mode. */
tushki7	0:60d829a0353a	111
tushki7	0:60d829a0353a	112
tushki7	0:60d829a0353a	113	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
tushki7	0:60d829a0353a	114	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
tushki7	0:60d829a0353a	115	@note This parameter is valid only for TIM1 and TIM8. */
tushki7	0:60d829a0353a	116
tushki7	0:60d829a0353a	117	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
tushki7	0:60d829a0353a	118	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
tushki7	0:60d829a0353a	119	@note This parameter is valid only for TIM1 and TIM8. */
tushki7	0:60d829a0353a	120	} TIM_OC_InitTypeDef;
tushki7	0:60d829a0353a	121
tushki7	0:60d829a0353a	122	/**
tushki7	0:60d829a0353a	123	* @brief TIM One Pulse Mode Configuration Structure definition
tushki7	0:60d829a0353a	124	*/
tushki7	0:60d829a0353a	125	typedef struct
tushki7	0:60d829a0353a	126	{
tushki7	0:60d829a0353a	127	uint32_t OCMode; /*!< Specifies the TIM mode.
tushki7	0:60d829a0353a	128	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
tushki7	0:60d829a0353a	129
tushki7	0:60d829a0353a	130	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
tushki7	0:60d829a0353a	131	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
tushki7	0:60d829a0353a	132
tushki7	0:60d829a0353a	133	uint32_t OCPolarity; /*!< Specifies the output polarity.
tushki7	0:60d829a0353a	134	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
tushki7	0:60d829a0353a	135
tushki7	0:60d829a0353a	136	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
tushki7	0:60d829a0353a	137	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
tushki7	0:60d829a0353a	138	@note This parameter is valid only for TIM1 and TIM8. */
tushki7	0:60d829a0353a	139
tushki7	0:60d829a0353a	140	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
tushki7	0:60d829a0353a	141	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
tushki7	0:60d829a0353a	142	@note This parameter is valid only for TIM1 and TIM8. */
tushki7	0:60d829a0353a	143
tushki7	0:60d829a0353a	144	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
tushki7	0:60d829a0353a	145	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
tushki7	0:60d829a0353a	146	@note This parameter is valid only for TIM1 and TIM8. */
tushki7	0:60d829a0353a	147
tushki7	0:60d829a0353a	148	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
tushki7	0:60d829a0353a	149	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
tushki7	0:60d829a0353a	150
tushki7	0:60d829a0353a	151	uint32_t ICSelection; /*!< Specifies the input.
tushki7	0:60d829a0353a	152	This parameter can be a value of @ref TIM_Input_Capture_Selection */
tushki7	0:60d829a0353a	153
tushki7	0:60d829a0353a	154	uint32_t ICFilter; /*!< Specifies the input capture filter.
tushki7	0:60d829a0353a	155	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
tushki7	0:60d829a0353a	156	} TIM_OnePulse_InitTypeDef;
tushki7	0:60d829a0353a	157
tushki7	0:60d829a0353a	158
tushki7	0:60d829a0353a	159	/**
tushki7	0:60d829a0353a	160	* @brief TIM Input Capture Configuration Structure definition
tushki7	0:60d829a0353a	161	*/
tushki7	0:60d829a0353a	162	typedef struct
tushki7	0:60d829a0353a	163	{
tushki7	0:60d829a0353a	164	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
tushki7	0:60d829a0353a	165	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
tushki7	0:60d829a0353a	166
tushki7	0:60d829a0353a	167	uint32_t ICSelection; /*!< Specifies the input.
tushki7	0:60d829a0353a	168	This parameter can be a value of @ref TIM_Input_Capture_Selection */
tushki7	0:60d829a0353a	169
tushki7	0:60d829a0353a	170	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
tushki7	0:60d829a0353a	171	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
tushki7	0:60d829a0353a	172
tushki7	0:60d829a0353a	173	uint32_t ICFilter; /*!< Specifies the input capture filter.
tushki7	0:60d829a0353a	174	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
tushki7	0:60d829a0353a	175	} TIM_IC_InitTypeDef;
tushki7	0:60d829a0353a	176
tushki7	0:60d829a0353a	177	/**
tushki7	0:60d829a0353a	178	* @brief TIM Encoder Configuration Structure definition
tushki7	0:60d829a0353a	179	*/
tushki7	0:60d829a0353a	180	typedef struct
tushki7	0:60d829a0353a	181	{
tushki7	0:60d829a0353a	182	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
tushki7	0:60d829a0353a	183	This parameter can be a value of @ref TIM_Encoder_Mode */
tushki7	0:60d829a0353a	184
tushki7	0:60d829a0353a	185	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
tushki7	0:60d829a0353a	186	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
tushki7	0:60d829a0353a	187
tushki7	0:60d829a0353a	188	uint32_t IC1Selection; /*!< Specifies the input.
tushki7	0:60d829a0353a	189	This parameter can be a value of @ref TIM_Input_Capture_Selection */
tushki7	0:60d829a0353a	190
tushki7	0:60d829a0353a	191	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
tushki7	0:60d829a0353a	192	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
tushki7	0:60d829a0353a	193
tushki7	0:60d829a0353a	194	uint32_t IC1Filter; /*!< Specifies the input capture filter.
tushki7	0:60d829a0353a	195	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
tushki7	0:60d829a0353a	196
tushki7	0:60d829a0353a	197	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
tushki7	0:60d829a0353a	198	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
tushki7	0:60d829a0353a	199
tushki7	0:60d829a0353a	200	uint32_t IC2Selection; /*!< Specifies the input.
tushki7	0:60d829a0353a	201	This parameter can be a value of @ref TIM_Input_Capture_Selection */
tushki7	0:60d829a0353a	202
tushki7	0:60d829a0353a	203	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
tushki7	0:60d829a0353a	204	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
tushki7	0:60d829a0353a	205
tushki7	0:60d829a0353a	206	uint32_t IC2Filter; /*!< Specifies the input capture filter.
tushki7	0:60d829a0353a	207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
tushki7	0:60d829a0353a	208	} TIM_Encoder_InitTypeDef;
tushki7	0:60d829a0353a	209
tushki7	0:60d829a0353a	210
tushki7	0:60d829a0353a	211	/**
tushki7	0:60d829a0353a	212	* @brief Clock Configuration Handle Structure definition
tushki7	0:60d829a0353a	213	*/
tushki7	0:60d829a0353a	214	typedef struct
tushki7	0:60d829a0353a	215	{
tushki7	0:60d829a0353a	216	uint32_t ClockSource; /*!< TIM clock sources
tushki7	0:60d829a0353a	217	This parameter can be a value of @ref TIM_Clock_Source */
tushki7	0:60d829a0353a	218	uint32_t ClockPolarity; /*!< TIM clock polarity
tushki7	0:60d829a0353a	219	This parameter can be a value of @ref TIM_Clock_Polarity */
tushki7	0:60d829a0353a	220	uint32_t ClockPrescaler; /*!< TIM clock prescaler
tushki7	0:60d829a0353a	221	This parameter can be a value of @ref TIM_Clock_Prescaler */
tushki7	0:60d829a0353a	222	uint32_t ClockFilter; /*!< TIM clock filter
tushki7	0:60d829a0353a	223	This parameter can be a value of @ref TIM_Clock_Filter */
tushki7	0:60d829a0353a	224	}TIM_ClockConfigTypeDef;
tushki7	0:60d829a0353a	225
tushki7	0:60d829a0353a	226	/**
tushki7	0:60d829a0353a	227	* @brief Clear Input Configuration Handle Structure definition
tushki7	0:60d829a0353a	228	*/
tushki7	0:60d829a0353a	229	typedef struct
tushki7	0:60d829a0353a	230	{
tushki7	0:60d829a0353a	231	uint32_t ClearInputState; /*!< TIM clear Input state
tushki7	0:60d829a0353a	232	This parameter can be ENABLE or DISABLE */
tushki7	0:60d829a0353a	233	uint32_t ClearInputSource; /*!< TIM clear Input sources
tushki7	0:60d829a0353a	234	This parameter can be a value of @ref TIM_ClearInput_Source */
tushki7	0:60d829a0353a	235	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
tushki7	0:60d829a0353a	236	This parameter can be a value of @ref TIM_ClearInput_Polarity */
tushki7	0:60d829a0353a	237	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
tushki7	0:60d829a0353a	238	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
tushki7	0:60d829a0353a	239	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
tushki7	0:60d829a0353a	240	This parameter can be a value of @ref TIM_ClearInput_Filter */
tushki7	0:60d829a0353a	241	}TIM_ClearInputConfigTypeDef;
tushki7	0:60d829a0353a	242
tushki7	0:60d829a0353a	243	/**
tushki7	0:60d829a0353a	244	* @brief TIM Slave configuration Structure definition
tushki7	0:60d829a0353a	245	*/
tushki7	0:60d829a0353a	246	typedef struct {
tushki7	0:60d829a0353a	247	uint32_t SlaveMode; /*!< Slave mode selection
tushki7	0:60d829a0353a	248	This parameter can be a value of @ref TIM_Slave_Mode */
tushki7	0:60d829a0353a	249	uint32_t InputTrigger; /*!< Input Trigger source
tushki7	0:60d829a0353a	250	This parameter can be a value of @ref TIM_Trigger_Selection */
tushki7	0:60d829a0353a	251	uint32_t TriggerPolarity; /*!< Input Trigger polarity
tushki7	0:60d829a0353a	252	This parameter can be a value of @ref TIM_Trigger_Polarity */
tushki7	0:60d829a0353a	253	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
tushki7	0:60d829a0353a	254	This parameter can be a value of @ref TIM_Trigger_Prescaler */
tushki7	0:60d829a0353a	255	uint32_t TriggerFilter; /*!< Input trigger filter
tushki7	0:60d829a0353a	256	This parameter can be a value of @ref TIM_Trigger_Filter */
tushki7	0:60d829a0353a	257
tushki7	0:60d829a0353a	258	}TIM_SlaveConfigTypeDef;
tushki7	0:60d829a0353a	259
tushki7	0:60d829a0353a	260	/**
tushki7	0:60d829a0353a	261	* @brief HAL State structures definition
tushki7	0:60d829a0353a	262	*/
tushki7	0:60d829a0353a	263	typedef enum
tushki7	0:60d829a0353a	264	{
tushki7	0:60d829a0353a	265	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
tushki7	0:60d829a0353a	266	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
tushki7	0:60d829a0353a	267	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
tushki7	0:60d829a0353a	268	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
tushki7	0:60d829a0353a	269	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
tushki7	0:60d829a0353a	270	}HAL_TIM_StateTypeDef;
tushki7	0:60d829a0353a	271
tushki7	0:60d829a0353a	272	/**
tushki7	0:60d829a0353a	273	* @brief HAL Active channel structures definition
tushki7	0:60d829a0353a	274	*/
tushki7	0:60d829a0353a	275	typedef enum
tushki7	0:60d829a0353a	276	{
tushki7	0:60d829a0353a	277	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
tushki7	0:60d829a0353a	278	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
tushki7	0:60d829a0353a	279	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
tushki7	0:60d829a0353a	280	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
tushki7	0:60d829a0353a	281	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
tushki7	0:60d829a0353a	282	}HAL_TIM_ActiveChannel;
tushki7	0:60d829a0353a	283
tushki7	0:60d829a0353a	284	/**
tushki7	0:60d829a0353a	285	* @brief TIM Time Base Handle Structure definition
tushki7	0:60d829a0353a	286	*/
tushki7	0:60d829a0353a	287	typedef struct
tushki7	0:60d829a0353a	288	{
tushki7	0:60d829a0353a	289	TIM_TypeDef Instance; /!< Register base address */
tushki7	0:60d829a0353a	290	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
tushki7	0:60d829a0353a	291	HAL_TIM_ActiveChannel Channel; /!< Active channel /
tushki7	0:60d829a0353a	292	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
tushki7	0:60d829a0353a	293	This array is accessed by a @ref TIM_DMA_Handle_index */
tushki7	0:60d829a0353a	294	HAL_LockTypeDef Lock; /!< Locking object /
tushki7	0:60d829a0353a	295	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
tushki7	0:60d829a0353a	296	}TIM_HandleTypeDef;
tushki7	0:60d829a0353a	297
tushki7	0:60d829a0353a	298	/**
tushki7	0:60d829a0353a	299	* @}
tushki7	0:60d829a0353a	300	*/
tushki7	0:60d829a0353a	301
tushki7	0:60d829a0353a	302	/* Exported constants --------------------------------------------------------*/
tushki7	0:60d829a0353a	303	/** @defgroup TIM_Exported_Constants TIM Exported Constants
tushki7	0:60d829a0353a	304	* @{
tushki7	0:60d829a0353a	305	*/
tushki7	0:60d829a0353a	306
tushki7	0:60d829a0353a	307	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
tushki7	0:60d829a0353a	308	* @{
tushki7	0:60d829a0353a	309	*/
tushki7	0:60d829a0353a	310	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
tushki7	0:60d829a0353a	311	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
tushki7	0:60d829a0353a	312	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
tushki7	0:60d829a0353a	313	/**
tushki7	0:60d829a0353a	314	* @}
tushki7	0:60d829a0353a	315	*/
tushki7	0:60d829a0353a	316
tushki7	0:60d829a0353a	317	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
tushki7	0:60d829a0353a	318	* @{
tushki7	0:60d829a0353a	319	*/
tushki7	0:60d829a0353a	320	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
tushki7	0:60d829a0353a	321	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
tushki7	0:60d829a0353a	322	/**
tushki7	0:60d829a0353a	323	* @}
tushki7	0:60d829a0353a	324	*/
tushki7	0:60d829a0353a	325
tushki7	0:60d829a0353a	326	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
tushki7	0:60d829a0353a	327	* @{
tushki7	0:60d829a0353a	328	*/
tushki7	0:60d829a0353a	329	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
tushki7	0:60d829a0353a	330	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
tushki7	0:60d829a0353a	331	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
tushki7	0:60d829a0353a	332	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
tushki7	0:60d829a0353a	333	/**
tushki7	0:60d829a0353a	334	* @}
tushki7	0:60d829a0353a	335	*/
tushki7	0:60d829a0353a	336
tushki7	0:60d829a0353a	337	/** @defgroup TIM_Counter_Mode TIM Counter Mode
tushki7	0:60d829a0353a	338	* @{
tushki7	0:60d829a0353a	339	*/
tushki7	0:60d829a0353a	340
tushki7	0:60d829a0353a	341	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
tushki7	0:60d829a0353a	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
tushki7	0:60d829a0353a	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
tushki7	0:60d829a0353a	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
tushki7	0:60d829a0353a	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
tushki7	0:60d829a0353a	346
tushki7	0:60d829a0353a	347	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
tushki7	0:60d829a0353a	348	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
tushki7	0:60d829a0353a	349	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
tushki7	0:60d829a0353a	350	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
tushki7	0:60d829a0353a	351	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
tushki7	0:60d829a0353a	352	/**
tushki7	0:60d829a0353a	353	* @}
tushki7	0:60d829a0353a	354	*/
tushki7	0:60d829a0353a	355
tushki7	0:60d829a0353a	356	/** @defgroup TIM_ClockDivision TIM Clock Division
tushki7	0:60d829a0353a	357	* @{
tushki7	0:60d829a0353a	358	*/
tushki7	0:60d829a0353a	359
tushki7	0:60d829a0353a	360	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
tushki7	0:60d829a0353a	361	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
tushki7	0:60d829a0353a	362	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
tushki7	0:60d829a0353a	363
tushki7	0:60d829a0353a	364	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
tushki7	0:60d829a0353a	365	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
tushki7	0:60d829a0353a	366	((DIV) == TIM_CLOCKDIVISION_DIV4))
tushki7	0:60d829a0353a	367	/**
tushki7	0:60d829a0353a	368	* @}
tushki7	0:60d829a0353a	369	*/
tushki7	0:60d829a0353a	370
tushki7	0:60d829a0353a	371	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare & PWM modes
tushki7	0:60d829a0353a	372	* @{
tushki7	0:60d829a0353a	373	*/
tushki7	0:60d829a0353a	374
tushki7	0:60d829a0353a	375	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
tushki7	0:60d829a0353a	376	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
tushki7	0:60d829a0353a	377	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
tushki7	0:60d829a0353a	378	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
tushki7	0:60d829a0353a	379	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
tushki7	0:60d829a0353a	380	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
tushki7	0:60d829a0353a	381	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
tushki7	0:60d829a0353a	382	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
tushki7	0:60d829a0353a	383
tushki7	0:60d829a0353a	384	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
tushki7	0:60d829a0353a	385	((MODE) == TIM_OCMODE_PWM2))
tushki7	0:60d829a0353a	386
tushki7	0:60d829a0353a	387	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
tushki7	0:60d829a0353a	388	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
tushki7	0:60d829a0353a	389	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
tushki7	0:60d829a0353a	390	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
tushki7	0:60d829a0353a	391	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
tushki7	0:60d829a0353a	392	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
tushki7	0:60d829a0353a	393	/**
tushki7	0:60d829a0353a	394	* @}
tushki7	0:60d829a0353a	395	*/
tushki7	0:60d829a0353a	396
tushki7	0:60d829a0353a	397	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
tushki7	0:60d829a0353a	398	* @{
tushki7	0:60d829a0353a	399	*/
tushki7	0:60d829a0353a	400
tushki7	0:60d829a0353a	401	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	402	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
tushki7	0:60d829a0353a	403
tushki7	0:60d829a0353a	404	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
tushki7	0:60d829a0353a	405	((STATE) == TIM_OUTPUTSTATE_ENABLE))
tushki7	0:60d829a0353a	406	/**
tushki7	0:60d829a0353a	407	* @}
tushki7	0:60d829a0353a	408	*/
tushki7	0:60d829a0353a	409	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
tushki7	0:60d829a0353a	410	* @{
tushki7	0:60d829a0353a	411	*/
tushki7	0:60d829a0353a	412	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	413	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
tushki7	0:60d829a0353a	414
tushki7	0:60d829a0353a	415	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
tushki7	0:60d829a0353a	416	((STATE) == TIM_OCFAST_ENABLE))
tushki7	0:60d829a0353a	417	/**
tushki7	0:60d829a0353a	418	* @}
tushki7	0:60d829a0353a	419	*/
tushki7	0:60d829a0353a	420	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
tushki7	0:60d829a0353a	421	* @{
tushki7	0:60d829a0353a	422	*/
tushki7	0:60d829a0353a	423
tushki7	0:60d829a0353a	424	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	425	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
tushki7	0:60d829a0353a	426
tushki7	0:60d829a0353a	427	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
tushki7	0:60d829a0353a	428	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
tushki7	0:60d829a0353a	429	/**
tushki7	0:60d829a0353a	430	* @}
tushki7	0:60d829a0353a	431	*/
tushki7	0:60d829a0353a	432
tushki7	0:60d829a0353a	433	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
tushki7	0:60d829a0353a	434	* @{
tushki7	0:60d829a0353a	435	*/
tushki7	0:60d829a0353a	436
tushki7	0:60d829a0353a	437	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
tushki7	0:60d829a0353a	438	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
tushki7	0:60d829a0353a	439
tushki7	0:60d829a0353a	440	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
tushki7	0:60d829a0353a	441	((POLARITY) == TIM_OCPOLARITY_LOW))
tushki7	0:60d829a0353a	442	/**
tushki7	0:60d829a0353a	443	* @}
tushki7	0:60d829a0353a	444	*/
tushki7	0:60d829a0353a	445
tushki7	0:60d829a0353a	446	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
tushki7	0:60d829a0353a	447	* @{
tushki7	0:60d829a0353a	448	*/
tushki7	0:60d829a0353a	449
tushki7	0:60d829a0353a	450	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
tushki7	0:60d829a0353a	451	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
tushki7	0:60d829a0353a	452
tushki7	0:60d829a0353a	453	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
tushki7	0:60d829a0353a	454	((POLARITY) == TIM_OCNPOLARITY_LOW))
tushki7	0:60d829a0353a	455	/**
tushki7	0:60d829a0353a	456	* @}
tushki7	0:60d829a0353a	457	*/
tushki7	0:60d829a0353a	458
tushki7	0:60d829a0353a	459	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
tushki7	0:60d829a0353a	460	* @{
tushki7	0:60d829a0353a	461	*/
tushki7	0:60d829a0353a	462
tushki7	0:60d829a0353a	463	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
tushki7	0:60d829a0353a	464	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
tushki7	0:60d829a0353a	465	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
tushki7	0:60d829a0353a	466	((STATE) == TIM_OCIDLESTATE_RESET))
tushki7	0:60d829a0353a	467	/**
tushki7	0:60d829a0353a	468	* @}
tushki7	0:60d829a0353a	469	*/
tushki7	0:60d829a0353a	470
tushki7	0:60d829a0353a	471	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
tushki7	0:60d829a0353a	472	* @{
tushki7	0:60d829a0353a	473	*/
tushki7	0:60d829a0353a	474
tushki7	0:60d829a0353a	475	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
tushki7	0:60d829a0353a	476	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
tushki7	0:60d829a0353a	477	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
tushki7	0:60d829a0353a	478	((STATE) == TIM_OCNIDLESTATE_RESET))
tushki7	0:60d829a0353a	479	/**
tushki7	0:60d829a0353a	480	* @}
tushki7	0:60d829a0353a	481	*/
tushki7	0:60d829a0353a	482
tushki7	0:60d829a0353a	483	/** @defgroup TIM_Channel TIM Channel
tushki7	0:60d829a0353a	484	* @{
tushki7	0:60d829a0353a	485	*/
tushki7	0:60d829a0353a	486	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
tushki7	0:60d829a0353a	487	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
tushki7	0:60d829a0353a	488	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
tushki7	0:60d829a0353a	489	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
tushki7	0:60d829a0353a	490	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
tushki7	0:60d829a0353a	491
tushki7	0:60d829a0353a	492	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	493	((CHANNEL) == TIM_CHANNEL_2) \|\| \
tushki7	0:60d829a0353a	494	((CHANNEL) == TIM_CHANNEL_3) \|\| \
tushki7	0:60d829a0353a	495	((CHANNEL) == TIM_CHANNEL_4) \|\| \
tushki7	0:60d829a0353a	496	((CHANNEL) == TIM_CHANNEL_ALL))
tushki7	0:60d829a0353a	497
tushki7	0:60d829a0353a	498	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	499	((CHANNEL) == TIM_CHANNEL_2))
tushki7	0:60d829a0353a	500
tushki7	0:60d829a0353a	501	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	502	((CHANNEL) == TIM_CHANNEL_2))
tushki7	0:60d829a0353a	503
tushki7	0:60d829a0353a	504	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
tushki7	0:60d829a0353a	505	((CHANNEL) == TIM_CHANNEL_2) \|\| \
tushki7	0:60d829a0353a	506	((CHANNEL) == TIM_CHANNEL_3))
tushki7	0:60d829a0353a	507	/**
tushki7	0:60d829a0353a	508	* @}
tushki7	0:60d829a0353a	509	*/
tushki7	0:60d829a0353a	510
tushki7	0:60d829a0353a	511	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
tushki7	0:60d829a0353a	512	* @{
tushki7	0:60d829a0353a	513	*/
tushki7	0:60d829a0353a	514
tushki7	0:60d829a0353a	515	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
tushki7	0:60d829a0353a	516	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
tushki7	0:60d829a0353a	517	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
tushki7	0:60d829a0353a	518
tushki7	0:60d829a0353a	519	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
tushki7	0:60d829a0353a	520	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
tushki7	0:60d829a0353a	521	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
tushki7	0:60d829a0353a	522	/**
tushki7	0:60d829a0353a	523	* @}
tushki7	0:60d829a0353a	524	*/
tushki7	0:60d829a0353a	525
tushki7	0:60d829a0353a	526	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
tushki7	0:60d829a0353a	527	* @{
tushki7	0:60d829a0353a	528	*/
tushki7	0:60d829a0353a	529
tushki7	0:60d829a0353a	530	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
tushki7	0:60d829a0353a	531	connected to IC1, IC2, IC3 or IC4, respectively */
tushki7	0:60d829a0353a	532	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
tushki7	0:60d829a0353a	533	connected to IC2, IC1, IC4 or IC3, respectively */
tushki7	0:60d829a0353a	534	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
tushki7	0:60d829a0353a	535
tushki7	0:60d829a0353a	536	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
tushki7	0:60d829a0353a	537	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
tushki7	0:60d829a0353a	538	((SELECTION) == TIM_ICSELECTION_TRC))
tushki7	0:60d829a0353a	539	/**
tushki7	0:60d829a0353a	540	* @}
tushki7	0:60d829a0353a	541	*/
tushki7	0:60d829a0353a	542
tushki7	0:60d829a0353a	543	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
tushki7	0:60d829a0353a	544	* @{
tushki7	0:60d829a0353a	545	*/
tushki7	0:60d829a0353a	546
tushki7	0:60d829a0353a	547	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
tushki7	0:60d829a0353a	548	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
tushki7	0:60d829a0353a	549	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
tushki7	0:60d829a0353a	550	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
tushki7	0:60d829a0353a	551
tushki7	0:60d829a0353a	552	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
tushki7	0:60d829a0353a	553	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
tushki7	0:60d829a0353a	554	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
tushki7	0:60d829a0353a	555	((PRESCALER) == TIM_ICPSC_DIV8))
tushki7	0:60d829a0353a	556	/**
tushki7	0:60d829a0353a	557	* @}
tushki7	0:60d829a0353a	558	*/
tushki7	0:60d829a0353a	559
tushki7	0:60d829a0353a	560	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
tushki7	0:60d829a0353a	561	* @{
tushki7	0:60d829a0353a	562	*/
tushki7	0:60d829a0353a	563
tushki7	0:60d829a0353a	564	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
tushki7	0:60d829a0353a	565	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	566
tushki7	0:60d829a0353a	567	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
tushki7	0:60d829a0353a	568	((MODE) == TIM_OPMODE_REPETITIVE))
tushki7	0:60d829a0353a	569	/**
tushki7	0:60d829a0353a	570	* @}
tushki7	0:60d829a0353a	571	*/
tushki7	0:60d829a0353a	572	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
tushki7	0:60d829a0353a	573	* @{
tushki7	0:60d829a0353a	574	*/
tushki7	0:60d829a0353a	575	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
tushki7	0:60d829a0353a	576	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
tushki7	0:60d829a0353a	577	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
tushki7	0:60d829a0353a	578
tushki7	0:60d829a0353a	579	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
tushki7	0:60d829a0353a	580	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
tushki7	0:60d829a0353a	581	((MODE) == TIM_ENCODERMODE_TI12))
tushki7	0:60d829a0353a	582	/**
tushki7	0:60d829a0353a	583	* @}
tushki7	0:60d829a0353a	584	*/
tushki7	0:60d829a0353a	585	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
tushki7	0:60d829a0353a	586	* @{
tushki7	0:60d829a0353a	587	*/
tushki7	0:60d829a0353a	588	#define TIM_IT_UPDATE (TIM_DIER_UIE)
tushki7	0:60d829a0353a	589	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
tushki7	0:60d829a0353a	590	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
tushki7	0:60d829a0353a	591	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
tushki7	0:60d829a0353a	592	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
tushki7	0:60d829a0353a	593	#define TIM_IT_COM (TIM_DIER_COMIE)
tushki7	0:60d829a0353a	594	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
tushki7	0:60d829a0353a	595	#define TIM_IT_BREAK (TIM_DIER_BIE)
tushki7	0:60d829a0353a	596	/**
tushki7	0:60d829a0353a	597	* @}
tushki7	0:60d829a0353a	598	*/
tushki7	0:60d829a0353a	599
tushki7	0:60d829a0353a	600	/** @defgroup TIM_COMMUTATION TIM Commutation
tushki7	0:60d829a0353a	601	* @{
tushki7	0:60d829a0353a	602	*/
tushki7	0:60d829a0353a	603	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
tushki7	0:60d829a0353a	604	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	605
tushki7	0:60d829a0353a	606	/**
tushki7	0:60d829a0353a	607	* @}
tushki7	0:60d829a0353a	608	*/
tushki7	0:60d829a0353a	609	/** @defgroup TIM_DMA_sources TIM DMA Sources
tushki7	0:60d829a0353a	610	* @{
tushki7	0:60d829a0353a	611	*/
tushki7	0:60d829a0353a	612
tushki7	0:60d829a0353a	613	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
tushki7	0:60d829a0353a	614	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
tushki7	0:60d829a0353a	615	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
tushki7	0:60d829a0353a	616	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
tushki7	0:60d829a0353a	617	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
tushki7	0:60d829a0353a	618	#define TIM_DMA_COM (TIM_DIER_COMDE)
tushki7	0:60d829a0353a	619	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
tushki7	0:60d829a0353a	620
tushki7	0:60d829a0353a	621	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
tushki7	0:60d829a0353a	622	/**
tushki7	0:60d829a0353a	623	* @}
tushki7	0:60d829a0353a	624	*/
tushki7	0:60d829a0353a	625
tushki7	0:60d829a0353a	626	/** @defgroup TIM_Event_Source TIM Event Source
tushki7	0:60d829a0353a	627	* @{
tushki7	0:60d829a0353a	628	*/
tushki7	0:60d829a0353a	629	#define TIM_EventSource_Update TIM_EGR_UG
tushki7	0:60d829a0353a	630	#define TIM_EventSource_CC1 TIM_EGR_CC1G
tushki7	0:60d829a0353a	631	#define TIM_EventSource_CC2 TIM_EGR_CC2G
tushki7	0:60d829a0353a	632	#define TIM_EventSource_CC3 TIM_EGR_CC3G
tushki7	0:60d829a0353a	633	#define TIM_EventSource_CC4 TIM_EGR_CC4G
tushki7	0:60d829a0353a	634	#define TIM_EventSource_COM TIM_EGR_COMG
tushki7	0:60d829a0353a	635	#define TIM_EventSource_Trigger TIM_EGR_TG
tushki7	0:60d829a0353a	636	#define TIM_EventSource_Break TIM_EGR_BG
tushki7	0:60d829a0353a	637
tushki7	0:60d829a0353a	638	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
tushki7	0:60d829a0353a	639	/**
tushki7	0:60d829a0353a	640	* @}
tushki7	0:60d829a0353a	641	*/
tushki7	0:60d829a0353a	642
tushki7	0:60d829a0353a	643	/** @defgroup TIM_Flag_definition TIM Flag Definition
tushki7	0:60d829a0353a	644	* @{
tushki7	0:60d829a0353a	645	*/
tushki7	0:60d829a0353a	646
tushki7	0:60d829a0353a	647	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
tushki7	0:60d829a0353a	648	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
tushki7	0:60d829a0353a	649	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
tushki7	0:60d829a0353a	650	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
tushki7	0:60d829a0353a	651	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
tushki7	0:60d829a0353a	652	#define TIM_FLAG_COM (TIM_SR_COMIF)
tushki7	0:60d829a0353a	653	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
tushki7	0:60d829a0353a	654	#define TIM_FLAG_BREAK (TIM_SR_BIF)
tushki7	0:60d829a0353a	655	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
tushki7	0:60d829a0353a	656	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
tushki7	0:60d829a0353a	657	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
tushki7	0:60d829a0353a	658	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
tushki7	0:60d829a0353a	659
tushki7	0:60d829a0353a	660	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
tushki7	0:60d829a0353a	661	((FLAG) == TIM_FLAG_CC1) \|\| \
tushki7	0:60d829a0353a	662	((FLAG) == TIM_FLAG_CC2) \|\| \
tushki7	0:60d829a0353a	663	((FLAG) == TIM_FLAG_CC3) \|\| \
tushki7	0:60d829a0353a	664	((FLAG) == TIM_FLAG_CC4) \|\| \
tushki7	0:60d829a0353a	665	((FLAG) == TIM_FLAG_COM) \|\| \
tushki7	0:60d829a0353a	666	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
tushki7	0:60d829a0353a	667	((FLAG) == TIM_FLAG_BREAK) \|\| \
tushki7	0:60d829a0353a	668	((FLAG) == TIM_FLAG_CC1OF) \|\| \
tushki7	0:60d829a0353a	669	((FLAG) == TIM_FLAG_CC2OF) \|\| \
tushki7	0:60d829a0353a	670	((FLAG) == TIM_FLAG_CC3OF) \|\| \
tushki7	0:60d829a0353a	671	((FLAG) == TIM_FLAG_CC4OF))
tushki7	0:60d829a0353a	672	/**
tushki7	0:60d829a0353a	673	* @}
tushki7	0:60d829a0353a	674	*/
tushki7	0:60d829a0353a	675
tushki7	0:60d829a0353a	676	/** @defgroup TIM_Clock_Source TIM Clock Source
tushki7	0:60d829a0353a	677	* @{
tushki7	0:60d829a0353a	678	*/
tushki7	0:60d829a0353a	679	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
tushki7	0:60d829a0353a	680	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
tushki7	0:60d829a0353a	681	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
tushki7	0:60d829a0353a	682	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
tushki7	0:60d829a0353a	683	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
tushki7	0:60d829a0353a	684	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
tushki7	0:60d829a0353a	685	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
tushki7	0:60d829a0353a	686	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
tushki7	0:60d829a0353a	687	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
tushki7	0:60d829a0353a	688	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
tushki7	0:60d829a0353a	689
tushki7	0:60d829a0353a	690	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
tushki7	0:60d829a0353a	691	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
tushki7	0:60d829a0353a	692	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
tushki7	0:60d829a0353a	693	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
tushki7	0:60d829a0353a	694	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
tushki7	0:60d829a0353a	695	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
tushki7	0:60d829a0353a	696	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
tushki7	0:60d829a0353a	697	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
tushki7	0:60d829a0353a	698	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
tushki7	0:60d829a0353a	699	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
tushki7	0:60d829a0353a	700	/**
tushki7	0:60d829a0353a	701	* @}
tushki7	0:60d829a0353a	702	*/
tushki7	0:60d829a0353a	703
tushki7	0:60d829a0353a	704	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
tushki7	0:60d829a0353a	705	* @{
tushki7	0:60d829a0353a	706	*/
tushki7	0:60d829a0353a	707	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
tushki7	0:60d829a0353a	708	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
tushki7	0:60d829a0353a	709	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
tushki7	0:60d829a0353a	710	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
tushki7	0:60d829a0353a	711	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
tushki7	0:60d829a0353a	712
tushki7	0:60d829a0353a	713	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
tushki7	0:60d829a0353a	714	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
tushki7	0:60d829a0353a	715	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
tushki7	0:60d829a0353a	716	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
tushki7	0:60d829a0353a	717	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
tushki7	0:60d829a0353a	718	/**
tushki7	0:60d829a0353a	719	* @}
tushki7	0:60d829a0353a	720	*/
tushki7	0:60d829a0353a	721	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
tushki7	0:60d829a0353a	722	* @{
tushki7	0:60d829a0353a	723	*/
tushki7	0:60d829a0353a	724	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
tushki7	0:60d829a0353a	725	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
tushki7	0:60d829a0353a	726	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
tushki7	0:60d829a0353a	727	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
tushki7	0:60d829a0353a	728
tushki7	0:60d829a0353a	729	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
tushki7	0:60d829a0353a	730	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
tushki7	0:60d829a0353a	731	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
tushki7	0:60d829a0353a	732	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
tushki7	0:60d829a0353a	733	/**
tushki7	0:60d829a0353a	734	* @}
tushki7	0:60d829a0353a	735	*/
tushki7	0:60d829a0353a	736	/** @defgroup TIM_Clock_Filter TIM Clock Filter
tushki7	0:60d829a0353a	737	* @{
tushki7	0:60d829a0353a	738	*/
tushki7	0:60d829a0353a	739
tushki7	0:60d829a0353a	740	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
tushki7	0:60d829a0353a	741	/**
tushki7	0:60d829a0353a	742	* @}
tushki7	0:60d829a0353a	743	*/
tushki7	0:60d829a0353a	744
tushki7	0:60d829a0353a	745	/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
tushki7	0:60d829a0353a	746	* @{
tushki7	0:60d829a0353a	747	*/
tushki7	0:60d829a0353a	748	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
tushki7	0:60d829a0353a	749	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	750
tushki7	0:60d829a0353a	751	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
tushki7	0:60d829a0353a	752	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
tushki7	0:60d829a0353a	753	/**
tushki7	0:60d829a0353a	754	* @}
tushki7	0:60d829a0353a	755	*/
tushki7	0:60d829a0353a	756
tushki7	0:60d829a0353a	757	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
tushki7	0:60d829a0353a	758	* @{
tushki7	0:60d829a0353a	759	*/
tushki7	0:60d829a0353a	760	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
tushki7	0:60d829a0353a	761	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
tushki7	0:60d829a0353a	762
tushki7	0:60d829a0353a	763
tushki7	0:60d829a0353a	764	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
tushki7	0:60d829a0353a	765	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
tushki7	0:60d829a0353a	766	/**
tushki7	0:60d829a0353a	767	* @}
tushki7	0:60d829a0353a	768	*/
tushki7	0:60d829a0353a	769
tushki7	0:60d829a0353a	770	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
tushki7	0:60d829a0353a	771	* @{
tushki7	0:60d829a0353a	772	*/
tushki7	0:60d829a0353a	773	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
tushki7	0:60d829a0353a	774	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
tushki7	0:60d829a0353a	775	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
tushki7	0:60d829a0353a	776	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
tushki7	0:60d829a0353a	777
tushki7	0:60d829a0353a	778	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
tushki7	0:60d829a0353a	779	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
tushki7	0:60d829a0353a	780	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
tushki7	0:60d829a0353a	781	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
tushki7	0:60d829a0353a	782	/**
tushki7	0:60d829a0353a	783	* @}
tushki7	0:60d829a0353a	784	*/
tushki7	0:60d829a0353a	785
tushki7	0:60d829a0353a	786	/** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter
tushki7	0:60d829a0353a	787	* @{
tushki7	0:60d829a0353a	788	*/
tushki7	0:60d829a0353a	789
tushki7	0:60d829a0353a	790	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
tushki7	0:60d829a0353a	791	/**
tushki7	0:60d829a0353a	792	* @}
tushki7	0:60d829a0353a	793	*/
tushki7	0:60d829a0353a	794
tushki7	0:60d829a0353a	795	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
tushki7	0:60d829a0353a	796	* @{
tushki7	0:60d829a0353a	797	*/
tushki7	0:60d829a0353a	798	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
tushki7	0:60d829a0353a	799	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	800
tushki7	0:60d829a0353a	801	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
tushki7	0:60d829a0353a	802	((STATE) == TIM_OSSR_DISABLE))
tushki7	0:60d829a0353a	803	/**
tushki7	0:60d829a0353a	804	* @}
tushki7	0:60d829a0353a	805	*/
tushki7	0:60d829a0353a	806
tushki7	0:60d829a0353a	807	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
tushki7	0:60d829a0353a	808	* @{
tushki7	0:60d829a0353a	809	*/
tushki7	0:60d829a0353a	810	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
tushki7	0:60d829a0353a	811	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	812
tushki7	0:60d829a0353a	813	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
tushki7	0:60d829a0353a	814	((STATE) == TIM_OSSI_DISABLE))
tushki7	0:60d829a0353a	815	/**
tushki7	0:60d829a0353a	816	* @}
tushki7	0:60d829a0353a	817	*/
tushki7	0:60d829a0353a	818	/** @defgroup TIM_Lock_level TIM Lock Configuration
tushki7	0:60d829a0353a	819	* @{
tushki7	0:60d829a0353a	820	*/
tushki7	0:60d829a0353a	821	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
tushki7	0:60d829a0353a	822	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
tushki7	0:60d829a0353a	823	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
tushki7	0:60d829a0353a	824	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
tushki7	0:60d829a0353a	825
tushki7	0:60d829a0353a	826	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
tushki7	0:60d829a0353a	827	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
tushki7	0:60d829a0353a	828	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
tushki7	0:60d829a0353a	829	((LEVEL) == TIM_LOCKLEVEL_3))
tushki7	0:60d829a0353a	830	/**
tushki7	0:60d829a0353a	831	* @}
tushki7	0:60d829a0353a	832	*/
tushki7	0:60d829a0353a	833	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
tushki7	0:60d829a0353a	834	* @{
tushki7	0:60d829a0353a	835	*/
tushki7	0:60d829a0353a	836	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
tushki7	0:60d829a0353a	837	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	838
tushki7	0:60d829a0353a	839	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
tushki7	0:60d829a0353a	840	((STATE) == TIM_BREAK_DISABLE))
tushki7	0:60d829a0353a	841	/**
tushki7	0:60d829a0353a	842	* @}
tushki7	0:60d829a0353a	843	*/
tushki7	0:60d829a0353a	844	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
tushki7	0:60d829a0353a	845	* @{
tushki7	0:60d829a0353a	846	*/
tushki7	0:60d829a0353a	847	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
tushki7	0:60d829a0353a	848	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
tushki7	0:60d829a0353a	849
tushki7	0:60d829a0353a	850	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
tushki7	0:60d829a0353a	851	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
tushki7	0:60d829a0353a	852	/**
tushki7	0:60d829a0353a	853	* @}
tushki7	0:60d829a0353a	854	*/
tushki7	0:60d829a0353a	855	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
tushki7	0:60d829a0353a	856	* @{
tushki7	0:60d829a0353a	857	*/
tushki7	0:60d829a0353a	858	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
tushki7	0:60d829a0353a	859	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	860
tushki7	0:60d829a0353a	861	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
tushki7	0:60d829a0353a	862	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
tushki7	0:60d829a0353a	863	/**
tushki7	0:60d829a0353a	864	* @}
tushki7	0:60d829a0353a	865	*/
tushki7	0:60d829a0353a	866
tushki7	0:60d829a0353a	867	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
tushki7	0:60d829a0353a	868	* @{
tushki7	0:60d829a0353a	869	*/
tushki7	0:60d829a0353a	870	#define TIM_TRGO_RESET ((uint32_t)0x0000)
tushki7	0:60d829a0353a	871	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
tushki7	0:60d829a0353a	872	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
tushki7	0:60d829a0353a	873	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
tushki7	0:60d829a0353a	874	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
tushki7	0:60d829a0353a	875	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
tushki7	0:60d829a0353a	876	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
tushki7	0:60d829a0353a	877	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
tushki7	0:60d829a0353a	878
tushki7	0:60d829a0353a	879	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
tushki7	0:60d829a0353a	880	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
tushki7	0:60d829a0353a	881	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
tushki7	0:60d829a0353a	882	((SOURCE) == TIM_TRGO_OC1) \|\| \
tushki7	0:60d829a0353a	883	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
tushki7	0:60d829a0353a	884	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
tushki7	0:60d829a0353a	885	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
tushki7	0:60d829a0353a	886	((SOURCE) == TIM_TRGO_OC4REF))
tushki7	0:60d829a0353a	887
tushki7	0:60d829a0353a	888
tushki7	0:60d829a0353a	889	/**
tushki7	0:60d829a0353a	890	* @}
tushki7	0:60d829a0353a	891	*/
tushki7	0:60d829a0353a	892
tushki7	0:60d829a0353a	893	/** @defgroup TIM_Slave_Mode TIM Slave Mode
tushki7	0:60d829a0353a	894	* @{
tushki7	0:60d829a0353a	895	*/
tushki7	0:60d829a0353a	896
tushki7	0:60d829a0353a	897	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	898	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
tushki7	0:60d829a0353a	899	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
tushki7	0:60d829a0353a	900	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
tushki7	0:60d829a0353a	901	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
tushki7	0:60d829a0353a	902
tushki7	0:60d829a0353a	903	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
tushki7	0:60d829a0353a	904	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
tushki7	0:60d829a0353a	905	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
tushki7	0:60d829a0353a	906	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
tushki7	0:60d829a0353a	907	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
tushki7	0:60d829a0353a	908	/**
tushki7	0:60d829a0353a	909	* @}
tushki7	0:60d829a0353a	910	*/
tushki7	0:60d829a0353a	911
tushki7	0:60d829a0353a	912	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
tushki7	0:60d829a0353a	913	* @{
tushki7	0:60d829a0353a	914	*/
tushki7	0:60d829a0353a	915
tushki7	0:60d829a0353a	916	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
tushki7	0:60d829a0353a	917	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	918
tushki7	0:60d829a0353a	919	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
tushki7	0:60d829a0353a	920	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
tushki7	0:60d829a0353a	921	/**
tushki7	0:60d829a0353a	922	* @}
tushki7	0:60d829a0353a	923	*/
tushki7	0:60d829a0353a	924	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
tushki7	0:60d829a0353a	925	* @{
tushki7	0:60d829a0353a	926	*/
tushki7	0:60d829a0353a	927
tushki7	0:60d829a0353a	928	#define TIM_TS_ITR0 ((uint32_t)0x0000)
tushki7	0:60d829a0353a	929	#define TIM_TS_ITR1 ((uint32_t)0x0010)
tushki7	0:60d829a0353a	930	#define TIM_TS_ITR2 ((uint32_t)0x0020)
tushki7	0:60d829a0353a	931	#define TIM_TS_ITR3 ((uint32_t)0x0030)
tushki7	0:60d829a0353a	932	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
tushki7	0:60d829a0353a	933	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
tushki7	0:60d829a0353a	934	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
tushki7	0:60d829a0353a	935	#define TIM_TS_ETRF ((uint32_t)0x0070)
tushki7	0:60d829a0353a	936	#define TIM_TS_NONE ((uint32_t)0xFFFF)
tushki7	0:60d829a0353a	937
tushki7	0:60d829a0353a	938	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
tushki7	0:60d829a0353a	939	((SELECTION) == TIM_TS_ITR1) \|\| \
tushki7	0:60d829a0353a	940	((SELECTION) == TIM_TS_ITR2) \|\| \
tushki7	0:60d829a0353a	941	((SELECTION) == TIM_TS_ITR3) \|\| \
tushki7	0:60d829a0353a	942	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
tushki7	0:60d829a0353a	943	((SELECTION) == TIM_TS_TI1FP1) \|\| \
tushki7	0:60d829a0353a	944	((SELECTION) == TIM_TS_TI2FP2) \|\| \
tushki7	0:60d829a0353a	945	((SELECTION) == TIM_TS_ETRF))
tushki7	0:60d829a0353a	946
tushki7	0:60d829a0353a	947	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
tushki7	0:60d829a0353a	948	((SELECTION) == TIM_TS_ITR1) \|\| \
tushki7	0:60d829a0353a	949	((SELECTION) == TIM_TS_ITR2) \|\| \
tushki7	0:60d829a0353a	950	((SELECTION) == TIM_TS_ITR3))
tushki7	0:60d829a0353a	951
tushki7	0:60d829a0353a	952	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
tushki7	0:60d829a0353a	953	((SELECTION) == TIM_TS_ITR1) \|\| \
tushki7	0:60d829a0353a	954	((SELECTION) == TIM_TS_ITR2) \|\| \
tushki7	0:60d829a0353a	955	((SELECTION) == TIM_TS_ITR3) \|\| \
tushki7	0:60d829a0353a	956	((SELECTION) == TIM_TS_NONE))
tushki7	0:60d829a0353a	957	/**
tushki7	0:60d829a0353a	958	* @}
tushki7	0:60d829a0353a	959	*/
tushki7	0:60d829a0353a	960
tushki7	0:60d829a0353a	961	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
tushki7	0:60d829a0353a	962	* @{
tushki7	0:60d829a0353a	963	*/
tushki7	0:60d829a0353a	964	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
tushki7	0:60d829a0353a	965	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
tushki7	0:60d829a0353a	966	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
tushki7	0:60d829a0353a	967	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
tushki7	0:60d829a0353a	968	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
tushki7	0:60d829a0353a	969
tushki7	0:60d829a0353a	970	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
tushki7	0:60d829a0353a	971	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
tushki7	0:60d829a0353a	972	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
tushki7	0:60d829a0353a	973	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
tushki7	0:60d829a0353a	974	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
tushki7	0:60d829a0353a	975	/**
tushki7	0:60d829a0353a	976	* @}
tushki7	0:60d829a0353a	977	*/
tushki7	0:60d829a0353a	978
tushki7	0:60d829a0353a	979	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
tushki7	0:60d829a0353a	980	* @{
tushki7	0:60d829a0353a	981	*/
tushki7	0:60d829a0353a	982	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
tushki7	0:60d829a0353a	983	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
tushki7	0:60d829a0353a	984	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
tushki7	0:60d829a0353a	985	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
tushki7	0:60d829a0353a	986
tushki7	0:60d829a0353a	987	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
tushki7	0:60d829a0353a	988	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
tushki7	0:60d829a0353a	989	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
tushki7	0:60d829a0353a	990	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
tushki7	0:60d829a0353a	991	/**
tushki7	0:60d829a0353a	992	* @}
tushki7	0:60d829a0353a	993	*/
tushki7	0:60d829a0353a	994
tushki7	0:60d829a0353a	995	/** @defgroup TIM_Trigger_Filter TIM Trigger Filter
tushki7	0:60d829a0353a	996	* @{
tushki7	0:60d829a0353a	997	*/
tushki7	0:60d829a0353a	998
tushki7	0:60d829a0353a	999	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
tushki7	0:60d829a0353a	1000	/**
tushki7	0:60d829a0353a	1001	* @}
tushki7	0:60d829a0353a	1002	*/
tushki7	0:60d829a0353a	1003
tushki7	0:60d829a0353a	1004	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
tushki7	0:60d829a0353a	1005	* @{
tushki7	0:60d829a0353a	1006	*/
tushki7	0:60d829a0353a	1007
tushki7	0:60d829a0353a	1008	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
tushki7	0:60d829a0353a	1009	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
tushki7	0:60d829a0353a	1010
tushki7	0:60d829a0353a	1011	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
tushki7	0:60d829a0353a	1012	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
tushki7	0:60d829a0353a	1013
tushki7	0:60d829a0353a	1014	/**
tushki7	0:60d829a0353a	1015	* @}
tushki7	0:60d829a0353a	1016	*/
tushki7	0:60d829a0353a	1017
tushki7	0:60d829a0353a	1018	/** @defgroup TIM_DMA_Base_address TIM DMA Base address
tushki7	0:60d829a0353a	1019	* @{
tushki7	0:60d829a0353a	1020	*/
tushki7	0:60d829a0353a	1021	#define TIM_DMABase_CR1 (0x00000000)
tushki7	0:60d829a0353a	1022	#define TIM_DMABase_CR2 (0x00000001)
tushki7	0:60d829a0353a	1023	#define TIM_DMABase_SMCR (0x00000002)
tushki7	0:60d829a0353a	1024	#define TIM_DMABase_DIER (0x00000003)
tushki7	0:60d829a0353a	1025	#define TIM_DMABase_SR (0x00000004)
tushki7	0:60d829a0353a	1026	#define TIM_DMABase_EGR (0x00000005)
tushki7	0:60d829a0353a	1027	#define TIM_DMABase_CCMR1 (0x00000006)
tushki7	0:60d829a0353a	1028	#define TIM_DMABase_CCMR2 (0x00000007)
tushki7	0:60d829a0353a	1029	#define TIM_DMABase_CCER (0x00000008)
tushki7	0:60d829a0353a	1030	#define TIM_DMABase_CNT (0x00000009)
tushki7	0:60d829a0353a	1031	#define TIM_DMABase_PSC (0x0000000A)
tushki7	0:60d829a0353a	1032	#define TIM_DMABase_ARR (0x0000000B)
tushki7	0:60d829a0353a	1033	#define TIM_DMABase_RCR (0x0000000C)
tushki7	0:60d829a0353a	1034	#define TIM_DMABase_CCR1 (0x0000000D)
tushki7	0:60d829a0353a	1035	#define TIM_DMABase_CCR2 (0x0000000E)
tushki7	0:60d829a0353a	1036	#define TIM_DMABase_CCR3 (0x0000000F)
tushki7	0:60d829a0353a	1037	#define TIM_DMABase_CCR4 (0x00000010)
tushki7	0:60d829a0353a	1038	#define TIM_DMABase_BDTR (0x00000011)
tushki7	0:60d829a0353a	1039	#define TIM_DMABase_DCR (0x00000012)
tushki7	0:60d829a0353a	1040	#define TIM_DMABase_OR (0x00000013)
tushki7	0:60d829a0353a	1041
tushki7	0:60d829a0353a	1042	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
tushki7	0:60d829a0353a	1043	((BASE) == TIM_DMABase_CR2) \|\| \
tushki7	0:60d829a0353a	1044	((BASE) == TIM_DMABase_SMCR) \|\| \
tushki7	0:60d829a0353a	1045	((BASE) == TIM_DMABase_DIER) \|\| \
tushki7	0:60d829a0353a	1046	((BASE) == TIM_DMABase_SR) \|\| \
tushki7	0:60d829a0353a	1047	((BASE) == TIM_DMABase_EGR) \|\| \
tushki7	0:60d829a0353a	1048	((BASE) == TIM_DMABase_CCMR1) \|\| \
tushki7	0:60d829a0353a	1049	((BASE) == TIM_DMABase_CCMR2) \|\| \
tushki7	0:60d829a0353a	1050	((BASE) == TIM_DMABase_CCER) \|\| \
tushki7	0:60d829a0353a	1051	((BASE) == TIM_DMABase_CNT) \|\| \
tushki7	0:60d829a0353a	1052	((BASE) == TIM_DMABase_PSC) \|\| \
tushki7	0:60d829a0353a	1053	((BASE) == TIM_DMABase_ARR) \|\| \
tushki7	0:60d829a0353a	1054	((BASE) == TIM_DMABase_RCR) \|\| \
tushki7	0:60d829a0353a	1055	((BASE) == TIM_DMABase_CCR1) \|\| \
tushki7	0:60d829a0353a	1056	((BASE) == TIM_DMABase_CCR2) \|\| \
tushki7	0:60d829a0353a	1057	((BASE) == TIM_DMABase_CCR3) \|\| \
tushki7	0:60d829a0353a	1058	((BASE) == TIM_DMABase_CCR4) \|\| \
tushki7	0:60d829a0353a	1059	((BASE) == TIM_DMABase_BDTR) \|\| \
tushki7	0:60d829a0353a	1060	((BASE) == TIM_DMABase_DCR) \|\| \
tushki7	0:60d829a0353a	1061	((BASE) == TIM_DMABase_OR))
tushki7	0:60d829a0353a	1062	/**
tushki7	0:60d829a0353a	1063	* @}
tushki7	0:60d829a0353a	1064	*/
tushki7	0:60d829a0353a	1065
tushki7	0:60d829a0353a	1066	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
tushki7	0:60d829a0353a	1067	* @{
tushki7	0:60d829a0353a	1068	*/
tushki7	0:60d829a0353a	1069
tushki7	0:60d829a0353a	1070	#define TIM_DMABurstLength_1Transfer (0x00000000)
tushki7	0:60d829a0353a	1071	#define TIM_DMABurstLength_2Transfers (0x00000100)
tushki7	0:60d829a0353a	1072	#define TIM_DMABurstLength_3Transfers (0x00000200)
tushki7	0:60d829a0353a	1073	#define TIM_DMABurstLength_4Transfers (0x00000300)
tushki7	0:60d829a0353a	1074	#define TIM_DMABurstLength_5Transfers (0x00000400)
tushki7	0:60d829a0353a	1075	#define TIM_DMABurstLength_6Transfers (0x00000500)
tushki7	0:60d829a0353a	1076	#define TIM_DMABurstLength_7Transfers (0x00000600)
tushki7	0:60d829a0353a	1077	#define TIM_DMABurstLength_8Transfers (0x00000700)
tushki7	0:60d829a0353a	1078	#define TIM_DMABurstLength_9Transfers (0x00000800)
tushki7	0:60d829a0353a	1079	#define TIM_DMABurstLength_10Transfers (0x00000900)
tushki7	0:60d829a0353a	1080	#define TIM_DMABurstLength_11Transfers (0x00000A00)
tushki7	0:60d829a0353a	1081	#define TIM_DMABurstLength_12Transfers (0x00000B00)
tushki7	0:60d829a0353a	1082	#define TIM_DMABurstLength_13Transfers (0x00000C00)
tushki7	0:60d829a0353a	1083	#define TIM_DMABurstLength_14Transfers (0x00000D00)
tushki7	0:60d829a0353a	1084	#define TIM_DMABurstLength_15Transfers (0x00000E00)
tushki7	0:60d829a0353a	1085	#define TIM_DMABurstLength_16Transfers (0x00000F00)
tushki7	0:60d829a0353a	1086	#define TIM_DMABurstLength_17Transfers (0x00001000)
tushki7	0:60d829a0353a	1087	#define TIM_DMABurstLength_18Transfers (0x00001100)
tushki7	0:60d829a0353a	1088
tushki7	0:60d829a0353a	1089	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
tushki7	0:60d829a0353a	1090	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
tushki7	0:60d829a0353a	1091	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
tushki7	0:60d829a0353a	1092	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
tushki7	0:60d829a0353a	1093	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
tushki7	0:60d829a0353a	1094	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
tushki7	0:60d829a0353a	1095	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
tushki7	0:60d829a0353a	1096	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
tushki7	0:60d829a0353a	1097	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
tushki7	0:60d829a0353a	1098	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
tushki7	0:60d829a0353a	1099	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
tushki7	0:60d829a0353a	1100	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
tushki7	0:60d829a0353a	1101	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
tushki7	0:60d829a0353a	1102	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
tushki7	0:60d829a0353a	1103	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
tushki7	0:60d829a0353a	1104	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
tushki7	0:60d829a0353a	1105	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
tushki7	0:60d829a0353a	1106	((LENGTH) == TIM_DMABurstLength_18Transfers))
tushki7	0:60d829a0353a	1107	/**
tushki7	0:60d829a0353a	1108	* @}
tushki7	0:60d829a0353a	1109	*/
tushki7	0:60d829a0353a	1110
tushki7	0:60d829a0353a	1111	/** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value
tushki7	0:60d829a0353a	1112	* @{
tushki7	0:60d829a0353a	1113	*/
tushki7	0:60d829a0353a	1114
tushki7	0:60d829a0353a	1115	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
tushki7	0:60d829a0353a	1116	/**
tushki7	0:60d829a0353a	1117	* @}
tushki7	0:60d829a0353a	1118	*/
tushki7	0:60d829a0353a	1119
tushki7	0:60d829a0353a	1120	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
tushki7	0:60d829a0353a	1121	* @{
tushki7	0:60d829a0353a	1122	*/
tushki7	0:60d829a0353a	1123	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
tushki7	0:60d829a0353a	1124	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
tushki7	0:60d829a0353a	1125	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
tushki7	0:60d829a0353a	1126	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
tushki7	0:60d829a0353a	1127	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
tushki7	0:60d829a0353a	1128	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
tushki7	0:60d829a0353a	1129	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
tushki7	0:60d829a0353a	1130	/**
tushki7	0:60d829a0353a	1131	* @}
tushki7	0:60d829a0353a	1132	*/
tushki7	0:60d829a0353a	1133
tushki7	0:60d829a0353a	1134	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
tushki7	0:60d829a0353a	1135	* @{
tushki7	0:60d829a0353a	1136	*/
tushki7	0:60d829a0353a	1137	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
tushki7	0:60d829a0353a	1138	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	1139	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
tushki7	0:60d829a0353a	1140	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
tushki7	0:60d829a0353a	1141	/**
tushki7	0:60d829a0353a	1142	* @}
tushki7	0:60d829a0353a	1143	*/
tushki7	0:60d829a0353a	1144
tushki7	0:60d829a0353a	1145	/**
tushki7	0:60d829a0353a	1146	* @}
tushki7	0:60d829a0353a	1147	*/
tushki7	0:60d829a0353a	1148
tushki7	0:60d829a0353a	1149	/* Exported macros -----------------------------------------------------------*/
tushki7	0:60d829a0353a	1150	/** @defgroup TIM_Exported_Macros TIM Exported Macros
tushki7	0:60d829a0353a	1151	* @{
tushki7	0:60d829a0353a	1152	*/
tushki7	0:60d829a0353a	1153
tushki7	0:60d829a0353a	1154	/** @brief Reset TIM handle state
tushki7	0:60d829a0353a	1155	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1156	* @retval None
tushki7	0:60d829a0353a	1157	*/
tushki7	0:60d829a0353a	1158	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
tushki7	0:60d829a0353a	1159
tushki7	0:60d829a0353a	1160	/**
tushki7	0:60d829a0353a	1161	* @brief Enable the TIM peripheral.
tushki7	0:60d829a0353a	1162	* @param __HANDLE__: TIM handle
tushki7	0:60d829a0353a	1163	* @retval None
tushki7	0:60d829a0353a	1164	*/
tushki7	0:60d829a0353a	1165	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
tushki7	0:60d829a0353a	1166
tushki7	0:60d829a0353a	1167	/**
tushki7	0:60d829a0353a	1168	* @brief Enable the TIM main Output.
tushki7	0:60d829a0353a	1169	* @param __HANDLE__: TIM handle
tushki7	0:60d829a0353a	1170	* @retval None
tushki7	0:60d829a0353a	1171	*/
tushki7	0:60d829a0353a	1172	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
tushki7	0:60d829a0353a	1173
tushki7	0:60d829a0353a	1174	/**
tushki7	0:60d829a0353a	1175	* @brief Disable the TIM peripheral.
tushki7	0:60d829a0353a	1176	* @param __HANDLE__: TIM handle
tushki7	0:60d829a0353a	1177	* @retval None
tushki7	0:60d829a0353a	1178	*/
tushki7	0:60d829a0353a	1179	#define __HAL_TIM_DISABLE(__HANDLE__) \
tushki7	0:60d829a0353a	1180	do { \
tushki7	0:60d829a0353a	1181	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
tushki7	0:60d829a0353a	1182	{ \
tushki7	0:60d829a0353a	1183	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
tushki7	0:60d829a0353a	1184	{ \
tushki7	0:60d829a0353a	1185	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
tushki7	0:60d829a0353a	1186	} \
tushki7	0:60d829a0353a	1187	} \
tushki7	0:60d829a0353a	1188	} while(0)
tushki7	0:60d829a0353a	1189	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
tushki7	0:60d829a0353a	1190	channels have been disabled */
tushki7	0:60d829a0353a	1191	/**
tushki7	0:60d829a0353a	1192	* @brief Disable the TIM main Output.
tushki7	0:60d829a0353a	1193	* @param __HANDLE__: TIM handle
tushki7	0:60d829a0353a	1194	* @retval None
tushki7	0:60d829a0353a	1195	*/
tushki7	0:60d829a0353a	1196	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
tushki7	0:60d829a0353a	1197	do { \
tushki7	0:60d829a0353a	1198	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
tushki7	0:60d829a0353a	1199	{ \
tushki7	0:60d829a0353a	1200	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
tushki7	0:60d829a0353a	1201	{ \
tushki7	0:60d829a0353a	1202	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
tushki7	0:60d829a0353a	1203	} \
tushki7	0:60d829a0353a	1204	} \
tushki7	0:60d829a0353a	1205	} while(0)
tushki7	0:60d829a0353a	1206
tushki7	0:60d829a0353a	1207	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
tushki7	0:60d829a0353a	1208	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
tushki7	0:60d829a0353a	1209	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
tushki7	0:60d829a0353a	1210	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
tushki7	0:60d829a0353a	1211	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
tushki7	0:60d829a0353a	1212	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
tushki7	0:60d829a0353a	1213
tushki7	0:60d829a0353a	1214	#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
tushki7	0:60d829a0353a	1215	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
tushki7	0:60d829a0353a	1216
tushki7	0:60d829a0353a	1217	#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
tushki7	0:60d829a0353a	1218	#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
tushki7	0:60d829a0353a	1219
tushki7	0:60d829a0353a	1220	#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
tushki7	0:60d829a0353a	1221	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
tushki7	0:60d829a0353a	1222	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
tushki7	0:60d829a0353a	1223	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
tushki7	0:60d829a0353a	1224	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
tushki7	0:60d829a0353a	1225
tushki7	0:60d829a0353a	1226	#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
tushki7	0:60d829a0353a	1227	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
tushki7	0:60d829a0353a	1228	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
tushki7	0:60d829a0353a	1229	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
tushki7	0:60d829a0353a	1230	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
tushki7	0:60d829a0353a	1231
tushki7	0:60d829a0353a	1232	/**
tushki7	0:60d829a0353a	1233	* @brief Sets the TIM Capture Compare Register value on runtime without
tushki7	0:60d829a0353a	1234	* calling another time ConfigChannel function.
tushki7	0:60d829a0353a	1235	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1236	* @param __CHANNEL__ : TIM Channels to be configured.
tushki7	0:60d829a0353a	1237	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	1238	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
tushki7	0:60d829a0353a	1239	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
tushki7	0:60d829a0353a	1240	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
tushki7	0:60d829a0353a	1241	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
tushki7	0:60d829a0353a	1242	* @param __COMPARE__: specifies the Capture Compare register new value.
tushki7	0:60d829a0353a	1243	* @retval None
tushki7	0:60d829a0353a	1244	*/
tushki7	0:60d829a0353a	1245	#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
tushki7	0:60d829a0353a	1246	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
tushki7	0:60d829a0353a	1247
tushki7	0:60d829a0353a	1248	/**
tushki7	0:60d829a0353a	1249	* @brief Gets the TIM Capture Compare Register value on runtime
tushki7	0:60d829a0353a	1250	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1251	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
tushki7	0:60d829a0353a	1252	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	1253	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
tushki7	0:60d829a0353a	1254	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
tushki7	0:60d829a0353a	1255	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
tushki7	0:60d829a0353a	1256	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
tushki7	0:60d829a0353a	1257	* @retval None
tushki7	0:60d829a0353a	1258	*/
tushki7	0:60d829a0353a	1259	#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
tushki7	0:60d829a0353a	1260	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
tushki7	0:60d829a0353a	1261
tushki7	0:60d829a0353a	1262	/**
tushki7	0:60d829a0353a	1263	* @brief Sets the TIM Counter Register value on runtime.
tushki7	0:60d829a0353a	1264	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1265	* @param __COUNTER__: specifies the Counter register new value.
tushki7	0:60d829a0353a	1266	* @retval None
tushki7	0:60d829a0353a	1267	*/
tushki7	0:60d829a0353a	1268	#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
tushki7	0:60d829a0353a	1269
tushki7	0:60d829a0353a	1270	/**
tushki7	0:60d829a0353a	1271	* @brief Gets the TIM Counter Register value on runtime.
tushki7	0:60d829a0353a	1272	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1273	* @retval None
tushki7	0:60d829a0353a	1274	*/
tushki7	0:60d829a0353a	1275	#define __HAL_TIM_GetCounter(__HANDLE__) \
tushki7	0:60d829a0353a	1276	((__HANDLE__)->Instance->CNT)
tushki7	0:60d829a0353a	1277
tushki7	0:60d829a0353a	1278	/**
tushki7	0:60d829a0353a	1279	* @brief Sets the TIM Autoreload Register value on runtime without calling
tushki7	0:60d829a0353a	1280	* another time any Init function.
tushki7	0:60d829a0353a	1281	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1282	* @param __AUTORELOAD__: specifies the Counter register new value.
tushki7	0:60d829a0353a	1283	* @retval None
tushki7	0:60d829a0353a	1284	*/
tushki7	0:60d829a0353a	1285	#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
tushki7	0:60d829a0353a	1286	do{ \
tushki7	0:60d829a0353a	1287	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
tushki7	0:60d829a0353a	1288	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
tushki7	0:60d829a0353a	1289	} while(0)
tushki7	0:60d829a0353a	1290
tushki7	0:60d829a0353a	1291	/**
tushki7	0:60d829a0353a	1292	* @brief Gets the TIM Autoreload Register value on runtime
tushki7	0:60d829a0353a	1293	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1294	* @retval None
tushki7	0:60d829a0353a	1295	*/
tushki7	0:60d829a0353a	1296	#define __HAL_TIM_GetAutoreload(__HANDLE__) \
tushki7	0:60d829a0353a	1297	((__HANDLE__)->Instance->ARR)
tushki7	0:60d829a0353a	1298
tushki7	0:60d829a0353a	1299	/**
tushki7	0:60d829a0353a	1300	* @brief Sets the TIM Clock Division value on runtime without calling
tushki7	0:60d829a0353a	1301	* another time any Init function.
tushki7	0:60d829a0353a	1302	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1303	* @param __CKD__: specifies the clock division value.
tushki7	0:60d829a0353a	1304	* This parameter can be one of the following value:
tushki7	0:60d829a0353a	1305	* @arg TIM_CLOCKDIVISION_DIV1
tushki7	0:60d829a0353a	1306	* @arg TIM_CLOCKDIVISION_DIV2
tushki7	0:60d829a0353a	1307	* @arg TIM_CLOCKDIVISION_DIV4
tushki7	0:60d829a0353a	1308	* @retval None
tushki7	0:60d829a0353a	1309	*/
tushki7	0:60d829a0353a	1310	#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
tushki7	0:60d829a0353a	1311	do{ \
tushki7	0:60d829a0353a	1312	(__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \
tushki7	0:60d829a0353a	1313	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
tushki7	0:60d829a0353a	1314	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
tushki7	0:60d829a0353a	1315	} while(0)
tushki7	0:60d829a0353a	1316
tushki7	0:60d829a0353a	1317	/**
tushki7	0:60d829a0353a	1318	* @brief Gets the TIM Clock Division value on runtime
tushki7	0:60d829a0353a	1319	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1320	* @retval None
tushki7	0:60d829a0353a	1321	*/
tushki7	0:60d829a0353a	1322	#define __HAL_TIM_GetClockDivision(__HANDLE__) \
tushki7	0:60d829a0353a	1323	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
tushki7	0:60d829a0353a	1324
tushki7	0:60d829a0353a	1325	/**
tushki7	0:60d829a0353a	1326	* @brief Sets the TIM Input Capture prescaler on runtime without calling
tushki7	0:60d829a0353a	1327	* another time HAL_TIM_IC_ConfigChannel() function.
tushki7	0:60d829a0353a	1328	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1329	* @param __CHANNEL__ : TIM Channels to be configured.
tushki7	0:60d829a0353a	1330	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	1331	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
tushki7	0:60d829a0353a	1332	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
tushki7	0:60d829a0353a	1333	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
tushki7	0:60d829a0353a	1334	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
tushki7	0:60d829a0353a	1335	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
tushki7	0:60d829a0353a	1336	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	1337	* @arg TIM_ICPSC_DIV1: no prescaler
tushki7	0:60d829a0353a	1338	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
tushki7	0:60d829a0353a	1339	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
tushki7	0:60d829a0353a	1340	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
tushki7	0:60d829a0353a	1341	* @retval None
tushki7	0:60d829a0353a	1342	*/
tushki7	0:60d829a0353a	1343	#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
tushki7	0:60d829a0353a	1344	do{ \
tushki7	0:60d829a0353a	1345	__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
tushki7	0:60d829a0353a	1346	__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
tushki7	0:60d829a0353a	1347	} while(0)
tushki7	0:60d829a0353a	1348
tushki7	0:60d829a0353a	1349	/**
tushki7	0:60d829a0353a	1350	* @brief Gets the TIM Input Capture prescaler on runtime
tushki7	0:60d829a0353a	1351	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1352	* @param __CHANNEL__: TIM Channels to be configured.
tushki7	0:60d829a0353a	1353	* This parameter can be one of the following values:
tushki7	0:60d829a0353a	1354	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
tushki7	0:60d829a0353a	1355	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
tushki7	0:60d829a0353a	1356	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
tushki7	0:60d829a0353a	1357	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
tushki7	0:60d829a0353a	1358	* @retval None
tushki7	0:60d829a0353a	1359	*/
tushki7	0:60d829a0353a	1360	#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
tushki7	0:60d829a0353a	1361	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
tushki7	0:60d829a0353a	1362	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
tushki7	0:60d829a0353a	1363	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
tushki7	0:60d829a0353a	1364	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
tushki7	0:60d829a0353a	1365
tushki7	0:60d829a0353a	1366	/**
tushki7	0:60d829a0353a	1367	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
tushki7	0:60d829a0353a	1368	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1369	* @note When the USR bit of the TIMx_CR1 register is set, only counter
tushki7	0:60d829a0353a	1370	* overflow/underflow generates an update interrupt or DMA request (if
tushki7	0:60d829a0353a	1371	* enabled)
tushki7	0:60d829a0353a	1372	* @retval None
tushki7	0:60d829a0353a	1373	*/
tushki7	0:60d829a0353a	1374	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
tushki7	0:60d829a0353a	1375	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
tushki7	0:60d829a0353a	1376
tushki7	0:60d829a0353a	1377	/**
tushki7	0:60d829a0353a	1378	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
tushki7	0:60d829a0353a	1379	* @param __HANDLE__: TIM handle.
tushki7	0:60d829a0353a	1380	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
tushki7	0:60d829a0353a	1381	* following events generate an update interrupt or DMA request (if
tushki7	0:60d829a0353a	1382	* enabled):
tushki7	0:60d829a0353a	1383	* (+) Counter overflow/underflow
tushki7	0:60d829a0353a	1384	* (+) Setting the UG bit
tushki7	0:60d829a0353a	1385	* (+) Update generation through the slave mode controller
tushki7	0:60d829a0353a	1386	* @retval None
tushki7	0:60d829a0353a	1387	*/
tushki7	0:60d829a0353a	1388	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
tushki7	0:60d829a0353a	1389	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
tushki7	0:60d829a0353a	1390
tushki7	0:60d829a0353a	1391	/**
tushki7	0:60d829a0353a	1392	* @}
tushki7	0:60d829a0353a	1393	*/
tushki7	0:60d829a0353a	1394
tushki7	0:60d829a0353a	1395	/* Include TIM HAL Extension module */
tushki7	0:60d829a0353a	1396	#include "stm32f0xx_hal_tim_ex.h"
tushki7	0:60d829a0353a	1397
tushki7	0:60d829a0353a	1398	/* Exported functions --------------------------------------------------------*/
tushki7	0:60d829a0353a	1399	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
tushki7	0:60d829a0353a	1400	* @{
tushki7	0:60d829a0353a	1401	*/
tushki7	0:60d829a0353a	1402
tushki7	0:60d829a0353a	1403	/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
tushki7	0:60d829a0353a	1404	* @brief Time Base functions
tushki7	0:60d829a0353a	1405	* @{
tushki7	0:60d829a0353a	1406	*/
tushki7	0:60d829a0353a	1407	/* Time Base functions ********************************************************/
tushki7	0:60d829a0353a	1408	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1409	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1410	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1411	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1412	/* Blocking mode: Polling */
tushki7	0:60d829a0353a	1413	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1414	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1415	/* Non-Blocking mode: Interrupt */
tushki7	0:60d829a0353a	1416	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1417	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1418	/* Non-Blocking mode: DMA */
tushki7	0:60d829a0353a	1419	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
tushki7	0:60d829a0353a	1420	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1421	/**
tushki7	0:60d829a0353a	1422	* @}
tushki7	0:60d829a0353a	1423	*/
tushki7	0:60d829a0353a	1424
tushki7	0:60d829a0353a	1425	/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
tushki7	0:60d829a0353a	1426	* @brief Time Output Compare functions
tushki7	0:60d829a0353a	1427	* @{
tushki7	0:60d829a0353a	1428	*/
tushki7	0:60d829a0353a	1429	/* Timer Output Compare functions **********************************************/
tushki7	0:60d829a0353a	1430	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1431	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1432	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1433	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1434	/* Blocking mode: Polling */
tushki7	0:60d829a0353a	1435	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1436	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1437	/* Non-Blocking mode: Interrupt */
tushki7	0:60d829a0353a	1438	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1439	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1440	/* Non-Blocking mode: DMA */
tushki7	0:60d829a0353a	1441	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
tushki7	0:60d829a0353a	1442	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1443	/**
tushki7	0:60d829a0353a	1444	* @}
tushki7	0:60d829a0353a	1445	*/
tushki7	0:60d829a0353a	1446
tushki7	0:60d829a0353a	1447	/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
tushki7	0:60d829a0353a	1448	* @brief Time PWM functions
tushki7	0:60d829a0353a	1449	* @{
tushki7	0:60d829a0353a	1450	*/
tushki7	0:60d829a0353a	1451	/* Timer PWM functions *********************************************************/
tushki7	0:60d829a0353a	1452	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1453	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1454	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1455	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1456	/* Blocking mode: Polling */
tushki7	0:60d829a0353a	1457	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1458	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1459	/* Non-Blocking mode: Interrupt */
tushki7	0:60d829a0353a	1460	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1461	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1462	/* Non-Blocking mode: DMA */
tushki7	0:60d829a0353a	1463	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
tushki7	0:60d829a0353a	1464	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1465	/**
tushki7	0:60d829a0353a	1466	* @}
tushki7	0:60d829a0353a	1467	*/
tushki7	0:60d829a0353a	1468
tushki7	0:60d829a0353a	1469	/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
tushki7	0:60d829a0353a	1470	* @brief Time Input Capture functions
tushki7	0:60d829a0353a	1471	* @{
tushki7	0:60d829a0353a	1472	*/
tushki7	0:60d829a0353a	1473	/* Timer Input Capture functions ***********************************************/
tushki7	0:60d829a0353a	1474	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1475	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1476	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1477	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1478	/* Blocking mode: Polling */
tushki7	0:60d829a0353a	1479	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1480	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1481	/* Non-Blocking mode: Interrupt */
tushki7	0:60d829a0353a	1482	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1483	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1484	/* Non-Blocking mode: DMA */
tushki7	0:60d829a0353a	1485	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
tushki7	0:60d829a0353a	1486	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1487	/**
tushki7	0:60d829a0353a	1488	* @}
tushki7	0:60d829a0353a	1489	*/
tushki7	0:60d829a0353a	1490
tushki7	0:60d829a0353a	1491	/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
tushki7	0:60d829a0353a	1492	* @brief Time One Pulse functions
tushki7	0:60d829a0353a	1493	* @{
tushki7	0:60d829a0353a	1494	*/
tushki7	0:60d829a0353a	1495	/* Timer One Pulse functions ***************************************************/
tushki7	0:60d829a0353a	1496	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
tushki7	0:60d829a0353a	1497	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1498	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1499	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1500	/* Blocking mode: Polling */
tushki7	0:60d829a0353a	1501	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
tushki7	0:60d829a0353a	1502	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
tushki7	0:60d829a0353a	1503	/* Non-Blocking mode: Interrupt */
tushki7	0:60d829a0353a	1504	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
tushki7	0:60d829a0353a	1505	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
tushki7	0:60d829a0353a	1506	/**
tushki7	0:60d829a0353a	1507	* @}
tushki7	0:60d829a0353a	1508	*/
tushki7	0:60d829a0353a	1509
tushki7	0:60d829a0353a	1510	/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
tushki7	0:60d829a0353a	1511	* @brief Time Encoder functions
tushki7	0:60d829a0353a	1512	* @{
tushki7	0:60d829a0353a	1513	*/
tushki7	0:60d829a0353a	1514	/* Timer Encoder functions *****************************************************/
tushki7	0:60d829a0353a	1515	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
tushki7	0:60d829a0353a	1516	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1517	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1518	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1519	/* Blocking mode: Polling */
tushki7	0:60d829a0353a	1520	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1521	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1522	/* Non-Blocking mode: Interrupt */
tushki7	0:60d829a0353a	1523	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1524	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1525	/* Non-Blocking mode: DMA */
tushki7	0:60d829a0353a	1526	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
tushki7	0:60d829a0353a	1527	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1528	/**
tushki7	0:60d829a0353a	1529	* @}
tushki7	0:60d829a0353a	1530	*/
tushki7	0:60d829a0353a	1531
tushki7	0:60d829a0353a	1532	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
tushki7	0:60d829a0353a	1533	* @brief IRQ handler management
tushki7	0:60d829a0353a	1534	* @{
tushki7	0:60d829a0353a	1535	*/
tushki7	0:60d829a0353a	1536	/* Interrupt Handler functions **********************************************/
tushki7	0:60d829a0353a	1537	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1538	/**
tushki7	0:60d829a0353a	1539	* @}
tushki7	0:60d829a0353a	1540	*/
tushki7	0:60d829a0353a	1541
tushki7	0:60d829a0353a	1542	/** @addtogroup TIM_Exported_Functions_Group8 Peripheral Control functions
tushki7	0:60d829a0353a	1543	* @brief Peripheral Control functions
tushki7	0:60d829a0353a	1544	* @{
tushki7	0:60d829a0353a	1545	*/
tushki7	0:60d829a0353a	1546	/* Control functions *********************************************************/
tushki7	0:60d829a0353a	1547	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
tushki7	0:60d829a0353a	1548	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
tushki7	0:60d829a0353a	1549	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
tushki7	0:60d829a0353a	1550	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
tushki7	0:60d829a0353a	1551	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
tushki7	0:60d829a0353a	1552	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
tushki7	0:60d829a0353a	1553	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
tushki7	0:60d829a0353a	1554	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
tushki7	0:60d829a0353a	1555	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
tushki7	0:60d829a0353a	1556	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
tushki7	0:60d829a0353a	1557	uint32_t *BurstBuffer, uint32_t BurstLength);
tushki7	0:60d829a0353a	1558	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
tushki7	0:60d829a0353a	1559	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
tushki7	0:60d829a0353a	1560	uint32_t *BurstBuffer, uint32_t BurstLength);
tushki7	0:60d829a0353a	1561	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
tushki7	0:60d829a0353a	1562	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
tushki7	0:60d829a0353a	1563	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
tushki7	0:60d829a0353a	1564	/**
tushki7	0:60d829a0353a	1565	* @}
tushki7	0:60d829a0353a	1566	*/
tushki7	0:60d829a0353a	1567
tushki7	0:60d829a0353a	1568	/** @addtogroup TIM_Exported_Functions_Group9
tushki7	0:60d829a0353a	1569	* @brief TIM Callbacks functions
tushki7	0:60d829a0353a	1570	* @{
tushki7	0:60d829a0353a	1571	*/
tushki7	0:60d829a0353a	1572	/* Callback in non blocking modes (Interrupt and DMA) *************************/
tushki7	0:60d829a0353a	1573	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1574	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1575	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1576	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1577	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1578	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1579	/**
tushki7	0:60d829a0353a	1580	* @}
tushki7	0:60d829a0353a	1581	*/
tushki7	0:60d829a0353a	1582
tushki7	0:60d829a0353a	1583	/** @addtogroup TIM_Exported_Functions_Group10
tushki7	0:60d829a0353a	1584	* @brief Peripheral State functions
tushki7	0:60d829a0353a	1585	* @{
tushki7	0:60d829a0353a	1586	*/
tushki7	0:60d829a0353a	1587	/* Peripheral State functions **************************************************/
tushki7	0:60d829a0353a	1588	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1589	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1590	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1591	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1592	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1593	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
tushki7	0:60d829a0353a	1594	/**
tushki7	0:60d829a0353a	1595	* @}
tushki7	0:60d829a0353a	1596	*/
tushki7	0:60d829a0353a	1597
tushki7	0:60d829a0353a	1598	/**
tushki7	0:60d829a0353a	1599	* @}
tushki7	0:60d829a0353a	1600	*/
tushki7	0:60d829a0353a	1601
tushki7	0:60d829a0353a	1602	/* Private Macros -----------------------------------------------------------*/
tushki7	0:60d829a0353a	1603	/** @defgroup TIM_Private_Macros TIM Private Macros
tushki7	0:60d829a0353a	1604	* @{
tushki7	0:60d829a0353a	1605	*/
tushki7	0:60d829a0353a	1606	/* The counter of a timer instance is disabled only if all the CCx and CCxN
tushki7	0:60d829a0353a	1607	channels have been disabled */
tushki7	0:60d829a0353a	1608	#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
tushki7	0:60d829a0353a	1609	#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
tushki7	0:60d829a0353a	1610	/**
tushki7	0:60d829a0353a	1611	* @}
tushki7	0:60d829a0353a	1612	*/
tushki7	0:60d829a0353a	1613
tushki7	0:60d829a0353a	1614	/* Private Functions --------------------------------------------------------*/
tushki7	0:60d829a0353a	1615	/** @addtogroup TIM_Private_Functions
tushki7	0:60d829a0353a	1616	* @{
tushki7	0:60d829a0353a	1617	*/
tushki7	0:60d829a0353a	1618	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
tushki7	0:60d829a0353a	1619	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
tushki7	0:60d829a0353a	1620	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
tushki7	0:60d829a0353a	1621	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
tushki7	0:60d829a0353a	1622	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
tushki7	0:60d829a0353a	1623	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
tushki7	0:60d829a0353a	1624	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
tushki7	0:60d829a0353a	1625
tushki7	0:60d829a0353a	1626	/**
tushki7	0:60d829a0353a	1627	* @}
tushki7	0:60d829a0353a	1628	*/
tushki7	0:60d829a0353a	1629
tushki7	0:60d829a0353a	1630	/**
tushki7	0:60d829a0353a	1631	* @}
tushki7	0:60d829a0353a	1632	*/
tushki7	0:60d829a0353a	1633
tushki7	0:60d829a0353a	1634	/**
tushki7	0:60d829a0353a	1635	* @}
tushki7	0:60d829a0353a	1636	*/
tushki7	0:60d829a0353a	1637
tushki7	0:60d829a0353a	1638	#ifdef __cplusplus
tushki7	0:60d829a0353a	1639	}
tushki7	0:60d829a0353a	1640	#endif
tushki7	0:60d829a0353a	1641
tushki7	0:60d829a0353a	1642	#endif /* __STM32F0xx_HAL_TIM_H */
tushki7	0:60d829a0353a	1643
tushki7	0:60d829a0353a	1644	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
tushki7	0:60d829a0353a	1645

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Type:	Program
Created:	11 Apr 2015
Imports:	100
Forks:	0
Commits:	2
Dependents:	0
Dependencies:	1
Followers:	2

mbed/TARGET_NUCLEO_F070RB/stm32f0xx_hal_tim.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

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