Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_NUCLEO_F070RB/stm32f0xx_hal_rcc.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a 
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /**
tushki7 0:60d829a0353a 2 ******************************************************************************
tushki7 0:60d829a0353a 3 * @file stm32f0xx_hal_rcc.h
tushki7 0:60d829a0353a 4 * @author MCD Application Team
tushki7 0:60d829a0353a 5 * @version V1.2.0
tushki7 0:60d829a0353a 6 * @date 11-December-2014
tushki7 0:60d829a0353a 7 * @brief Header file of RCC HAL module.
tushki7 0:60d829a0353a 8 ******************************************************************************
tushki7 0:60d829a0353a 9 * @attention
tushki7 0:60d829a0353a 10 *
tushki7 0:60d829a0353a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
tushki7 0:60d829a0353a 12 *
tushki7 0:60d829a0353a 13 * Redistribution and use in source and binary forms, with or without modification,
tushki7 0:60d829a0353a 14 * are permitted provided that the following conditions are met:
tushki7 0:60d829a0353a 15 * 1. Redistributions of source code must retain the above copyright notice,
tushki7 0:60d829a0353a 16 * this list of conditions and the following disclaimer.
tushki7 0:60d829a0353a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
tushki7 0:60d829a0353a 18 * this list of conditions and the following disclaimer in the documentation
tushki7 0:60d829a0353a 19 * and/or other materials provided with the distribution.
tushki7 0:60d829a0353a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
tushki7 0:60d829a0353a 21 * may be used to endorse or promote products derived from this software
tushki7 0:60d829a0353a 22 * without specific prior written permission.
tushki7 0:60d829a0353a 23 *
tushki7 0:60d829a0353a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
tushki7 0:60d829a0353a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
tushki7 0:60d829a0353a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
tushki7 0:60d829a0353a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
tushki7 0:60d829a0353a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
tushki7 0:60d829a0353a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
tushki7 0:60d829a0353a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
tushki7 0:60d829a0353a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
tushki7 0:60d829a0353a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
tushki7 0:60d829a0353a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
tushki7 0:60d829a0353a 34 *
tushki7 0:60d829a0353a 35 ******************************************************************************
tushki7 0:60d829a0353a 36 */
tushki7 0:60d829a0353a 37
tushki7 0:60d829a0353a 38 /* Define to prevent recursive inclusion -------------------------------------*/
tushki7 0:60d829a0353a 39 #ifndef __STM32F0xx_HAL_RCC_H
tushki7 0:60d829a0353a 40 #define __STM32F0xx_HAL_RCC_H
tushki7 0:60d829a0353a 41
tushki7 0:60d829a0353a 42 #ifdef __cplusplus
tushki7 0:60d829a0353a 43 extern "C" {
tushki7 0:60d829a0353a 44 #endif
tushki7 0:60d829a0353a 45
tushki7 0:60d829a0353a 46 /* Includes ------------------------------------------------------------------*/
tushki7 0:60d829a0353a 47 #include "stm32f0xx_hal_def.h"
tushki7 0:60d829a0353a 48
tushki7 0:60d829a0353a 49 /** @addtogroup STM32F0xx_HAL_Driver
tushki7 0:60d829a0353a 50 * @{
tushki7 0:60d829a0353a 51 */
tushki7 0:60d829a0353a 52
tushki7 0:60d829a0353a 53 /** @addtogroup RCC
tushki7 0:60d829a0353a 54 * @{
tushki7 0:60d829a0353a 55 */
tushki7 0:60d829a0353a 56
tushki7 0:60d829a0353a 57 /* Exported types ------------------------------------------------------------*/
tushki7 0:60d829a0353a 58
tushki7 0:60d829a0353a 59 /** @defgroup RCC_Exported_Types RCC Exported Types
tushki7 0:60d829a0353a 60 * @{
tushki7 0:60d829a0353a 61 */
tushki7 0:60d829a0353a 62
tushki7 0:60d829a0353a 63 /**
tushki7 0:60d829a0353a 64 * @brief RCC PLL configuration structure definition
tushki7 0:60d829a0353a 65 */
tushki7 0:60d829a0353a 66 typedef struct
tushki7 0:60d829a0353a 67 {
tushki7 0:60d829a0353a 68 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
tushki7 0:60d829a0353a 69 This parameter can be a value of @ref RCC_PLL_Config */
tushki7 0:60d829a0353a 70
tushki7 0:60d829a0353a 71 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
tushki7 0:60d829a0353a 72 This parameter must be a value of @ref RCC_PLL_Clock_Source */
tushki7 0:60d829a0353a 73
tushki7 0:60d829a0353a 74 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
tushki7 0:60d829a0353a 75 This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
tushki7 0:60d829a0353a 76
tushki7 0:60d829a0353a 77 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
tushki7 0:60d829a0353a 78 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */
tushki7 0:60d829a0353a 79
tushki7 0:60d829a0353a 80 }RCC_PLLInitTypeDef;
tushki7 0:60d829a0353a 81
tushki7 0:60d829a0353a 82 /**
tushki7 0:60d829a0353a 83 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
tushki7 0:60d829a0353a 84 */
tushki7 0:60d829a0353a 85 typedef struct
tushki7 0:60d829a0353a 86 {
tushki7 0:60d829a0353a 87 uint32_t OscillatorType; /*!< The Oscillators to be configured.
tushki7 0:60d829a0353a 88 This parameter can be a value of @ref RCC_Oscillator_Type */
tushki7 0:60d829a0353a 89
tushki7 0:60d829a0353a 90 uint32_t HSEState; /*!< The new state of the HSE.
tushki7 0:60d829a0353a 91 This parameter can be a value of @ref RCC_HSE_Config */
tushki7 0:60d829a0353a 92
tushki7 0:60d829a0353a 93 uint32_t LSEState; /*!< The new state of the LSE.
tushki7 0:60d829a0353a 94 This parameter can be a value of @ref RCC_LSE_Config */
tushki7 0:60d829a0353a 95
tushki7 0:60d829a0353a 96 uint32_t HSIState; /*!< The new state of the HSI.
tushki7 0:60d829a0353a 97 This parameter can be a value of @ref RCC_HSI_Config */
tushki7 0:60d829a0353a 98
tushki7 0:60d829a0353a 99 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
tushki7 0:60d829a0353a 100 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
tushki7 0:60d829a0353a 101
tushki7 0:60d829a0353a 102 uint32_t HSI14State; /*!< The new state of the HSI14.
tushki7 0:60d829a0353a 103 This parameter can be a value of @ref RCC_HSI14_Config */
tushki7 0:60d829a0353a 104
tushki7 0:60d829a0353a 105 uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
tushki7 0:60d829a0353a 106 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
tushki7 0:60d829a0353a 107
tushki7 0:60d829a0353a 108 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
tushki7 0:60d829a0353a 109 This parameter can be a value of @ref RCCEx_HSI48_Config */
tushki7 0:60d829a0353a 110
tushki7 0:60d829a0353a 111 uint32_t LSIState; /*!< The new state of the LSI.
tushki7 0:60d829a0353a 112 This parameter can be a value of @ref RCC_LSI_Config */
tushki7 0:60d829a0353a 113
tushki7 0:60d829a0353a 114 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
tushki7 0:60d829a0353a 115
tushki7 0:60d829a0353a 116 }RCC_OscInitTypeDef;
tushki7 0:60d829a0353a 117
tushki7 0:60d829a0353a 118 /**
tushki7 0:60d829a0353a 119 * @brief RCC System, AHB and APB busses clock configuration structure definition
tushki7 0:60d829a0353a 120 */
tushki7 0:60d829a0353a 121 typedef struct
tushki7 0:60d829a0353a 122 {
tushki7 0:60d829a0353a 123 uint32_t ClockType; /*!< The clock to be configured.
tushki7 0:60d829a0353a 124 This parameter can be a value of @ref RCC_System_Clock_Type */
tushki7 0:60d829a0353a 125
tushki7 0:60d829a0353a 126 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
tushki7 0:60d829a0353a 127 This parameter can be a value of @ref RCC_System_Clock_Source */
tushki7 0:60d829a0353a 128
tushki7 0:60d829a0353a 129 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
tushki7 0:60d829a0353a 130 This parameter can be a value of @ref RCC_AHB_Clock_Source */
tushki7 0:60d829a0353a 131
tushki7 0:60d829a0353a 132 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
tushki7 0:60d829a0353a 133 This parameter can be a value of @ref RCC_APB1_Clock_Source */
tushki7 0:60d829a0353a 134
tushki7 0:60d829a0353a 135 }RCC_ClkInitTypeDef;
tushki7 0:60d829a0353a 136
tushki7 0:60d829a0353a 137 /**
tushki7 0:60d829a0353a 138 * @}
tushki7 0:60d829a0353a 139 */
tushki7 0:60d829a0353a 140
tushki7 0:60d829a0353a 141 /* Exported constants --------------------------------------------------------*/
tushki7 0:60d829a0353a 142 /** @defgroup RCC_Exported_Constants RCC Exported Constants
tushki7 0:60d829a0353a 143 * @{
tushki7 0:60d829a0353a 144 */
tushki7 0:60d829a0353a 145
tushki7 0:60d829a0353a 146 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
tushki7 0:60d829a0353a 147 * @brief RCC registers bit address in the alias region
tushki7 0:60d829a0353a 148 * @{
tushki7 0:60d829a0353a 149 */
tushki7 0:60d829a0353a 150 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
tushki7 0:60d829a0353a 151 /* --- CR Register ---*/
tushki7 0:60d829a0353a 152 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
tushki7 0:60d829a0353a 153 /* --- CFGR Register ---*/
tushki7 0:60d829a0353a 154 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
tushki7 0:60d829a0353a 155 /* --- CIR Register ---*/
tushki7 0:60d829a0353a 156 #define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
tushki7 0:60d829a0353a 157 /* --- BDCR Register ---*/
tushki7 0:60d829a0353a 158 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
tushki7 0:60d829a0353a 159 /* --- CSR Register ---*/
tushki7 0:60d829a0353a 160 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
tushki7 0:60d829a0353a 161 /* --- CR2 Register ---*/
tushki7 0:60d829a0353a 162 #define RCC_CR2_OFFSET (RCC_OFFSET + 0x34)
tushki7 0:60d829a0353a 163
tushki7 0:60d829a0353a 164 /* CR register byte 2 (Bits[23:16]) base address */
tushki7 0:60d829a0353a 165 #define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
tushki7 0:60d829a0353a 166
tushki7 0:60d829a0353a 167 /* CIR register byte 1 (Bits[15:8]) base address */
tushki7 0:60d829a0353a 168 #define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
tushki7 0:60d829a0353a 169
tushki7 0:60d829a0353a 170 /* CIR register byte 2 (Bits[23:16]) base address */
tushki7 0:60d829a0353a 171 #define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
tushki7 0:60d829a0353a 172
tushki7 0:60d829a0353a 173 /* CSR register byte 1 (Bits[15:8]) base address */
tushki7 0:60d829a0353a 174 #define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
tushki7 0:60d829a0353a 175
tushki7 0:60d829a0353a 176 /* BDCR register byte 0 (Bits[7:0] base address */
tushki7 0:60d829a0353a 177 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
tushki7 0:60d829a0353a 178
tushki7 0:60d829a0353a 179 #define RCC_CFGR_PLLMUL_BITNUMBER 18
tushki7 0:60d829a0353a 180 #define RCC_CFGR2_PREDIV_BITNUMBER 0
tushki7 0:60d829a0353a 181
tushki7 0:60d829a0353a 182 /**
tushki7 0:60d829a0353a 183 * @}
tushki7 0:60d829a0353a 184 */
tushki7 0:60d829a0353a 185
tushki7 0:60d829a0353a 186 /** @defgroup RCC_Timeout RCC Timeout
tushki7 0:60d829a0353a 187 * @{
tushki7 0:60d829a0353a 188 */
tushki7 0:60d829a0353a 189 /* LSE state change timeout */
tushki7 0:60d829a0353a 190 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
tushki7 0:60d829a0353a 191
tushki7 0:60d829a0353a 192 /* Disable Backup domain write protection state change timeout */
tushki7 0:60d829a0353a 193 #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
tushki7 0:60d829a0353a 194 /**
tushki7 0:60d829a0353a 195 * @}
tushki7 0:60d829a0353a 196 */
tushki7 0:60d829a0353a 197
tushki7 0:60d829a0353a 198 /** @defgroup RCC_Oscillator_Type RCC Oscillator Type
tushki7 0:60d829a0353a 199 * @{
tushki7 0:60d829a0353a 200 */
tushki7 0:60d829a0353a 201 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
tushki7 0:60d829a0353a 202 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 203 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 204 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 205 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 206 #define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 207 #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 208
tushki7 0:60d829a0353a 209 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
tushki7 0:60d829a0353a 210 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
tushki7 0:60d829a0353a 211 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
tushki7 0:60d829a0353a 212 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
tushki7 0:60d829a0353a 213 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
tushki7 0:60d829a0353a 214 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
tushki7 0:60d829a0353a 215 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
tushki7 0:60d829a0353a 216 /**
tushki7 0:60d829a0353a 217 * @}
tushki7 0:60d829a0353a 218 */
tushki7 0:60d829a0353a 219
tushki7 0:60d829a0353a 220 /** @defgroup RCC_HSE_Config RCC HSE Config
tushki7 0:60d829a0353a 221 * @{
tushki7 0:60d829a0353a 222 */
tushki7 0:60d829a0353a 223 #define RCC_HSE_OFF ((uint8_t)0x00)
tushki7 0:60d829a0353a 224 #define RCC_HSE_ON ((uint8_t)0x01)
tushki7 0:60d829a0353a 225 #define RCC_HSE_BYPASS ((uint8_t)0x05)
tushki7 0:60d829a0353a 226
tushki7 0:60d829a0353a 227 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
tushki7 0:60d829a0353a 228 ((HSE) == RCC_HSE_BYPASS))
tushki7 0:60d829a0353a 229 /**
tushki7 0:60d829a0353a 230 * @}
tushki7 0:60d829a0353a 231 */
tushki7 0:60d829a0353a 232
tushki7 0:60d829a0353a 233 /** @defgroup RCC_LSE_Config RCC_LSE_Config
tushki7 0:60d829a0353a 234 * @{
tushki7 0:60d829a0353a 235 */
tushki7 0:60d829a0353a 236 #define RCC_LSE_OFF ((uint8_t)0x00)
tushki7 0:60d829a0353a 237 #define RCC_LSE_ON ((uint8_t)0x01)
tushki7 0:60d829a0353a 238 #define RCC_LSE_BYPASS ((uint8_t)0x05)
tushki7 0:60d829a0353a 239
tushki7 0:60d829a0353a 240 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
tushki7 0:60d829a0353a 241 ((LSE) == RCC_LSE_BYPASS))
tushki7 0:60d829a0353a 242 /**
tushki7 0:60d829a0353a 243 * @}
tushki7 0:60d829a0353a 244 */
tushki7 0:60d829a0353a 245
tushki7 0:60d829a0353a 246 /** @defgroup RCC_HSI_Config RCC HSI Config
tushki7 0:60d829a0353a 247 * @{
tushki7 0:60d829a0353a 248 */
tushki7 0:60d829a0353a 249 #define RCC_HSI_OFF ((uint8_t)0x00)
tushki7 0:60d829a0353a 250 #define RCC_HSI_ON ((uint8_t)0x01)
tushki7 0:60d829a0353a 251
tushki7 0:60d829a0353a 252 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
tushki7 0:60d829a0353a 253
tushki7 0:60d829a0353a 254 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
tushki7 0:60d829a0353a 255 /**
tushki7 0:60d829a0353a 256 * @}
tushki7 0:60d829a0353a 257 */
tushki7 0:60d829a0353a 258
tushki7 0:60d829a0353a 259 /** @defgroup RCC_HSI14_Config RCC HSI14 Config
tushki7 0:60d829a0353a 260 * @{
tushki7 0:60d829a0353a 261 */
tushki7 0:60d829a0353a 262 #define RCC_HSI14_OFF ((uint32_t)0x00)
tushki7 0:60d829a0353a 263 #define RCC_HSI14_ON RCC_CR2_HSI14ON
tushki7 0:60d829a0353a 264 #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
tushki7 0:60d829a0353a 265
tushki7 0:60d829a0353a 266 #define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) || ((HSI14) == RCC_HSI14_ON) || ((HSI14) == RCC_HSI14_ADC_CONTROL))
tushki7 0:60d829a0353a 267
tushki7 0:60d829a0353a 268 #define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
tushki7 0:60d829a0353a 269 /**
tushki7 0:60d829a0353a 270 * @}
tushki7 0:60d829a0353a 271 */
tushki7 0:60d829a0353a 272
tushki7 0:60d829a0353a 273 /** @defgroup RCC_LSI_Config RCC LSI Config
tushki7 0:60d829a0353a 274 * @{
tushki7 0:60d829a0353a 275 */
tushki7 0:60d829a0353a 276 #define RCC_LSI_OFF ((uint8_t)0x00)
tushki7 0:60d829a0353a 277 #define RCC_LSI_ON ((uint8_t)0x01)
tushki7 0:60d829a0353a 278
tushki7 0:60d829a0353a 279 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
tushki7 0:60d829a0353a 280 /**
tushki7 0:60d829a0353a 281 * @}
tushki7 0:60d829a0353a 282 */
tushki7 0:60d829a0353a 283
tushki7 0:60d829a0353a 284 /** @defgroup RCC_PLL_Config RCC PLL Config
tushki7 0:60d829a0353a 285 * @{
tushki7 0:60d829a0353a 286 */
tushki7 0:60d829a0353a 287 #define RCC_PLL_NONE ((uint8_t)0x00)
tushki7 0:60d829a0353a 288 #define RCC_PLL_OFF ((uint8_t)0x01)
tushki7 0:60d829a0353a 289 #define RCC_PLL_ON ((uint8_t)0x02)
tushki7 0:60d829a0353a 290
tushki7 0:60d829a0353a 291 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
tushki7 0:60d829a0353a 292 /**
tushki7 0:60d829a0353a 293 * @}
tushki7 0:60d829a0353a 294 */
tushki7 0:60d829a0353a 295
tushki7 0:60d829a0353a 296 /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
tushki7 0:60d829a0353a 297 * @{
tushki7 0:60d829a0353a 298 */
tushki7 0:60d829a0353a 299 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
tushki7 0:60d829a0353a 300 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
tushki7 0:60d829a0353a 301 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
tushki7 0:60d829a0353a 302 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
tushki7 0:60d829a0353a 303 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
tushki7 0:60d829a0353a 304 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
tushki7 0:60d829a0353a 305 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
tushki7 0:60d829a0353a 306 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
tushki7 0:60d829a0353a 307 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
tushki7 0:60d829a0353a 308 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
tushki7 0:60d829a0353a 309 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
tushki7 0:60d829a0353a 310 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
tushki7 0:60d829a0353a 311 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
tushki7 0:60d829a0353a 312 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
tushki7 0:60d829a0353a 313 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
tushki7 0:60d829a0353a 314 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
tushki7 0:60d829a0353a 315
tushki7 0:60d829a0353a 316 #define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \
tushki7 0:60d829a0353a 317 ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \
tushki7 0:60d829a0353a 318 ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \
tushki7 0:60d829a0353a 319 ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \
tushki7 0:60d829a0353a 320 ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \
tushki7 0:60d829a0353a 321 ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \
tushki7 0:60d829a0353a 322 ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \
tushki7 0:60d829a0353a 323 ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16))
tushki7 0:60d829a0353a 324 /**
tushki7 0:60d829a0353a 325 * @}
tushki7 0:60d829a0353a 326 */
tushki7 0:60d829a0353a 327
tushki7 0:60d829a0353a 328 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
tushki7 0:60d829a0353a 329 * @{
tushki7 0:60d829a0353a 330 */
tushki7 0:60d829a0353a 331 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
tushki7 0:60d829a0353a 332 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
tushki7 0:60d829a0353a 333 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
tushki7 0:60d829a0353a 334 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
tushki7 0:60d829a0353a 335 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
tushki7 0:60d829a0353a 336 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
tushki7 0:60d829a0353a 337 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
tushki7 0:60d829a0353a 338 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
tushki7 0:60d829a0353a 339 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
tushki7 0:60d829a0353a 340 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
tushki7 0:60d829a0353a 341 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
tushki7 0:60d829a0353a 342 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
tushki7 0:60d829a0353a 343 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
tushki7 0:60d829a0353a 344 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
tushki7 0:60d829a0353a 345 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
tushki7 0:60d829a0353a 346
tushki7 0:60d829a0353a 347 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \
tushki7 0:60d829a0353a 348 ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \
tushki7 0:60d829a0353a 349 ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \
tushki7 0:60d829a0353a 350 ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \
tushki7 0:60d829a0353a 351 ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \
tushki7 0:60d829a0353a 352 ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \
tushki7 0:60d829a0353a 353 ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \
tushki7 0:60d829a0353a 354 ((MUL) == RCC_PLL_MUL16))
tushki7 0:60d829a0353a 355 /**
tushki7 0:60d829a0353a 356 * @}
tushki7 0:60d829a0353a 357 */
tushki7 0:60d829a0353a 358
tushki7 0:60d829a0353a 359 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
tushki7 0:60d829a0353a 360 * @{
tushki7 0:60d829a0353a 361 */
tushki7 0:60d829a0353a 362 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
tushki7 0:60d829a0353a 363 /**
tushki7 0:60d829a0353a 364 * @}
tushki7 0:60d829a0353a 365 */
tushki7 0:60d829a0353a 366
tushki7 0:60d829a0353a 367 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
tushki7 0:60d829a0353a 368 * @{
tushki7 0:60d829a0353a 369 */
tushki7 0:60d829a0353a 370 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 371 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 372 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 373
tushki7 0:60d829a0353a 374 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
tushki7 0:60d829a0353a 375 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
tushki7 0:60d829a0353a 376 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
tushki7 0:60d829a0353a 377 /**
tushki7 0:60d829a0353a 378 * @}
tushki7 0:60d829a0353a 379 */
tushki7 0:60d829a0353a 380
tushki7 0:60d829a0353a 381 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
tushki7 0:60d829a0353a 382 * @{
tushki7 0:60d829a0353a 383 */
tushki7 0:60d829a0353a 384 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
tushki7 0:60d829a0353a 385 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
tushki7 0:60d829a0353a 386 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
tushki7 0:60d829a0353a 387 /**
tushki7 0:60d829a0353a 388 * @}
tushki7 0:60d829a0353a 389 */
tushki7 0:60d829a0353a 390
tushki7 0:60d829a0353a 391 /** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
tushki7 0:60d829a0353a 392 * @{
tushki7 0:60d829a0353a 393 */
tushki7 0:60d829a0353a 394 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
tushki7 0:60d829a0353a 395 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
tushki7 0:60d829a0353a 396 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
tushki7 0:60d829a0353a 397 /**
tushki7 0:60d829a0353a 398 * @}
tushki7 0:60d829a0353a 399 */
tushki7 0:60d829a0353a 400
tushki7 0:60d829a0353a 401 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
tushki7 0:60d829a0353a 402 * @{
tushki7 0:60d829a0353a 403 */
tushki7 0:60d829a0353a 404 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
tushki7 0:60d829a0353a 405 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
tushki7 0:60d829a0353a 406 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
tushki7 0:60d829a0353a 407 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
tushki7 0:60d829a0353a 408 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
tushki7 0:60d829a0353a 409 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
tushki7 0:60d829a0353a 410 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
tushki7 0:60d829a0353a 411 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
tushki7 0:60d829a0353a 412 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
tushki7 0:60d829a0353a 413
tushki7 0:60d829a0353a 414 #define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \
tushki7 0:60d829a0353a 415 ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \
tushki7 0:60d829a0353a 416 ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \
tushki7 0:60d829a0353a 417 ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \
tushki7 0:60d829a0353a 418 ((DIV) == RCC_SYSCLK_DIV512))
tushki7 0:60d829a0353a 419 /**
tushki7 0:60d829a0353a 420 * @}
tushki7 0:60d829a0353a 421 */
tushki7 0:60d829a0353a 422
tushki7 0:60d829a0353a 423 /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
tushki7 0:60d829a0353a 424 * @{
tushki7 0:60d829a0353a 425 */
tushki7 0:60d829a0353a 426 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
tushki7 0:60d829a0353a 427 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
tushki7 0:60d829a0353a 428 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
tushki7 0:60d829a0353a 429 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
tushki7 0:60d829a0353a 430 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
tushki7 0:60d829a0353a 431
tushki7 0:60d829a0353a 432 #define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \
tushki7 0:60d829a0353a 433 ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \
tushki7 0:60d829a0353a 434 ((DIV) == RCC_HCLK_DIV16))
tushki7 0:60d829a0353a 435 /**
tushki7 0:60d829a0353a 436 * @}
tushki7 0:60d829a0353a 437 */
tushki7 0:60d829a0353a 438
tushki7 0:60d829a0353a 439 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
tushki7 0:60d829a0353a 440 * @{
tushki7 0:60d829a0353a 441 */
tushki7 0:60d829a0353a 442 #define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
tushki7 0:60d829a0353a 443 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
tushki7 0:60d829a0353a 444 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
tushki7 0:60d829a0353a 445 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
tushki7 0:60d829a0353a 446
tushki7 0:60d829a0353a 447 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \
tushki7 0:60d829a0353a 448 ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
tushki7 0:60d829a0353a 449 ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
tushki7 0:60d829a0353a 450 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
tushki7 0:60d829a0353a 451 /**
tushki7 0:60d829a0353a 452 * @}
tushki7 0:60d829a0353a 453 */
tushki7 0:60d829a0353a 454
tushki7 0:60d829a0353a 455 /** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
tushki7 0:60d829a0353a 456 * @{
tushki7 0:60d829a0353a 457 */
tushki7 0:60d829a0353a 458 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
tushki7 0:60d829a0353a 459 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
tushki7 0:60d829a0353a 460 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
tushki7 0:60d829a0353a 461 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
tushki7 0:60d829a0353a 462
tushki7 0:60d829a0353a 463 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
tushki7 0:60d829a0353a 464 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
tushki7 0:60d829a0353a 465 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
tushki7 0:60d829a0353a 466 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
tushki7 0:60d829a0353a 467 /**
tushki7 0:60d829a0353a 468 * @}
tushki7 0:60d829a0353a 469 */
tushki7 0:60d829a0353a 470
tushki7 0:60d829a0353a 471 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
tushki7 0:60d829a0353a 472 * @{
tushki7 0:60d829a0353a 473 */
tushki7 0:60d829a0353a 474 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
tushki7 0:60d829a0353a 475 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
tushki7 0:60d829a0353a 476
tushki7 0:60d829a0353a 477 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
tushki7 0:60d829a0353a 478 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
tushki7 0:60d829a0353a 479 /**
tushki7 0:60d829a0353a 480 * @}
tushki7 0:60d829a0353a 481 */
tushki7 0:60d829a0353a 482
tushki7 0:60d829a0353a 483 /** @defgroup RCC_MCOx_Index RCC MCOx Index
tushki7 0:60d829a0353a 484 * @{
tushki7 0:60d829a0353a 485 */
tushki7 0:60d829a0353a 486 #define RCC_MCO ((uint32_t)0x00000000)
tushki7 0:60d829a0353a 487
tushki7 0:60d829a0353a 488 #define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
tushki7 0:60d829a0353a 489 /**
tushki7 0:60d829a0353a 490 * @}
tushki7 0:60d829a0353a 491 */
tushki7 0:60d829a0353a 492
tushki7 0:60d829a0353a 493 /** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
tushki7 0:60d829a0353a 494 * @{
tushki7 0:60d829a0353a 495 */
tushki7 0:60d829a0353a 496 #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
tushki7 0:60d829a0353a 497 #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
tushki7 0:60d829a0353a 498 #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
tushki7 0:60d829a0353a 499 #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
tushki7 0:60d829a0353a 500 #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
tushki7 0:60d829a0353a 501 #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
tushki7 0:60d829a0353a 502 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
tushki7 0:60d829a0353a 503 #define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
tushki7 0:60d829a0353a 504 /**
tushki7 0:60d829a0353a 505 * @}
tushki7 0:60d829a0353a 506 */
tushki7 0:60d829a0353a 507
tushki7 0:60d829a0353a 508 /** @defgroup RCC_Interrupt RCC Interrupt
tushki7 0:60d829a0353a 509 * @{
tushki7 0:60d829a0353a 510 */
tushki7 0:60d829a0353a 511 #define RCC_IT_LSIRDY ((uint8_t)0x01)
tushki7 0:60d829a0353a 512 #define RCC_IT_LSERDY ((uint8_t)0x02)
tushki7 0:60d829a0353a 513 #define RCC_IT_HSIRDY ((uint8_t)0x04)
tushki7 0:60d829a0353a 514 #define RCC_IT_HSERDY ((uint8_t)0x08)
tushki7 0:60d829a0353a 515 #define RCC_IT_PLLRDY ((uint8_t)0x10)
tushki7 0:60d829a0353a 516 #define RCC_IT_HSI14 ((uint8_t)0x20)
tushki7 0:60d829a0353a 517 #define RCC_IT_CSS ((uint8_t)0x80)
tushki7 0:60d829a0353a 518 /**
tushki7 0:60d829a0353a 519 * @}
tushki7 0:60d829a0353a 520 */
tushki7 0:60d829a0353a 521
tushki7 0:60d829a0353a 522 /** @defgroup RCC_Flag RCC Flag
tushki7 0:60d829a0353a 523 * Elements values convention: 0XXYYYYYb
tushki7 0:60d829a0353a 524 * - YYYYY : Flag position in the register
tushki7 0:60d829a0353a 525 * - XX : Register index
tushki7 0:60d829a0353a 526 * - 00: CR register
tushki7 0:60d829a0353a 527 * - 01: CR2 register
tushki7 0:60d829a0353a 528 * - 10: BDCR register
tushki7 0:60d829a0353a 529 * - 11: CSR register
tushki7 0:60d829a0353a 530 * @{
tushki7 0:60d829a0353a 531 */
tushki7 0:60d829a0353a 532 #define CR_REG_INDEX 0
tushki7 0:60d829a0353a 533 #define CR2_REG_INDEX 1
tushki7 0:60d829a0353a 534 #define BDCR_REG_INDEX 2
tushki7 0:60d829a0353a 535 #define CSR_REG_INDEX 3
tushki7 0:60d829a0353a 536
tushki7 0:60d829a0353a 537 /* Flags in the CR register */
tushki7 0:60d829a0353a 538 #define RCC_CR_HSIRDY_BitNumber 1
tushki7 0:60d829a0353a 539 #define RCC_CR_HSERDY_BitNumber 17
tushki7 0:60d829a0353a 540 #define RCC_CR_PLLRDY_BitNumber 25
tushki7 0:60d829a0353a 541
tushki7 0:60d829a0353a 542 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_BitNumber))
tushki7 0:60d829a0353a 543 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_BitNumber))
tushki7 0:60d829a0353a 544 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_BitNumber))
tushki7 0:60d829a0353a 545
tushki7 0:60d829a0353a 546 /* Flags in the CR2 register */
tushki7 0:60d829a0353a 547 #define RCC_CR2_HSI14RDY_BitNumber 1
tushki7 0:60d829a0353a 548
tushki7 0:60d829a0353a 549 #define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI14RDY_BitNumber))
tushki7 0:60d829a0353a 550
tushki7 0:60d829a0353a 551 /* Flags in the BDCR register */
tushki7 0:60d829a0353a 552 #define RCC_BDCR_LSERDY_BitNumber 1
tushki7 0:60d829a0353a 553
tushki7 0:60d829a0353a 554 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber))
tushki7 0:60d829a0353a 555
tushki7 0:60d829a0353a 556 /* Flags in the CSR register */
tushki7 0:60d829a0353a 557 #define RCC_CSR_LSIRDY_BitNumber 1
tushki7 0:60d829a0353a 558 #define RCC_CSR_V18PWRRSTF_BitNumber 23
tushki7 0:60d829a0353a 559 #define RCC_CSR_RMVF_BitNumber 24
tushki7 0:60d829a0353a 560 #define RCC_CSR_OBLRSTF_BitNumber 25
tushki7 0:60d829a0353a 561 #define RCC_CSR_PINRSTF_BitNumber 26
tushki7 0:60d829a0353a 562 #define RCC_CSR_PORRSTF_BitNumber 27
tushki7 0:60d829a0353a 563 #define RCC_CSR_SFTRSTF_BitNumber 28
tushki7 0:60d829a0353a 564 #define RCC_CSR_IWDGRSTF_BitNumber 29
tushki7 0:60d829a0353a 565 #define RCC_CSR_WWDGRSTF_BitNumber 30
tushki7 0:60d829a0353a 566 #define RCC_CSR_LPWRRSTF_BitNumber 31
tushki7 0:60d829a0353a 567
tushki7 0:60d829a0353a 568 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
tushki7 0:60d829a0353a 569 #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
tushki7 0:60d829a0353a 570 #define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber))
tushki7 0:60d829a0353a 571 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_BitNumber))
tushki7 0:60d829a0353a 572 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_BitNumber))
tushki7 0:60d829a0353a 573 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_BitNumber))
tushki7 0:60d829a0353a 574 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_BitNumber))
tushki7 0:60d829a0353a 575 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_BitNumber))
tushki7 0:60d829a0353a 576 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_BitNumber))
tushki7 0:60d829a0353a 577 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_BitNumber))
tushki7 0:60d829a0353a 578 /**
tushki7 0:60d829a0353a 579 * @}
tushki7 0:60d829a0353a 580 */
tushki7 0:60d829a0353a 581
tushki7 0:60d829a0353a 582 /** @defgroup RCC_Calibration_values RCC Calibration values
tushki7 0:60d829a0353a 583 * @{
tushki7 0:60d829a0353a 584 */
tushki7 0:60d829a0353a 585 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
tushki7 0:60d829a0353a 586
tushki7 0:60d829a0353a 587 /**
tushki7 0:60d829a0353a 588 * @}
tushki7 0:60d829a0353a 589 */
tushki7 0:60d829a0353a 590
tushki7 0:60d829a0353a 591 /** @addtogroup RCC_Timeout
tushki7 0:60d829a0353a 592 * @{
tushki7 0:60d829a0353a 593 */
tushki7 0:60d829a0353a 594
tushki7 0:60d829a0353a 595 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
tushki7 0:60d829a0353a 596 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
tushki7 0:60d829a0353a 597 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
tushki7 0:60d829a0353a 598 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
tushki7 0:60d829a0353a 599 #define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
tushki7 0:60d829a0353a 600 #define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
tushki7 0:60d829a0353a 601 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
tushki7 0:60d829a0353a 602 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
tushki7 0:60d829a0353a 603
tushki7 0:60d829a0353a 604 /**
tushki7 0:60d829a0353a 605 * @}
tushki7 0:60d829a0353a 606 */
tushki7 0:60d829a0353a 607
tushki7 0:60d829a0353a 608 /**
tushki7 0:60d829a0353a 609 * @}
tushki7 0:60d829a0353a 610 */
tushki7 0:60d829a0353a 611
tushki7 0:60d829a0353a 612 /* Exported macro ------------------------------------------------------------*/
tushki7 0:60d829a0353a 613
tushki7 0:60d829a0353a 614 /** @defgroup RCC_Exported_Macros RCC Exported Macros
tushki7 0:60d829a0353a 615 * @{
tushki7 0:60d829a0353a 616 */
tushki7 0:60d829a0353a 617
tushki7 0:60d829a0353a 618 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
tushki7 0:60d829a0353a 619 * @brief Enable or disable the AHB peripheral clock.
tushki7 0:60d829a0353a 620 * @note After reset, the peripheral clock (used for registers read/write access)
tushki7 0:60d829a0353a 621 * is disabled and the application software has to enable this clock before
tushki7 0:60d829a0353a 622 * using it.
tushki7 0:60d829a0353a 623 * @{
tushki7 0:60d829a0353a 624 */
tushki7 0:60d829a0353a 625 #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
tushki7 0:60d829a0353a 626 #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
tushki7 0:60d829a0353a 627 #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
tushki7 0:60d829a0353a 628 #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
tushki7 0:60d829a0353a 629 #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
tushki7 0:60d829a0353a 630 #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
tushki7 0:60d829a0353a 631 #define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN))
tushki7 0:60d829a0353a 632 #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
tushki7 0:60d829a0353a 633
tushki7 0:60d829a0353a 634 #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
tushki7 0:60d829a0353a 635 #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
tushki7 0:60d829a0353a 636 #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
tushki7 0:60d829a0353a 637 #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
tushki7 0:60d829a0353a 638 #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
tushki7 0:60d829a0353a 639 #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
tushki7 0:60d829a0353a 640 #define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
tushki7 0:60d829a0353a 641 #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
tushki7 0:60d829a0353a 642 /**
tushki7 0:60d829a0353a 643 * @}
tushki7 0:60d829a0353a 644 */
tushki7 0:60d829a0353a 645
tushki7 0:60d829a0353a 646 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
tushki7 0:60d829a0353a 647 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
tushki7 0:60d829a0353a 648 * @note After reset, the peripheral clock (used for registers read/write access)
tushki7 0:60d829a0353a 649 * is disabled and the application software has to enable this clock before
tushki7 0:60d829a0353a 650 * using it.
tushki7 0:60d829a0353a 651 * @{
tushki7 0:60d829a0353a 652 */
tushki7 0:60d829a0353a 653 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
tushki7 0:60d829a0353a 654 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
tushki7 0:60d829a0353a 655 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
tushki7 0:60d829a0353a 656 #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
tushki7 0:60d829a0353a 657 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
tushki7 0:60d829a0353a 658
tushki7 0:60d829a0353a 659 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
tushki7 0:60d829a0353a 660 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
tushki7 0:60d829a0353a 661 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
tushki7 0:60d829a0353a 662 #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
tushki7 0:60d829a0353a 663 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
tushki7 0:60d829a0353a 664 /**
tushki7 0:60d829a0353a 665 * @}
tushki7 0:60d829a0353a 666 */
tushki7 0:60d829a0353a 667
tushki7 0:60d829a0353a 668 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
tushki7 0:60d829a0353a 669 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
tushki7 0:60d829a0353a 670 * @note After reset, the peripheral clock (used for registers read/write access)
tushki7 0:60d829a0353a 671 * is disabled and the application software has to enable this clock before
tushki7 0:60d829a0353a 672 * using it.
tushki7 0:60d829a0353a 673 * @{
tushki7 0:60d829a0353a 674 */
tushki7 0:60d829a0353a 675 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
tushki7 0:60d829a0353a 676 #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
tushki7 0:60d829a0353a 677 #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
tushki7 0:60d829a0353a 678 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
tushki7 0:60d829a0353a 679 #define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN))
tushki7 0:60d829a0353a 680 #define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN))
tushki7 0:60d829a0353a 681 #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
tushki7 0:60d829a0353a 682 #define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN))
tushki7 0:60d829a0353a 683
tushki7 0:60d829a0353a 684 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
tushki7 0:60d829a0353a 685 #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
tushki7 0:60d829a0353a 686 #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
tushki7 0:60d829a0353a 687 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
tushki7 0:60d829a0353a 688 #define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
tushki7 0:60d829a0353a 689 #define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
tushki7 0:60d829a0353a 690 #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
tushki7 0:60d829a0353a 691 #define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
tushki7 0:60d829a0353a 692 /**
tushki7 0:60d829a0353a 693 * @}
tushki7 0:60d829a0353a 694 */
tushki7 0:60d829a0353a 695
tushki7 0:60d829a0353a 696 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
tushki7 0:60d829a0353a 697 * @brief Force or release AHB peripheral reset.
tushki7 0:60d829a0353a 698 * @{
tushki7 0:60d829a0353a 699 */
tushki7 0:60d829a0353a 700 #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
tushki7 0:60d829a0353a 701 #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
tushki7 0:60d829a0353a 702 #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
tushki7 0:60d829a0353a 703 #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
tushki7 0:60d829a0353a 704 #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
tushki7 0:60d829a0353a 705
tushki7 0:60d829a0353a 706 #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
tushki7 0:60d829a0353a 707 #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
tushki7 0:60d829a0353a 708 #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
tushki7 0:60d829a0353a 709 #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
tushki7 0:60d829a0353a 710 #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
tushki7 0:60d829a0353a 711 /**
tushki7 0:60d829a0353a 712 * @}
tushki7 0:60d829a0353a 713 */
tushki7 0:60d829a0353a 714
tushki7 0:60d829a0353a 715 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
tushki7 0:60d829a0353a 716 * @brief Force or release APB1 peripheral reset.
tushki7 0:60d829a0353a 717 * @{
tushki7 0:60d829a0353a 718 */
tushki7 0:60d829a0353a 719 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
tushki7 0:60d829a0353a 720 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
tushki7 0:60d829a0353a 721 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
tushki7 0:60d829a0353a 722 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
tushki7 0:60d829a0353a 723 #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
tushki7 0:60d829a0353a 724 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
tushki7 0:60d829a0353a 725
tushki7 0:60d829a0353a 726 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
tushki7 0:60d829a0353a 727 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
tushki7 0:60d829a0353a 728 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
tushki7 0:60d829a0353a 729 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
tushki7 0:60d829a0353a 730 #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
tushki7 0:60d829a0353a 731 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
tushki7 0:60d829a0353a 732 /**
tushki7 0:60d829a0353a 733 * @}
tushki7 0:60d829a0353a 734 */
tushki7 0:60d829a0353a 735
tushki7 0:60d829a0353a 736 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
tushki7 0:60d829a0353a 737 * @brief Force or release APB2 peripheral reset.
tushki7 0:60d829a0353a 738 * @{
tushki7 0:60d829a0353a 739 */
tushki7 0:60d829a0353a 740 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
tushki7 0:60d829a0353a 741 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
tushki7 0:60d829a0353a 742 #define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
tushki7 0:60d829a0353a 743 #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
tushki7 0:60d829a0353a 744 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
tushki7 0:60d829a0353a 745 #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
tushki7 0:60d829a0353a 746 #define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
tushki7 0:60d829a0353a 747 #define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
tushki7 0:60d829a0353a 748 #define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
tushki7 0:60d829a0353a 749
tushki7 0:60d829a0353a 750 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
tushki7 0:60d829a0353a 751 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
tushki7 0:60d829a0353a 752 #define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
tushki7 0:60d829a0353a 753 #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
tushki7 0:60d829a0353a 754 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
tushki7 0:60d829a0353a 755 #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
tushki7 0:60d829a0353a 756 #define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
tushki7 0:60d829a0353a 757 #define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
tushki7 0:60d829a0353a 758 #define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
tushki7 0:60d829a0353a 759 /**
tushki7 0:60d829a0353a 760 * @}
tushki7 0:60d829a0353a 761 */
tushki7 0:60d829a0353a 762
tushki7 0:60d829a0353a 763 /** @defgroup RCC_HSI_Configuration RCC HSI Configuration
tushki7 0:60d829a0353a 764 * @{
tushki7 0:60d829a0353a 765 */
tushki7 0:60d829a0353a 766
tushki7 0:60d829a0353a 767 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
tushki7 0:60d829a0353a 768 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
tushki7 0:60d829a0353a 769 * It is used (enabled by hardware) as system clock source after startup
tushki7 0:60d829a0353a 770 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
tushki7 0:60d829a0353a 771 * of the HSE used directly or indirectly as system clock (if the Clock
tushki7 0:60d829a0353a 772 * Security System CSS is enabled).
tushki7 0:60d829a0353a 773 * @note HSI can not be stopped if it is used as system clock source. In this case,
tushki7 0:60d829a0353a 774 * you have to select another source of the system clock then stop the HSI.
tushki7 0:60d829a0353a 775 * @note After enabling the HSI, the application software should wait on HSIRDY
tushki7 0:60d829a0353a 776 * flag to be set indicating that HSI clock is stable and can be used as
tushki7 0:60d829a0353a 777 * system clock source.
tushki7 0:60d829a0353a 778 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
tushki7 0:60d829a0353a 779 * clock cycles.
tushki7 0:60d829a0353a 780 */
tushki7 0:60d829a0353a 781 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
tushki7 0:60d829a0353a 782 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
tushki7 0:60d829a0353a 783
tushki7 0:60d829a0353a 784 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
tushki7 0:60d829a0353a 785 * @note The calibration is used to compensate for the variations in voltage
tushki7 0:60d829a0353a 786 * and temperature that influence the frequency of the internal HSI RC.
tushki7 0:60d829a0353a 787 * @param __HSICalibrationValue__: specifies the calibration trimming value
tushki7 0:60d829a0353a 788 * (default is RCC_HSICALIBRATION_DEFAULT).
tushki7 0:60d829a0353a 789 * This parameter must be a number between 0 and 0x1F.
tushki7 0:60d829a0353a 790 */
tushki7 0:60d829a0353a 791 #define RCC_CR_HSITRIM_BitNumber 3
tushki7 0:60d829a0353a 792 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
tushki7 0:60d829a0353a 793 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber)
tushki7 0:60d829a0353a 794 /**
tushki7 0:60d829a0353a 795 * @}
tushki7 0:60d829a0353a 796 */
tushki7 0:60d829a0353a 797
tushki7 0:60d829a0353a 798 /** @defgroup RCC_LSI_Configuration RCC LSI Configuration
tushki7 0:60d829a0353a 799 * @{
tushki7 0:60d829a0353a 800 */
tushki7 0:60d829a0353a 801
tushki7 0:60d829a0353a 802 /** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
tushki7 0:60d829a0353a 803 * @note After enabling the LSI, the application software should wait on
tushki7 0:60d829a0353a 804 * LSIRDY flag to be set indicating that LSI clock is stable and can
tushki7 0:60d829a0353a 805 * be used to clock the IWDG and/or the RTC.
tushki7 0:60d829a0353a 806 * @note LSI can not be disabled if the IWDG is running.
tushki7 0:60d829a0353a 807 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
tushki7 0:60d829a0353a 808 * clock cycles.
tushki7 0:60d829a0353a 809 */
tushki7 0:60d829a0353a 810 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
tushki7 0:60d829a0353a 811 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
tushki7 0:60d829a0353a 812 /**
tushki7 0:60d829a0353a 813 * @}
tushki7 0:60d829a0353a 814 */
tushki7 0:60d829a0353a 815
tushki7 0:60d829a0353a 816 /** @defgroup RCC_HSE_Configuration RCC HSE Configuration
tushki7 0:60d829a0353a 817 * @{
tushki7 0:60d829a0353a 818 */
tushki7 0:60d829a0353a 819
tushki7 0:60d829a0353a 820 /**
tushki7 0:60d829a0353a 821 * @brief Macro to configure the External High Speed oscillator (HSE).
tushki7 0:60d829a0353a 822 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
tushki7 0:60d829a0353a 823 * software should wait on HSERDY flag to be set indicating that HSE clock
tushki7 0:60d829a0353a 824 * is stable and can be used to clock the PLL and/or system clock.
tushki7 0:60d829a0353a 825 * @note HSE state can not be changed if it is used directly or through the
tushki7 0:60d829a0353a 826 * PLL as system clock. In this case, you have to select another source
tushki7 0:60d829a0353a 827 * of the system clock then change the HSE state (ex. disable it).
tushki7 0:60d829a0353a 828 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
tushki7 0:60d829a0353a 829 * @note This function reset the CSSON bit, so if the Clock security system(CSS)
tushki7 0:60d829a0353a 830 * was previously enabled you have to enable it again after calling this
tushki7 0:60d829a0353a 831 * function.
tushki7 0:60d829a0353a 832 * @param __STATE__: specifies the new state of the HSE.
tushki7 0:60d829a0353a 833 * This parameter can be one of the following values:
tushki7 0:60d829a0353a 834 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
tushki7 0:60d829a0353a 835 * 6 HSE oscillator clock cycles.
tushki7 0:60d829a0353a 836 * @arg RCC_HSE_ON: turn ON the HSE oscillator
tushki7 0:60d829a0353a 837 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
tushki7 0:60d829a0353a 838 */
tushki7 0:60d829a0353a 839 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)RCC_CR_BYTE2_ADDRESS = (__STATE__))
tushki7 0:60d829a0353a 840
tushki7 0:60d829a0353a 841 /**
tushki7 0:60d829a0353a 842 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
tushki7 0:60d829a0353a 843 * @note Predivision factor can not be changed if PLL is used as system clock
tushki7 0:60d829a0353a 844 * In this case, you have to select another source of the system clock, disable the PLL and
tushki7 0:60d829a0353a 845 * then change the HSE predivision factor.
tushki7 0:60d829a0353a 846 * @param __HSEPredivValue__: specifies the division value applied to HSE.
tushki7 0:60d829a0353a 847 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
tushki7 0:60d829a0353a 848 */
tushki7 0:60d829a0353a 849 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
tushki7 0:60d829a0353a 850 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
tushki7 0:60d829a0353a 851 /**
tushki7 0:60d829a0353a 852 * @}
tushki7 0:60d829a0353a 853 */
tushki7 0:60d829a0353a 854
tushki7 0:60d829a0353a 855 /** @defgroup RCC_LSE_Configuration RCC LSE Configuration
tushki7 0:60d829a0353a 856 * @{
tushki7 0:60d829a0353a 857 */
tushki7 0:60d829a0353a 858 /**
tushki7 0:60d829a0353a 859 * @brief Macro to configure the External Low Speed oscillator (LSE).
tushki7 0:60d829a0353a 860 * @note As the LSE is in the Backup domain and write access is denied to
tushki7 0:60d829a0353a 861 * this domain after reset, you have to enable write access using
tushki7 0:60d829a0353a 862 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
tushki7 0:60d829a0353a 863 * (to be done once after reset).
tushki7 0:60d829a0353a 864 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
tushki7 0:60d829a0353a 865 * software should wait on LSERDY flag to be set indicating that LSE clock
tushki7 0:60d829a0353a 866 * is stable and can be used to clock the RTC.
tushki7 0:60d829a0353a 867 * @param __STATE__: specifies the new state of the LSE.
tushki7 0:60d829a0353a 868 * This parameter can be one of the following values:
tushki7 0:60d829a0353a 869 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
tushki7 0:60d829a0353a 870 * 6 LSE oscillator clock cycles.
tushki7 0:60d829a0353a 871 * @arg RCC_LSE_ON: turn ON the LSE oscillator
tushki7 0:60d829a0353a 872 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
tushki7 0:60d829a0353a 873 */
tushki7 0:60d829a0353a 874 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
tushki7 0:60d829a0353a 875 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
tushki7 0:60d829a0353a 876 /**
tushki7 0:60d829a0353a 877 * @}
tushki7 0:60d829a0353a 878 */
tushki7 0:60d829a0353a 879
tushki7 0:60d829a0353a 880 /** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
tushki7 0:60d829a0353a 881 * @{
tushki7 0:60d829a0353a 882 */
tushki7 0:60d829a0353a 883
tushki7 0:60d829a0353a 884 /** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14).
tushki7 0:60d829a0353a 885 * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
tushki7 0:60d829a0353a 886 * @note HSI14 can not be stopped if it is used as system clock source. In this case,
tushki7 0:60d829a0353a 887 * you have to select another source of the system clock then stop the HSI14.
tushki7 0:60d829a0353a 888 * @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software
tushki7 0:60d829a0353a 889 * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
tushki7 0:60d829a0353a 890 * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
tushki7 0:60d829a0353a 891 * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
tushki7 0:60d829a0353a 892 * clock cycles.
tushki7 0:60d829a0353a 893 */
tushki7 0:60d829a0353a 894 #define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
tushki7 0:60d829a0353a 895 #define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
tushki7 0:60d829a0353a 896
tushki7 0:60d829a0353a 897 /** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC.
tushki7 0:60d829a0353a 898 */
tushki7 0:60d829a0353a 899 #define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
tushki7 0:60d829a0353a 900 #define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
tushki7 0:60d829a0353a 901
tushki7 0:60d829a0353a 902 /** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
tushki7 0:60d829a0353a 903 * @note The calibration is used to compensate for the variations in voltage
tushki7 0:60d829a0353a 904 * and temperature that influence the frequency of the internal HSI14 RC.
tushki7 0:60d829a0353a 905 * @param __HSI14CalibrationValue__: specifies the calibration trimming value
tushki7 0:60d829a0353a 906 * (default is RCC_HSI14CALIBRATION_DEFAULT).
tushki7 0:60d829a0353a 907 * This parameter must be a number between 0 and 0x1F.
tushki7 0:60d829a0353a 908 */
tushki7 0:60d829a0353a 909 #define RCC_CR2_HSI14TRIM_BitNumber 3
tushki7 0:60d829a0353a 910 #define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \
tushki7 0:60d829a0353a 911 MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber)
tushki7 0:60d829a0353a 912 /**
tushki7 0:60d829a0353a 913 * @}
tushki7 0:60d829a0353a 914 */
tushki7 0:60d829a0353a 915
tushki7 0:60d829a0353a 916 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
tushki7 0:60d829a0353a 917 * @{
tushki7 0:60d829a0353a 918 */
tushki7 0:60d829a0353a 919
tushki7 0:60d829a0353a 920 /** @brief Macro to configure the USART1 clock (USART1CLK).
tushki7 0:60d829a0353a 921 * @param __USART1CLKSource__: specifies the USART1 clock source.
tushki7 0:60d829a0353a 922 * This parameter can be one of the following values:
tushki7 0:60d829a0353a 923 * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
tushki7 0:60d829a0353a 924 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
tushki7 0:60d829a0353a 925 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
tushki7 0:60d829a0353a 926 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
tushki7 0:60d829a0353a 927 */
tushki7 0:60d829a0353a 928 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
tushki7 0:60d829a0353a 929 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
tushki7 0:60d829a0353a 930
tushki7 0:60d829a0353a 931 /** @brief Macro to get the USART1 clock source.
tushki7 0:60d829a0353a 932 * @retval The clock source can be one of the following values:
tushki7 0:60d829a0353a 933 * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
tushki7 0:60d829a0353a 934 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
tushki7 0:60d829a0353a 935 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
tushki7 0:60d829a0353a 936 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
tushki7 0:60d829a0353a 937 */
tushki7 0:60d829a0353a 938 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
tushki7 0:60d829a0353a 939 /**
tushki7 0:60d829a0353a 940 * @}
tushki7 0:60d829a0353a 941 */
tushki7 0:60d829a0353a 942
tushki7 0:60d829a0353a 943 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
tushki7 0:60d829a0353a 944 * @{
tushki7 0:60d829a0353a 945 */
tushki7 0:60d829a0353a 946
tushki7 0:60d829a0353a 947 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
tushki7 0:60d829a0353a 948 * @param __I2C1CLKSource__: specifies the I2C1 clock source.
tushki7 0:60d829a0353a 949 * This parameter can be one of the following values:
tushki7 0:60d829a0353a 950 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
tushki7 0:60d829a0353a 951 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
tushki7 0:60d829a0353a 952 */
tushki7 0:60d829a0353a 953 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
tushki7 0:60d829a0353a 954 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
tushki7 0:60d829a0353a 955
tushki7 0:60d829a0353a 956 /** @brief Macro to get the I2C1 clock source.
tushki7 0:60d829a0353a 957 * @retval The clock source can be one of the following values:
tushki7 0:60d829a0353a 958 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
tushki7 0:60d829a0353a 959 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
tushki7 0:60d829a0353a 960 */
tushki7 0:60d829a0353a 961 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
tushki7 0:60d829a0353a 962 /**
tushki7 0:60d829a0353a 963 * @}
tushki7 0:60d829a0353a 964 */
tushki7 0:60d829a0353a 965
tushki7 0:60d829a0353a 966 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
tushki7 0:60d829a0353a 967 * @{
tushki7 0:60d829a0353a 968 */
tushki7 0:60d829a0353a 969 /** @brief Macros to enable or disable the the RTC clock.
tushki7 0:60d829a0353a 970 * @note These macros must be used only after the RTC clock source was selected.
tushki7 0:60d829a0353a 971 */
tushki7 0:60d829a0353a 972 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
tushki7 0:60d829a0353a 973 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
tushki7 0:60d829a0353a 974
tushki7 0:60d829a0353a 975 /** @brief Macro to configure the RTC clock (RTCCLK).
tushki7 0:60d829a0353a 976 * @note As the RTC clock configuration bits are in the Backup domain and write
tushki7 0:60d829a0353a 977 * access is denied to this domain after reset, you have to enable write
tushki7 0:60d829a0353a 978 * access using the Power Backup Access macro before to configure
tushki7 0:60d829a0353a 979 * the RTC clock source (to be done once after reset).
tushki7 0:60d829a0353a 980 * @note Once the RTC clock is configured it can't be changed unless the
tushki7 0:60d829a0353a 981 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
tushki7 0:60d829a0353a 982 * a Power On Reset (POR).
tushki7 0:60d829a0353a 983 * @param __RTCCLKSource__: specifies the RTC clock source.
tushki7 0:60d829a0353a 984 * This parameter can be one of the following values:
tushki7 0:60d829a0353a 985 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
tushki7 0:60d829a0353a 986 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
tushki7 0:60d829a0353a 987 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
tushki7 0:60d829a0353a 988 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
tushki7 0:60d829a0353a 989 *
tushki7 0:60d829a0353a 990 * @note If the LSE is used as RTC clock source, the RTC continues to
tushki7 0:60d829a0353a 991 * work in STOP and STANDBY modes, and can be used as wakeup source.
tushki7 0:60d829a0353a 992 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
tushki7 0:60d829a0353a 993 * the RTC cannot be used in STOP and STANDBY modes.
tushki7 0:60d829a0353a 994 * @note The system must always be configured so as to get a PCLK frequency greater than or
tushki7 0:60d829a0353a 995 * equal to the RTCCLK frequency for a proper operation of the RTC.
tushki7 0:60d829a0353a 996 */
tushki7 0:60d829a0353a 997 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
tushki7 0:60d829a0353a 998 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
tushki7 0:60d829a0353a 999
tushki7 0:60d829a0353a 1000 /** @brief Macro to get the RTC clock source.
tushki7 0:60d829a0353a 1001 * @retval The clock source can be one of the following values:
tushki7 0:60d829a0353a 1002 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
tushki7 0:60d829a0353a 1003 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
tushki7 0:60d829a0353a 1004 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
tushki7 0:60d829a0353a 1005 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
tushki7 0:60d829a0353a 1006 */
tushki7 0:60d829a0353a 1007 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
tushki7 0:60d829a0353a 1008 /**
tushki7 0:60d829a0353a 1009 * @}
tushki7 0:60d829a0353a 1010 */
tushki7 0:60d829a0353a 1011
tushki7 0:60d829a0353a 1012 /** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
tushki7 0:60d829a0353a 1013 * @{
tushki7 0:60d829a0353a 1014 */
tushki7 0:60d829a0353a 1015
tushki7 0:60d829a0353a 1016 /** @brief Macro to force or release the Backup domain reset.
tushki7 0:60d829a0353a 1017 * @note These macros reset the RTC peripheral (including the backup registers)
tushki7 0:60d829a0353a 1018 * and the RTC clock source selection in RCC_CSR register.
tushki7 0:60d829a0353a 1019 * @note The BKPSRAM is not affected by this reset.
tushki7 0:60d829a0353a 1020 */
tushki7 0:60d829a0353a 1021 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
tushki7 0:60d829a0353a 1022 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
tushki7 0:60d829a0353a 1023 /**
tushki7 0:60d829a0353a 1024 * @}
tushki7 0:60d829a0353a 1025 */
tushki7 0:60d829a0353a 1026
tushki7 0:60d829a0353a 1027 /** @defgroup RCC_PLL_Configuration RCC PLL Configuration
tushki7 0:60d829a0353a 1028 * @{
tushki7 0:60d829a0353a 1029 */
tushki7 0:60d829a0353a 1030
tushki7 0:60d829a0353a 1031 /** @brief Macro to enable or disable the PLL.
tushki7 0:60d829a0353a 1032 * @note After enabling the PLL, the application software should wait on
tushki7 0:60d829a0353a 1033 * PLLRDY flag to be set indicating that PLL clock is stable and can
tushki7 0:60d829a0353a 1034 * be used as system clock source.
tushki7 0:60d829a0353a 1035 * @note The PLL can not be disabled if it is used as system clock source
tushki7 0:60d829a0353a 1036 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
tushki7 0:60d829a0353a 1037 */
tushki7 0:60d829a0353a 1038 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
tushki7 0:60d829a0353a 1039 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
tushki7 0:60d829a0353a 1040
tushki7 0:60d829a0353a 1041 /** @brief Macro to configure the PLL clock source, multiplication and division factors.
tushki7 0:60d829a0353a 1042 * @note This macro must be used only when the PLL is disabled.
tushki7 0:60d829a0353a 1043 *
tushki7 0:60d829a0353a 1044 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
tushki7 0:60d829a0353a 1045 * This parameter can be one of the following values:
tushki7 0:60d829a0353a 1046 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
tushki7 0:60d829a0353a 1047 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
tushki7 0:60d829a0353a 1048 * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
tushki7 0:60d829a0353a 1049 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
tushki7 0:60d829a0353a 1050 * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
tushki7 0:60d829a0353a 1051 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
tushki7 0:60d829a0353a 1052 *
tushki7 0:60d829a0353a 1053 */
tushki7 0:60d829a0353a 1054 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
tushki7 0:60d829a0353a 1055 do { \
tushki7 0:60d829a0353a 1056 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
tushki7 0:60d829a0353a 1057 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
tushki7 0:60d829a0353a 1058 } while(0)
tushki7 0:60d829a0353a 1059 /**
tushki7 0:60d829a0353a 1060 * @}
tushki7 0:60d829a0353a 1061 */
tushki7 0:60d829a0353a 1062
tushki7 0:60d829a0353a 1063 /** @defgroup RCC_Get_Clock_source RCC Get Clock source
tushki7 0:60d829a0353a 1064 * @{
tushki7 0:60d829a0353a 1065 */
tushki7 0:60d829a0353a 1066
tushki7 0:60d829a0353a 1067 /** @brief Macro to get the clock source used as system clock.
tushki7 0:60d829a0353a 1068 * @retval The clock source used as system clock.
tushki7 0:60d829a0353a 1069 * The returned value can be one of the following value:
tushki7 0:60d829a0353a 1070 * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
tushki7 0:60d829a0353a 1071 * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
tushki7 0:60d829a0353a 1072 * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
tushki7 0:60d829a0353a 1073 */
tushki7 0:60d829a0353a 1074 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
tushki7 0:60d829a0353a 1075
tushki7 0:60d829a0353a 1076 /** @brief Macro to get the oscillator used as PLL clock source.
tushki7 0:60d829a0353a 1077 * @retval The oscillator used as PLL clock source. The returned value can be one
tushki7 0:60d829a0353a 1078 * of the following:
tushki7 0:60d829a0353a 1079 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
tushki7 0:60d829a0353a 1080 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
tushki7 0:60d829a0353a 1081 */
tushki7 0:60d829a0353a 1082 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
tushki7 0:60d829a0353a 1083 /**
tushki7 0:60d829a0353a 1084 * @}
tushki7 0:60d829a0353a 1085 */
tushki7 0:60d829a0353a 1086
tushki7 0:60d829a0353a 1087 /** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
tushki7 0:60d829a0353a 1088 * @brief macros to manage the specified RCC Flags and interrupts.
tushki7 0:60d829a0353a 1089 * @{
tushki7 0:60d829a0353a 1090 */
tushki7 0:60d829a0353a 1091
tushki7 0:60d829a0353a 1092 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
tushki7 0:60d829a0353a 1093 * the selected interrupts.).
tushki7 0:60d829a0353a 1094 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
tushki7 0:60d829a0353a 1095 * This parameter can be any combination of the following values:
tushki7 0:60d829a0353a 1096 * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
tushki7 0:60d829a0353a 1097 * @arg RCC_IT_LSERDY: LSE ready interrupt enable
tushki7 0:60d829a0353a 1098 * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
tushki7 0:60d829a0353a 1099 * @arg RCC_IT_HSERDY: HSE ready interrupt enable
tushki7 0:60d829a0353a 1100 * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
tushki7 0:60d829a0353a 1101 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
tushki7 0:60d829a0353a 1102 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
tushki7 0:60d829a0353a 1103 */
tushki7 0:60d829a0353a 1104 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
tushki7 0:60d829a0353a 1105
tushki7 0:60d829a0353a 1106 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
tushki7 0:60d829a0353a 1107 * the selected interrupts.).
tushki7 0:60d829a0353a 1108 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
tushki7 0:60d829a0353a 1109 * This parameter can be any combination of the following values:
tushki7 0:60d829a0353a 1110 * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
tushki7 0:60d829a0353a 1111 * @arg RCC_IT_LSERDY: LSE ready interrupt enable
tushki7 0:60d829a0353a 1112 * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
tushki7 0:60d829a0353a 1113 * @arg RCC_IT_HSERDY: HSE ready interrupt enable
tushki7 0:60d829a0353a 1114 * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
tushki7 0:60d829a0353a 1115 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
tushki7 0:60d829a0353a 1116 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
tushki7 0:60d829a0353a 1117 */
tushki7 0:60d829a0353a 1118 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
tushki7 0:60d829a0353a 1119
tushki7 0:60d829a0353a 1120 /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
tushki7 0:60d829a0353a 1121 * bits to clear the selected interrupt pending bits.
tushki7 0:60d829a0353a 1122 * @param __IT__: specifies the interrupt pending bit to clear.
tushki7 0:60d829a0353a 1123 * This parameter can be any combination of the following values:
tushki7 0:60d829a0353a 1124 * @arg RCC_IT_LSIRDY: LSI ready interrupt clear
tushki7 0:60d829a0353a 1125 * @arg RCC_IT_LSERDY: LSE ready interrupt clear
tushki7 0:60d829a0353a 1126 * @arg RCC_IT_HSIRDY: HSI ready interrupt clear
tushki7 0:60d829a0353a 1127 * @arg RCC_IT_HSERDY: HSE ready interrupt clear
tushki7 0:60d829a0353a 1128 * @arg RCC_IT_PLLRDY: PLL ready interrupt clear
tushki7 0:60d829a0353a 1129 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear
tushki7 0:60d829a0353a 1130 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices)
tushki7 0:60d829a0353a 1131 * @arg RCC_IT_CSS: Clock Security System interrupt clear
tushki7 0:60d829a0353a 1132 */
tushki7 0:60d829a0353a 1133 #define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__IT__))
tushki7 0:60d829a0353a 1134
tushki7 0:60d829a0353a 1135 /** @brief Check the RCC's interrupt has occurred or not.
tushki7 0:60d829a0353a 1136 * @param __IT__: specifies the RCC interrupt source to check.
tushki7 0:60d829a0353a 1137 * This parameter can be one of the following values:
tushki7 0:60d829a0353a 1138 * @arg RCC_IT_LSIRDY: LSI ready interrupt flag
tushki7 0:60d829a0353a 1139 * @arg RCC_IT_LSERDY: LSE ready interrupt flag
tushki7 0:60d829a0353a 1140 * @arg RCC_IT_HSIRDY: HSI ready interrupt flag
tushki7 0:60d829a0353a 1141 * @arg RCC_IT_HSERDY: HSE ready interrupt flag
tushki7 0:60d829a0353a 1142 * @arg RCC_IT_PLLRDY: PLL ready interrupt flag
tushki7 0:60d829a0353a 1143 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag
tushki7 0:60d829a0353a 1144 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices)
tushki7 0:60d829a0353a 1145 * @arg RCC_IT_CSS: Clock Security System interrupt flag
tushki7 0:60d829a0353a 1146 * @retval The new state of __IT__ (TRUE or FALSE).
tushki7 0:60d829a0353a 1147 */
tushki7 0:60d829a0353a 1148 #define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
tushki7 0:60d829a0353a 1149
tushki7 0:60d829a0353a 1150 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
tushki7 0:60d829a0353a 1151 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
tushki7 0:60d829a0353a 1152 */
tushki7 0:60d829a0353a 1153 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
tushki7 0:60d829a0353a 1154
tushki7 0:60d829a0353a 1155 /** @brief Check RCC flag is set or not.
tushki7 0:60d829a0353a 1156 * @param __FLAG__: specifies the flag to check.
tushki7 0:60d829a0353a 1157 * This parameter can be one of the following values:
tushki7 0:60d829a0353a 1158 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
tushki7 0:60d829a0353a 1159 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
tushki7 0:60d829a0353a 1160 * @arg RCC_FLAG_PLLRDY: PLL clock ready
tushki7 0:60d829a0353a 1161 * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
tushki7 0:60d829a0353a 1162 * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
tushki7 0:60d829a0353a 1163 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
tushki7 0:60d829a0353a 1164 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
tushki7 0:60d829a0353a 1165 * @arg RCC_FLAG_OBLRST: Option Byte Load reset
tushki7 0:60d829a0353a 1166 * @arg RCC_FLAG_PINRST: Pin reset
tushki7 0:60d829a0353a 1167 * @arg RCC_FLAG_PORRST: POR/PDR reset
tushki7 0:60d829a0353a 1168 * @arg RCC_FLAG_SFTRST: Software reset
tushki7 0:60d829a0353a 1169 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
tushki7 0:60d829a0353a 1170 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
tushki7 0:60d829a0353a 1171 * @arg RCC_FLAG_LPWRRST: Low Power reset
tushki7 0:60d829a0353a 1172 * @retval The new state of __FLAG__ (TRUE or FALSE).
tushki7 0:60d829a0353a 1173 */
tushki7 0:60d829a0353a 1174 #define RCC_FLAG_MASK ((uint8_t)0x1F)
tushki7 0:60d829a0353a 1175 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
tushki7 0:60d829a0353a 1176 (((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
tushki7 0:60d829a0353a 1177 (((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
tushki7 0:60d829a0353a 1178 RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
tushki7 0:60d829a0353a 1179
tushki7 0:60d829a0353a 1180
tushki7 0:60d829a0353a 1181
tushki7 0:60d829a0353a 1182 /**
tushki7 0:60d829a0353a 1183 * @}
tushki7 0:60d829a0353a 1184 */
tushki7 0:60d829a0353a 1185
tushki7 0:60d829a0353a 1186 /**
tushki7 0:60d829a0353a 1187 * @}
tushki7 0:60d829a0353a 1188 */
tushki7 0:60d829a0353a 1189
tushki7 0:60d829a0353a 1190 /* Include RCC HAL Extension module */
tushki7 0:60d829a0353a 1191 #include "stm32f0xx_hal_rcc_ex.h"
tushki7 0:60d829a0353a 1192
tushki7 0:60d829a0353a 1193 /* Exported functions --------------------------------------------------------*/
tushki7 0:60d829a0353a 1194
tushki7 0:60d829a0353a 1195 /** @addtogroup RCC_Exported_Functions
tushki7 0:60d829a0353a 1196 * @{
tushki7 0:60d829a0353a 1197 */
tushki7 0:60d829a0353a 1198
tushki7 0:60d829a0353a 1199 /** @addtogroup RCC_Exported_Functions_Group1
tushki7 0:60d829a0353a 1200 * @{
tushki7 0:60d829a0353a 1201 */
tushki7 0:60d829a0353a 1202
tushki7 0:60d829a0353a 1203 /* Initialization and de-initialization functions ***************************/
tushki7 0:60d829a0353a 1204 void HAL_RCC_DeInit(void);
tushki7 0:60d829a0353a 1205 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
tushki7 0:60d829a0353a 1206 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
tushki7 0:60d829a0353a 1207
tushki7 0:60d829a0353a 1208 /**
tushki7 0:60d829a0353a 1209 * @}
tushki7 0:60d829a0353a 1210 */
tushki7 0:60d829a0353a 1211
tushki7 0:60d829a0353a 1212 /** @addtogroup RCC_Exported_Functions_Group2
tushki7 0:60d829a0353a 1213 * @{
tushki7 0:60d829a0353a 1214 */
tushki7 0:60d829a0353a 1215
tushki7 0:60d829a0353a 1216 /* Peripheral Control functions *********************************************/
tushki7 0:60d829a0353a 1217 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
tushki7 0:60d829a0353a 1218 void HAL_RCC_EnableCSS(void);
tushki7 0:60d829a0353a 1219 void HAL_RCC_DisableCSS(void);
tushki7 0:60d829a0353a 1220 uint32_t HAL_RCC_GetSysClockFreq(void);
tushki7 0:60d829a0353a 1221 uint32_t HAL_RCC_GetHCLKFreq(void);
tushki7 0:60d829a0353a 1222 uint32_t HAL_RCC_GetPCLK1Freq(void);
tushki7 0:60d829a0353a 1223 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
tushki7 0:60d829a0353a 1224 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
tushki7 0:60d829a0353a 1225
tushki7 0:60d829a0353a 1226 /* CSS NMI IRQ handler */
tushki7 0:60d829a0353a 1227 void HAL_RCC_NMI_IRQHandler(void);
tushki7 0:60d829a0353a 1228
tushki7 0:60d829a0353a 1229 /* User Callbacks in non blocking mode (IT mode) */
tushki7 0:60d829a0353a 1230 void HAL_RCC_CCSCallback(void);
tushki7 0:60d829a0353a 1231
tushki7 0:60d829a0353a 1232 /**
tushki7 0:60d829a0353a 1233 * @}
tushki7 0:60d829a0353a 1234 */
tushki7 0:60d829a0353a 1235
tushki7 0:60d829a0353a 1236 /**
tushki7 0:60d829a0353a 1237 * @}
tushki7 0:60d829a0353a 1238 */
tushki7 0:60d829a0353a 1239
tushki7 0:60d829a0353a 1240 /**
tushki7 0:60d829a0353a 1241 * @}
tushki7 0:60d829a0353a 1242 */
tushki7 0:60d829a0353a 1243
tushki7 0:60d829a0353a 1244 /**
tushki7 0:60d829a0353a 1245 * @}
tushki7 0:60d829a0353a 1246 */
tushki7 0:60d829a0353a 1247
tushki7 0:60d829a0353a 1248 #ifdef __cplusplus
tushki7 0:60d829a0353a 1249 }
tushki7 0:60d829a0353a 1250 #endif
tushki7 0:60d829a0353a 1251
tushki7 0:60d829a0353a 1252 #endif /* __STM32F0xx_HAL_RCC_H */
tushki7 0:60d829a0353a 1253
tushki7 0:60d829a0353a 1254 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
tushki7 0:60d829a0353a 1255