Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_NUCLEO_F070RB/stm32f070xb.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a 
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /**
tushki7 0:60d829a0353a 2 ******************************************************************************
tushki7 0:60d829a0353a 3 * @file stm32f070xb.h
tushki7 0:60d829a0353a 4 * @author MCD Application Team
tushki7 0:60d829a0353a 5 * @version V2.2.0
tushki7 0:60d829a0353a 6 * @date 05-December-2014
tushki7 0:60d829a0353a 7 * @brief CMSIS STM32F070xB devices Peripheral Access Layer Header File.
tushki7 0:60d829a0353a 8 *
tushki7 0:60d829a0353a 9 * This file contains:
tushki7 0:60d829a0353a 10 * - Data structures and the address mapping for all peripherals
tushki7 0:60d829a0353a 11 * - Peripheral's registers declarations and bits definition
tushki7 0:60d829a0353a 12 * - Macros to access peripheral’s registers hardware
tushki7 0:60d829a0353a 13 *
tushki7 0:60d829a0353a 14 ******************************************************************************
tushki7 0:60d829a0353a 15 * @attention
tushki7 0:60d829a0353a 16 *
tushki7 0:60d829a0353a 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
tushki7 0:60d829a0353a 18 *
tushki7 0:60d829a0353a 19 * Redistribution and use in source and binary forms, with or without modification,
tushki7 0:60d829a0353a 20 * are permitted provided that the following conditions are met:
tushki7 0:60d829a0353a 21 * 1. Redistributions of source code must retain the above copyright notice,
tushki7 0:60d829a0353a 22 * this list of conditions and the following disclaimer.
tushki7 0:60d829a0353a 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
tushki7 0:60d829a0353a 24 * this list of conditions and the following disclaimer in the documentation
tushki7 0:60d829a0353a 25 * and/or other materials provided with the distribution.
tushki7 0:60d829a0353a 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
tushki7 0:60d829a0353a 27 * may be used to endorse or promote products derived from this software
tushki7 0:60d829a0353a 28 * without specific prior written permission.
tushki7 0:60d829a0353a 29 *
tushki7 0:60d829a0353a 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
tushki7 0:60d829a0353a 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
tushki7 0:60d829a0353a 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
tushki7 0:60d829a0353a 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
tushki7 0:60d829a0353a 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
tushki7 0:60d829a0353a 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
tushki7 0:60d829a0353a 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
tushki7 0:60d829a0353a 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
tushki7 0:60d829a0353a 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
tushki7 0:60d829a0353a 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
tushki7 0:60d829a0353a 40 *
tushki7 0:60d829a0353a 41 ******************************************************************************
tushki7 0:60d829a0353a 42 */
tushki7 0:60d829a0353a 43
tushki7 0:60d829a0353a 44 /** @addtogroup CMSIS_Device
tushki7 0:60d829a0353a 45 * @{
tushki7 0:60d829a0353a 46 */
tushki7 0:60d829a0353a 47
tushki7 0:60d829a0353a 48 /** @addtogroup stm32f070xb
tushki7 0:60d829a0353a 49 * @{
tushki7 0:60d829a0353a 50 */
tushki7 0:60d829a0353a 51
tushki7 0:60d829a0353a 52 #ifndef __STM32F070xB_H
tushki7 0:60d829a0353a 53 #define __STM32F070xB_H
tushki7 0:60d829a0353a 54
tushki7 0:60d829a0353a 55 #ifdef __cplusplus
tushki7 0:60d829a0353a 56 extern "C" {
tushki7 0:60d829a0353a 57 #endif /* __cplusplus */
tushki7 0:60d829a0353a 58
tushki7 0:60d829a0353a 59 /** @addtogroup Configuration_section_for_CMSIS
tushki7 0:60d829a0353a 60 * @{
tushki7 0:60d829a0353a 61 */
tushki7 0:60d829a0353a 62
tushki7 0:60d829a0353a 63 /**
tushki7 0:60d829a0353a 64 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
tushki7 0:60d829a0353a 65 */
tushki7 0:60d829a0353a 66 #define __CM0_REV 0 /*!< Core Revision r0p0 */
tushki7 0:60d829a0353a 67 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
tushki7 0:60d829a0353a 68 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
tushki7 0:60d829a0353a 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
tushki7 0:60d829a0353a 70
tushki7 0:60d829a0353a 71 /**
tushki7 0:60d829a0353a 72 * @}
tushki7 0:60d829a0353a 73 */
tushki7 0:60d829a0353a 74
tushki7 0:60d829a0353a 75 /** @addtogroup Peripheral_interrupt_number_definition
tushki7 0:60d829a0353a 76 * @{
tushki7 0:60d829a0353a 77 */
tushki7 0:60d829a0353a 78
tushki7 0:60d829a0353a 79 /**
tushki7 0:60d829a0353a 80 * @brief STM32F070xB device Interrupt Number Definition
tushki7 0:60d829a0353a 81 */
tushki7 0:60d829a0353a 82 typedef enum
tushki7 0:60d829a0353a 83 {
tushki7 0:60d829a0353a 84 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
tushki7 0:60d829a0353a 85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
tushki7 0:60d829a0353a 86 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
tushki7 0:60d829a0353a 87 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
tushki7 0:60d829a0353a 88 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
tushki7 0:60d829a0353a 89 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
tushki7 0:60d829a0353a 90
tushki7 0:60d829a0353a 91 /****** STM32F070xB specific Interrupt Numbers **************************************************/
tushki7 0:60d829a0353a 92 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
tushki7 0:60d829a0353a 93 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
tushki7 0:60d829a0353a 94 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
tushki7 0:60d829a0353a 95 RCC_IRQn = 4, /*!< RCC Global Interrupts */
tushki7 0:60d829a0353a 96 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
tushki7 0:60d829a0353a 97 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
tushki7 0:60d829a0353a 98 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
tushki7 0:60d829a0353a 99 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
tushki7 0:60d829a0353a 100 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
tushki7 0:60d829a0353a 101 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
tushki7 0:60d829a0353a 102 ADC1_IRQn = 12, /*!< ADC1 interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
tushki7 0:60d829a0353a 103 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
tushki7 0:60d829a0353a 104 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
tushki7 0:60d829a0353a 105 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
tushki7 0:60d829a0353a 106 TIM6_IRQn = 17, /*!< TIM6 global Interrupts */
tushki7 0:60d829a0353a 107 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
tushki7 0:60d829a0353a 108 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
tushki7 0:60d829a0353a 109 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
tushki7 0:60d829a0353a 110 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
tushki7 0:60d829a0353a 111 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
tushki7 0:60d829a0353a 112 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
tushki7 0:60d829a0353a 113 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
tushki7 0:60d829a0353a 114 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
tushki7 0:60d829a0353a 115 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
tushki7 0:60d829a0353a 116 USART1_IRQn = 27, /*!< USART1 global Interrupt */
tushki7 0:60d829a0353a 117 USART2_IRQn = 28, /*!< USART2 global Interrupt */
tushki7 0:60d829a0353a 118 USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupts */
tushki7 0:60d829a0353a 119 USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */
tushki7 0:60d829a0353a 120 } IRQn_Type;
tushki7 0:60d829a0353a 121
tushki7 0:60d829a0353a 122 /**
tushki7 0:60d829a0353a 123 * @}
tushki7 0:60d829a0353a 124 */
tushki7 0:60d829a0353a 125
tushki7 0:60d829a0353a 126 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
tushki7 0:60d829a0353a 127 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
tushki7 0:60d829a0353a 128 #include <stdint.h>
tushki7 0:60d829a0353a 129
tushki7 0:60d829a0353a 130 /** @addtogroup Peripheral_registers_structures
tushki7 0:60d829a0353a 131 * @{
tushki7 0:60d829a0353a 132 */
tushki7 0:60d829a0353a 133
tushki7 0:60d829a0353a 134 /**
tushki7 0:60d829a0353a 135 * @brief Analog to Digital Converter
tushki7 0:60d829a0353a 136 */
tushki7 0:60d829a0353a 137
tushki7 0:60d829a0353a 138 typedef struct
tushki7 0:60d829a0353a 139 {
tushki7 0:60d829a0353a 140 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
tushki7 0:60d829a0353a 141 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
tushki7 0:60d829a0353a 142 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
tushki7 0:60d829a0353a 143 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
tushki7 0:60d829a0353a 144 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
tushki7 0:60d829a0353a 145 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
tushki7 0:60d829a0353a 146 uint32_t RESERVED1; /*!< Reserved, 0x18 */
tushki7 0:60d829a0353a 147 uint32_t RESERVED2; /*!< Reserved, 0x1C */
tushki7 0:60d829a0353a 148 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
tushki7 0:60d829a0353a 149 uint32_t RESERVED3; /*!< Reserved, 0x24 */
tushki7 0:60d829a0353a 150 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
tushki7 0:60d829a0353a 151 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
tushki7 0:60d829a0353a 152 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
tushki7 0:60d829a0353a 153 }ADC_TypeDef;
tushki7 0:60d829a0353a 154
tushki7 0:60d829a0353a 155 typedef struct
tushki7 0:60d829a0353a 156 {
tushki7 0:60d829a0353a 157 __IO uint32_t CCR;
tushki7 0:60d829a0353a 158 }ADC_Common_TypeDef;
tushki7 0:60d829a0353a 159
tushki7 0:60d829a0353a 160 /**
tushki7 0:60d829a0353a 161 * @brief CRC calculation unit
tushki7 0:60d829a0353a 162 */
tushki7 0:60d829a0353a 163
tushki7 0:60d829a0353a 164 typedef struct
tushki7 0:60d829a0353a 165 {
tushki7 0:60d829a0353a 166 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
tushki7 0:60d829a0353a 167 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
tushki7 0:60d829a0353a 168 uint8_t RESERVED0; /*!< Reserved, 0x05 */
tushki7 0:60d829a0353a 169 uint16_t RESERVED1; /*!< Reserved, 0x06 */
tushki7 0:60d829a0353a 170 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
tushki7 0:60d829a0353a 171 uint32_t RESERVED2; /*!< Reserved, 0x0C */
tushki7 0:60d829a0353a 172 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
tushki7 0:60d829a0353a 173 __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */
tushki7 0:60d829a0353a 174 }CRC_TypeDef;
tushki7 0:60d829a0353a 175
tushki7 0:60d829a0353a 176 /**
tushki7 0:60d829a0353a 177 * @brief Debug MCU
tushki7 0:60d829a0353a 178 */
tushki7 0:60d829a0353a 179
tushki7 0:60d829a0353a 180 typedef struct
tushki7 0:60d829a0353a 181 {
tushki7 0:60d829a0353a 182 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
tushki7 0:60d829a0353a 183 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
tushki7 0:60d829a0353a 184 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
tushki7 0:60d829a0353a 185 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
tushki7 0:60d829a0353a 186 }DBGMCU_TypeDef;
tushki7 0:60d829a0353a 187
tushki7 0:60d829a0353a 188 /**
tushki7 0:60d829a0353a 189 * @brief DMA Controller
tushki7 0:60d829a0353a 190 */
tushki7 0:60d829a0353a 191
tushki7 0:60d829a0353a 192 typedef struct
tushki7 0:60d829a0353a 193 {
tushki7 0:60d829a0353a 194 __IO uint32_t CCR; /*!< DMA channel x configuration register */
tushki7 0:60d829a0353a 195 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
tushki7 0:60d829a0353a 196 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
tushki7 0:60d829a0353a 197 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
tushki7 0:60d829a0353a 198 }DMA_Channel_TypeDef;
tushki7 0:60d829a0353a 199
tushki7 0:60d829a0353a 200 typedef struct
tushki7 0:60d829a0353a 201 {
tushki7 0:60d829a0353a 202 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
tushki7 0:60d829a0353a 203 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
tushki7 0:60d829a0353a 204 }DMA_TypeDef;
tushki7 0:60d829a0353a 205
tushki7 0:60d829a0353a 206 /**
tushki7 0:60d829a0353a 207 * @brief External Interrupt/Event Controller
tushki7 0:60d829a0353a 208 */
tushki7 0:60d829a0353a 209
tushki7 0:60d829a0353a 210 typedef struct
tushki7 0:60d829a0353a 211 {
tushki7 0:60d829a0353a 212 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
tushki7 0:60d829a0353a 213 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
tushki7 0:60d829a0353a 214 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
tushki7 0:60d829a0353a 215 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
tushki7 0:60d829a0353a 216 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
tushki7 0:60d829a0353a 217 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
tushki7 0:60d829a0353a 218 }EXTI_TypeDef;
tushki7 0:60d829a0353a 219
tushki7 0:60d829a0353a 220 /**
tushki7 0:60d829a0353a 221 * @brief FLASH Registers
tushki7 0:60d829a0353a 222 */
tushki7 0:60d829a0353a 223 typedef struct
tushki7 0:60d829a0353a 224 {
tushki7 0:60d829a0353a 225 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
tushki7 0:60d829a0353a 226 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
tushki7 0:60d829a0353a 227 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
tushki7 0:60d829a0353a 228 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
tushki7 0:60d829a0353a 229 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
tushki7 0:60d829a0353a 230 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
tushki7 0:60d829a0353a 231 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
tushki7 0:60d829a0353a 232 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
tushki7 0:60d829a0353a 233 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
tushki7 0:60d829a0353a 234 }FLASH_TypeDef;
tushki7 0:60d829a0353a 235
tushki7 0:60d829a0353a 236
tushki7 0:60d829a0353a 237 /**
tushki7 0:60d829a0353a 238 * @brief Option Bytes Registers
tushki7 0:60d829a0353a 239 */
tushki7 0:60d829a0353a 240 typedef struct
tushki7 0:60d829a0353a 241 {
tushki7 0:60d829a0353a 242 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
tushki7 0:60d829a0353a 243 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
tushki7 0:60d829a0353a 244 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
tushki7 0:60d829a0353a 245 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
tushki7 0:60d829a0353a 246 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
tushki7 0:60d829a0353a 247 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
tushki7 0:60d829a0353a 248 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
tushki7 0:60d829a0353a 249 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
tushki7 0:60d829a0353a 250 }OB_TypeDef;
tushki7 0:60d829a0353a 251
tushki7 0:60d829a0353a 252 /**
tushki7 0:60d829a0353a 253 * @brief General Purpose I/O
tushki7 0:60d829a0353a 254 */
tushki7 0:60d829a0353a 255
tushki7 0:60d829a0353a 256 typedef struct
tushki7 0:60d829a0353a 257 {
tushki7 0:60d829a0353a 258 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
tushki7 0:60d829a0353a 259 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
tushki7 0:60d829a0353a 260 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
tushki7 0:60d829a0353a 261 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
tushki7 0:60d829a0353a 262 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
tushki7 0:60d829a0353a 263 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
tushki7 0:60d829a0353a 264 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
tushki7 0:60d829a0353a 265 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
tushki7 0:60d829a0353a 266 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
tushki7 0:60d829a0353a 267 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
tushki7 0:60d829a0353a 268 }GPIO_TypeDef;
tushki7 0:60d829a0353a 269
tushki7 0:60d829a0353a 270 /**
tushki7 0:60d829a0353a 271 * @brief SysTem Configuration
tushki7 0:60d829a0353a 272 */
tushki7 0:60d829a0353a 273
tushki7 0:60d829a0353a 274 typedef struct
tushki7 0:60d829a0353a 275 {
tushki7 0:60d829a0353a 276 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
tushki7 0:60d829a0353a 277 uint32_t RESERVED; /*!< Reserved, 0x04 */
tushki7 0:60d829a0353a 278 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
tushki7 0:60d829a0353a 279 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
tushki7 0:60d829a0353a 280 }SYSCFG_TypeDef;
tushki7 0:60d829a0353a 281
tushki7 0:60d829a0353a 282 /**
tushki7 0:60d829a0353a 283 * @brief Inter-integrated Circuit Interface
tushki7 0:60d829a0353a 284 */
tushki7 0:60d829a0353a 285
tushki7 0:60d829a0353a 286 typedef struct
tushki7 0:60d829a0353a 287 {
tushki7 0:60d829a0353a 288 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
tushki7 0:60d829a0353a 289 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
tushki7 0:60d829a0353a 290 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
tushki7 0:60d829a0353a 291 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
tushki7 0:60d829a0353a 292 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
tushki7 0:60d829a0353a 293 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
tushki7 0:60d829a0353a 294 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
tushki7 0:60d829a0353a 295 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
tushki7 0:60d829a0353a 296 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
tushki7 0:60d829a0353a 297 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
tushki7 0:60d829a0353a 298 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
tushki7 0:60d829a0353a 299 }I2C_TypeDef;
tushki7 0:60d829a0353a 300
tushki7 0:60d829a0353a 301 /**
tushki7 0:60d829a0353a 302 * @brief Independent WATCHDOG
tushki7 0:60d829a0353a 303 */
tushki7 0:60d829a0353a 304
tushki7 0:60d829a0353a 305 typedef struct
tushki7 0:60d829a0353a 306 {
tushki7 0:60d829a0353a 307 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
tushki7 0:60d829a0353a 308 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
tushki7 0:60d829a0353a 309 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
tushki7 0:60d829a0353a 310 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
tushki7 0:60d829a0353a 311 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
tushki7 0:60d829a0353a 312 }IWDG_TypeDef;
tushki7 0:60d829a0353a 313
tushki7 0:60d829a0353a 314 /**
tushki7 0:60d829a0353a 315 * @brief Power Control
tushki7 0:60d829a0353a 316 */
tushki7 0:60d829a0353a 317
tushki7 0:60d829a0353a 318 typedef struct
tushki7 0:60d829a0353a 319 {
tushki7 0:60d829a0353a 320 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
tushki7 0:60d829a0353a 321 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
tushki7 0:60d829a0353a 322 }PWR_TypeDef;
tushki7 0:60d829a0353a 323
tushki7 0:60d829a0353a 324 /**
tushki7 0:60d829a0353a 325 * @brief Reset and Clock Control
tushki7 0:60d829a0353a 326 */
tushki7 0:60d829a0353a 327 typedef struct
tushki7 0:60d829a0353a 328 {
tushki7 0:60d829a0353a 329 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
tushki7 0:60d829a0353a 330 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
tushki7 0:60d829a0353a 331 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
tushki7 0:60d829a0353a 332 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
tushki7 0:60d829a0353a 333 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
tushki7 0:60d829a0353a 334 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
tushki7 0:60d829a0353a 335 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
tushki7 0:60d829a0353a 336 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
tushki7 0:60d829a0353a 337 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
tushki7 0:60d829a0353a 338 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
tushki7 0:60d829a0353a 339 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
tushki7 0:60d829a0353a 340 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
tushki7 0:60d829a0353a 341 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
tushki7 0:60d829a0353a 342 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
tushki7 0:60d829a0353a 343 }RCC_TypeDef;
tushki7 0:60d829a0353a 344
tushki7 0:60d829a0353a 345 /**
tushki7 0:60d829a0353a 346 * @brief Real-Time Clock
tushki7 0:60d829a0353a 347 */
tushki7 0:60d829a0353a 348
tushki7 0:60d829a0353a 349 typedef struct
tushki7 0:60d829a0353a 350 {
tushki7 0:60d829a0353a 351 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
tushki7 0:60d829a0353a 352 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
tushki7 0:60d829a0353a 353 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
tushki7 0:60d829a0353a 354 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
tushki7 0:60d829a0353a 355 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
tushki7 0:60d829a0353a 356 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
tushki7 0:60d829a0353a 357 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
tushki7 0:60d829a0353a 358 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
tushki7 0:60d829a0353a 359 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
tushki7 0:60d829a0353a 360 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
tushki7 0:60d829a0353a 361 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
tushki7 0:60d829a0353a 362 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
tushki7 0:60d829a0353a 363 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
tushki7 0:60d829a0353a 364 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
tushki7 0:60d829a0353a 365 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
tushki7 0:60d829a0353a 366 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
tushki7 0:60d829a0353a 367 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
tushki7 0:60d829a0353a 368 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
tushki7 0:60d829a0353a 369 }RTC_TypeDef;
tushki7 0:60d829a0353a 370
tushki7 0:60d829a0353a 371 /**
tushki7 0:60d829a0353a 372 * @brief Serial Peripheral Interface
tushki7 0:60d829a0353a 373 */
tushki7 0:60d829a0353a 374
tushki7 0:60d829a0353a 375 typedef struct
tushki7 0:60d829a0353a 376 {
tushki7 0:60d829a0353a 377 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
tushki7 0:60d829a0353a 378 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
tushki7 0:60d829a0353a 379 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
tushki7 0:60d829a0353a 380 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
tushki7 0:60d829a0353a 381 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
tushki7 0:60d829a0353a 382 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
tushki7 0:60d829a0353a 383 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
tushki7 0:60d829a0353a 384 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
tushki7 0:60d829a0353a 385 __IO uint32_t RESERVED1;/*!< Reserved, Address offset: 0x20 */
tushki7 0:60d829a0353a 386 }SPI_TypeDef;
tushki7 0:60d829a0353a 387
tushki7 0:60d829a0353a 388 /**
tushki7 0:60d829a0353a 389 * @brief TIM
tushki7 0:60d829a0353a 390 */
tushki7 0:60d829a0353a 391 typedef struct
tushki7 0:60d829a0353a 392 {
tushki7 0:60d829a0353a 393 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
tushki7 0:60d829a0353a 394 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
tushki7 0:60d829a0353a 395 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
tushki7 0:60d829a0353a 396 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
tushki7 0:60d829a0353a 397 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
tushki7 0:60d829a0353a 398 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
tushki7 0:60d829a0353a 399 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
tushki7 0:60d829a0353a 400 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
tushki7 0:60d829a0353a 401 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
tushki7 0:60d829a0353a 402 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
tushki7 0:60d829a0353a 403 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
tushki7 0:60d829a0353a 404 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
tushki7 0:60d829a0353a 405 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
tushki7 0:60d829a0353a 406 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
tushki7 0:60d829a0353a 407 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
tushki7 0:60d829a0353a 408 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
tushki7 0:60d829a0353a 409 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
tushki7 0:60d829a0353a 410 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
tushki7 0:60d829a0353a 411 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
tushki7 0:60d829a0353a 412 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
tushki7 0:60d829a0353a 413 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
tushki7 0:60d829a0353a 414 }TIM_TypeDef;
tushki7 0:60d829a0353a 415
tushki7 0:60d829a0353a 416
tushki7 0:60d829a0353a 417 /**
tushki7 0:60d829a0353a 418 * @brief Universal Synchronous Asynchronous Receiver Transmitter
tushki7 0:60d829a0353a 419 */
tushki7 0:60d829a0353a 420
tushki7 0:60d829a0353a 421 typedef struct
tushki7 0:60d829a0353a 422 {
tushki7 0:60d829a0353a 423 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
tushki7 0:60d829a0353a 424 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
tushki7 0:60d829a0353a 425 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
tushki7 0:60d829a0353a 426 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
tushki7 0:60d829a0353a 427 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
tushki7 0:60d829a0353a 428 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
tushki7 0:60d829a0353a 429 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
tushki7 0:60d829a0353a 430 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
tushki7 0:60d829a0353a 431 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
tushki7 0:60d829a0353a 432 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
tushki7 0:60d829a0353a 433 uint16_t RESERVED1; /*!< Reserved, 0x26 */
tushki7 0:60d829a0353a 434 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
tushki7 0:60d829a0353a 435 uint16_t RESERVED2; /*!< Reserved, 0x2A */
tushki7 0:60d829a0353a 436 }USART_TypeDef;
tushki7 0:60d829a0353a 437
tushki7 0:60d829a0353a 438 /**
tushki7 0:60d829a0353a 439 * @brief Universal Serial Bus Full Speed Device
tushki7 0:60d829a0353a 440 */
tushki7 0:60d829a0353a 441
tushki7 0:60d829a0353a 442 typedef struct
tushki7 0:60d829a0353a 443 {
tushki7 0:60d829a0353a 444 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
tushki7 0:60d829a0353a 445 __IO uint16_t RESERVED0; /*!< Reserved */
tushki7 0:60d829a0353a 446 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
tushki7 0:60d829a0353a 447 __IO uint16_t RESERVED1; /*!< Reserved */
tushki7 0:60d829a0353a 448 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
tushki7 0:60d829a0353a 449 __IO uint16_t RESERVED2; /*!< Reserved */
tushki7 0:60d829a0353a 450 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
tushki7 0:60d829a0353a 451 __IO uint16_t RESERVED3; /*!< Reserved */
tushki7 0:60d829a0353a 452 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
tushki7 0:60d829a0353a 453 __IO uint16_t RESERVED4; /*!< Reserved */
tushki7 0:60d829a0353a 454 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
tushki7 0:60d829a0353a 455 __IO uint16_t RESERVED5; /*!< Reserved */
tushki7 0:60d829a0353a 456 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
tushki7 0:60d829a0353a 457 __IO uint16_t RESERVED6; /*!< Reserved */
tushki7 0:60d829a0353a 458 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
tushki7 0:60d829a0353a 459 __IO uint16_t RESERVED7[17]; /*!< Reserved */
tushki7 0:60d829a0353a 460 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
tushki7 0:60d829a0353a 461 __IO uint16_t RESERVED8; /*!< Reserved */
tushki7 0:60d829a0353a 462 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
tushki7 0:60d829a0353a 463 __IO uint16_t RESERVED9; /*!< Reserved */
tushki7 0:60d829a0353a 464 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
tushki7 0:60d829a0353a 465 __IO uint16_t RESERVEDA; /*!< Reserved */
tushki7 0:60d829a0353a 466 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
tushki7 0:60d829a0353a 467 __IO uint16_t RESERVEDB; /*!< Reserved */
tushki7 0:60d829a0353a 468 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
tushki7 0:60d829a0353a 469 __IO uint16_t RESERVEDC; /*!< Reserved */
tushki7 0:60d829a0353a 470 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
tushki7 0:60d829a0353a 471 __IO uint16_t RESERVEDD; /*!< Reserved */
tushki7 0:60d829a0353a 472 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
tushki7 0:60d829a0353a 473 __IO uint16_t RESERVEDE; /*!< Reserved */
tushki7 0:60d829a0353a 474 }USB_TypeDef;
tushki7 0:60d829a0353a 475
tushki7 0:60d829a0353a 476 /**
tushki7 0:60d829a0353a 477 * @brief Window WATCHDOG
tushki7 0:60d829a0353a 478 */
tushki7 0:60d829a0353a 479 typedef struct
tushki7 0:60d829a0353a 480 {
tushki7 0:60d829a0353a 481 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
tushki7 0:60d829a0353a 482 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
tushki7 0:60d829a0353a 483 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
tushki7 0:60d829a0353a 484 }WWDG_TypeDef;
tushki7 0:60d829a0353a 485
tushki7 0:60d829a0353a 486 /**
tushki7 0:60d829a0353a 487 * @}
tushki7 0:60d829a0353a 488 */
tushki7 0:60d829a0353a 489
tushki7 0:60d829a0353a 490 /** @addtogroup Peripheral_memory_map
tushki7 0:60d829a0353a 491 * @{
tushki7 0:60d829a0353a 492 */
tushki7 0:60d829a0353a 493
tushki7 0:60d829a0353a 494 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
tushki7 0:60d829a0353a 495 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
tushki7 0:60d829a0353a 496 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
tushki7 0:60d829a0353a 497
tushki7 0:60d829a0353a 498 /*!< Peripheral memory map */
tushki7 0:60d829a0353a 499 #define APBPERIPH_BASE PERIPH_BASE
tushki7 0:60d829a0353a 500 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
tushki7 0:60d829a0353a 501 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
tushki7 0:60d829a0353a 502
tushki7 0:60d829a0353a 503 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
tushki7 0:60d829a0353a 504 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
tushki7 0:60d829a0353a 505 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
tushki7 0:60d829a0353a 506 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
tushki7 0:60d829a0353a 507 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
tushki7 0:60d829a0353a 508 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
tushki7 0:60d829a0353a 509 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
tushki7 0:60d829a0353a 510 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
tushki7 0:60d829a0353a 511 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
tushki7 0:60d829a0353a 512 #define USART3_BASE (APBPERIPH_BASE + 0x00004800)
tushki7 0:60d829a0353a 513 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
tushki7 0:60d829a0353a 514 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
tushki7 0:60d829a0353a 515 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
tushki7 0:60d829a0353a 516 #define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
tushki7 0:60d829a0353a 517 #define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
tushki7 0:60d829a0353a 518 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
tushki7 0:60d829a0353a 519 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
tushki7 0:60d829a0353a 520 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
tushki7 0:60d829a0353a 521 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
tushki7 0:60d829a0353a 522 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
tushki7 0:60d829a0353a 523 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
tushki7 0:60d829a0353a 524 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
tushki7 0:60d829a0353a 525 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
tushki7 0:60d829a0353a 526 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
tushki7 0:60d829a0353a 527 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
tushki7 0:60d829a0353a 528 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
tushki7 0:60d829a0353a 529 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
tushki7 0:60d829a0353a 530
tushki7 0:60d829a0353a 531 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
tushki7 0:60d829a0353a 532 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
tushki7 0:60d829a0353a 533 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
tushki7 0:60d829a0353a 534 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
tushki7 0:60d829a0353a 535 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
tushki7 0:60d829a0353a 536 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
tushki7 0:60d829a0353a 537
tushki7 0:60d829a0353a 538 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
tushki7 0:60d829a0353a 539 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
tushki7 0:60d829a0353a 540 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
tushki7 0:60d829a0353a 541 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
tushki7 0:60d829a0353a 542
tushki7 0:60d829a0353a 543 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
tushki7 0:60d829a0353a 544 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
tushki7 0:60d829a0353a 545 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
tushki7 0:60d829a0353a 546 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
tushki7 0:60d829a0353a 547 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
tushki7 0:60d829a0353a 548
tushki7 0:60d829a0353a 549 /**
tushki7 0:60d829a0353a 550 * @}
tushki7 0:60d829a0353a 551 */
tushki7 0:60d829a0353a 552
tushki7 0:60d829a0353a 553 /** @addtogroup Peripheral_declaration
tushki7 0:60d829a0353a 554 * @{
tushki7 0:60d829a0353a 555 */
tushki7 0:60d829a0353a 556
tushki7 0:60d829a0353a 557 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
tushki7 0:60d829a0353a 558 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
tushki7 0:60d829a0353a 559 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
tushki7 0:60d829a0353a 560 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
tushki7 0:60d829a0353a 561 #define RTC ((RTC_TypeDef *) RTC_BASE)
tushki7 0:60d829a0353a 562 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
tushki7 0:60d829a0353a 563 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
tushki7 0:60d829a0353a 564 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
tushki7 0:60d829a0353a 565 #define USART2 ((USART_TypeDef *) USART2_BASE)
tushki7 0:60d829a0353a 566 #define USART3 ((USART_TypeDef *) USART3_BASE)
tushki7 0:60d829a0353a 567 #define USART4 ((USART_TypeDef *) USART4_BASE)
tushki7 0:60d829a0353a 568 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
tushki7 0:60d829a0353a 569 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
tushki7 0:60d829a0353a 570 #define PWR ((PWR_TypeDef *) PWR_BASE)
tushki7 0:60d829a0353a 571 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
tushki7 0:60d829a0353a 572 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
tushki7 0:60d829a0353a 573 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
tushki7 0:60d829a0353a 574 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
tushki7 0:60d829a0353a 575 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
tushki7 0:60d829a0353a 576 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
tushki7 0:60d829a0353a 577 #define USART1 ((USART_TypeDef *) USART1_BASE)
tushki7 0:60d829a0353a 578 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
tushki7 0:60d829a0353a 579 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
tushki7 0:60d829a0353a 580 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
tushki7 0:60d829a0353a 581 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
tushki7 0:60d829a0353a 582 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
tushki7 0:60d829a0353a 583 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
tushki7 0:60d829a0353a 584 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
tushki7 0:60d829a0353a 585 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
tushki7 0:60d829a0353a 586 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
tushki7 0:60d829a0353a 587 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
tushki7 0:60d829a0353a 588 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
tushki7 0:60d829a0353a 589 #define OB ((OB_TypeDef *) OB_BASE)
tushki7 0:60d829a0353a 590 #define RCC ((RCC_TypeDef *) RCC_BASE)
tushki7 0:60d829a0353a 591 #define CRC ((CRC_TypeDef *) CRC_BASE)
tushki7 0:60d829a0353a 592 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
tushki7 0:60d829a0353a 593 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
tushki7 0:60d829a0353a 594 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
tushki7 0:60d829a0353a 595 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
tushki7 0:60d829a0353a 596 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
tushki7 0:60d829a0353a 597 #define USB ((USB_TypeDef *) USB_BASE)
tushki7 0:60d829a0353a 598 /**
tushki7 0:60d829a0353a 599 * @}
tushki7 0:60d829a0353a 600 */
tushki7 0:60d829a0353a 601
tushki7 0:60d829a0353a 602 /** @addtogroup Exported_constants
tushki7 0:60d829a0353a 603 * @{
tushki7 0:60d829a0353a 604 */
tushki7 0:60d829a0353a 605
tushki7 0:60d829a0353a 606 /** @addtogroup Peripheral_Registers_Bits_Definition
tushki7 0:60d829a0353a 607 * @{
tushki7 0:60d829a0353a 608 */
tushki7 0:60d829a0353a 609
tushki7 0:60d829a0353a 610 /******************************************************************************/
tushki7 0:60d829a0353a 611 /* Peripheral Registers Bits Definition */
tushki7 0:60d829a0353a 612 /******************************************************************************/
tushki7 0:60d829a0353a 613 /******************************************************************************/
tushki7 0:60d829a0353a 614 /* */
tushki7 0:60d829a0353a 615 /* Analog to Digital Converter (ADC) */
tushki7 0:60d829a0353a 616 /* */
tushki7 0:60d829a0353a 617 /******************************************************************************/
tushki7 0:60d829a0353a 618 /******************** Bits definition for ADC_ISR register ******************/
tushki7 0:60d829a0353a 619 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
tushki7 0:60d829a0353a 620 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
tushki7 0:60d829a0353a 621 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
tushki7 0:60d829a0353a 622 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
tushki7 0:60d829a0353a 623 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
tushki7 0:60d829a0353a 624 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
tushki7 0:60d829a0353a 625
tushki7 0:60d829a0353a 626 /* Old EOSEQ bit definition, maintained for legacy purpose */
tushki7 0:60d829a0353a 627 #define ADC_ISR_EOS ADC_ISR_EOSEQ
tushki7 0:60d829a0353a 628
tushki7 0:60d829a0353a 629 /******************** Bits definition for ADC_IER register ******************/
tushki7 0:60d829a0353a 630 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
tushki7 0:60d829a0353a 631 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
tushki7 0:60d829a0353a 632 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
tushki7 0:60d829a0353a 633 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
tushki7 0:60d829a0353a 634 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
tushki7 0:60d829a0353a 635 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
tushki7 0:60d829a0353a 636
tushki7 0:60d829a0353a 637 /* Old EOSEQIE bit definition, maintained for legacy purpose */
tushki7 0:60d829a0353a 638 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
tushki7 0:60d829a0353a 639
tushki7 0:60d829a0353a 640 /******************** Bits definition for ADC_CR register *******************/
tushki7 0:60d829a0353a 641 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
tushki7 0:60d829a0353a 642 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
tushki7 0:60d829a0353a 643 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
tushki7 0:60d829a0353a 644 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
tushki7 0:60d829a0353a 645 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
tushki7 0:60d829a0353a 646
tushki7 0:60d829a0353a 647 /******************* Bits definition for ADC_CFGR1 register *****************/
tushki7 0:60d829a0353a 648 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
tushki7 0:60d829a0353a 649 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
tushki7 0:60d829a0353a 650 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
tushki7 0:60d829a0353a 651 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
tushki7 0:60d829a0353a 652 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
tushki7 0:60d829a0353a 653 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
tushki7 0:60d829a0353a 654 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
tushki7 0:60d829a0353a 655 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
tushki7 0:60d829a0353a 656 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
tushki7 0:60d829a0353a 657 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
tushki7 0:60d829a0353a 658 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
tushki7 0:60d829a0353a 659 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
tushki7 0:60d829a0353a 660 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
tushki7 0:60d829a0353a 661 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
tushki7 0:60d829a0353a 662 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
tushki7 0:60d829a0353a 663 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
tushki7 0:60d829a0353a 664 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
tushki7 0:60d829a0353a 665 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
tushki7 0:60d829a0353a 666 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
tushki7 0:60d829a0353a 667 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
tushki7 0:60d829a0353a 668 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
tushki7 0:60d829a0353a 669 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
tushki7 0:60d829a0353a 670 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
tushki7 0:60d829a0353a 671 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
tushki7 0:60d829a0353a 672 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
tushki7 0:60d829a0353a 673 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
tushki7 0:60d829a0353a 674 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
tushki7 0:60d829a0353a 675
tushki7 0:60d829a0353a 676 /* Old WAIT bit definition, maintained for legacy purpose */
tushki7 0:60d829a0353a 677 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
tushki7 0:60d829a0353a 678
tushki7 0:60d829a0353a 679 /******************* Bits definition for ADC_CFGR2 register *****************/
tushki7 0:60d829a0353a 680 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
tushki7 0:60d829a0353a 681 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
tushki7 0:60d829a0353a 682 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
tushki7 0:60d829a0353a 683
tushki7 0:60d829a0353a 684 /* Old bit definition, maintained for legacy purpose */
tushki7 0:60d829a0353a 685 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
tushki7 0:60d829a0353a 686 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
tushki7 0:60d829a0353a 687
tushki7 0:60d829a0353a 688 /****************** Bit definition for ADC_SMPR register ********************/
tushki7 0:60d829a0353a 689 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
tushki7 0:60d829a0353a 690 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
tushki7 0:60d829a0353a 691 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
tushki7 0:60d829a0353a 692 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
tushki7 0:60d829a0353a 693
tushki7 0:60d829a0353a 694 /* Old bit definition, maintained for legacy purpose */
tushki7 0:60d829a0353a 695 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
tushki7 0:60d829a0353a 696 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
tushki7 0:60d829a0353a 697 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
tushki7 0:60d829a0353a 698 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
tushki7 0:60d829a0353a 699
tushki7 0:60d829a0353a 700 /******************* Bit definition for ADC_TR register ********************/
tushki7 0:60d829a0353a 701 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
tushki7 0:60d829a0353a 702 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
tushki7 0:60d829a0353a 703
tushki7 0:60d829a0353a 704 /* Old bit definition, maintained for legacy purpose */
tushki7 0:60d829a0353a 705 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
tushki7 0:60d829a0353a 706 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
tushki7 0:60d829a0353a 707
tushki7 0:60d829a0353a 708 /****************** Bit definition for ADC_CHSELR register ******************/
tushki7 0:60d829a0353a 709 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
tushki7 0:60d829a0353a 710 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
tushki7 0:60d829a0353a 711 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
tushki7 0:60d829a0353a 712 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
tushki7 0:60d829a0353a 713 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
tushki7 0:60d829a0353a 714 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
tushki7 0:60d829a0353a 715 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
tushki7 0:60d829a0353a 716 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
tushki7 0:60d829a0353a 717 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
tushki7 0:60d829a0353a 718 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
tushki7 0:60d829a0353a 719 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
tushki7 0:60d829a0353a 720 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
tushki7 0:60d829a0353a 721 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
tushki7 0:60d829a0353a 722 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
tushki7 0:60d829a0353a 723 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
tushki7 0:60d829a0353a 724 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
tushki7 0:60d829a0353a 725 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
tushki7 0:60d829a0353a 726 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
tushki7 0:60d829a0353a 727 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
tushki7 0:60d829a0353a 728
tushki7 0:60d829a0353a 729 /******************** Bit definition for ADC_DR register ********************/
tushki7 0:60d829a0353a 730 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
tushki7 0:60d829a0353a 731
tushki7 0:60d829a0353a 732 /******************* Bit definition for ADC_CCR register ********************/
tushki7 0:60d829a0353a 733 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
tushki7 0:60d829a0353a 734 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
tushki7 0:60d829a0353a 735 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
tushki7 0:60d829a0353a 736
tushki7 0:60d829a0353a 737 /******************************************************************************/
tushki7 0:60d829a0353a 738 /* */
tushki7 0:60d829a0353a 739 /* CRC calculation unit (CRC) */
tushki7 0:60d829a0353a 740 /* */
tushki7 0:60d829a0353a 741 /******************************************************************************/
tushki7 0:60d829a0353a 742 /******************* Bit definition for CRC_DR register *********************/
tushki7 0:60d829a0353a 743 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
tushki7 0:60d829a0353a 744
tushki7 0:60d829a0353a 745 /******************* Bit definition for CRC_IDR register ********************/
tushki7 0:60d829a0353a 746 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
tushki7 0:60d829a0353a 747
tushki7 0:60d829a0353a 748 /******************** Bit definition for CRC_CR register ********************/
tushki7 0:60d829a0353a 749 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
tushki7 0:60d829a0353a 750 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
tushki7 0:60d829a0353a 751 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
tushki7 0:60d829a0353a 752 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
tushki7 0:60d829a0353a 753 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
tushki7 0:60d829a0353a 754
tushki7 0:60d829a0353a 755 /******************* Bit definition for CRC_INIT register *******************/
tushki7 0:60d829a0353a 756 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
tushki7 0:60d829a0353a 757
tushki7 0:60d829a0353a 758 /******************************************************************************/
tushki7 0:60d829a0353a 759 /* */
tushki7 0:60d829a0353a 760 /* Debug MCU (DBGMCU) */
tushki7 0:60d829a0353a 761 /* */
tushki7 0:60d829a0353a 762 /******************************************************************************/
tushki7 0:60d829a0353a 763
tushki7 0:60d829a0353a 764 /**************** Bit definition for DBGMCU_IDCODE register *****************/
tushki7 0:60d829a0353a 765 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
tushki7 0:60d829a0353a 766
tushki7 0:60d829a0353a 767 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
tushki7 0:60d829a0353a 768 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
tushki7 0:60d829a0353a 769 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
tushki7 0:60d829a0353a 770 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
tushki7 0:60d829a0353a 771 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
tushki7 0:60d829a0353a 772 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
tushki7 0:60d829a0353a 773 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
tushki7 0:60d829a0353a 774 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
tushki7 0:60d829a0353a 775 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
tushki7 0:60d829a0353a 776 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
tushki7 0:60d829a0353a 777 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
tushki7 0:60d829a0353a 778 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
tushki7 0:60d829a0353a 779 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
tushki7 0:60d829a0353a 780 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
tushki7 0:60d829a0353a 781 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
tushki7 0:60d829a0353a 782 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
tushki7 0:60d829a0353a 783 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
tushki7 0:60d829a0353a 784
tushki7 0:60d829a0353a 785 /****************** Bit definition for DBGMCU_CR register *******************/
tushki7 0:60d829a0353a 786 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
tushki7 0:60d829a0353a 787 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
tushki7 0:60d829a0353a 788
tushki7 0:60d829a0353a 789 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
tushki7 0:60d829a0353a 790 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
tushki7 0:60d829a0353a 791 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
tushki7 0:60d829a0353a 792 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
tushki7 0:60d829a0353a 793 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
tushki7 0:60d829a0353a 794 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
tushki7 0:60d829a0353a 795 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
tushki7 0:60d829a0353a 796 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
tushki7 0:60d829a0353a 797 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
tushki7 0:60d829a0353a 798
tushki7 0:60d829a0353a 799 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
tushki7 0:60d829a0353a 800 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
tushki7 0:60d829a0353a 801 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
tushki7 0:60d829a0353a 802 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
tushki7 0:60d829a0353a 803 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
tushki7 0:60d829a0353a 804
tushki7 0:60d829a0353a 805 /******************************************************************************/
tushki7 0:60d829a0353a 806 /* */
tushki7 0:60d829a0353a 807 /* DMA Controller (DMA) */
tushki7 0:60d829a0353a 808 /* */
tushki7 0:60d829a0353a 809 /******************************************************************************/
tushki7 0:60d829a0353a 810 /******************* Bit definition for DMA_ISR register ********************/
tushki7 0:60d829a0353a 811 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
tushki7 0:60d829a0353a 812 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
tushki7 0:60d829a0353a 813 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
tushki7 0:60d829a0353a 814 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
tushki7 0:60d829a0353a 815 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
tushki7 0:60d829a0353a 816 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
tushki7 0:60d829a0353a 817 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
tushki7 0:60d829a0353a 818 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
tushki7 0:60d829a0353a 819 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
tushki7 0:60d829a0353a 820 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
tushki7 0:60d829a0353a 821 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
tushki7 0:60d829a0353a 822 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
tushki7 0:60d829a0353a 823 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
tushki7 0:60d829a0353a 824 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
tushki7 0:60d829a0353a 825 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
tushki7 0:60d829a0353a 826 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
tushki7 0:60d829a0353a 827 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
tushki7 0:60d829a0353a 828 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
tushki7 0:60d829a0353a 829 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
tushki7 0:60d829a0353a 830 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
tushki7 0:60d829a0353a 831
tushki7 0:60d829a0353a 832 /******************* Bit definition for DMA_IFCR register *******************/
tushki7 0:60d829a0353a 833 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
tushki7 0:60d829a0353a 834 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
tushki7 0:60d829a0353a 835 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
tushki7 0:60d829a0353a 836 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
tushki7 0:60d829a0353a 837 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
tushki7 0:60d829a0353a 838 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
tushki7 0:60d829a0353a 839 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
tushki7 0:60d829a0353a 840 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
tushki7 0:60d829a0353a 841 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
tushki7 0:60d829a0353a 842 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
tushki7 0:60d829a0353a 843 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
tushki7 0:60d829a0353a 844 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
tushki7 0:60d829a0353a 845 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
tushki7 0:60d829a0353a 846 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
tushki7 0:60d829a0353a 847 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
tushki7 0:60d829a0353a 848 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
tushki7 0:60d829a0353a 849 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
tushki7 0:60d829a0353a 850 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
tushki7 0:60d829a0353a 851 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
tushki7 0:60d829a0353a 852 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
tushki7 0:60d829a0353a 853
tushki7 0:60d829a0353a 854 /******************* Bit definition for DMA_CCR register ********************/
tushki7 0:60d829a0353a 855 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
tushki7 0:60d829a0353a 856 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
tushki7 0:60d829a0353a 857 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
tushki7 0:60d829a0353a 858 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
tushki7 0:60d829a0353a 859 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
tushki7 0:60d829a0353a 860 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
tushki7 0:60d829a0353a 861 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
tushki7 0:60d829a0353a 862 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
tushki7 0:60d829a0353a 863
tushki7 0:60d829a0353a 864 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
tushki7 0:60d829a0353a 865 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
tushki7 0:60d829a0353a 866 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
tushki7 0:60d829a0353a 867
tushki7 0:60d829a0353a 868 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
tushki7 0:60d829a0353a 869 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
tushki7 0:60d829a0353a 870 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
tushki7 0:60d829a0353a 871
tushki7 0:60d829a0353a 872 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
tushki7 0:60d829a0353a 873 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
tushki7 0:60d829a0353a 874 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
tushki7 0:60d829a0353a 875
tushki7 0:60d829a0353a 876 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
tushki7 0:60d829a0353a 877
tushki7 0:60d829a0353a 878 /****************** Bit definition for DMA_CNDTR register *******************/
tushki7 0:60d829a0353a 879 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
tushki7 0:60d829a0353a 880
tushki7 0:60d829a0353a 881 /****************** Bit definition for DMA_CPAR register ********************/
tushki7 0:60d829a0353a 882 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
tushki7 0:60d829a0353a 883
tushki7 0:60d829a0353a 884 /****************** Bit definition for DMA_CMAR register ********************/
tushki7 0:60d829a0353a 885 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
tushki7 0:60d829a0353a 886
tushki7 0:60d829a0353a 887 /******************************************************************************/
tushki7 0:60d829a0353a 888 /* */
tushki7 0:60d829a0353a 889 /* External Interrupt/Event Controller (EXTI) */
tushki7 0:60d829a0353a 890 /* */
tushki7 0:60d829a0353a 891 /******************************************************************************/
tushki7 0:60d829a0353a 892 /******************* Bit definition for EXTI_IMR register *******************/
tushki7 0:60d829a0353a 893 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
tushki7 0:60d829a0353a 894 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
tushki7 0:60d829a0353a 895 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
tushki7 0:60d829a0353a 896 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
tushki7 0:60d829a0353a 897 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
tushki7 0:60d829a0353a 898 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
tushki7 0:60d829a0353a 899 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
tushki7 0:60d829a0353a 900 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
tushki7 0:60d829a0353a 901 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
tushki7 0:60d829a0353a 902 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
tushki7 0:60d829a0353a 903 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
tushki7 0:60d829a0353a 904 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
tushki7 0:60d829a0353a 905 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
tushki7 0:60d829a0353a 906 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
tushki7 0:60d829a0353a 907 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
tushki7 0:60d829a0353a 908 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
tushki7 0:60d829a0353a 909 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
tushki7 0:60d829a0353a 910 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
tushki7 0:60d829a0353a 911 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
tushki7 0:60d829a0353a 912 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
tushki7 0:60d829a0353a 913 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
tushki7 0:60d829a0353a 914
tushki7 0:60d829a0353a 915 /****************** Bit definition for EXTI_EMR register ********************/
tushki7 0:60d829a0353a 916 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
tushki7 0:60d829a0353a 917 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
tushki7 0:60d829a0353a 918 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
tushki7 0:60d829a0353a 919 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
tushki7 0:60d829a0353a 920 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
tushki7 0:60d829a0353a 921 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
tushki7 0:60d829a0353a 922 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
tushki7 0:60d829a0353a 923 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
tushki7 0:60d829a0353a 924 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
tushki7 0:60d829a0353a 925 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
tushki7 0:60d829a0353a 926 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
tushki7 0:60d829a0353a 927 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
tushki7 0:60d829a0353a 928 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
tushki7 0:60d829a0353a 929 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
tushki7 0:60d829a0353a 930 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
tushki7 0:60d829a0353a 931 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
tushki7 0:60d829a0353a 932 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
tushki7 0:60d829a0353a 933 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
tushki7 0:60d829a0353a 934 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
tushki7 0:60d829a0353a 935 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
tushki7 0:60d829a0353a 936 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
tushki7 0:60d829a0353a 937
tushki7 0:60d829a0353a 938 /******************* Bit definition for EXTI_RTSR register ******************/
tushki7 0:60d829a0353a 939 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
tushki7 0:60d829a0353a 940 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
tushki7 0:60d829a0353a 941 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
tushki7 0:60d829a0353a 942 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
tushki7 0:60d829a0353a 943 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
tushki7 0:60d829a0353a 944 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
tushki7 0:60d829a0353a 945 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
tushki7 0:60d829a0353a 946 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
tushki7 0:60d829a0353a 947 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
tushki7 0:60d829a0353a 948 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
tushki7 0:60d829a0353a 949 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
tushki7 0:60d829a0353a 950 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
tushki7 0:60d829a0353a 951 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
tushki7 0:60d829a0353a 952 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
tushki7 0:60d829a0353a 953 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
tushki7 0:60d829a0353a 954 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
tushki7 0:60d829a0353a 955 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
tushki7 0:60d829a0353a 956 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
tushki7 0:60d829a0353a 957 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
tushki7 0:60d829a0353a 958 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
tushki7 0:60d829a0353a 959 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
tushki7 0:60d829a0353a 960 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
tushki7 0:60d829a0353a 961
tushki7 0:60d829a0353a 962 /******************* Bit definition for EXTI_FTSR register *******************/
tushki7 0:60d829a0353a 963 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
tushki7 0:60d829a0353a 964 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
tushki7 0:60d829a0353a 965 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
tushki7 0:60d829a0353a 966 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
tushki7 0:60d829a0353a 967 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
tushki7 0:60d829a0353a 968 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
tushki7 0:60d829a0353a 969 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
tushki7 0:60d829a0353a 970 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
tushki7 0:60d829a0353a 971 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
tushki7 0:60d829a0353a 972 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
tushki7 0:60d829a0353a 973 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
tushki7 0:60d829a0353a 974 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
tushki7 0:60d829a0353a 975 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
tushki7 0:60d829a0353a 976 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
tushki7 0:60d829a0353a 977 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
tushki7 0:60d829a0353a 978 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
tushki7 0:60d829a0353a 979 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
tushki7 0:60d829a0353a 980 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
tushki7 0:60d829a0353a 981 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
tushki7 0:60d829a0353a 982 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
tushki7 0:60d829a0353a 983 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
tushki7 0:60d829a0353a 984 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
tushki7 0:60d829a0353a 985
tushki7 0:60d829a0353a 986 /******************* Bit definition for EXTI_SWIER register *******************/
tushki7 0:60d829a0353a 987 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
tushki7 0:60d829a0353a 988 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
tushki7 0:60d829a0353a 989 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
tushki7 0:60d829a0353a 990 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
tushki7 0:60d829a0353a 991 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
tushki7 0:60d829a0353a 992 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
tushki7 0:60d829a0353a 993 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
tushki7 0:60d829a0353a 994 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
tushki7 0:60d829a0353a 995 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
tushki7 0:60d829a0353a 996 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
tushki7 0:60d829a0353a 997 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
tushki7 0:60d829a0353a 998 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
tushki7 0:60d829a0353a 999 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
tushki7 0:60d829a0353a 1000 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
tushki7 0:60d829a0353a 1001 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
tushki7 0:60d829a0353a 1002 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
tushki7 0:60d829a0353a 1003 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
tushki7 0:60d829a0353a 1004 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
tushki7 0:60d829a0353a 1005 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
tushki7 0:60d829a0353a 1006 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
tushki7 0:60d829a0353a 1007 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
tushki7 0:60d829a0353a 1008 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
tushki7 0:60d829a0353a 1009
tushki7 0:60d829a0353a 1010 /****************** Bit definition for EXTI_PR register *********************/
tushki7 0:60d829a0353a 1011 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
tushki7 0:60d829a0353a 1012 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
tushki7 0:60d829a0353a 1013 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
tushki7 0:60d829a0353a 1014 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
tushki7 0:60d829a0353a 1015 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
tushki7 0:60d829a0353a 1016 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
tushki7 0:60d829a0353a 1017 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
tushki7 0:60d829a0353a 1018 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
tushki7 0:60d829a0353a 1019 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
tushki7 0:60d829a0353a 1020 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
tushki7 0:60d829a0353a 1021 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
tushki7 0:60d829a0353a 1022 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
tushki7 0:60d829a0353a 1023 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
tushki7 0:60d829a0353a 1024 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
tushki7 0:60d829a0353a 1025 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
tushki7 0:60d829a0353a 1026 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
tushki7 0:60d829a0353a 1027 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
tushki7 0:60d829a0353a 1028 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
tushki7 0:60d829a0353a 1029 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
tushki7 0:60d829a0353a 1030 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
tushki7 0:60d829a0353a 1031 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
tushki7 0:60d829a0353a 1032 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
tushki7 0:60d829a0353a 1033
tushki7 0:60d829a0353a 1034 /******************************************************************************/
tushki7 0:60d829a0353a 1035 /* */
tushki7 0:60d829a0353a 1036 /* FLASH and Option Bytes Registers */
tushki7 0:60d829a0353a 1037 /* */
tushki7 0:60d829a0353a 1038 /******************************************************************************/
tushki7 0:60d829a0353a 1039
tushki7 0:60d829a0353a 1040 /******************* Bit definition for FLASH_ACR register ******************/
tushki7 0:60d829a0353a 1041 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
tushki7 0:60d829a0353a 1042
tushki7 0:60d829a0353a 1043 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
tushki7 0:60d829a0353a 1044 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
tushki7 0:60d829a0353a 1045
tushki7 0:60d829a0353a 1046 /****************** Bit definition for FLASH_KEYR register ******************/
tushki7 0:60d829a0353a 1047 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
tushki7 0:60d829a0353a 1048
tushki7 0:60d829a0353a 1049 /***************** Bit definition for FLASH_OPTKEYR register ****************/
tushki7 0:60d829a0353a 1050 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
tushki7 0:60d829a0353a 1051
tushki7 0:60d829a0353a 1052 /****************** FLASH Keys **********************************************/
tushki7 0:60d829a0353a 1053 #define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
tushki7 0:60d829a0353a 1054 #define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
tushki7 0:60d829a0353a 1055 to unlock the write access to the FPEC. */
tushki7 0:60d829a0353a 1056
tushki7 0:60d829a0353a 1057 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
tushki7 0:60d829a0353a 1058 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
tushki7 0:60d829a0353a 1059 unlock the write access to the option byte block */
tushki7 0:60d829a0353a 1060
tushki7 0:60d829a0353a 1061 /****************** Bit definition for FLASH_SR register *******************/
tushki7 0:60d829a0353a 1062 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
tushki7 0:60d829a0353a 1063 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
tushki7 0:60d829a0353a 1064 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
tushki7 0:60d829a0353a 1065 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
tushki7 0:60d829a0353a 1066 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
tushki7 0:60d829a0353a 1067
tushki7 0:60d829a0353a 1068 /******************* Bit definition for FLASH_CR register *******************/
tushki7 0:60d829a0353a 1069 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
tushki7 0:60d829a0353a 1070 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
tushki7 0:60d829a0353a 1071 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
tushki7 0:60d829a0353a 1072 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
tushki7 0:60d829a0353a 1073 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
tushki7 0:60d829a0353a 1074 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
tushki7 0:60d829a0353a 1075 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
tushki7 0:60d829a0353a 1076 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
tushki7 0:60d829a0353a 1077 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
tushki7 0:60d829a0353a 1078 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
tushki7 0:60d829a0353a 1079 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
tushki7 0:60d829a0353a 1080
tushki7 0:60d829a0353a 1081 /******************* Bit definition for FLASH_AR register *******************/
tushki7 0:60d829a0353a 1082 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
tushki7 0:60d829a0353a 1083
tushki7 0:60d829a0353a 1084 /****************** Bit definition for FLASH_OBR register *******************/
tushki7 0:60d829a0353a 1085 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
tushki7 0:60d829a0353a 1086 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
tushki7 0:60d829a0353a 1087 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
tushki7 0:60d829a0353a 1088
tushki7 0:60d829a0353a 1089 #define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
tushki7 0:60d829a0353a 1090 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
tushki7 0:60d829a0353a 1091 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
tushki7 0:60d829a0353a 1092 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
tushki7 0:60d829a0353a 1093 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
tushki7 0:60d829a0353a 1094 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
tushki7 0:60d829a0353a 1095
tushki7 0:60d829a0353a 1096 /* Old BOOT1 bit definition, maintained for legacy purpose */
tushki7 0:60d829a0353a 1097 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
tushki7 0:60d829a0353a 1098
tushki7 0:60d829a0353a 1099 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
tushki7 0:60d829a0353a 1100 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
tushki7 0:60d829a0353a 1101
tushki7 0:60d829a0353a 1102 /****************** Bit definition for FLASH_WRPR register ******************/
tushki7 0:60d829a0353a 1103 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
tushki7 0:60d829a0353a 1104
tushki7 0:60d829a0353a 1105 /*----------------------------------------------------------------------------*/
tushki7 0:60d829a0353a 1106
tushki7 0:60d829a0353a 1107 /****************** Bit definition for OB_RDP register **********************/
tushki7 0:60d829a0353a 1108 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
tushki7 0:60d829a0353a 1109 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
tushki7 0:60d829a0353a 1110
tushki7 0:60d829a0353a 1111 /****************** Bit definition for OB_USER register *********************/
tushki7 0:60d829a0353a 1112 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
tushki7 0:60d829a0353a 1113 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
tushki7 0:60d829a0353a 1114
tushki7 0:60d829a0353a 1115 /****************** Bit definition for OB_WRP0 register *********************/
tushki7 0:60d829a0353a 1116 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
tushki7 0:60d829a0353a 1117 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
tushki7 0:60d829a0353a 1118
tushki7 0:60d829a0353a 1119 /****************** Bit definition for OB_WRP1 register *********************/
tushki7 0:60d829a0353a 1120 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
tushki7 0:60d829a0353a 1121 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
tushki7 0:60d829a0353a 1122
tushki7 0:60d829a0353a 1123 /****************** Bit definition for OB_WRP2 register *********************/
tushki7 0:60d829a0353a 1124 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
tushki7 0:60d829a0353a 1125 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
tushki7 0:60d829a0353a 1126
tushki7 0:60d829a0353a 1127 /****************** Bit definition for OB_WRP3 register *********************/
tushki7 0:60d829a0353a 1128 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
tushki7 0:60d829a0353a 1129 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
tushki7 0:60d829a0353a 1130
tushki7 0:60d829a0353a 1131 /******************************************************************************/
tushki7 0:60d829a0353a 1132 /* */
tushki7 0:60d829a0353a 1133 /* General Purpose IOs (GPIO) */
tushki7 0:60d829a0353a 1134 /* */
tushki7 0:60d829a0353a 1135 /******************************************************************************/
tushki7 0:60d829a0353a 1136 /******************* Bit definition for GPIO_MODER register *****************/
tushki7 0:60d829a0353a 1137 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
tushki7 0:60d829a0353a 1138 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 1139 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 1140 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
tushki7 0:60d829a0353a 1141 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 1142 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 1143 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
tushki7 0:60d829a0353a 1144 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 1145 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 1146 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
tushki7 0:60d829a0353a 1147 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 1148 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 1149 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
tushki7 0:60d829a0353a 1150 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 1151 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 1152 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
tushki7 0:60d829a0353a 1153 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 1154 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 1155 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
tushki7 0:60d829a0353a 1156 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 1157 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 1158 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
tushki7 0:60d829a0353a 1159 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 1160 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 1161 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
tushki7 0:60d829a0353a 1162 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
tushki7 0:60d829a0353a 1163 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
tushki7 0:60d829a0353a 1164 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
tushki7 0:60d829a0353a 1165 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
tushki7 0:60d829a0353a 1166 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
tushki7 0:60d829a0353a 1167 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
tushki7 0:60d829a0353a 1168 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
tushki7 0:60d829a0353a 1169 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
tushki7 0:60d829a0353a 1170 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
tushki7 0:60d829a0353a 1171 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
tushki7 0:60d829a0353a 1172 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
tushki7 0:60d829a0353a 1173 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
tushki7 0:60d829a0353a 1174 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
tushki7 0:60d829a0353a 1175 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
tushki7 0:60d829a0353a 1176 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
tushki7 0:60d829a0353a 1177 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
tushki7 0:60d829a0353a 1178 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
tushki7 0:60d829a0353a 1179 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
tushki7 0:60d829a0353a 1180 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
tushki7 0:60d829a0353a 1181 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
tushki7 0:60d829a0353a 1182 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
tushki7 0:60d829a0353a 1183 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
tushki7 0:60d829a0353a 1184 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
tushki7 0:60d829a0353a 1185
tushki7 0:60d829a0353a 1186 /****************** Bit definition for GPIO_OTYPER register *****************/
tushki7 0:60d829a0353a 1187 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 1188 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 1189 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 1190 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 1191 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 1192 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 1193 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 1194 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 1195 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 1196 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 1197 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 1198 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 1199 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 1200 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 1201 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 1202 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 1203
tushki7 0:60d829a0353a 1204 /**************** Bit definition for GPIO_OSPEEDR register ******************/
tushki7 0:60d829a0353a 1205 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
tushki7 0:60d829a0353a 1206 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 1207 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 1208 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
tushki7 0:60d829a0353a 1209 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 1210 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 1211 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
tushki7 0:60d829a0353a 1212 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 1213 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 1214 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
tushki7 0:60d829a0353a 1215 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 1216 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 1217 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
tushki7 0:60d829a0353a 1218 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 1219 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 1220 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
tushki7 0:60d829a0353a 1221 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 1222 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 1223 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
tushki7 0:60d829a0353a 1224 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 1225 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 1226 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
tushki7 0:60d829a0353a 1227 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 1228 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 1229 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
tushki7 0:60d829a0353a 1230 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
tushki7 0:60d829a0353a 1231 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
tushki7 0:60d829a0353a 1232 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
tushki7 0:60d829a0353a 1233 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
tushki7 0:60d829a0353a 1234 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
tushki7 0:60d829a0353a 1235 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
tushki7 0:60d829a0353a 1236 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
tushki7 0:60d829a0353a 1237 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
tushki7 0:60d829a0353a 1238 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
tushki7 0:60d829a0353a 1239 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
tushki7 0:60d829a0353a 1240 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
tushki7 0:60d829a0353a 1241 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
tushki7 0:60d829a0353a 1242 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
tushki7 0:60d829a0353a 1243 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
tushki7 0:60d829a0353a 1244 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
tushki7 0:60d829a0353a 1245 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
tushki7 0:60d829a0353a 1246 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
tushki7 0:60d829a0353a 1247 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
tushki7 0:60d829a0353a 1248 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
tushki7 0:60d829a0353a 1249 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
tushki7 0:60d829a0353a 1250 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
tushki7 0:60d829a0353a 1251 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
tushki7 0:60d829a0353a 1252 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
tushki7 0:60d829a0353a 1253
tushki7 0:60d829a0353a 1254 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
tushki7 0:60d829a0353a 1255 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
tushki7 0:60d829a0353a 1256 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
tushki7 0:60d829a0353a 1257 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
tushki7 0:60d829a0353a 1258 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
tushki7 0:60d829a0353a 1259 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
tushki7 0:60d829a0353a 1260 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
tushki7 0:60d829a0353a 1261 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
tushki7 0:60d829a0353a 1262 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
tushki7 0:60d829a0353a 1263 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
tushki7 0:60d829a0353a 1264 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
tushki7 0:60d829a0353a 1265 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
tushki7 0:60d829a0353a 1266 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
tushki7 0:60d829a0353a 1267 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
tushki7 0:60d829a0353a 1268 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
tushki7 0:60d829a0353a 1269 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
tushki7 0:60d829a0353a 1270 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
tushki7 0:60d829a0353a 1271 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
tushki7 0:60d829a0353a 1272 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
tushki7 0:60d829a0353a 1273 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
tushki7 0:60d829a0353a 1274 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
tushki7 0:60d829a0353a 1275 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
tushki7 0:60d829a0353a 1276 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
tushki7 0:60d829a0353a 1277 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
tushki7 0:60d829a0353a 1278 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
tushki7 0:60d829a0353a 1279 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
tushki7 0:60d829a0353a 1280 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
tushki7 0:60d829a0353a 1281 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
tushki7 0:60d829a0353a 1282 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
tushki7 0:60d829a0353a 1283 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
tushki7 0:60d829a0353a 1284 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
tushki7 0:60d829a0353a 1285 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
tushki7 0:60d829a0353a 1286 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
tushki7 0:60d829a0353a 1287 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
tushki7 0:60d829a0353a 1288 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
tushki7 0:60d829a0353a 1289 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
tushki7 0:60d829a0353a 1290 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
tushki7 0:60d829a0353a 1291 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
tushki7 0:60d829a0353a 1292 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
tushki7 0:60d829a0353a 1293 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
tushki7 0:60d829a0353a 1294 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
tushki7 0:60d829a0353a 1295 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
tushki7 0:60d829a0353a 1296 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
tushki7 0:60d829a0353a 1297 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
tushki7 0:60d829a0353a 1298 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
tushki7 0:60d829a0353a 1299 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
tushki7 0:60d829a0353a 1300 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
tushki7 0:60d829a0353a 1301 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
tushki7 0:60d829a0353a 1302 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
tushki7 0:60d829a0353a 1303
tushki7 0:60d829a0353a 1304 /******************* Bit definition for GPIO_PUPDR register ******************/
tushki7 0:60d829a0353a 1305 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
tushki7 0:60d829a0353a 1306 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 1307 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 1308 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
tushki7 0:60d829a0353a 1309 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 1310 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 1311 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
tushki7 0:60d829a0353a 1312 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 1313 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 1314 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
tushki7 0:60d829a0353a 1315 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 1316 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 1317 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
tushki7 0:60d829a0353a 1318 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 1319 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 1320 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
tushki7 0:60d829a0353a 1321 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 1322 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 1323 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
tushki7 0:60d829a0353a 1324 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 1325 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 1326 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
tushki7 0:60d829a0353a 1327 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 1328 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 1329 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
tushki7 0:60d829a0353a 1330 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
tushki7 0:60d829a0353a 1331 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
tushki7 0:60d829a0353a 1332 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
tushki7 0:60d829a0353a 1333 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
tushki7 0:60d829a0353a 1334 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
tushki7 0:60d829a0353a 1335 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
tushki7 0:60d829a0353a 1336 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
tushki7 0:60d829a0353a 1337 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
tushki7 0:60d829a0353a 1338 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
tushki7 0:60d829a0353a 1339 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
tushki7 0:60d829a0353a 1340 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
tushki7 0:60d829a0353a 1341 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
tushki7 0:60d829a0353a 1342 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
tushki7 0:60d829a0353a 1343 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
tushki7 0:60d829a0353a 1344 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
tushki7 0:60d829a0353a 1345 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
tushki7 0:60d829a0353a 1346 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
tushki7 0:60d829a0353a 1347 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
tushki7 0:60d829a0353a 1348 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
tushki7 0:60d829a0353a 1349 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
tushki7 0:60d829a0353a 1350 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
tushki7 0:60d829a0353a 1351 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
tushki7 0:60d829a0353a 1352 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
tushki7 0:60d829a0353a 1353
tushki7 0:60d829a0353a 1354 /******************* Bit definition for GPIO_IDR register *******************/
tushki7 0:60d829a0353a 1355 #define GPIO_IDR_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 1356 #define GPIO_IDR_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 1357 #define GPIO_IDR_2 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 1358 #define GPIO_IDR_3 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 1359 #define GPIO_IDR_4 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 1360 #define GPIO_IDR_5 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 1361 #define GPIO_IDR_6 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 1362 #define GPIO_IDR_7 ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 1363 #define GPIO_IDR_8 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 1364 #define GPIO_IDR_9 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 1365 #define GPIO_IDR_10 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 1366 #define GPIO_IDR_11 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 1367 #define GPIO_IDR_12 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 1368 #define GPIO_IDR_13 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 1369 #define GPIO_IDR_14 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 1370 #define GPIO_IDR_15 ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 1371
tushki7 0:60d829a0353a 1372 /****************** Bit definition for GPIO_ODR register ********************/
tushki7 0:60d829a0353a 1373 #define GPIO_ODR_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 1374 #define GPIO_ODR_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 1375 #define GPIO_ODR_2 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 1376 #define GPIO_ODR_3 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 1377 #define GPIO_ODR_4 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 1378 #define GPIO_ODR_5 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 1379 #define GPIO_ODR_6 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 1380 #define GPIO_ODR_7 ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 1381 #define GPIO_ODR_8 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 1382 #define GPIO_ODR_9 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 1383 #define GPIO_ODR_10 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 1384 #define GPIO_ODR_11 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 1385 #define GPIO_ODR_12 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 1386 #define GPIO_ODR_13 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 1387 #define GPIO_ODR_14 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 1388 #define GPIO_ODR_15 ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 1389
tushki7 0:60d829a0353a 1390 /****************** Bit definition for GPIO_BSRR register ********************/
tushki7 0:60d829a0353a 1391 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 1392 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 1393 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 1394 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 1395 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 1396 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 1397 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 1398 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 1399 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 1400 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 1401 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 1402 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 1403 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 1404 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 1405 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 1406 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 1407 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
tushki7 0:60d829a0353a 1408 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
tushki7 0:60d829a0353a 1409 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
tushki7 0:60d829a0353a 1410 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
tushki7 0:60d829a0353a 1411 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
tushki7 0:60d829a0353a 1412 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
tushki7 0:60d829a0353a 1413 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
tushki7 0:60d829a0353a 1414 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
tushki7 0:60d829a0353a 1415 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
tushki7 0:60d829a0353a 1416 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
tushki7 0:60d829a0353a 1417 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
tushki7 0:60d829a0353a 1418 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
tushki7 0:60d829a0353a 1419 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
tushki7 0:60d829a0353a 1420 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
tushki7 0:60d829a0353a 1421 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
tushki7 0:60d829a0353a 1422 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
tushki7 0:60d829a0353a 1423
tushki7 0:60d829a0353a 1424 /****************** Bit definition for GPIO_LCKR register ********************/
tushki7 0:60d829a0353a 1425 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 1426 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 1427 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 1428 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 1429 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 1430 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 1431 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 1432 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 1433 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 1434 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 1435 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 1436 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 1437 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 1438 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 1439 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 1440 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 1441 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
tushki7 0:60d829a0353a 1442
tushki7 0:60d829a0353a 1443 /****************** Bit definition for GPIO_AFRL register ********************/
tushki7 0:60d829a0353a 1444 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
tushki7 0:60d829a0353a 1445 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
tushki7 0:60d829a0353a 1446 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
tushki7 0:60d829a0353a 1447 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
tushki7 0:60d829a0353a 1448 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
tushki7 0:60d829a0353a 1449 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
tushki7 0:60d829a0353a 1450 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
tushki7 0:60d829a0353a 1451 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
tushki7 0:60d829a0353a 1452
tushki7 0:60d829a0353a 1453 /****************** Bit definition for GPIO_AFRH register ********************/
tushki7 0:60d829a0353a 1454 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
tushki7 0:60d829a0353a 1455 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
tushki7 0:60d829a0353a 1456 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
tushki7 0:60d829a0353a 1457 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
tushki7 0:60d829a0353a 1458 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
tushki7 0:60d829a0353a 1459 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
tushki7 0:60d829a0353a 1460 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
tushki7 0:60d829a0353a 1461 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
tushki7 0:60d829a0353a 1462
tushki7 0:60d829a0353a 1463 /****************** Bit definition for GPIO_BRR register *********************/
tushki7 0:60d829a0353a 1464 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 1465 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 1466 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 1467 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 1468 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 1469 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 1470 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 1471 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 1472 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 1473 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 1474 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 1475 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 1476 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 1477 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 1478 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 1479 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 1480
tushki7 0:60d829a0353a 1481 /******************************************************************************/
tushki7 0:60d829a0353a 1482 /* */
tushki7 0:60d829a0353a 1483 /* Inter-integrated Circuit Interface (I2C) */
tushki7 0:60d829a0353a 1484 /* */
tushki7 0:60d829a0353a 1485 /******************************************************************************/
tushki7 0:60d829a0353a 1486
tushki7 0:60d829a0353a 1487 /******************* Bit definition for I2C_CR1 register *******************/
tushki7 0:60d829a0353a 1488 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
tushki7 0:60d829a0353a 1489 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
tushki7 0:60d829a0353a 1490 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
tushki7 0:60d829a0353a 1491 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
tushki7 0:60d829a0353a 1492 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
tushki7 0:60d829a0353a 1493 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
tushki7 0:60d829a0353a 1494 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
tushki7 0:60d829a0353a 1495 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
tushki7 0:60d829a0353a 1496 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
tushki7 0:60d829a0353a 1497 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
tushki7 0:60d829a0353a 1498 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
tushki7 0:60d829a0353a 1499 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
tushki7 0:60d829a0353a 1500 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
tushki7 0:60d829a0353a 1501 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
tushki7 0:60d829a0353a 1502 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
tushki7 0:60d829a0353a 1503 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
tushki7 0:60d829a0353a 1504 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
tushki7 0:60d829a0353a 1505 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
tushki7 0:60d829a0353a 1506 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
tushki7 0:60d829a0353a 1507 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
tushki7 0:60d829a0353a 1508
tushki7 0:60d829a0353a 1509 /****************** Bit definition for I2C_CR2 register ********************/
tushki7 0:60d829a0353a 1510 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
tushki7 0:60d829a0353a 1511 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
tushki7 0:60d829a0353a 1512 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
tushki7 0:60d829a0353a 1513 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
tushki7 0:60d829a0353a 1514 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
tushki7 0:60d829a0353a 1515 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
tushki7 0:60d829a0353a 1516 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
tushki7 0:60d829a0353a 1517 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
tushki7 0:60d829a0353a 1518 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
tushki7 0:60d829a0353a 1519 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
tushki7 0:60d829a0353a 1520 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
tushki7 0:60d829a0353a 1521
tushki7 0:60d829a0353a 1522 /******************* Bit definition for I2C_OAR1 register ******************/
tushki7 0:60d829a0353a 1523 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
tushki7 0:60d829a0353a 1524 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
tushki7 0:60d829a0353a 1525 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
tushki7 0:60d829a0353a 1526
tushki7 0:60d829a0353a 1527 /******************* Bit definition for I2C_OAR2 register ******************/
tushki7 0:60d829a0353a 1528 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
tushki7 0:60d829a0353a 1529 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
tushki7 0:60d829a0353a 1530 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
tushki7 0:60d829a0353a 1531
tushki7 0:60d829a0353a 1532 /******************* Bit definition for I2C_TIMINGR register ****************/
tushki7 0:60d829a0353a 1533 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
tushki7 0:60d829a0353a 1534 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
tushki7 0:60d829a0353a 1535 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
tushki7 0:60d829a0353a 1536 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
tushki7 0:60d829a0353a 1537 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
tushki7 0:60d829a0353a 1538
tushki7 0:60d829a0353a 1539 /******************* Bit definition for I2C_TIMEOUTR register ****************/
tushki7 0:60d829a0353a 1540 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
tushki7 0:60d829a0353a 1541 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
tushki7 0:60d829a0353a 1542 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
tushki7 0:60d829a0353a 1543 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
tushki7 0:60d829a0353a 1544 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
tushki7 0:60d829a0353a 1545
tushki7 0:60d829a0353a 1546 /****************** Bit definition for I2C_ISR register ********************/
tushki7 0:60d829a0353a 1547 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
tushki7 0:60d829a0353a 1548 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
tushki7 0:60d829a0353a 1549 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
tushki7 0:60d829a0353a 1550 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
tushki7 0:60d829a0353a 1551 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
tushki7 0:60d829a0353a 1552 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
tushki7 0:60d829a0353a 1553 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
tushki7 0:60d829a0353a 1554 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
tushki7 0:60d829a0353a 1555 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
tushki7 0:60d829a0353a 1556 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
tushki7 0:60d829a0353a 1557 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
tushki7 0:60d829a0353a 1558 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
tushki7 0:60d829a0353a 1559 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
tushki7 0:60d829a0353a 1560 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
tushki7 0:60d829a0353a 1561 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
tushki7 0:60d829a0353a 1562 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
tushki7 0:60d829a0353a 1563 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
tushki7 0:60d829a0353a 1564
tushki7 0:60d829a0353a 1565 /****************** Bit definition for I2C_ICR register ********************/
tushki7 0:60d829a0353a 1566 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
tushki7 0:60d829a0353a 1567 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
tushki7 0:60d829a0353a 1568 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
tushki7 0:60d829a0353a 1569 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
tushki7 0:60d829a0353a 1570 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
tushki7 0:60d829a0353a 1571 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
tushki7 0:60d829a0353a 1572 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
tushki7 0:60d829a0353a 1573 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
tushki7 0:60d829a0353a 1574 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
tushki7 0:60d829a0353a 1575
tushki7 0:60d829a0353a 1576 /****************** Bit definition for I2C_PECR register *******************/
tushki7 0:60d829a0353a 1577 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
tushki7 0:60d829a0353a 1578
tushki7 0:60d829a0353a 1579 /****************** Bit definition for I2C_RXDR register *********************/
tushki7 0:60d829a0353a 1580 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
tushki7 0:60d829a0353a 1581
tushki7 0:60d829a0353a 1582 /****************** Bit definition for I2C_TXDR register *******************/
tushki7 0:60d829a0353a 1583 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
tushki7 0:60d829a0353a 1584
tushki7 0:60d829a0353a 1585 /*****************************************************************************/
tushki7 0:60d829a0353a 1586 /* */
tushki7 0:60d829a0353a 1587 /* Independent WATCHDOG (IWDG) */
tushki7 0:60d829a0353a 1588 /* */
tushki7 0:60d829a0353a 1589 /*****************************************************************************/
tushki7 0:60d829a0353a 1590 /******************* Bit definition for IWDG_KR register *******************/
tushki7 0:60d829a0353a 1591 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
tushki7 0:60d829a0353a 1592
tushki7 0:60d829a0353a 1593 /******************* Bit definition for IWDG_PR register *******************/
tushki7 0:60d829a0353a 1594 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
tushki7 0:60d829a0353a 1595 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
tushki7 0:60d829a0353a 1596 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
tushki7 0:60d829a0353a 1597 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
tushki7 0:60d829a0353a 1598
tushki7 0:60d829a0353a 1599 /******************* Bit definition for IWDG_RLR register ******************/
tushki7 0:60d829a0353a 1600 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
tushki7 0:60d829a0353a 1601
tushki7 0:60d829a0353a 1602 /******************* Bit definition for IWDG_SR register *******************/
tushki7 0:60d829a0353a 1603 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
tushki7 0:60d829a0353a 1604 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
tushki7 0:60d829a0353a 1605 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
tushki7 0:60d829a0353a 1606
tushki7 0:60d829a0353a 1607 /******************* Bit definition for IWDG_KR register *******************/
tushki7 0:60d829a0353a 1608 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
tushki7 0:60d829a0353a 1609
tushki7 0:60d829a0353a 1610 /*****************************************************************************/
tushki7 0:60d829a0353a 1611 /* */
tushki7 0:60d829a0353a 1612 /* Power Control (PWR) */
tushki7 0:60d829a0353a 1613 /* */
tushki7 0:60d829a0353a 1614 /*****************************************************************************/
tushki7 0:60d829a0353a 1615
tushki7 0:60d829a0353a 1616 /******************** Bit definition for PWR_CR register *******************/
tushki7 0:60d829a0353a 1617 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
tushki7 0:60d829a0353a 1618 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
tushki7 0:60d829a0353a 1619 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
tushki7 0:60d829a0353a 1620 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
tushki7 0:60d829a0353a 1621 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
tushki7 0:60d829a0353a 1622
tushki7 0:60d829a0353a 1623 /******************* Bit definition for PWR_CSR register *******************/
tushki7 0:60d829a0353a 1624 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
tushki7 0:60d829a0353a 1625 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
tushki7 0:60d829a0353a 1626
tushki7 0:60d829a0353a 1627 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
tushki7 0:60d829a0353a 1628 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
tushki7 0:60d829a0353a 1629 #define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
tushki7 0:60d829a0353a 1630 #define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
tushki7 0:60d829a0353a 1631 #define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
tushki7 0:60d829a0353a 1632 #define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
tushki7 0:60d829a0353a 1633
tushki7 0:60d829a0353a 1634 /*****************************************************************************/
tushki7 0:60d829a0353a 1635 /* */
tushki7 0:60d829a0353a 1636 /* Reset and Clock Control */
tushki7 0:60d829a0353a 1637 /* */
tushki7 0:60d829a0353a 1638 /*****************************************************************************/
tushki7 0:60d829a0353a 1639
tushki7 0:60d829a0353a 1640 /******************** Bit definition for RCC_CR register *******************/
tushki7 0:60d829a0353a 1641 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
tushki7 0:60d829a0353a 1642 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
tushki7 0:60d829a0353a 1643
tushki7 0:60d829a0353a 1644 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
tushki7 0:60d829a0353a 1645 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
tushki7 0:60d829a0353a 1646 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
tushki7 0:60d829a0353a 1647 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
tushki7 0:60d829a0353a 1648 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
tushki7 0:60d829a0353a 1649 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
tushki7 0:60d829a0353a 1650
tushki7 0:60d829a0353a 1651 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
tushki7 0:60d829a0353a 1652 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
tushki7 0:60d829a0353a 1653 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
tushki7 0:60d829a0353a 1654 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
tushki7 0:60d829a0353a 1655 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
tushki7 0:60d829a0353a 1656 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
tushki7 0:60d829a0353a 1657 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
tushki7 0:60d829a0353a 1658 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
tushki7 0:60d829a0353a 1659 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
tushki7 0:60d829a0353a 1660
tushki7 0:60d829a0353a 1661 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
tushki7 0:60d829a0353a 1662 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
tushki7 0:60d829a0353a 1663 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
tushki7 0:60d829a0353a 1664 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
tushki7 0:60d829a0353a 1665 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
tushki7 0:60d829a0353a 1666 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
tushki7 0:60d829a0353a 1667
tushki7 0:60d829a0353a 1668 /******************** Bit definition for RCC_CFGR register *****************/
tushki7 0:60d829a0353a 1669 /*!< SW configuration */
tushki7 0:60d829a0353a 1670 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
tushki7 0:60d829a0353a 1671 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
tushki7 0:60d829a0353a 1672 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
tushki7 0:60d829a0353a 1673
tushki7 0:60d829a0353a 1674 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
tushki7 0:60d829a0353a 1675 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
tushki7 0:60d829a0353a 1676 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
tushki7 0:60d829a0353a 1677
tushki7 0:60d829a0353a 1678 /*!< SWS configuration */
tushki7 0:60d829a0353a 1679 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
tushki7 0:60d829a0353a 1680 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
tushki7 0:60d829a0353a 1681 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
tushki7 0:60d829a0353a 1682
tushki7 0:60d829a0353a 1683 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
tushki7 0:60d829a0353a 1684 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
tushki7 0:60d829a0353a 1685 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
tushki7 0:60d829a0353a 1686
tushki7 0:60d829a0353a 1687 /*!< HPRE configuration */
tushki7 0:60d829a0353a 1688 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
tushki7 0:60d829a0353a 1689 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
tushki7 0:60d829a0353a 1690 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
tushki7 0:60d829a0353a 1691 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
tushki7 0:60d829a0353a 1692 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
tushki7 0:60d829a0353a 1693
tushki7 0:60d829a0353a 1694 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
tushki7 0:60d829a0353a 1695 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
tushki7 0:60d829a0353a 1696 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
tushki7 0:60d829a0353a 1697 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
tushki7 0:60d829a0353a 1698 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
tushki7 0:60d829a0353a 1699 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
tushki7 0:60d829a0353a 1700 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
tushki7 0:60d829a0353a 1701 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
tushki7 0:60d829a0353a 1702 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
tushki7 0:60d829a0353a 1703
tushki7 0:60d829a0353a 1704 /*!< PPRE configuration */
tushki7 0:60d829a0353a 1705 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
tushki7 0:60d829a0353a 1706 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
tushki7 0:60d829a0353a 1707 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
tushki7 0:60d829a0353a 1708 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
tushki7 0:60d829a0353a 1709
tushki7 0:60d829a0353a 1710 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
tushki7 0:60d829a0353a 1711 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
tushki7 0:60d829a0353a 1712 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
tushki7 0:60d829a0353a 1713 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
tushki7 0:60d829a0353a 1714 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
tushki7 0:60d829a0353a 1715
tushki7 0:60d829a0353a 1716 /*!< ADCPPRE configuration */
tushki7 0:60d829a0353a 1717 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
tushki7 0:60d829a0353a 1718
tushki7 0:60d829a0353a 1719 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
tushki7 0:60d829a0353a 1720 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
tushki7 0:60d829a0353a 1721
tushki7 0:60d829a0353a 1722 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
tushki7 0:60d829a0353a 1723 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
tushki7 0:60d829a0353a 1724 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
tushki7 0:60d829a0353a 1725 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
tushki7 0:60d829a0353a 1726
tushki7 0:60d829a0353a 1727 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
tushki7 0:60d829a0353a 1728 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
tushki7 0:60d829a0353a 1729 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
tushki7 0:60d829a0353a 1730
tushki7 0:60d829a0353a 1731 /*!< PLLMUL configuration */
tushki7 0:60d829a0353a 1732 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
tushki7 0:60d829a0353a 1733 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
tushki7 0:60d829a0353a 1734 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
tushki7 0:60d829a0353a 1735 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
tushki7 0:60d829a0353a 1736 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
tushki7 0:60d829a0353a 1737
tushki7 0:60d829a0353a 1738 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
tushki7 0:60d829a0353a 1739 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
tushki7 0:60d829a0353a 1740 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
tushki7 0:60d829a0353a 1741 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
tushki7 0:60d829a0353a 1742 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
tushki7 0:60d829a0353a 1743 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
tushki7 0:60d829a0353a 1744 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
tushki7 0:60d829a0353a 1745 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
tushki7 0:60d829a0353a 1746 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
tushki7 0:60d829a0353a 1747 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
tushki7 0:60d829a0353a 1748 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
tushki7 0:60d829a0353a 1749 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
tushki7 0:60d829a0353a 1750 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
tushki7 0:60d829a0353a 1751 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
tushki7 0:60d829a0353a 1752 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
tushki7 0:60d829a0353a 1753
tushki7 0:60d829a0353a 1754 /*!< USB configuration */
tushki7 0:60d829a0353a 1755 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
tushki7 0:60d829a0353a 1756
tushki7 0:60d829a0353a 1757 /*!< MCO configuration */
tushki7 0:60d829a0353a 1758 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
tushki7 0:60d829a0353a 1759 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
tushki7 0:60d829a0353a 1760 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
tushki7 0:60d829a0353a 1761 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
tushki7 0:60d829a0353a 1762 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
tushki7 0:60d829a0353a 1763
tushki7 0:60d829a0353a 1764 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
tushki7 0:60d829a0353a 1765 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
tushki7 0:60d829a0353a 1766 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
tushki7 0:60d829a0353a 1767 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
tushki7 0:60d829a0353a 1768 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
tushki7 0:60d829a0353a 1769 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
tushki7 0:60d829a0353a 1770 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
tushki7 0:60d829a0353a 1771 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
tushki7 0:60d829a0353a 1772
tushki7 0:60d829a0353a 1773 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
tushki7 0:60d829a0353a 1774 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
tushki7 0:60d829a0353a 1775 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
tushki7 0:60d829a0353a 1776 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
tushki7 0:60d829a0353a 1777 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
tushki7 0:60d829a0353a 1778 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
tushki7 0:60d829a0353a 1779 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
tushki7 0:60d829a0353a 1780 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
tushki7 0:60d829a0353a 1781 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
tushki7 0:60d829a0353a 1782
tushki7 0:60d829a0353a 1783 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
tushki7 0:60d829a0353a 1784
tushki7 0:60d829a0353a 1785 /*!<****************** Bit definition for RCC_CIR register *****************/
tushki7 0:60d829a0353a 1786 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
tushki7 0:60d829a0353a 1787 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
tushki7 0:60d829a0353a 1788 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
tushki7 0:60d829a0353a 1789 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
tushki7 0:60d829a0353a 1790 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
tushki7 0:60d829a0353a 1791 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
tushki7 0:60d829a0353a 1792 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
tushki7 0:60d829a0353a 1793 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
tushki7 0:60d829a0353a 1794 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
tushki7 0:60d829a0353a 1795 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
tushki7 0:60d829a0353a 1796 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
tushki7 0:60d829a0353a 1797 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
tushki7 0:60d829a0353a 1798 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
tushki7 0:60d829a0353a 1799 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
tushki7 0:60d829a0353a 1800 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
tushki7 0:60d829a0353a 1801 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
tushki7 0:60d829a0353a 1802 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
tushki7 0:60d829a0353a 1803 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
tushki7 0:60d829a0353a 1804 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
tushki7 0:60d829a0353a 1805 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
tushki7 0:60d829a0353a 1806
tushki7 0:60d829a0353a 1807 /***************** Bit definition for RCC_APB2RSTR register ****************/
tushki7 0:60d829a0353a 1808 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
tushki7 0:60d829a0353a 1809 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
tushki7 0:60d829a0353a 1810 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
tushki7 0:60d829a0353a 1811 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
tushki7 0:60d829a0353a 1812 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
tushki7 0:60d829a0353a 1813 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
tushki7 0:60d829a0353a 1814 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
tushki7 0:60d829a0353a 1815 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
tushki7 0:60d829a0353a 1816 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
tushki7 0:60d829a0353a 1817
tushki7 0:60d829a0353a 1818 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
tushki7 0:60d829a0353a 1819 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
tushki7 0:60d829a0353a 1820
tushki7 0:60d829a0353a 1821 /***************** Bit definition for RCC_APB1RSTR register ****************/
tushki7 0:60d829a0353a 1822 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
tushki7 0:60d829a0353a 1823 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
tushki7 0:60d829a0353a 1824 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
tushki7 0:60d829a0353a 1825 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
tushki7 0:60d829a0353a 1826 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
tushki7 0:60d829a0353a 1827 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
tushki7 0:60d829a0353a 1828 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
tushki7 0:60d829a0353a 1829 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
tushki7 0:60d829a0353a 1830 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
tushki7 0:60d829a0353a 1831 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
tushki7 0:60d829a0353a 1832 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
tushki7 0:60d829a0353a 1833 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
tushki7 0:60d829a0353a 1834 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
tushki7 0:60d829a0353a 1835
tushki7 0:60d829a0353a 1836 /****************** Bit definition for RCC_AHBENR register *****************/
tushki7 0:60d829a0353a 1837 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
tushki7 0:60d829a0353a 1838 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
tushki7 0:60d829a0353a 1839 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
tushki7 0:60d829a0353a 1840 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
tushki7 0:60d829a0353a 1841 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
tushki7 0:60d829a0353a 1842 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
tushki7 0:60d829a0353a 1843 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
tushki7 0:60d829a0353a 1844 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
tushki7 0:60d829a0353a 1845 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
tushki7 0:60d829a0353a 1846
tushki7 0:60d829a0353a 1847 /* Old Bit definition maintained for legacy purpose */
tushki7 0:60d829a0353a 1848 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
tushki7 0:60d829a0353a 1849
tushki7 0:60d829a0353a 1850 /***************** Bit definition for RCC_APB2ENR register *****************/
tushki7 0:60d829a0353a 1851 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
tushki7 0:60d829a0353a 1852 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
tushki7 0:60d829a0353a 1853 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
tushki7 0:60d829a0353a 1854 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
tushki7 0:60d829a0353a 1855 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
tushki7 0:60d829a0353a 1856 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
tushki7 0:60d829a0353a 1857 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
tushki7 0:60d829a0353a 1858 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
tushki7 0:60d829a0353a 1859 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
tushki7 0:60d829a0353a 1860
tushki7 0:60d829a0353a 1861 /* Old Bit definition maintained for legacy purpose */
tushki7 0:60d829a0353a 1862 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
tushki7 0:60d829a0353a 1863 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
tushki7 0:60d829a0353a 1864
tushki7 0:60d829a0353a 1865 /***************** Bit definition for RCC_APB1ENR register *****************/
tushki7 0:60d829a0353a 1866 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
tushki7 0:60d829a0353a 1867 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
tushki7 0:60d829a0353a 1868 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
tushki7 0:60d829a0353a 1869 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
tushki7 0:60d829a0353a 1870 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
tushki7 0:60d829a0353a 1871 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
tushki7 0:60d829a0353a 1872 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
tushki7 0:60d829a0353a 1873 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
tushki7 0:60d829a0353a 1874 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
tushki7 0:60d829a0353a 1875 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
tushki7 0:60d829a0353a 1876 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
tushki7 0:60d829a0353a 1877 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
tushki7 0:60d829a0353a 1878 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
tushki7 0:60d829a0353a 1879
tushki7 0:60d829a0353a 1880 /******************* Bit definition for RCC_BDCR register ******************/
tushki7 0:60d829a0353a 1881 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
tushki7 0:60d829a0353a 1882 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
tushki7 0:60d829a0353a 1883 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
tushki7 0:60d829a0353a 1884
tushki7 0:60d829a0353a 1885 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
tushki7 0:60d829a0353a 1886 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
tushki7 0:60d829a0353a 1887 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
tushki7 0:60d829a0353a 1888
tushki7 0:60d829a0353a 1889 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
tushki7 0:60d829a0353a 1890 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
tushki7 0:60d829a0353a 1891 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
tushki7 0:60d829a0353a 1892
tushki7 0:60d829a0353a 1893 /*!< RTC configuration */
tushki7 0:60d829a0353a 1894 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
tushki7 0:60d829a0353a 1895 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
tushki7 0:60d829a0353a 1896 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
tushki7 0:60d829a0353a 1897 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
tushki7 0:60d829a0353a 1898
tushki7 0:60d829a0353a 1899 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
tushki7 0:60d829a0353a 1900 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
tushki7 0:60d829a0353a 1901
tushki7 0:60d829a0353a 1902 /******************* Bit definition for RCC_CSR register *******************/
tushki7 0:60d829a0353a 1903 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
tushki7 0:60d829a0353a 1904 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
tushki7 0:60d829a0353a 1905 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
tushki7 0:60d829a0353a 1906 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
tushki7 0:60d829a0353a 1907 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
tushki7 0:60d829a0353a 1908 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
tushki7 0:60d829a0353a 1909 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
tushki7 0:60d829a0353a 1910 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
tushki7 0:60d829a0353a 1911 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
tushki7 0:60d829a0353a 1912 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
tushki7 0:60d829a0353a 1913 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
tushki7 0:60d829a0353a 1914
tushki7 0:60d829a0353a 1915 /* Old Bit definition maintained for legacy purpose */
tushki7 0:60d829a0353a 1916 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
tushki7 0:60d829a0353a 1917
tushki7 0:60d829a0353a 1918 /******************* Bit definition for RCC_AHBRSTR register ***************/
tushki7 0:60d829a0353a 1919 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
tushki7 0:60d829a0353a 1920 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
tushki7 0:60d829a0353a 1921 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
tushki7 0:60d829a0353a 1922 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
tushki7 0:60d829a0353a 1923 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
tushki7 0:60d829a0353a 1924
tushki7 0:60d829a0353a 1925 /******************* Bit definition for RCC_CFGR2 register *****************/
tushki7 0:60d829a0353a 1926 /*!< PREDIV configuration */
tushki7 0:60d829a0353a 1927 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
tushki7 0:60d829a0353a 1928 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
tushki7 0:60d829a0353a 1929 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
tushki7 0:60d829a0353a 1930 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
tushki7 0:60d829a0353a 1931 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
tushki7 0:60d829a0353a 1932
tushki7 0:60d829a0353a 1933 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
tushki7 0:60d829a0353a 1934 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
tushki7 0:60d829a0353a 1935 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
tushki7 0:60d829a0353a 1936 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
tushki7 0:60d829a0353a 1937 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
tushki7 0:60d829a0353a 1938 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
tushki7 0:60d829a0353a 1939 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
tushki7 0:60d829a0353a 1940 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
tushki7 0:60d829a0353a 1941 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
tushki7 0:60d829a0353a 1942 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
tushki7 0:60d829a0353a 1943 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
tushki7 0:60d829a0353a 1944 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
tushki7 0:60d829a0353a 1945 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
tushki7 0:60d829a0353a 1946 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
tushki7 0:60d829a0353a 1947 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
tushki7 0:60d829a0353a 1948 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
tushki7 0:60d829a0353a 1949
tushki7 0:60d829a0353a 1950 /******************* Bit definition for RCC_CFGR3 register *****************/
tushki7 0:60d829a0353a 1951 /*!< USART1 Clock source selection */
tushki7 0:60d829a0353a 1952 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
tushki7 0:60d829a0353a 1953 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
tushki7 0:60d829a0353a 1954 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
tushki7 0:60d829a0353a 1955
tushki7 0:60d829a0353a 1956 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
tushki7 0:60d829a0353a 1957 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
tushki7 0:60d829a0353a 1958 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
tushki7 0:60d829a0353a 1959 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
tushki7 0:60d829a0353a 1960
tushki7 0:60d829a0353a 1961 /*!< I2C1 Clock source selection */
tushki7 0:60d829a0353a 1962 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
tushki7 0:60d829a0353a 1963
tushki7 0:60d829a0353a 1964 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
tushki7 0:60d829a0353a 1965 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
tushki7 0:60d829a0353a 1966
tushki7 0:60d829a0353a 1967 /*!< USB Clock source selection */
tushki7 0:60d829a0353a 1968 #define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
tushki7 0:60d829a0353a 1969
tushki7 0:60d829a0353a 1970 #define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /*!< PLLCLK selected as USB clock source */
tushki7 0:60d829a0353a 1971
tushki7 0:60d829a0353a 1972 /******************* Bit definition for RCC_CR2 register *******************/
tushki7 0:60d829a0353a 1973 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
tushki7 0:60d829a0353a 1974 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
tushki7 0:60d829a0353a 1975 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
tushki7 0:60d829a0353a 1976 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
tushki7 0:60d829a0353a 1977 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
tushki7 0:60d829a0353a 1978
tushki7 0:60d829a0353a 1979 /*****************************************************************************/
tushki7 0:60d829a0353a 1980 /* */
tushki7 0:60d829a0353a 1981 /* Real-Time Clock (RTC) */
tushki7 0:60d829a0353a 1982 /* */
tushki7 0:60d829a0353a 1983 /*****************************************************************************/
tushki7 0:60d829a0353a 1984 /******************** Bits definition for RTC_TR register ******************/
tushki7 0:60d829a0353a 1985 #define RTC_TR_PM ((uint32_t)0x00400000)
tushki7 0:60d829a0353a 1986 #define RTC_TR_HT ((uint32_t)0x00300000)
tushki7 0:60d829a0353a 1987 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
tushki7 0:60d829a0353a 1988 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
tushki7 0:60d829a0353a 1989 #define RTC_TR_HU ((uint32_t)0x000F0000)
tushki7 0:60d829a0353a 1990 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
tushki7 0:60d829a0353a 1991 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
tushki7 0:60d829a0353a 1992 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
tushki7 0:60d829a0353a 1993 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
tushki7 0:60d829a0353a 1994 #define RTC_TR_MNT ((uint32_t)0x00007000)
tushki7 0:60d829a0353a 1995 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 1996 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 1997 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 1998 #define RTC_TR_MNU ((uint32_t)0x00000F00)
tushki7 0:60d829a0353a 1999 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 2000 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 2001 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 2002 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 2003 #define RTC_TR_ST ((uint32_t)0x00000070)
tushki7 0:60d829a0353a 2004 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 2005 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 2006 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 2007 #define RTC_TR_SU ((uint32_t)0x0000000F)
tushki7 0:60d829a0353a 2008 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 2009 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 2010 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 2011 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 2012
tushki7 0:60d829a0353a 2013 /******************** Bits definition for RTC_DR register ******************/
tushki7 0:60d829a0353a 2014 #define RTC_DR_YT ((uint32_t)0x00F00000)
tushki7 0:60d829a0353a 2015 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
tushki7 0:60d829a0353a 2016 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
tushki7 0:60d829a0353a 2017 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
tushki7 0:60d829a0353a 2018 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
tushki7 0:60d829a0353a 2019 #define RTC_DR_YU ((uint32_t)0x000F0000)
tushki7 0:60d829a0353a 2020 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
tushki7 0:60d829a0353a 2021 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
tushki7 0:60d829a0353a 2022 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
tushki7 0:60d829a0353a 2023 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
tushki7 0:60d829a0353a 2024 #define RTC_DR_WDU ((uint32_t)0x0000E000)
tushki7 0:60d829a0353a 2025 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 2026 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 2027 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 2028 #define RTC_DR_MT ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 2029 #define RTC_DR_MU ((uint32_t)0x00000F00)
tushki7 0:60d829a0353a 2030 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 2031 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 2032 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 2033 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 2034 #define RTC_DR_DT ((uint32_t)0x00000030)
tushki7 0:60d829a0353a 2035 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 2036 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 2037 #define RTC_DR_DU ((uint32_t)0x0000000F)
tushki7 0:60d829a0353a 2038 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 2039 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 2040 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 2041 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 2042
tushki7 0:60d829a0353a 2043 /******************** Bits definition for RTC_CR register ******************/
tushki7 0:60d829a0353a 2044 #define RTC_CR_COE ((uint32_t)0x00800000)
tushki7 0:60d829a0353a 2045 #define RTC_CR_OSEL ((uint32_t)0x00600000)
tushki7 0:60d829a0353a 2046 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
tushki7 0:60d829a0353a 2047 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
tushki7 0:60d829a0353a 2048 #define RTC_CR_POL ((uint32_t)0x00100000)
tushki7 0:60d829a0353a 2049 #define RTC_CR_COSEL ((uint32_t)0x00080000)
tushki7 0:60d829a0353a 2050 #define RTC_CR_BCK ((uint32_t)0x00040000)
tushki7 0:60d829a0353a 2051 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
tushki7 0:60d829a0353a 2052 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
tushki7 0:60d829a0353a 2053 #define RTC_CR_TSIE ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 2054 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 2055 #define RTC_CR_TSE ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 2056 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 2057 #define RTC_CR_FMT ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 2058 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 2059 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 2060 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 2061
tushki7 0:60d829a0353a 2062 /******************** Bits definition for RTC_ISR register *****************/
tushki7 0:60d829a0353a 2063 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
tushki7 0:60d829a0353a 2064 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 2065 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 2066 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 2067 #define RTC_ISR_TSF ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 2068 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 2069 #define RTC_ISR_INIT ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 2070 #define RTC_ISR_INITF ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 2071 #define RTC_ISR_RSF ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 2072 #define RTC_ISR_INITS ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 2073 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 2074 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 2075
tushki7 0:60d829a0353a 2076 /******************** Bits definition for RTC_PRER register ****************/
tushki7 0:60d829a0353a 2077 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
tushki7 0:60d829a0353a 2078 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
tushki7 0:60d829a0353a 2079
tushki7 0:60d829a0353a 2080 /******************** Bits definition for RTC_ALRMAR register **************/
tushki7 0:60d829a0353a 2081 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
tushki7 0:60d829a0353a 2082 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
tushki7 0:60d829a0353a 2083 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
tushki7 0:60d829a0353a 2084 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
tushki7 0:60d829a0353a 2085 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
tushki7 0:60d829a0353a 2086 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
tushki7 0:60d829a0353a 2087 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
tushki7 0:60d829a0353a 2088 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
tushki7 0:60d829a0353a 2089 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
tushki7 0:60d829a0353a 2090 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
tushki7 0:60d829a0353a 2091 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
tushki7 0:60d829a0353a 2092 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
tushki7 0:60d829a0353a 2093 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
tushki7 0:60d829a0353a 2094 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
tushki7 0:60d829a0353a 2095 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
tushki7 0:60d829a0353a 2096 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
tushki7 0:60d829a0353a 2097 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
tushki7 0:60d829a0353a 2098 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
tushki7 0:60d829a0353a 2099 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
tushki7 0:60d829a0353a 2100 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
tushki7 0:60d829a0353a 2101 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 2102 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
tushki7 0:60d829a0353a 2103 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 2104 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 2105 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 2106 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
tushki7 0:60d829a0353a 2107 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 2108 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 2109 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 2110 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 2111 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 2112 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
tushki7 0:60d829a0353a 2113 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 2114 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 2115 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 2116 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
tushki7 0:60d829a0353a 2117 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 2118 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 2119 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 2120 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 2121
tushki7 0:60d829a0353a 2122 /******************** Bits definition for RTC_WPR register *****************/
tushki7 0:60d829a0353a 2123 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
tushki7 0:60d829a0353a 2124
tushki7 0:60d829a0353a 2125 /******************** Bits definition for RTC_SSR register *****************/
tushki7 0:60d829a0353a 2126 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
tushki7 0:60d829a0353a 2127
tushki7 0:60d829a0353a 2128 /******************** Bits definition for RTC_SHIFTR register **************/
tushki7 0:60d829a0353a 2129 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
tushki7 0:60d829a0353a 2130 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
tushki7 0:60d829a0353a 2131
tushki7 0:60d829a0353a 2132 /******************** Bits definition for RTC_TSTR register ****************/
tushki7 0:60d829a0353a 2133 #define RTC_TSTR_PM ((uint32_t)0x00400000)
tushki7 0:60d829a0353a 2134 #define RTC_TSTR_HT ((uint32_t)0x00300000)
tushki7 0:60d829a0353a 2135 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
tushki7 0:60d829a0353a 2136 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
tushki7 0:60d829a0353a 2137 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
tushki7 0:60d829a0353a 2138 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
tushki7 0:60d829a0353a 2139 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
tushki7 0:60d829a0353a 2140 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
tushki7 0:60d829a0353a 2141 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
tushki7 0:60d829a0353a 2142 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
tushki7 0:60d829a0353a 2143 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 2144 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 2145 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 2146 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
tushki7 0:60d829a0353a 2147 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 2148 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 2149 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 2150 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 2151 #define RTC_TSTR_ST ((uint32_t)0x00000070)
tushki7 0:60d829a0353a 2152 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 2153 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 2154 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 2155 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
tushki7 0:60d829a0353a 2156 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 2157 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 2158 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 2159 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 2160
tushki7 0:60d829a0353a 2161 /******************** Bits definition for RTC_TSDR register ****************/
tushki7 0:60d829a0353a 2162 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
tushki7 0:60d829a0353a 2163 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 2164 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 2165 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 2166 #define RTC_TSDR_MT ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 2167 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
tushki7 0:60d829a0353a 2168 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 2169 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 2170 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 2171 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 2172 #define RTC_TSDR_DT ((uint32_t)0x00000030)
tushki7 0:60d829a0353a 2173 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 2174 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 2175 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
tushki7 0:60d829a0353a 2176 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 2177 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 2178 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 2179 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 2180
tushki7 0:60d829a0353a 2181 /******************** Bits definition for RTC_TSSSR register ***************/
tushki7 0:60d829a0353a 2182 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
tushki7 0:60d829a0353a 2183
tushki7 0:60d829a0353a 2184 /******************** Bits definition for RTC_CALR register ****************/
tushki7 0:60d829a0353a 2185 #define RTC_CALR_CALP ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 2186 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 2187 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 2188 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
tushki7 0:60d829a0353a 2189 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 2190 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 2191 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 2192 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 2193 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 2194 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
tushki7 0:60d829a0353a 2195 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
tushki7 0:60d829a0353a 2196 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 2197 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 2198
tushki7 0:60d829a0353a 2199 /******************** Bits definition for RTC_TAFCR register ***************/
tushki7 0:60d829a0353a 2200 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
tushki7 0:60d829a0353a 2201 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
tushki7 0:60d829a0353a 2202 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
tushki7 0:60d829a0353a 2203 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
tushki7 0:60d829a0353a 2204 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
tushki7 0:60d829a0353a 2205 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
tushki7 0:60d829a0353a 2206 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
tushki7 0:60d829a0353a 2207 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
tushki7 0:60d829a0353a 2208 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
tushki7 0:60d829a0353a 2209 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
tushki7 0:60d829a0353a 2210 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
tushki7 0:60d829a0353a 2211 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
tushki7 0:60d829a0353a 2212 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
tushki7 0:60d829a0353a 2213 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
tushki7 0:60d829a0353a 2214 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
tushki7 0:60d829a0353a 2215 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
tushki7 0:60d829a0353a 2216 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
tushki7 0:60d829a0353a 2217 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
tushki7 0:60d829a0353a 2218
tushki7 0:60d829a0353a 2219 /******************** Bits definition for RTC_ALRMASSR register ************/
tushki7 0:60d829a0353a 2220 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
tushki7 0:60d829a0353a 2221 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
tushki7 0:60d829a0353a 2222 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
tushki7 0:60d829a0353a 2223 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
tushki7 0:60d829a0353a 2224 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
tushki7 0:60d829a0353a 2225 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
tushki7 0:60d829a0353a 2226
tushki7 0:60d829a0353a 2227 /*****************************************************************************/
tushki7 0:60d829a0353a 2228 /* */
tushki7 0:60d829a0353a 2229 /* Serial Peripheral Interface (SPI) */
tushki7 0:60d829a0353a 2230 /* */
tushki7 0:60d829a0353a 2231 /*****************************************************************************/
tushki7 0:60d829a0353a 2232 /******************* Bit definition for SPI_CR1 register *******************/
tushki7 0:60d829a0353a 2233 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
tushki7 0:60d829a0353a 2234 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
tushki7 0:60d829a0353a 2235 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
tushki7 0:60d829a0353a 2236 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
tushki7 0:60d829a0353a 2237 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
tushki7 0:60d829a0353a 2238 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
tushki7 0:60d829a0353a 2239 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
tushki7 0:60d829a0353a 2240 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
tushki7 0:60d829a0353a 2241 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
tushki7 0:60d829a0353a 2242 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
tushki7 0:60d829a0353a 2243 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
tushki7 0:60d829a0353a 2244 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
tushki7 0:60d829a0353a 2245 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
tushki7 0:60d829a0353a 2246 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
tushki7 0:60d829a0353a 2247 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
tushki7 0:60d829a0353a 2248 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
tushki7 0:60d829a0353a 2249 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
tushki7 0:60d829a0353a 2250
tushki7 0:60d829a0353a 2251 /******************* Bit definition for SPI_CR2 register *******************/
tushki7 0:60d829a0353a 2252 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
tushki7 0:60d829a0353a 2253 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
tushki7 0:60d829a0353a 2254 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
tushki7 0:60d829a0353a 2255 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
tushki7 0:60d829a0353a 2256 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
tushki7 0:60d829a0353a 2257 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
tushki7 0:60d829a0353a 2258 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
tushki7 0:60d829a0353a 2259 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
tushki7 0:60d829a0353a 2260 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
tushki7 0:60d829a0353a 2261 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
tushki7 0:60d829a0353a 2262 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
tushki7 0:60d829a0353a 2263 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
tushki7 0:60d829a0353a 2264 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
tushki7 0:60d829a0353a 2265 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
tushki7 0:60d829a0353a 2266 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
tushki7 0:60d829a0353a 2267 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
tushki7 0:60d829a0353a 2268
tushki7 0:60d829a0353a 2269 /******************** Bit definition for SPI_SR register *******************/
tushki7 0:60d829a0353a 2270 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
tushki7 0:60d829a0353a 2271 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
tushki7 0:60d829a0353a 2272 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
tushki7 0:60d829a0353a 2273 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
tushki7 0:60d829a0353a 2274 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
tushki7 0:60d829a0353a 2275 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
tushki7 0:60d829a0353a 2276 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
tushki7 0:60d829a0353a 2277 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
tushki7 0:60d829a0353a 2278 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
tushki7 0:60d829a0353a 2279 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
tushki7 0:60d829a0353a 2280 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
tushki7 0:60d829a0353a 2281 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
tushki7 0:60d829a0353a 2282 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
tushki7 0:60d829a0353a 2283
tushki7 0:60d829a0353a 2284 /******************** Bit definition for SPI_DR register *******************/
tushki7 0:60d829a0353a 2285 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
tushki7 0:60d829a0353a 2286
tushki7 0:60d829a0353a 2287 /******************* Bit definition for SPI_CRCPR register *****************/
tushki7 0:60d829a0353a 2288 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
tushki7 0:60d829a0353a 2289
tushki7 0:60d829a0353a 2290 /****************** Bit definition for SPI_RXCRCR register *****************/
tushki7 0:60d829a0353a 2291 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
tushki7 0:60d829a0353a 2292
tushki7 0:60d829a0353a 2293 /****************** Bit definition for SPI_TXCRCR register *****************/
tushki7 0:60d829a0353a 2294 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
tushki7 0:60d829a0353a 2295
tushki7 0:60d829a0353a 2296 /****************** Bit definition for SPI_I2SCFGR register ****************/
tushki7 0:60d829a0353a 2297 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!< Keep for compatibility */
tushki7 0:60d829a0353a 2298
tushki7 0:60d829a0353a 2299 /*****************************************************************************/
tushki7 0:60d829a0353a 2300 /* */
tushki7 0:60d829a0353a 2301 /* System Configuration (SYSCFG) */
tushki7 0:60d829a0353a 2302 /* */
tushki7 0:60d829a0353a 2303 /*****************************************************************************/
tushki7 0:60d829a0353a 2304 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
tushki7 0:60d829a0353a 2305 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
tushki7 0:60d829a0353a 2306 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
tushki7 0:60d829a0353a 2307 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
tushki7 0:60d829a0353a 2308
tushki7 0:60d829a0353a 2309 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
tushki7 0:60d829a0353a 2310 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
tushki7 0:60d829a0353a 2311 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
tushki7 0:60d829a0353a 2312 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
tushki7 0:60d829a0353a 2313 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
tushki7 0:60d829a0353a 2314 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
tushki7 0:60d829a0353a 2315
tushki7 0:60d829a0353a 2316 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
tushki7 0:60d829a0353a 2317 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
tushki7 0:60d829a0353a 2318 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
tushki7 0:60d829a0353a 2319 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
tushki7 0:60d829a0353a 2320 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
tushki7 0:60d829a0353a 2321 #define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
tushki7 0:60d829a0353a 2322
tushki7 0:60d829a0353a 2323 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
tushki7 0:60d829a0353a 2324 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
tushki7 0:60d829a0353a 2325 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
tushki7 0:60d829a0353a 2326 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
tushki7 0:60d829a0353a 2327 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
tushki7 0:60d829a0353a 2328
tushki7 0:60d829a0353a 2329 /**
tushki7 0:60d829a0353a 2330 * @brief EXTI0 configuration
tushki7 0:60d829a0353a 2331 */
tushki7 0:60d829a0353a 2332 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
tushki7 0:60d829a0353a 2333 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
tushki7 0:60d829a0353a 2334 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
tushki7 0:60d829a0353a 2335 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
tushki7 0:60d829a0353a 2336 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
tushki7 0:60d829a0353a 2337
tushki7 0:60d829a0353a 2338 /**
tushki7 0:60d829a0353a 2339 * @brief EXTI1 configuration
tushki7 0:60d829a0353a 2340 */
tushki7 0:60d829a0353a 2341 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
tushki7 0:60d829a0353a 2342 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
tushki7 0:60d829a0353a 2343 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
tushki7 0:60d829a0353a 2344 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
tushki7 0:60d829a0353a 2345 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
tushki7 0:60d829a0353a 2346
tushki7 0:60d829a0353a 2347 /**
tushki7 0:60d829a0353a 2348 * @brief EXTI2 configuration
tushki7 0:60d829a0353a 2349 */
tushki7 0:60d829a0353a 2350 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
tushki7 0:60d829a0353a 2351 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
tushki7 0:60d829a0353a 2352 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
tushki7 0:60d829a0353a 2353 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
tushki7 0:60d829a0353a 2354 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
tushki7 0:60d829a0353a 2355
tushki7 0:60d829a0353a 2356 /**
tushki7 0:60d829a0353a 2357 * @brief EXTI3 configuration
tushki7 0:60d829a0353a 2358 */
tushki7 0:60d829a0353a 2359 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
tushki7 0:60d829a0353a 2360 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
tushki7 0:60d829a0353a 2361 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
tushki7 0:60d829a0353a 2362 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
tushki7 0:60d829a0353a 2363 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
tushki7 0:60d829a0353a 2364
tushki7 0:60d829a0353a 2365 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
tushki7 0:60d829a0353a 2366 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
tushki7 0:60d829a0353a 2367 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
tushki7 0:60d829a0353a 2368 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
tushki7 0:60d829a0353a 2369 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
tushki7 0:60d829a0353a 2370
tushki7 0:60d829a0353a 2371 /**
tushki7 0:60d829a0353a 2372 * @brief EXTI4 configuration
tushki7 0:60d829a0353a 2373 */
tushki7 0:60d829a0353a 2374 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
tushki7 0:60d829a0353a 2375 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
tushki7 0:60d829a0353a 2376 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
tushki7 0:60d829a0353a 2377 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
tushki7 0:60d829a0353a 2378 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
tushki7 0:60d829a0353a 2379
tushki7 0:60d829a0353a 2380 /**
tushki7 0:60d829a0353a 2381 * @brief EXTI5 configuration
tushki7 0:60d829a0353a 2382 */
tushki7 0:60d829a0353a 2383 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
tushki7 0:60d829a0353a 2384 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
tushki7 0:60d829a0353a 2385 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
tushki7 0:60d829a0353a 2386 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
tushki7 0:60d829a0353a 2387 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
tushki7 0:60d829a0353a 2388
tushki7 0:60d829a0353a 2389 /**
tushki7 0:60d829a0353a 2390 * @brief EXTI6 configuration
tushki7 0:60d829a0353a 2391 */
tushki7 0:60d829a0353a 2392 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
tushki7 0:60d829a0353a 2393 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
tushki7 0:60d829a0353a 2394 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
tushki7 0:60d829a0353a 2395 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
tushki7 0:60d829a0353a 2396 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
tushki7 0:60d829a0353a 2397
tushki7 0:60d829a0353a 2398 /**
tushki7 0:60d829a0353a 2399 * @brief EXTI7 configuration
tushki7 0:60d829a0353a 2400 */
tushki7 0:60d829a0353a 2401 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
tushki7 0:60d829a0353a 2402 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
tushki7 0:60d829a0353a 2403 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
tushki7 0:60d829a0353a 2404 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
tushki7 0:60d829a0353a 2405 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
tushki7 0:60d829a0353a 2406
tushki7 0:60d829a0353a 2407 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
tushki7 0:60d829a0353a 2408 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
tushki7 0:60d829a0353a 2409 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
tushki7 0:60d829a0353a 2410 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
tushki7 0:60d829a0353a 2411 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
tushki7 0:60d829a0353a 2412
tushki7 0:60d829a0353a 2413 /**
tushki7 0:60d829a0353a 2414 * @brief EXTI8 configuration
tushki7 0:60d829a0353a 2415 */
tushki7 0:60d829a0353a 2416 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
tushki7 0:60d829a0353a 2417 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
tushki7 0:60d829a0353a 2418 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
tushki7 0:60d829a0353a 2419 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
tushki7 0:60d829a0353a 2420 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
tushki7 0:60d829a0353a 2421
tushki7 0:60d829a0353a 2422 /**
tushki7 0:60d829a0353a 2423 * @brief EXTI9 configuration
tushki7 0:60d829a0353a 2424 */
tushki7 0:60d829a0353a 2425 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
tushki7 0:60d829a0353a 2426 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
tushki7 0:60d829a0353a 2427 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
tushki7 0:60d829a0353a 2428 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
tushki7 0:60d829a0353a 2429 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
tushki7 0:60d829a0353a 2430
tushki7 0:60d829a0353a 2431 /**
tushki7 0:60d829a0353a 2432 * @brief EXTI10 configuration
tushki7 0:60d829a0353a 2433 */
tushki7 0:60d829a0353a 2434 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
tushki7 0:60d829a0353a 2435 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
tushki7 0:60d829a0353a 2436 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
tushki7 0:60d829a0353a 2437 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
tushki7 0:60d829a0353a 2438 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
tushki7 0:60d829a0353a 2439
tushki7 0:60d829a0353a 2440 /**
tushki7 0:60d829a0353a 2441 * @brief EXTI11 configuration
tushki7 0:60d829a0353a 2442 */
tushki7 0:60d829a0353a 2443 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
tushki7 0:60d829a0353a 2444 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
tushki7 0:60d829a0353a 2445 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
tushki7 0:60d829a0353a 2446 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
tushki7 0:60d829a0353a 2447 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
tushki7 0:60d829a0353a 2448
tushki7 0:60d829a0353a 2449 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
tushki7 0:60d829a0353a 2450 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
tushki7 0:60d829a0353a 2451 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
tushki7 0:60d829a0353a 2452 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
tushki7 0:60d829a0353a 2453 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
tushki7 0:60d829a0353a 2454
tushki7 0:60d829a0353a 2455 /**
tushki7 0:60d829a0353a 2456 * @brief EXTI12 configuration
tushki7 0:60d829a0353a 2457 */
tushki7 0:60d829a0353a 2458 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
tushki7 0:60d829a0353a 2459 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
tushki7 0:60d829a0353a 2460 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
tushki7 0:60d829a0353a 2461 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
tushki7 0:60d829a0353a 2462 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
tushki7 0:60d829a0353a 2463
tushki7 0:60d829a0353a 2464 /**
tushki7 0:60d829a0353a 2465 * @brief EXTI13 configuration
tushki7 0:60d829a0353a 2466 */
tushki7 0:60d829a0353a 2467 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
tushki7 0:60d829a0353a 2468 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
tushki7 0:60d829a0353a 2469 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
tushki7 0:60d829a0353a 2470 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
tushki7 0:60d829a0353a 2471 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
tushki7 0:60d829a0353a 2472
tushki7 0:60d829a0353a 2473 /**
tushki7 0:60d829a0353a 2474 * @brief EXTI14 configuration
tushki7 0:60d829a0353a 2475 */
tushki7 0:60d829a0353a 2476 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
tushki7 0:60d829a0353a 2477 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
tushki7 0:60d829a0353a 2478 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
tushki7 0:60d829a0353a 2479 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
tushki7 0:60d829a0353a 2480 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
tushki7 0:60d829a0353a 2481
tushki7 0:60d829a0353a 2482 /**
tushki7 0:60d829a0353a 2483 * @brief EXTI15 configuration
tushki7 0:60d829a0353a 2484 */
tushki7 0:60d829a0353a 2485 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
tushki7 0:60d829a0353a 2486 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
tushki7 0:60d829a0353a 2487 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
tushki7 0:60d829a0353a 2488 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
tushki7 0:60d829a0353a 2489 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
tushki7 0:60d829a0353a 2490
tushki7 0:60d829a0353a 2491 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
tushki7 0:60d829a0353a 2492 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
tushki7 0:60d829a0353a 2493 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
tushki7 0:60d829a0353a 2494 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
tushki7 0:60d829a0353a 2495 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
tushki7 0:60d829a0353a 2496
tushki7 0:60d829a0353a 2497 /*****************************************************************************/
tushki7 0:60d829a0353a 2498 /* */
tushki7 0:60d829a0353a 2499 /* Timers (TIM) */
tushki7 0:60d829a0353a 2500 /* */
tushki7 0:60d829a0353a 2501 /*****************************************************************************/
tushki7 0:60d829a0353a 2502 /******************* Bit definition for TIM_CR1 register *******************/
tushki7 0:60d829a0353a 2503 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
tushki7 0:60d829a0353a 2504 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
tushki7 0:60d829a0353a 2505 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
tushki7 0:60d829a0353a 2506 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
tushki7 0:60d829a0353a 2507 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
tushki7 0:60d829a0353a 2508
tushki7 0:60d829a0353a 2509 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
tushki7 0:60d829a0353a 2510 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
tushki7 0:60d829a0353a 2511 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
tushki7 0:60d829a0353a 2512
tushki7 0:60d829a0353a 2513 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
tushki7 0:60d829a0353a 2514
tushki7 0:60d829a0353a 2515 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
tushki7 0:60d829a0353a 2516 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
tushki7 0:60d829a0353a 2517 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
tushki7 0:60d829a0353a 2518
tushki7 0:60d829a0353a 2519 /******************* Bit definition for TIM_CR2 register *******************/
tushki7 0:60d829a0353a 2520 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
tushki7 0:60d829a0353a 2521 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
tushki7 0:60d829a0353a 2522 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
tushki7 0:60d829a0353a 2523
tushki7 0:60d829a0353a 2524 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
tushki7 0:60d829a0353a 2525 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
tushki7 0:60d829a0353a 2526 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
tushki7 0:60d829a0353a 2527 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
tushki7 0:60d829a0353a 2528
tushki7 0:60d829a0353a 2529 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
tushki7 0:60d829a0353a 2530 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
tushki7 0:60d829a0353a 2531 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
tushki7 0:60d829a0353a 2532 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
tushki7 0:60d829a0353a 2533 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
tushki7 0:60d829a0353a 2534 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
tushki7 0:60d829a0353a 2535 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
tushki7 0:60d829a0353a 2536 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
tushki7 0:60d829a0353a 2537
tushki7 0:60d829a0353a 2538 /******************* Bit definition for TIM_SMCR register ******************/
tushki7 0:60d829a0353a 2539 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
tushki7 0:60d829a0353a 2540 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
tushki7 0:60d829a0353a 2541 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
tushki7 0:60d829a0353a 2542 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
tushki7 0:60d829a0353a 2543
tushki7 0:60d829a0353a 2544 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
tushki7 0:60d829a0353a 2545
tushki7 0:60d829a0353a 2546 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
tushki7 0:60d829a0353a 2547 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
tushki7 0:60d829a0353a 2548 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
tushki7 0:60d829a0353a 2549 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
tushki7 0:60d829a0353a 2550
tushki7 0:60d829a0353a 2551 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
tushki7 0:60d829a0353a 2552
tushki7 0:60d829a0353a 2553 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
tushki7 0:60d829a0353a 2554 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
tushki7 0:60d829a0353a 2555 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
tushki7 0:60d829a0353a 2556 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
tushki7 0:60d829a0353a 2557 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
tushki7 0:60d829a0353a 2558
tushki7 0:60d829a0353a 2559 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
tushki7 0:60d829a0353a 2560 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
tushki7 0:60d829a0353a 2561 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
tushki7 0:60d829a0353a 2562
tushki7 0:60d829a0353a 2563 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
tushki7 0:60d829a0353a 2564 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
tushki7 0:60d829a0353a 2565
tushki7 0:60d829a0353a 2566 /******************* Bit definition for TIM_DIER register ******************/
tushki7 0:60d829a0353a 2567 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
tushki7 0:60d829a0353a 2568 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
tushki7 0:60d829a0353a 2569 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
tushki7 0:60d829a0353a 2570 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
tushki7 0:60d829a0353a 2571 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
tushki7 0:60d829a0353a 2572 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
tushki7 0:60d829a0353a 2573 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
tushki7 0:60d829a0353a 2574 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
tushki7 0:60d829a0353a 2575 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
tushki7 0:60d829a0353a 2576 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
tushki7 0:60d829a0353a 2577 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
tushki7 0:60d829a0353a 2578 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
tushki7 0:60d829a0353a 2579 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
tushki7 0:60d829a0353a 2580 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
tushki7 0:60d829a0353a 2581 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
tushki7 0:60d829a0353a 2582
tushki7 0:60d829a0353a 2583 /******************** Bit definition for TIM_SR register *******************/
tushki7 0:60d829a0353a 2584 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
tushki7 0:60d829a0353a 2585 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
tushki7 0:60d829a0353a 2586 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
tushki7 0:60d829a0353a 2587 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
tushki7 0:60d829a0353a 2588 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
tushki7 0:60d829a0353a 2589 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
tushki7 0:60d829a0353a 2590 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
tushki7 0:60d829a0353a 2591 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
tushki7 0:60d829a0353a 2592 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
tushki7 0:60d829a0353a 2593 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
tushki7 0:60d829a0353a 2594 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
tushki7 0:60d829a0353a 2595 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
tushki7 0:60d829a0353a 2596
tushki7 0:60d829a0353a 2597 /******************* Bit definition for TIM_EGR register *******************/
tushki7 0:60d829a0353a 2598 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
tushki7 0:60d829a0353a 2599 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
tushki7 0:60d829a0353a 2600 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
tushki7 0:60d829a0353a 2601 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
tushki7 0:60d829a0353a 2602 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
tushki7 0:60d829a0353a 2603 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
tushki7 0:60d829a0353a 2604 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
tushki7 0:60d829a0353a 2605 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
tushki7 0:60d829a0353a 2606
tushki7 0:60d829a0353a 2607 /****************** Bit definition for TIM_CCMR1 register ******************/
tushki7 0:60d829a0353a 2608 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
tushki7 0:60d829a0353a 2609 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
tushki7 0:60d829a0353a 2610 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
tushki7 0:60d829a0353a 2611
tushki7 0:60d829a0353a 2612 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
tushki7 0:60d829a0353a 2613 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
tushki7 0:60d829a0353a 2614
tushki7 0:60d829a0353a 2615 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
tushki7 0:60d829a0353a 2616 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
tushki7 0:60d829a0353a 2617 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
tushki7 0:60d829a0353a 2618 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
tushki7 0:60d829a0353a 2619
tushki7 0:60d829a0353a 2620 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
tushki7 0:60d829a0353a 2621
tushki7 0:60d829a0353a 2622 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
tushki7 0:60d829a0353a 2623 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
tushki7 0:60d829a0353a 2624 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
tushki7 0:60d829a0353a 2625
tushki7 0:60d829a0353a 2626 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
tushki7 0:60d829a0353a 2627 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
tushki7 0:60d829a0353a 2628
tushki7 0:60d829a0353a 2629 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
tushki7 0:60d829a0353a 2630 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
tushki7 0:60d829a0353a 2631 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
tushki7 0:60d829a0353a 2632 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
tushki7 0:60d829a0353a 2633
tushki7 0:60d829a0353a 2634 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
tushki7 0:60d829a0353a 2635
tushki7 0:60d829a0353a 2636 /*---------------------------------------------------------------------------*/
tushki7 0:60d829a0353a 2637
tushki7 0:60d829a0353a 2638 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
tushki7 0:60d829a0353a 2639 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
tushki7 0:60d829a0353a 2640 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
tushki7 0:60d829a0353a 2641
tushki7 0:60d829a0353a 2642 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
tushki7 0:60d829a0353a 2643 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
tushki7 0:60d829a0353a 2644 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
tushki7 0:60d829a0353a 2645 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
tushki7 0:60d829a0353a 2646 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
tushki7 0:60d829a0353a 2647
tushki7 0:60d829a0353a 2648 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
tushki7 0:60d829a0353a 2649 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
tushki7 0:60d829a0353a 2650 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
tushki7 0:60d829a0353a 2651
tushki7 0:60d829a0353a 2652 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
tushki7 0:60d829a0353a 2653 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
tushki7 0:60d829a0353a 2654 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
tushki7 0:60d829a0353a 2655 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
tushki7 0:60d829a0353a 2656 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
tushki7 0:60d829a0353a 2657
tushki7 0:60d829a0353a 2658 /****************** Bit definition for TIM_CCMR2 register ******************/
tushki7 0:60d829a0353a 2659 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
tushki7 0:60d829a0353a 2660 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
tushki7 0:60d829a0353a 2661 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
tushki7 0:60d829a0353a 2662
tushki7 0:60d829a0353a 2663 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
tushki7 0:60d829a0353a 2664 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
tushki7 0:60d829a0353a 2665
tushki7 0:60d829a0353a 2666 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
tushki7 0:60d829a0353a 2667 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
tushki7 0:60d829a0353a 2668 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
tushki7 0:60d829a0353a 2669 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
tushki7 0:60d829a0353a 2670
tushki7 0:60d829a0353a 2671 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
tushki7 0:60d829a0353a 2672
tushki7 0:60d829a0353a 2673 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
tushki7 0:60d829a0353a 2674 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
tushki7 0:60d829a0353a 2675 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
tushki7 0:60d829a0353a 2676
tushki7 0:60d829a0353a 2677 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
tushki7 0:60d829a0353a 2678 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
tushki7 0:60d829a0353a 2679
tushki7 0:60d829a0353a 2680 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
tushki7 0:60d829a0353a 2681 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
tushki7 0:60d829a0353a 2682 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
tushki7 0:60d829a0353a 2683 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
tushki7 0:60d829a0353a 2684
tushki7 0:60d829a0353a 2685 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
tushki7 0:60d829a0353a 2686
tushki7 0:60d829a0353a 2687 /*---------------------------------------------------------------------------*/
tushki7 0:60d829a0353a 2688
tushki7 0:60d829a0353a 2689 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
tushki7 0:60d829a0353a 2690 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
tushki7 0:60d829a0353a 2691 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
tushki7 0:60d829a0353a 2692
tushki7 0:60d829a0353a 2693 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
tushki7 0:60d829a0353a 2694 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
tushki7 0:60d829a0353a 2695 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
tushki7 0:60d829a0353a 2696 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
tushki7 0:60d829a0353a 2697 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
tushki7 0:60d829a0353a 2698
tushki7 0:60d829a0353a 2699 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
tushki7 0:60d829a0353a 2700 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
tushki7 0:60d829a0353a 2701 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
tushki7 0:60d829a0353a 2702
tushki7 0:60d829a0353a 2703 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
tushki7 0:60d829a0353a 2704 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
tushki7 0:60d829a0353a 2705 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
tushki7 0:60d829a0353a 2706 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
tushki7 0:60d829a0353a 2707 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
tushki7 0:60d829a0353a 2708
tushki7 0:60d829a0353a 2709 /******************* Bit definition for TIM_CCER register ******************/
tushki7 0:60d829a0353a 2710 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
tushki7 0:60d829a0353a 2711 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
tushki7 0:60d829a0353a 2712 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
tushki7 0:60d829a0353a 2713 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
tushki7 0:60d829a0353a 2714 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
tushki7 0:60d829a0353a 2715 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
tushki7 0:60d829a0353a 2716 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
tushki7 0:60d829a0353a 2717 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
tushki7 0:60d829a0353a 2718 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
tushki7 0:60d829a0353a 2719 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
tushki7 0:60d829a0353a 2720 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
tushki7 0:60d829a0353a 2721 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
tushki7 0:60d829a0353a 2722 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
tushki7 0:60d829a0353a 2723 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
tushki7 0:60d829a0353a 2724 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
tushki7 0:60d829a0353a 2725
tushki7 0:60d829a0353a 2726 /******************* Bit definition for TIM_CNT register *******************/
tushki7 0:60d829a0353a 2727 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
tushki7 0:60d829a0353a 2728
tushki7 0:60d829a0353a 2729 /******************* Bit definition for TIM_PSC register *******************/
tushki7 0:60d829a0353a 2730 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
tushki7 0:60d829a0353a 2731
tushki7 0:60d829a0353a 2732 /******************* Bit definition for TIM_ARR register *******************/
tushki7 0:60d829a0353a 2733 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
tushki7 0:60d829a0353a 2734
tushki7 0:60d829a0353a 2735 /******************* Bit definition for TIM_RCR register *******************/
tushki7 0:60d829a0353a 2736 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
tushki7 0:60d829a0353a 2737
tushki7 0:60d829a0353a 2738 /******************* Bit definition for TIM_CCR1 register ******************/
tushki7 0:60d829a0353a 2739 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
tushki7 0:60d829a0353a 2740
tushki7 0:60d829a0353a 2741 /******************* Bit definition for TIM_CCR2 register ******************/
tushki7 0:60d829a0353a 2742 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
tushki7 0:60d829a0353a 2743
tushki7 0:60d829a0353a 2744 /******************* Bit definition for TIM_CCR3 register ******************/
tushki7 0:60d829a0353a 2745 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
tushki7 0:60d829a0353a 2746
tushki7 0:60d829a0353a 2747 /******************* Bit definition for TIM_CCR4 register ******************/
tushki7 0:60d829a0353a 2748 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
tushki7 0:60d829a0353a 2749
tushki7 0:60d829a0353a 2750 /******************* Bit definition for TIM_BDTR register ******************/
tushki7 0:60d829a0353a 2751 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
tushki7 0:60d829a0353a 2752 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
tushki7 0:60d829a0353a 2753 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
tushki7 0:60d829a0353a 2754 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
tushki7 0:60d829a0353a 2755 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
tushki7 0:60d829a0353a 2756 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
tushki7 0:60d829a0353a 2757 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
tushki7 0:60d829a0353a 2758 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
tushki7 0:60d829a0353a 2759 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
tushki7 0:60d829a0353a 2760
tushki7 0:60d829a0353a 2761 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
tushki7 0:60d829a0353a 2762 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
tushki7 0:60d829a0353a 2763 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
tushki7 0:60d829a0353a 2764
tushki7 0:60d829a0353a 2765 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
tushki7 0:60d829a0353a 2766 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
tushki7 0:60d829a0353a 2767 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
tushki7 0:60d829a0353a 2768 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
tushki7 0:60d829a0353a 2769 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
tushki7 0:60d829a0353a 2770 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
tushki7 0:60d829a0353a 2771
tushki7 0:60d829a0353a 2772 /******************* Bit definition for TIM_DCR register *******************/
tushki7 0:60d829a0353a 2773 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
tushki7 0:60d829a0353a 2774 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
tushki7 0:60d829a0353a 2775 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
tushki7 0:60d829a0353a 2776 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
tushki7 0:60d829a0353a 2777 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
tushki7 0:60d829a0353a 2778 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
tushki7 0:60d829a0353a 2779
tushki7 0:60d829a0353a 2780 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
tushki7 0:60d829a0353a 2781 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
tushki7 0:60d829a0353a 2782 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
tushki7 0:60d829a0353a 2783 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
tushki7 0:60d829a0353a 2784 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
tushki7 0:60d829a0353a 2785 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
tushki7 0:60d829a0353a 2786
tushki7 0:60d829a0353a 2787 /******************* Bit definition for TIM_DMAR register ******************/
tushki7 0:60d829a0353a 2788 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
tushki7 0:60d829a0353a 2789
tushki7 0:60d829a0353a 2790 /******************* Bit definition for TIM14_OR register ********************/
tushki7 0:60d829a0353a 2791 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
tushki7 0:60d829a0353a 2792 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
tushki7 0:60d829a0353a 2793 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
tushki7 0:60d829a0353a 2794
tushki7 0:60d829a0353a 2795 /******************************************************************************/
tushki7 0:60d829a0353a 2796 /* */
tushki7 0:60d829a0353a 2797 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
tushki7 0:60d829a0353a 2798 /* */
tushki7 0:60d829a0353a 2799 /******************************************************************************/
tushki7 0:60d829a0353a 2800 /****************** Bit definition for USART_CR1 register *******************/
tushki7 0:60d829a0353a 2801 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
tushki7 0:60d829a0353a 2802 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
tushki7 0:60d829a0353a 2803 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
tushki7 0:60d829a0353a 2804 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
tushki7 0:60d829a0353a 2805 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
tushki7 0:60d829a0353a 2806 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
tushki7 0:60d829a0353a 2807 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
tushki7 0:60d829a0353a 2808 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
tushki7 0:60d829a0353a 2809 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
tushki7 0:60d829a0353a 2810 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
tushki7 0:60d829a0353a 2811 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
tushki7 0:60d829a0353a 2812 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
tushki7 0:60d829a0353a 2813 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
tushki7 0:60d829a0353a 2814 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
tushki7 0:60d829a0353a 2815 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
tushki7 0:60d829a0353a 2816 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
tushki7 0:60d829a0353a 2817 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
tushki7 0:60d829a0353a 2818 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
tushki7 0:60d829a0353a 2819 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
tushki7 0:60d829a0353a 2820 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
tushki7 0:60d829a0353a 2821 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
tushki7 0:60d829a0353a 2822 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
tushki7 0:60d829a0353a 2823 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
tushki7 0:60d829a0353a 2824 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
tushki7 0:60d829a0353a 2825 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
tushki7 0:60d829a0353a 2826 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
tushki7 0:60d829a0353a 2827 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
tushki7 0:60d829a0353a 2828 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
tushki7 0:60d829a0353a 2829 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
tushki7 0:60d829a0353a 2830 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
tushki7 0:60d829a0353a 2831 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
tushki7 0:60d829a0353a 2832
tushki7 0:60d829a0353a 2833 /****************** Bit definition for USART_CR2 register *******************/
tushki7 0:60d829a0353a 2834 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
tushki7 0:60d829a0353a 2835 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
tushki7 0:60d829a0353a 2836 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
tushki7 0:60d829a0353a 2837 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
tushki7 0:60d829a0353a 2838 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
tushki7 0:60d829a0353a 2839 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
tushki7 0:60d829a0353a 2840 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
tushki7 0:60d829a0353a 2841 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
tushki7 0:60d829a0353a 2842 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< Keep for compatibility */
tushki7 0:60d829a0353a 2843 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
tushki7 0:60d829a0353a 2844 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
tushki7 0:60d829a0353a 2845 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
tushki7 0:60d829a0353a 2846 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
tushki7 0:60d829a0353a 2847 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
tushki7 0:60d829a0353a 2848 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
tushki7 0:60d829a0353a 2849 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
tushki7 0:60d829a0353a 2850 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
tushki7 0:60d829a0353a 2851 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
tushki7 0:60d829a0353a 2852 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
tushki7 0:60d829a0353a 2853 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
tushki7 0:60d829a0353a 2854
tushki7 0:60d829a0353a 2855 /****************** Bit definition for USART_CR3 register *******************/
tushki7 0:60d829a0353a 2856 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
tushki7 0:60d829a0353a 2857 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< Keep for compatibility */
tushki7 0:60d829a0353a 2858 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
tushki7 0:60d829a0353a 2859 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Keep for compatibility */
tushki7 0:60d829a0353a 2860 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
tushki7 0:60d829a0353a 2861 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
tushki7 0:60d829a0353a 2862 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
tushki7 0:60d829a0353a 2863 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
tushki7 0:60d829a0353a 2864 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
tushki7 0:60d829a0353a 2865 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
tushki7 0:60d829a0353a 2866 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
tushki7 0:60d829a0353a 2867 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
tushki7 0:60d829a0353a 2868 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
tushki7 0:60d829a0353a 2869 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
tushki7 0:60d829a0353a 2870
tushki7 0:60d829a0353a 2871 /****************** Bit definition for USART_BRR register *******************/
tushki7 0:60d829a0353a 2872 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
tushki7 0:60d829a0353a 2873 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
tushki7 0:60d829a0353a 2874
tushki7 0:60d829a0353a 2875 /****************** Bit definition for USART_GTPR register ******************/
tushki7 0:60d829a0353a 2876 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
tushki7 0:60d829a0353a 2877 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
tushki7 0:60d829a0353a 2878
tushki7 0:60d829a0353a 2879
tushki7 0:60d829a0353a 2880 /******************* Bit definition for USART_RTOR register *****************/
tushki7 0:60d829a0353a 2881 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
tushki7 0:60d829a0353a 2882 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
tushki7 0:60d829a0353a 2883
tushki7 0:60d829a0353a 2884 /******************* Bit definition for USART_RQR register ******************/
tushki7 0:60d829a0353a 2885 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
tushki7 0:60d829a0353a 2886 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
tushki7 0:60d829a0353a 2887 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
tushki7 0:60d829a0353a 2888 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
tushki7 0:60d829a0353a 2889
tushki7 0:60d829a0353a 2890 /******************* Bit definition for USART_ISR register ******************/
tushki7 0:60d829a0353a 2891 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
tushki7 0:60d829a0353a 2892 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
tushki7 0:60d829a0353a 2893 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
tushki7 0:60d829a0353a 2894 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
tushki7 0:60d829a0353a 2895 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
tushki7 0:60d829a0353a 2896 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
tushki7 0:60d829a0353a 2897 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
tushki7 0:60d829a0353a 2898 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
tushki7 0:60d829a0353a 2899 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
tushki7 0:60d829a0353a 2900 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
tushki7 0:60d829a0353a 2901 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
tushki7 0:60d829a0353a 2902 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
tushki7 0:60d829a0353a 2903 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
tushki7 0:60d829a0353a 2904 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
tushki7 0:60d829a0353a 2905 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
tushki7 0:60d829a0353a 2906 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
tushki7 0:60d829a0353a 2907 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
tushki7 0:60d829a0353a 2908 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
tushki7 0:60d829a0353a 2909 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
tushki7 0:60d829a0353a 2910
tushki7 0:60d829a0353a 2911 /******************* Bit definition for USART_ICR register ******************/
tushki7 0:60d829a0353a 2912 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
tushki7 0:60d829a0353a 2913 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
tushki7 0:60d829a0353a 2914 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
tushki7 0:60d829a0353a 2915 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
tushki7 0:60d829a0353a 2916 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
tushki7 0:60d829a0353a 2917 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
tushki7 0:60d829a0353a 2918 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
tushki7 0:60d829a0353a 2919 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
tushki7 0:60d829a0353a 2920 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
tushki7 0:60d829a0353a 2921
tushki7 0:60d829a0353a 2922 /******************* Bit definition for USART_RDR register ******************/
tushki7 0:60d829a0353a 2923 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
tushki7 0:60d829a0353a 2924
tushki7 0:60d829a0353a 2925 /******************* Bit definition for USART_TDR register ******************/
tushki7 0:60d829a0353a 2926 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
tushki7 0:60d829a0353a 2927
tushki7 0:60d829a0353a 2928 /******************************************************************************/
tushki7 0:60d829a0353a 2929 /* */
tushki7 0:60d829a0353a 2930 /* USB Device General registers */
tushki7 0:60d829a0353a 2931 /* */
tushki7 0:60d829a0353a 2932 /******************************************************************************/
tushki7 0:60d829a0353a 2933 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
tushki7 0:60d829a0353a 2934 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
tushki7 0:60d829a0353a 2935 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
tushki7 0:60d829a0353a 2936 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
tushki7 0:60d829a0353a 2937 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
tushki7 0:60d829a0353a 2938 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
tushki7 0:60d829a0353a 2939 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
tushki7 0:60d829a0353a 2940
tushki7 0:60d829a0353a 2941 /**************************** ISTR interrupt events *************************/
tushki7 0:60d829a0353a 2942 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
tushki7 0:60d829a0353a 2943 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
tushki7 0:60d829a0353a 2944 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
tushki7 0:60d829a0353a 2945 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
tushki7 0:60d829a0353a 2946 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
tushki7 0:60d829a0353a 2947 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
tushki7 0:60d829a0353a 2948 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
tushki7 0:60d829a0353a 2949 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
tushki7 0:60d829a0353a 2950 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
tushki7 0:60d829a0353a 2951 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
tushki7 0:60d829a0353a 2952 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
tushki7 0:60d829a0353a 2953
tushki7 0:60d829a0353a 2954 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
tushki7 0:60d829a0353a 2955 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
tushki7 0:60d829a0353a 2956 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
tushki7 0:60d829a0353a 2957 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
tushki7 0:60d829a0353a 2958 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
tushki7 0:60d829a0353a 2959 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
tushki7 0:60d829a0353a 2960 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
tushki7 0:60d829a0353a 2961 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
tushki7 0:60d829a0353a 2962 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
tushki7 0:60d829a0353a 2963
tushki7 0:60d829a0353a 2964 /************************* CNTR control register bits definitions ***********/
tushki7 0:60d829a0353a 2965 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
tushki7 0:60d829a0353a 2966 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
tushki7 0:60d829a0353a 2967 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
tushki7 0:60d829a0353a 2968 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
tushki7 0:60d829a0353a 2969 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
tushki7 0:60d829a0353a 2970 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
tushki7 0:60d829a0353a 2971 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
tushki7 0:60d829a0353a 2972 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
tushki7 0:60d829a0353a 2973 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
tushki7 0:60d829a0353a 2974 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
tushki7 0:60d829a0353a 2975 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
tushki7 0:60d829a0353a 2976 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
tushki7 0:60d829a0353a 2977 #define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
tushki7 0:60d829a0353a 2978 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
tushki7 0:60d829a0353a 2979 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
tushki7 0:60d829a0353a 2980
tushki7 0:60d829a0353a 2981 /************************* BCDR control register bits definitions ***********/
tushki7 0:60d829a0353a 2982 #define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
tushki7 0:60d829a0353a 2983 #define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
tushki7 0:60d829a0353a 2984 #define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
tushki7 0:60d829a0353a 2985 #define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
tushki7 0:60d829a0353a 2986 #define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
tushki7 0:60d829a0353a 2987 #define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
tushki7 0:60d829a0353a 2988 #define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
tushki7 0:60d829a0353a 2989 #define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
tushki7 0:60d829a0353a 2990 #define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
tushki7 0:60d829a0353a 2991
tushki7 0:60d829a0353a 2992 /*************************** LPM register bits definitions ******************/
tushki7 0:60d829a0353a 2993 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
tushki7 0:60d829a0353a 2994 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
tushki7 0:60d829a0353a 2995 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
tushki7 0:60d829a0353a 2996 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
tushki7 0:60d829a0353a 2997
tushki7 0:60d829a0353a 2998 /******************** FNR Frame Number Register bit definitions ************/
tushki7 0:60d829a0353a 2999 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
tushki7 0:60d829a0353a 3000 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
tushki7 0:60d829a0353a 3001 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
tushki7 0:60d829a0353a 3002 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
tushki7 0:60d829a0353a 3003 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
tushki7 0:60d829a0353a 3004
tushki7 0:60d829a0353a 3005 /******************** DADDR Device ADDRess bit definitions ****************/
tushki7 0:60d829a0353a 3006 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
tushki7 0:60d829a0353a 3007 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
tushki7 0:60d829a0353a 3008
tushki7 0:60d829a0353a 3009 /****************************** Endpoint register *************************/
tushki7 0:60d829a0353a 3010 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
tushki7 0:60d829a0353a 3011 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
tushki7 0:60d829a0353a 3012 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
tushki7 0:60d829a0353a 3013 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
tushki7 0:60d829a0353a 3014 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
tushki7 0:60d829a0353a 3015 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
tushki7 0:60d829a0353a 3016 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
tushki7 0:60d829a0353a 3017 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
tushki7 0:60d829a0353a 3018 /* bit positions */
tushki7 0:60d829a0353a 3019 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
tushki7 0:60d829a0353a 3020 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
tushki7 0:60d829a0353a 3021 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
tushki7 0:60d829a0353a 3022 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
tushki7 0:60d829a0353a 3023 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
tushki7 0:60d829a0353a 3024 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
tushki7 0:60d829a0353a 3025 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
tushki7 0:60d829a0353a 3026 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
tushki7 0:60d829a0353a 3027 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
tushki7 0:60d829a0353a 3028 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
tushki7 0:60d829a0353a 3029
tushki7 0:60d829a0353a 3030 /* EndPoint REGister MASK (no toggle fields) */
tushki7 0:60d829a0353a 3031 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
tushki7 0:60d829a0353a 3032 /*!< EP_TYPE[1:0] EndPoint TYPE */
tushki7 0:60d829a0353a 3033 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
tushki7 0:60d829a0353a 3034 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
tushki7 0:60d829a0353a 3035 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
tushki7 0:60d829a0353a 3036 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
tushki7 0:60d829a0353a 3037 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
tushki7 0:60d829a0353a 3038 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
tushki7 0:60d829a0353a 3039
tushki7 0:60d829a0353a 3040 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
tushki7 0:60d829a0353a 3041 /*!< STAT_TX[1:0] STATus for TX transfer */
tushki7 0:60d829a0353a 3042 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
tushki7 0:60d829a0353a 3043 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
tushki7 0:60d829a0353a 3044 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
tushki7 0:60d829a0353a 3045 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
tushki7 0:60d829a0353a 3046 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
tushki7 0:60d829a0353a 3047 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
tushki7 0:60d829a0353a 3048 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
tushki7 0:60d829a0353a 3049 /*!< STAT_RX[1:0] STATus for RX transfer */
tushki7 0:60d829a0353a 3050 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
tushki7 0:60d829a0353a 3051 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
tushki7 0:60d829a0353a 3052 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
tushki7 0:60d829a0353a 3053 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
tushki7 0:60d829a0353a 3054 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
tushki7 0:60d829a0353a 3055 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
tushki7 0:60d829a0353a 3056 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
tushki7 0:60d829a0353a 3057
tushki7 0:60d829a0353a 3058 /******************************************************************************/
tushki7 0:60d829a0353a 3059 /* */
tushki7 0:60d829a0353a 3060 /* Window WATCHDOG (WWDG) */
tushki7 0:60d829a0353a 3061 /* */
tushki7 0:60d829a0353a 3062 /******************************************************************************/
tushki7 0:60d829a0353a 3063 /******************* Bit definition for WWDG_CR register ********************/
tushki7 0:60d829a0353a 3064 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
tushki7 0:60d829a0353a 3065 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
tushki7 0:60d829a0353a 3066 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
tushki7 0:60d829a0353a 3067 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
tushki7 0:60d829a0353a 3068 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
tushki7 0:60d829a0353a 3069 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
tushki7 0:60d829a0353a 3070 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
tushki7 0:60d829a0353a 3071 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
tushki7 0:60d829a0353a 3072
tushki7 0:60d829a0353a 3073 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
tushki7 0:60d829a0353a 3074
tushki7 0:60d829a0353a 3075 /******************* Bit definition for WWDG_CFR register *******************/
tushki7 0:60d829a0353a 3076 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
tushki7 0:60d829a0353a 3077 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
tushki7 0:60d829a0353a 3078 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
tushki7 0:60d829a0353a 3079 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
tushki7 0:60d829a0353a 3080 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
tushki7 0:60d829a0353a 3081 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
tushki7 0:60d829a0353a 3082 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
tushki7 0:60d829a0353a 3083 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
tushki7 0:60d829a0353a 3084
tushki7 0:60d829a0353a 3085 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
tushki7 0:60d829a0353a 3086 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
tushki7 0:60d829a0353a 3087 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
tushki7 0:60d829a0353a 3088
tushki7 0:60d829a0353a 3089 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
tushki7 0:60d829a0353a 3090
tushki7 0:60d829a0353a 3091 /******************* Bit definition for WWDG_SR register ********************/
tushki7 0:60d829a0353a 3092 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
tushki7 0:60d829a0353a 3093
tushki7 0:60d829a0353a 3094 /**
tushki7 0:60d829a0353a 3095 * @}
tushki7 0:60d829a0353a 3096 */
tushki7 0:60d829a0353a 3097
tushki7 0:60d829a0353a 3098 /**
tushki7 0:60d829a0353a 3099 * @}
tushki7 0:60d829a0353a 3100 */
tushki7 0:60d829a0353a 3101
tushki7 0:60d829a0353a 3102
tushki7 0:60d829a0353a 3103 /** @addtogroup Exported_macro
tushki7 0:60d829a0353a 3104 * @{
tushki7 0:60d829a0353a 3105 */
tushki7 0:60d829a0353a 3106
tushki7 0:60d829a0353a 3107 /****************************** ADC Instances *********************************/
tushki7 0:60d829a0353a 3108 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
tushki7 0:60d829a0353a 3109
tushki7 0:60d829a0353a 3110 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
tushki7 0:60d829a0353a 3111
tushki7 0:60d829a0353a 3112 /****************************** CRC Instances *********************************/
tushki7 0:60d829a0353a 3113 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
tushki7 0:60d829a0353a 3114
tushki7 0:60d829a0353a 3115 /******************************* DMA Instances ******************************/
tushki7 0:60d829a0353a 3116 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
tushki7 0:60d829a0353a 3117 ((INSTANCE) == DMA1_Channel2) || \
tushki7 0:60d829a0353a 3118 ((INSTANCE) == DMA1_Channel3) || \
tushki7 0:60d829a0353a 3119 ((INSTANCE) == DMA1_Channel4) || \
tushki7 0:60d829a0353a 3120 ((INSTANCE) == DMA1_Channel5))
tushki7 0:60d829a0353a 3121
tushki7 0:60d829a0353a 3122 /****************************** GPIO Instances ********************************/
tushki7 0:60d829a0353a 3123 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
tushki7 0:60d829a0353a 3124 ((INSTANCE) == GPIOB) || \
tushki7 0:60d829a0353a 3125 ((INSTANCE) == GPIOC) || \
tushki7 0:60d829a0353a 3126 ((INSTANCE) == GPIOD) || \
tushki7 0:60d829a0353a 3127 ((INSTANCE) == GPIOF))
tushki7 0:60d829a0353a 3128
tushki7 0:60d829a0353a 3129 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
tushki7 0:60d829a0353a 3130 ((INSTANCE) == GPIOB) || \
tushki7 0:60d829a0353a 3131 ((INSTANCE) == GPIOC) || \
tushki7 0:60d829a0353a 3132 ((INSTANCE) == GPIOD) || \
tushki7 0:60d829a0353a 3133 ((INSTANCE) == GPIOF))
tushki7 0:60d829a0353a 3134
tushki7 0:60d829a0353a 3135 /****************************** GPIO Lock Instances ****************************/
tushki7 0:60d829a0353a 3136 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
tushki7 0:60d829a0353a 3137 ((INSTANCE) == GPIOB))
tushki7 0:60d829a0353a 3138
tushki7 0:60d829a0353a 3139 /****************************** I2C Instances *********************************/
tushki7 0:60d829a0353a 3140 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
tushki7 0:60d829a0353a 3141 ((INSTANCE) == I2C2))
tushki7 0:60d829a0353a 3142
tushki7 0:60d829a0353a 3143 /****************************** IWDG Instances ********************************/
tushki7 0:60d829a0353a 3144 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
tushki7 0:60d829a0353a 3145
tushki7 0:60d829a0353a 3146 /****************************** RTC Instances *********************************/
tushki7 0:60d829a0353a 3147 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
tushki7 0:60d829a0353a 3148
tushki7 0:60d829a0353a 3149 /****************************** SMBUS Instances *********************************/
tushki7 0:60d829a0353a 3150 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
tushki7 0:60d829a0353a 3151
tushki7 0:60d829a0353a 3152 /****************************** SPI Instances *********************************/
tushki7 0:60d829a0353a 3153 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
tushki7 0:60d829a0353a 3154 ((INSTANCE) == SPI2))
tushki7 0:60d829a0353a 3155
tushki7 0:60d829a0353a 3156 /****************************** TIM Instances *********************************/
tushki7 0:60d829a0353a 3157 #define IS_TIM_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3158 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3159 ((INSTANCE) == TIM3) || \
tushki7 0:60d829a0353a 3160 ((INSTANCE) == TIM6) || \
tushki7 0:60d829a0353a 3161 ((INSTANCE) == TIM7) || \
tushki7 0:60d829a0353a 3162 ((INSTANCE) == TIM14) || \
tushki7 0:60d829a0353a 3163 ((INSTANCE) == TIM15) || \
tushki7 0:60d829a0353a 3164 ((INSTANCE) == TIM16) || \
tushki7 0:60d829a0353a 3165 ((INSTANCE) == TIM17))
tushki7 0:60d829a0353a 3166
tushki7 0:60d829a0353a 3167 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3168 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3169 ((INSTANCE) == TIM3) || \
tushki7 0:60d829a0353a 3170 ((INSTANCE) == TIM14) || \
tushki7 0:60d829a0353a 3171 ((INSTANCE) == TIM15) || \
tushki7 0:60d829a0353a 3172 ((INSTANCE) == TIM16) || \
tushki7 0:60d829a0353a 3173 ((INSTANCE) == TIM17))
tushki7 0:60d829a0353a 3174
tushki7 0:60d829a0353a 3175 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3176 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3177 ((INSTANCE) == TIM3) || \
tushki7 0:60d829a0353a 3178 ((INSTANCE) == TIM15))
tushki7 0:60d829a0353a 3179
tushki7 0:60d829a0353a 3180 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3181 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3182 ((INSTANCE) == TIM3))
tushki7 0:60d829a0353a 3183
tushki7 0:60d829a0353a 3184 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3185 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3186 ((INSTANCE) == TIM3))
tushki7 0:60d829a0353a 3187
tushki7 0:60d829a0353a 3188 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3189 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3190 ((INSTANCE) == TIM3))
tushki7 0:60d829a0353a 3191
tushki7 0:60d829a0353a 3192 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3193 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3194 ((INSTANCE) == TIM3))
tushki7 0:60d829a0353a 3195
tushki7 0:60d829a0353a 3196 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3197 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3198 ((INSTANCE) == TIM3) || \
tushki7 0:60d829a0353a 3199 ((INSTANCE) == TIM15))
tushki7 0:60d829a0353a 3200
tushki7 0:60d829a0353a 3201 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3202 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3203 ((INSTANCE) == TIM3) || \
tushki7 0:60d829a0353a 3204 ((INSTANCE) == TIM15))
tushki7 0:60d829a0353a 3205
tushki7 0:60d829a0353a 3206 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3207 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3208 ((INSTANCE) == TIM3))
tushki7 0:60d829a0353a 3209
tushki7 0:60d829a0353a 3210 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3211 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3212 ((INSTANCE) == TIM3))
tushki7 0:60d829a0353a 3213
tushki7 0:60d829a0353a 3214 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3215 (((INSTANCE) == TIM1))
tushki7 0:60d829a0353a 3216
tushki7 0:60d829a0353a 3217 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3218 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3219 ((INSTANCE) == TIM3))
tushki7 0:60d829a0353a 3220
tushki7 0:60d829a0353a 3221 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3222 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3223 ((INSTANCE) == TIM3) || \
tushki7 0:60d829a0353a 3224 ((INSTANCE) == TIM6) || \
tushki7 0:60d829a0353a 3225 ((INSTANCE) == TIM7) || \
tushki7 0:60d829a0353a 3226 ((INSTANCE) == TIM15))
tushki7 0:60d829a0353a 3227
tushki7 0:60d829a0353a 3228 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3229 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3230 ((INSTANCE) == TIM3) || \
tushki7 0:60d829a0353a 3231 ((INSTANCE) == TIM15))
tushki7 0:60d829a0353a 3232
tushki7 0:60d829a0353a 3233 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(0)
tushki7 0:60d829a0353a 3234
tushki7 0:60d829a0353a 3235 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3236 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3237 ((INSTANCE) == TIM3) || \
tushki7 0:60d829a0353a 3238 ((INSTANCE) == TIM15) || \
tushki7 0:60d829a0353a 3239 ((INSTANCE) == TIM16) || \
tushki7 0:60d829a0353a 3240 ((INSTANCE) == TIM17))
tushki7 0:60d829a0353a 3241
tushki7 0:60d829a0353a 3242 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3243 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3244 ((INSTANCE) == TIM15) || \
tushki7 0:60d829a0353a 3245 ((INSTANCE) == TIM16) || \
tushki7 0:60d829a0353a 3246 ((INSTANCE) == TIM17))
tushki7 0:60d829a0353a 3247
tushki7 0:60d829a0353a 3248 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
tushki7 0:60d829a0353a 3249 ((((INSTANCE) == TIM1) && \
tushki7 0:60d829a0353a 3250 (((CHANNEL) == TIM_CHANNEL_1) || \
tushki7 0:60d829a0353a 3251 ((CHANNEL) == TIM_CHANNEL_2) || \
tushki7 0:60d829a0353a 3252 ((CHANNEL) == TIM_CHANNEL_3) || \
tushki7 0:60d829a0353a 3253 ((CHANNEL) == TIM_CHANNEL_4))) \
tushki7 0:60d829a0353a 3254 || \
tushki7 0:60d829a0353a 3255 (((INSTANCE) == TIM3) && \
tushki7 0:60d829a0353a 3256 (((CHANNEL) == TIM_CHANNEL_1) || \
tushki7 0:60d829a0353a 3257 ((CHANNEL) == TIM_CHANNEL_2) || \
tushki7 0:60d829a0353a 3258 ((CHANNEL) == TIM_CHANNEL_3) || \
tushki7 0:60d829a0353a 3259 ((CHANNEL) == TIM_CHANNEL_4))) \
tushki7 0:60d829a0353a 3260 || \
tushki7 0:60d829a0353a 3261 (((INSTANCE) == TIM14) && \
tushki7 0:60d829a0353a 3262 (((CHANNEL) == TIM_CHANNEL_1))) \
tushki7 0:60d829a0353a 3263 || \
tushki7 0:60d829a0353a 3264 (((INSTANCE) == TIM15) && \
tushki7 0:60d829a0353a 3265 (((CHANNEL) == TIM_CHANNEL_1) || \
tushki7 0:60d829a0353a 3266 ((CHANNEL) == TIM_CHANNEL_2))) \
tushki7 0:60d829a0353a 3267 || \
tushki7 0:60d829a0353a 3268 (((INSTANCE) == TIM16) && \
tushki7 0:60d829a0353a 3269 (((CHANNEL) == TIM_CHANNEL_1))) \
tushki7 0:60d829a0353a 3270 || \
tushki7 0:60d829a0353a 3271 (((INSTANCE) == TIM17) && \
tushki7 0:60d829a0353a 3272 (((CHANNEL) == TIM_CHANNEL_1))))
tushki7 0:60d829a0353a 3273
tushki7 0:60d829a0353a 3274 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
tushki7 0:60d829a0353a 3275 ((((INSTANCE) == TIM1) && \
tushki7 0:60d829a0353a 3276 (((CHANNEL) == TIM_CHANNEL_1) || \
tushki7 0:60d829a0353a 3277 ((CHANNEL) == TIM_CHANNEL_2) || \
tushki7 0:60d829a0353a 3278 ((CHANNEL) == TIM_CHANNEL_3))) \
tushki7 0:60d829a0353a 3279 || \
tushki7 0:60d829a0353a 3280 (((INSTANCE) == TIM15) && \
tushki7 0:60d829a0353a 3281 ((CHANNEL) == TIM_CHANNEL_1)) \
tushki7 0:60d829a0353a 3282 || \
tushki7 0:60d829a0353a 3283 (((INSTANCE) == TIM16) && \
tushki7 0:60d829a0353a 3284 ((CHANNEL) == TIM_CHANNEL_1)) \
tushki7 0:60d829a0353a 3285 || \
tushki7 0:60d829a0353a 3286 (((INSTANCE) == TIM17) && \
tushki7 0:60d829a0353a 3287 ((CHANNEL) == TIM_CHANNEL_1)))
tushki7 0:60d829a0353a 3288
tushki7 0:60d829a0353a 3289 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3290 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3291 ((INSTANCE) == TIM3))
tushki7 0:60d829a0353a 3292
tushki7 0:60d829a0353a 3293 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3294 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3295 ((INSTANCE) == TIM15) || \
tushki7 0:60d829a0353a 3296 ((INSTANCE) == TIM16) || \
tushki7 0:60d829a0353a 3297 ((INSTANCE) == TIM17))
tushki7 0:60d829a0353a 3298
tushki7 0:60d829a0353a 3299 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3300 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3301 ((INSTANCE) == TIM3) || \
tushki7 0:60d829a0353a 3302 ((INSTANCE) == TIM14) || \
tushki7 0:60d829a0353a 3303 ((INSTANCE) == TIM15) || \
tushki7 0:60d829a0353a 3304 ((INSTANCE) == TIM16) || \
tushki7 0:60d829a0353a 3305 ((INSTANCE) == TIM17))
tushki7 0:60d829a0353a 3306
tushki7 0:60d829a0353a 3307 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3308 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3309 ((INSTANCE) == TIM3) || \
tushki7 0:60d829a0353a 3310 ((INSTANCE) == TIM6) || \
tushki7 0:60d829a0353a 3311 ((INSTANCE) == TIM7) || \
tushki7 0:60d829a0353a 3312 ((INSTANCE) == TIM15) || \
tushki7 0:60d829a0353a 3313 ((INSTANCE) == TIM16) || \
tushki7 0:60d829a0353a 3314 ((INSTANCE) == TIM17))
tushki7 0:60d829a0353a 3315
tushki7 0:60d829a0353a 3316 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3317 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3318 ((INSTANCE) == TIM3) || \
tushki7 0:60d829a0353a 3319 ((INSTANCE) == TIM15) || \
tushki7 0:60d829a0353a 3320 ((INSTANCE) == TIM16) || \
tushki7 0:60d829a0353a 3321 ((INSTANCE) == TIM17))
tushki7 0:60d829a0353a 3322
tushki7 0:60d829a0353a 3323 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3324 (((INSTANCE) == TIM1) || \
tushki7 0:60d829a0353a 3325 ((INSTANCE) == TIM15) || \
tushki7 0:60d829a0353a 3326 ((INSTANCE) == TIM16) || \
tushki7 0:60d829a0353a 3327 ((INSTANCE) == TIM17))
tushki7 0:60d829a0353a 3328
tushki7 0:60d829a0353a 3329 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
tushki7 0:60d829a0353a 3330 ((INSTANCE) == TIM14)
tushki7 0:60d829a0353a 3331
tushki7 0:60d829a0353a 3332 /******************** USART Instances : Synchronous mode **********************/
tushki7 0:60d829a0353a 3333 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
tushki7 0:60d829a0353a 3334 ((INSTANCE) == USART2) || \
tushki7 0:60d829a0353a 3335 ((INSTANCE) == USART3) || \
tushki7 0:60d829a0353a 3336 ((INSTANCE) == USART4))
tushki7 0:60d829a0353a 3337
tushki7 0:60d829a0353a 3338 /******************** USART Instances : auto Baud rate detection **************/
tushki7 0:60d829a0353a 3339 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
tushki7 0:60d829a0353a 3340 ((INSTANCE) == USART2))
tushki7 0:60d829a0353a 3341
tushki7 0:60d829a0353a 3342 /******************** UART Instances : Asynchronous mode **********************/
tushki7 0:60d829a0353a 3343 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
tushki7 0:60d829a0353a 3344 ((INSTANCE) == USART2) || \
tushki7 0:60d829a0353a 3345 ((INSTANCE) == USART3) || \
tushki7 0:60d829a0353a 3346 ((INSTANCE) == USART4))
tushki7 0:60d829a0353a 3347
tushki7 0:60d829a0353a 3348 /******************** UART Instances : Half-Duplex mode **********************/
tushki7 0:60d829a0353a 3349 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
tushki7 0:60d829a0353a 3350 ((INSTANCE) == USART2) || \
tushki7 0:60d829a0353a 3351 ((INSTANCE) == USART3) || \
tushki7 0:60d829a0353a 3352 ((INSTANCE) == USART4))
tushki7 0:60d829a0353a 3353
tushki7 0:60d829a0353a 3354 /****************** UART Instances : Hardware Flow control ********************/
tushki7 0:60d829a0353a 3355 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
tushki7 0:60d829a0353a 3356 ((INSTANCE) == USART2) || \
tushki7 0:60d829a0353a 3357 ((INSTANCE) == USART3) || \
tushki7 0:60d829a0353a 3358 ((INSTANCE) == USART4))
tushki7 0:60d829a0353a 3359
tushki7 0:60d829a0353a 3360 /****************** UART Instances : Auto Baud Rate detection ********************/
tushki7 0:60d829a0353a 3361 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
tushki7 0:60d829a0353a 3362 ((INSTANCE) == USART2))
tushki7 0:60d829a0353a 3363
tushki7 0:60d829a0353a 3364
tushki7 0:60d829a0353a 3365 /****************************** USB Instances ********************************/
tushki7 0:60d829a0353a 3366 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
tushki7 0:60d829a0353a 3367
tushki7 0:60d829a0353a 3368 /****************************** WWDG Instances ********************************/
tushki7 0:60d829a0353a 3369 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
tushki7 0:60d829a0353a 3370
tushki7 0:60d829a0353a 3371 /**
tushki7 0:60d829a0353a 3372 * @}
tushki7 0:60d829a0353a 3373 */
tushki7 0:60d829a0353a 3374
tushki7 0:60d829a0353a 3375
tushki7 0:60d829a0353a 3376 /******************************************************************************/
tushki7 0:60d829a0353a 3377 /* For a painless codes migration between the STM32F0xx device product */
tushki7 0:60d829a0353a 3378 /* lines, the aliases defined below are put in place to overcome the */
tushki7 0:60d829a0353a 3379 /* differences in the interrupt handlers and IRQn definitions. */
tushki7 0:60d829a0353a 3380 /* No need to update developed interrupt code when moving across */
tushki7 0:60d829a0353a 3381 /* product lines within the same STM32F0 Family */
tushki7 0:60d829a0353a 3382 /******************************************************************************/
tushki7 0:60d829a0353a 3383
tushki7 0:60d829a0353a 3384 /* Aliases for __IRQn */
tushki7 0:60d829a0353a 3385 #define RCC_CRS_IRQn RCC_IRQn
tushki7 0:60d829a0353a 3386 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
tushki7 0:60d829a0353a 3387 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
tushki7 0:60d829a0353a 3388 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
tushki7 0:60d829a0353a 3389 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
tushki7 0:60d829a0353a 3390 #define ADC1_COMP_IRQn ADC1_IRQn
tushki7 0:60d829a0353a 3391 #define TIM6_DAC_IRQn TIM6_IRQn
tushki7 0:60d829a0353a 3392 #define USART3_8_IRQn USART3_4_IRQn
tushki7 0:60d829a0353a 3393 #define USART3_6_IRQn USART3_4_IRQn
tushki7 0:60d829a0353a 3394
tushki7 0:60d829a0353a 3395 /* Aliases for __IRQHandler */
tushki7 0:60d829a0353a 3396 #define RCC_CRS_IRQHandler RCC_IRQHandler
tushki7 0:60d829a0353a 3397 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
tushki7 0:60d829a0353a 3398 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
tushki7 0:60d829a0353a 3399 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
tushki7 0:60d829a0353a 3400 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
tushki7 0:60d829a0353a 3401 #define ADC1_COMP_IRQHandler ADC1_IRQHandler
tushki7 0:60d829a0353a 3402 #define TIM6_DAC_IRQHandler TIM6_IRQHandler
tushki7 0:60d829a0353a 3403 #define USART3_8_IRQHandler USART3_4_IRQHandler
tushki7 0:60d829a0353a 3404 #define USART3_6_IRQHandler USART3_4_IRQHandler
tushki7 0:60d829a0353a 3405
tushki7 0:60d829a0353a 3406 #ifdef __cplusplus
tushki7 0:60d829a0353a 3407 }
tushki7 0:60d829a0353a 3408 #endif /* __cplusplus */
tushki7 0:60d829a0353a 3409
tushki7 0:60d829a0353a 3410 #endif /* __STM32F070xB_H */
tushki7 0:60d829a0353a 3411
tushki7 0:60d829a0353a 3412 /**
tushki7 0:60d829a0353a 3413 * @}
tushki7 0:60d829a0353a 3414 */
tushki7 0:60d829a0353a 3415
tushki7 0:60d829a0353a 3416 /**
tushki7 0:60d829a0353a 3417 * @}
tushki7 0:60d829a0353a 3418 */
tushki7 0:60d829a0353a 3419
tushki7 0:60d829a0353a 3420 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/