FRDM_K64F_LCD - A simple 128x32 graphical LCD program to quicksta…

Users » tushki7 » Code » FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies: C12832

mbed/TARGET_MTS_MDOT_F411RE/stm32f4xx_ll_fmc.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:: tushki7
Date:: Sun Apr 12 15:45:52 2015 +0000
Revision:: 1:eb68c94a8ee5
Parent:: 0:60d829a0353a

A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

User	Revision	Line number	New contents of line
tushki7	0:60d829a0353a	1	/**
tushki7	0:60d829a0353a	2	******************************************************************************
tushki7	0:60d829a0353a	3	* @file stm32f4xx_ll_fmc.h
tushki7	0:60d829a0353a	4	* @author MCD Application Team
tushki7	0:60d829a0353a	5	* @version V1.1.0
tushki7	0:60d829a0353a	6	* @date 19-June-2014
tushki7	0:60d829a0353a	7	* @brief Header file of FMC HAL module.
tushki7	0:60d829a0353a	8	******************************************************************************
tushki7	0:60d829a0353a	9	* @attention
tushki7	0:60d829a0353a	10	*
tushki7	0:60d829a0353a	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
tushki7	0:60d829a0353a	12	*
tushki7	0:60d829a0353a	13	* Redistribution and use in source and binary forms, with or without modification,
tushki7	0:60d829a0353a	14	* are permitted provided that the following conditions are met:
tushki7	0:60d829a0353a	15	* 1. Redistributions of source code must retain the above copyright notice,
tushki7	0:60d829a0353a	16	* this list of conditions and the following disclaimer.
tushki7	0:60d829a0353a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
tushki7	0:60d829a0353a	18	* this list of conditions and the following disclaimer in the documentation
tushki7	0:60d829a0353a	19	* and/or other materials provided with the distribution.
tushki7	0:60d829a0353a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
tushki7	0:60d829a0353a	21	* may be used to endorse or promote products derived from this software
tushki7	0:60d829a0353a	22	* without specific prior written permission.
tushki7	0:60d829a0353a	23	*
tushki7	0:60d829a0353a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
tushki7	0:60d829a0353a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
tushki7	0:60d829a0353a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
tushki7	0:60d829a0353a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
tushki7	0:60d829a0353a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
tushki7	0:60d829a0353a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
tushki7	0:60d829a0353a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
tushki7	0:60d829a0353a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
tushki7	0:60d829a0353a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
tushki7	0:60d829a0353a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
tushki7	0:60d829a0353a	34	*
tushki7	0:60d829a0353a	35	******************************************************************************
tushki7	0:60d829a0353a	36	*/
tushki7	0:60d829a0353a	37
tushki7	0:60d829a0353a	38	/* Define to prevent recursive inclusion -------------------------------------*/
tushki7	0:60d829a0353a	39	#ifndef __STM32F4xx_LL_FMC_H
tushki7	0:60d829a0353a	40	#define __STM32F4xx_LL_FMC_H
tushki7	0:60d829a0353a	41
tushki7	0:60d829a0353a	42	#ifdef __cplusplus
tushki7	0:60d829a0353a	43	extern "C" {
tushki7	0:60d829a0353a	44	#endif
tushki7	0:60d829a0353a	45
tushki7	0:60d829a0353a	46	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
tushki7	0:60d829a0353a	47
tushki7	0:60d829a0353a	48	/* Includes ------------------------------------------------------------------*/
tushki7	0:60d829a0353a	49	#include "stm32f4xx_hal_def.h"
tushki7	0:60d829a0353a	50
tushki7	0:60d829a0353a	51	/** @addtogroup STM32F4xx_HAL_Driver
tushki7	0:60d829a0353a	52	* @{
tushki7	0:60d829a0353a	53	*/
tushki7	0:60d829a0353a	54
tushki7	0:60d829a0353a	55	/** @addtogroup FMC
tushki7	0:60d829a0353a	56	* @{
tushki7	0:60d829a0353a	57	*/
tushki7	0:60d829a0353a	58
tushki7	0:60d829a0353a	59	/* Exported typedef ----------------------------------------------------------*/
tushki7	0:60d829a0353a	60	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
tushki7	0:60d829a0353a	61	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
tushki7	0:60d829a0353a	62	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
tushki7	0:60d829a0353a	63	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
tushki7	0:60d829a0353a	64	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
tushki7	0:60d829a0353a	65
tushki7	0:60d829a0353a	66	#define FMC_NORSRAM_DEVICE FMC_Bank1
tushki7	0:60d829a0353a	67	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
tushki7	0:60d829a0353a	68	#define FMC_NAND_DEVICE FMC_Bank2_3
tushki7	0:60d829a0353a	69	#define FMC_PCCARD_DEVICE FMC_Bank4
tushki7	0:60d829a0353a	70	#define FMC_SDRAM_DEVICE FMC_Bank5_6
tushki7	0:60d829a0353a	71
tushki7	0:60d829a0353a	72	/**
tushki7	0:60d829a0353a	73	* @brief FMC_NORSRAM Configuration Structure definition
tushki7	0:60d829a0353a	74	*/
tushki7	0:60d829a0353a	75	typedef struct
tushki7	0:60d829a0353a	76	{
tushki7	0:60d829a0353a	77	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
tushki7	0:60d829a0353a	78	This parameter can be a value of @ref FMC_NORSRAM_Bank */
tushki7	0:60d829a0353a	79
tushki7	0:60d829a0353a	80	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
tushki7	0:60d829a0353a	81	multiplexed on the data bus or not.
tushki7	0:60d829a0353a	82	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
tushki7	0:60d829a0353a	83
tushki7	0:60d829a0353a	84	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
tushki7	0:60d829a0353a	85	the corresponding memory device.
tushki7	0:60d829a0353a	86	This parameter can be a value of @ref FMC_Memory_Type */
tushki7	0:60d829a0353a	87
tushki7	0:60d829a0353a	88	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
tushki7	0:60d829a0353a	89	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
tushki7	0:60d829a0353a	90
tushki7	0:60d829a0353a	91	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
tushki7	0:60d829a0353a	92	valid only with synchronous burst Flash memories.
tushki7	0:60d829a0353a	93	This parameter can be a value of @ref FMC_Burst_Access_Mode */
tushki7	0:60d829a0353a	94
tushki7	0:60d829a0353a	95	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
tushki7	0:60d829a0353a	96	the Flash memory in burst mode.
tushki7	0:60d829a0353a	97	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
tushki7	0:60d829a0353a	98
tushki7	0:60d829a0353a	99	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
tushki7	0:60d829a0353a	100	memory, valid only when accessing Flash memories in burst mode.
tushki7	0:60d829a0353a	101	This parameter can be a value of @ref FMC_Wrap_Mode */
tushki7	0:60d829a0353a	102
tushki7	0:60d829a0353a	103	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
tushki7	0:60d829a0353a	104	clock cycle before the wait state or during the wait state,
tushki7	0:60d829a0353a	105	valid only when accessing memories in burst mode.
tushki7	0:60d829a0353a	106	This parameter can be a value of @ref FMC_Wait_Timing */
tushki7	0:60d829a0353a	107
tushki7	0:60d829a0353a	108	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
tushki7	0:60d829a0353a	109	This parameter can be a value of @ref FMC_Write_Operation */
tushki7	0:60d829a0353a	110
tushki7	0:60d829a0353a	111	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
tushki7	0:60d829a0353a	112	signal, valid for Flash memory access in burst mode.
tushki7	0:60d829a0353a	113	This parameter can be a value of @ref FMC_Wait_Signal */
tushki7	0:60d829a0353a	114
tushki7	0:60d829a0353a	115	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
tushki7	0:60d829a0353a	116	This parameter can be a value of @ref FMC_Extended_Mode */
tushki7	0:60d829a0353a	117
tushki7	0:60d829a0353a	118	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
tushki7	0:60d829a0353a	119	valid only with asynchronous Flash memories.
tushki7	0:60d829a0353a	120	This parameter can be a value of @ref FMC_AsynchronousWait */
tushki7	0:60d829a0353a	121
tushki7	0:60d829a0353a	122	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
tushki7	0:60d829a0353a	123	This parameter can be a value of @ref FMC_Write_Burst */
tushki7	0:60d829a0353a	124
tushki7	0:60d829a0353a	125	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
tushki7	0:60d829a0353a	126	This parameter is only enabled through the FMC_BCR1 register, and don't care
tushki7	0:60d829a0353a	127	through FMC_BCR2..4 registers.
tushki7	0:60d829a0353a	128	This parameter can be a value of @ref FMC_Continous_Clock */
tushki7	0:60d829a0353a	129
tushki7	0:60d829a0353a	130	}FMC_NORSRAM_InitTypeDef;
tushki7	0:60d829a0353a	131
tushki7	0:60d829a0353a	132	/**
tushki7	0:60d829a0353a	133	* @brief FMC_NORSRAM Timing parameters structure definition
tushki7	0:60d829a0353a	134	*/
tushki7	0:60d829a0353a	135	typedef struct
tushki7	0:60d829a0353a	136	{
tushki7	0:60d829a0353a	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
tushki7	0:60d829a0353a	138	the duration of the address setup time.
tushki7	0:60d829a0353a	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
tushki7	0:60d829a0353a	140	@note This parameter is not used with synchronous NOR Flash memories. */
tushki7	0:60d829a0353a	141
tushki7	0:60d829a0353a	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
tushki7	0:60d829a0353a	143	the duration of the address hold time.
tushki7	0:60d829a0353a	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
tushki7	0:60d829a0353a	145	@note This parameter is not used with synchronous NOR Flash memories. */
tushki7	0:60d829a0353a	146
tushki7	0:60d829a0353a	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
tushki7	0:60d829a0353a	148	the duration of the data setup time.
tushki7	0:60d829a0353a	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
tushki7	0:60d829a0353a	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
tushki7	0:60d829a0353a	151	NOR Flash memories. */
tushki7	0:60d829a0353a	152
tushki7	0:60d829a0353a	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
tushki7	0:60d829a0353a	154	the duration of the bus turnaround.
tushki7	0:60d829a0353a	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
tushki7	0:60d829a0353a	156	@note This parameter is only used for multiplexed NOR Flash memories. */
tushki7	0:60d829a0353a	157
tushki7	0:60d829a0353a	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
tushki7	0:60d829a0353a	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
tushki7	0:60d829a0353a	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
tushki7	0:60d829a0353a	161	accesses. */
tushki7	0:60d829a0353a	162
tushki7	0:60d829a0353a	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
tushki7	0:60d829a0353a	164	to the memory before getting the first data.
tushki7	0:60d829a0353a	165	The parameter value depends on the memory type as shown below:
tushki7	0:60d829a0353a	166	- It must be set to 0 in case of a CRAM
tushki7	0:60d829a0353a	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
tushki7	0:60d829a0353a	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
tushki7	0:60d829a0353a	169	with synchronous burst mode enable */
tushki7	0:60d829a0353a	170
tushki7	0:60d829a0353a	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
tushki7	0:60d829a0353a	172	This parameter can be a value of @ref FMC_Access_Mode */
tushki7	0:60d829a0353a	173	}FMC_NORSRAM_TimingTypeDef;
tushki7	0:60d829a0353a	174
tushki7	0:60d829a0353a	175	/**
tushki7	0:60d829a0353a	176	* @brief FMC_NAND Configuration Structure definition
tushki7	0:60d829a0353a	177	*/
tushki7	0:60d829a0353a	178	typedef struct
tushki7	0:60d829a0353a	179	{
tushki7	0:60d829a0353a	180	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
tushki7	0:60d829a0353a	181	This parameter can be a value of @ref FMC_NAND_Bank */
tushki7	0:60d829a0353a	182
tushki7	0:60d829a0353a	183	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
tushki7	0:60d829a0353a	184	This parameter can be any value of @ref FMC_Wait_feature */
tushki7	0:60d829a0353a	185
tushki7	0:60d829a0353a	186	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
tushki7	0:60d829a0353a	187	This parameter can be any value of @ref FMC_NAND_Data_Width */
tushki7	0:60d829a0353a	188
tushki7	0:60d829a0353a	189	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
tushki7	0:60d829a0353a	190	This parameter can be any value of @ref FMC_ECC */
tushki7	0:60d829a0353a	191
tushki7	0:60d829a0353a	192	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
tushki7	0:60d829a0353a	193	This parameter can be any value of @ref FMC_ECC_Page_Size */
tushki7	0:60d829a0353a	194
tushki7	0:60d829a0353a	195	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
tushki7	0:60d829a0353a	196	delay between CLE low and RE low.
tushki7	0:60d829a0353a	197	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
tushki7	0:60d829a0353a	198
tushki7	0:60d829a0353a	199	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
tushki7	0:60d829a0353a	200	delay between ALE low and RE low.
tushki7	0:60d829a0353a	201	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
tushki7	0:60d829a0353a	202	}FMC_NAND_InitTypeDef;
tushki7	0:60d829a0353a	203
tushki7	0:60d829a0353a	204	/**
tushki7	0:60d829a0353a	205	* @brief FMC_NAND_PCCARD Timing parameters structure definition
tushki7	0:60d829a0353a	206	*/
tushki7	0:60d829a0353a	207	typedef struct
tushki7	0:60d829a0353a	208	{
tushki7	0:60d829a0353a	209	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
tushki7	0:60d829a0353a	210	the command assertion for NAND-Flash read or write access
tushki7	0:60d829a0353a	211	to common/Attribute or I/O memory space (depending on
tushki7	0:60d829a0353a	212	the memory space timing to be configured).
tushki7	0:60d829a0353a	213	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
tushki7	0:60d829a0353a	214
tushki7	0:60d829a0353a	215	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
tushki7	0:60d829a0353a	216	command for NAND-Flash read or write access to
tushki7	0:60d829a0353a	217	common/Attribute or I/O memory space (depending on the
tushki7	0:60d829a0353a	218	memory space timing to be configured).
tushki7	0:60d829a0353a	219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
tushki7	0:60d829a0353a	220
tushki7	0:60d829a0353a	221	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
tushki7	0:60d829a0353a	222	(and data for write access) after the command de-assertion
tushki7	0:60d829a0353a	223	for NAND-Flash read or write access to common/Attribute
tushki7	0:60d829a0353a	224	or I/O memory space (depending on the memory space timing
tushki7	0:60d829a0353a	225	to be configured).
tushki7	0:60d829a0353a	226	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
tushki7	0:60d829a0353a	227
tushki7	0:60d829a0353a	228	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
tushki7	0:60d829a0353a	229	data bus is kept in HiZ after the start of a NAND-Flash
tushki7	0:60d829a0353a	230	write access to common/Attribute or I/O memory space (depending
tushki7	0:60d829a0353a	231	on the memory space timing to be configured).
tushki7	0:60d829a0353a	232	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
tushki7	0:60d829a0353a	233	}FMC_NAND_PCC_TimingTypeDef;
tushki7	0:60d829a0353a	234
tushki7	0:60d829a0353a	235	/**
tushki7	0:60d829a0353a	236	* @brief FMC_NAND Configuration Structure definition
tushki7	0:60d829a0353a	237	*/
tushki7	0:60d829a0353a	238	typedef struct
tushki7	0:60d829a0353a	239	{
tushki7	0:60d829a0353a	240	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
tushki7	0:60d829a0353a	241	This parameter can be any value of @ref FMC_Wait_feature */
tushki7	0:60d829a0353a	242
tushki7	0:60d829a0353a	243	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
tushki7	0:60d829a0353a	244	delay between CLE low and RE low.
tushki7	0:60d829a0353a	245	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
tushki7	0:60d829a0353a	246
tushki7	0:60d829a0353a	247	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
tushki7	0:60d829a0353a	248	delay between ALE low and RE low.
tushki7	0:60d829a0353a	249	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
tushki7	0:60d829a0353a	250	}FMC_PCCARD_InitTypeDef;
tushki7	0:60d829a0353a	251
tushki7	0:60d829a0353a	252	/**
tushki7	0:60d829a0353a	253	* @brief FMC_SDRAM Configuration Structure definition
tushki7	0:60d829a0353a	254	*/
tushki7	0:60d829a0353a	255	typedef struct
tushki7	0:60d829a0353a	256	{
tushki7	0:60d829a0353a	257	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
tushki7	0:60d829a0353a	258	This parameter can be a value of @ref FMC_SDRAM_Bank */
tushki7	0:60d829a0353a	259
tushki7	0:60d829a0353a	260	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
tushki7	0:60d829a0353a	261	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
tushki7	0:60d829a0353a	262
tushki7	0:60d829a0353a	263	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
tushki7	0:60d829a0353a	264	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
tushki7	0:60d829a0353a	265
tushki7	0:60d829a0353a	266	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
tushki7	0:60d829a0353a	267	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
tushki7	0:60d829a0353a	268
tushki7	0:60d829a0353a	269	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
tushki7	0:60d829a0353a	270	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
tushki7	0:60d829a0353a	271
tushki7	0:60d829a0353a	272	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
tushki7	0:60d829a0353a	273	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
tushki7	0:60d829a0353a	274
tushki7	0:60d829a0353a	275	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
tushki7	0:60d829a0353a	276	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
tushki7	0:60d829a0353a	277
tushki7	0:60d829a0353a	278	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
tushki7	0:60d829a0353a	279	to disable the clock before changing frequency.
tushki7	0:60d829a0353a	280	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
tushki7	0:60d829a0353a	281
tushki7	0:60d829a0353a	282	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
tushki7	0:60d829a0353a	283	commands during the CAS latency and stores data in the Read FIFO.
tushki7	0:60d829a0353a	284	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
tushki7	0:60d829a0353a	285
tushki7	0:60d829a0353a	286	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
tushki7	0:60d829a0353a	287	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
tushki7	0:60d829a0353a	288	}FMC_SDRAM_InitTypeDef;
tushki7	0:60d829a0353a	289
tushki7	0:60d829a0353a	290	/**
tushki7	0:60d829a0353a	291	* @brief FMC_SDRAM Timing parameters structure definition
tushki7	0:60d829a0353a	292	*/
tushki7	0:60d829a0353a	293	typedef struct
tushki7	0:60d829a0353a	294	{
tushki7	0:60d829a0353a	295	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
tushki7	0:60d829a0353a	296	an active or Refresh command in number of memory clock cycles.
tushki7	0:60d829a0353a	297	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
tushki7	0:60d829a0353a	298
tushki7	0:60d829a0353a	299	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
tushki7	0:60d829a0353a	300	issuing the Activate command in number of memory clock cycles.
tushki7	0:60d829a0353a	301	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
tushki7	0:60d829a0353a	302
tushki7	0:60d829a0353a	303	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
tushki7	0:60d829a0353a	304	cycles.
tushki7	0:60d829a0353a	305	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
tushki7	0:60d829a0353a	306
tushki7	0:60d829a0353a	307	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
tushki7	0:60d829a0353a	308	and the delay between two consecutive Refresh commands in number of
tushki7	0:60d829a0353a	309	memory clock cycles.
tushki7	0:60d829a0353a	310	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
tushki7	0:60d829a0353a	311
tushki7	0:60d829a0353a	312	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
tushki7	0:60d829a0353a	313	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
tushki7	0:60d829a0353a	314
tushki7	0:60d829a0353a	315	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
tushki7	0:60d829a0353a	316	in number of memory clock cycles.
tushki7	0:60d829a0353a	317	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
tushki7	0:60d829a0353a	318
tushki7	0:60d829a0353a	319	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
tushki7	0:60d829a0353a	320	command in number of memory clock cycles.
tushki7	0:60d829a0353a	321	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
tushki7	0:60d829a0353a	322	}FMC_SDRAM_TimingTypeDef;
tushki7	0:60d829a0353a	323
tushki7	0:60d829a0353a	324	/**
tushki7	0:60d829a0353a	325	* @brief SDRAM command parameters structure definition
tushki7	0:60d829a0353a	326	*/
tushki7	0:60d829a0353a	327	typedef struct
tushki7	0:60d829a0353a	328	{
tushki7	0:60d829a0353a	329	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
tushki7	0:60d829a0353a	330	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
tushki7	0:60d829a0353a	331
tushki7	0:60d829a0353a	332	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
tushki7	0:60d829a0353a	333	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
tushki7	0:60d829a0353a	334
tushki7	0:60d829a0353a	335	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
tushki7	0:60d829a0353a	336	in auto refresh mode.
tushki7	0:60d829a0353a	337	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
tushki7	0:60d829a0353a	338	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
tushki7	0:60d829a0353a	339	}FMC_SDRAM_CommandTypeDef;
tushki7	0:60d829a0353a	340
tushki7	0:60d829a0353a	341	/* Exported constants --------------------------------------------------------*/
tushki7	0:60d829a0353a	342
tushki7	0:60d829a0353a	343	/** @defgroup FMC_NOR_SRAM_Controller
tushki7	0:60d829a0353a	344	* @{
tushki7	0:60d829a0353a	345	*/
tushki7	0:60d829a0353a	346
tushki7	0:60d829a0353a	347	/** @defgroup FMC_NORSRAM_Bank
tushki7	0:60d829a0353a	348	* @{
tushki7	0:60d829a0353a	349	*/
tushki7	0:60d829a0353a	350	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	351	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	352	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	353	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
tushki7	0:60d829a0353a	354
tushki7	0:60d829a0353a	355	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
tushki7	0:60d829a0353a	356	((BANK) == FMC_NORSRAM_BANK2) \|\| \
tushki7	0:60d829a0353a	357	((BANK) == FMC_NORSRAM_BANK3) \|\| \
tushki7	0:60d829a0353a	358	((BANK) == FMC_NORSRAM_BANK4))
tushki7	0:60d829a0353a	359	/**
tushki7	0:60d829a0353a	360	* @}
tushki7	0:60d829a0353a	361	*/
tushki7	0:60d829a0353a	362
tushki7	0:60d829a0353a	363	/** @defgroup FMC_Data_Address_Bus_Multiplexing
tushki7	0:60d829a0353a	364	* @{
tushki7	0:60d829a0353a	365	*/
tushki7	0:60d829a0353a	366	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	367	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	368
tushki7	0:60d829a0353a	369	#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
tushki7	0:60d829a0353a	370	((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
tushki7	0:60d829a0353a	371	/**
tushki7	0:60d829a0353a	372	* @}
tushki7	0:60d829a0353a	373	*/
tushki7	0:60d829a0353a	374
tushki7	0:60d829a0353a	375	/** @defgroup FMC_Memory_Type
tushki7	0:60d829a0353a	376	* @{
tushki7	0:60d829a0353a	377	*/
tushki7	0:60d829a0353a	378	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	379	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	380	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	381
tushki7	0:60d829a0353a	382	#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) \|\| \
tushki7	0:60d829a0353a	383	((MEMORY) == FMC_MEMORY_TYPE_PSRAM)\|\| \
tushki7	0:60d829a0353a	384	((MEMORY) == FMC_MEMORY_TYPE_NOR))
tushki7	0:60d829a0353a	385	/**
tushki7	0:60d829a0353a	386	* @}
tushki7	0:60d829a0353a	387	*/
tushki7	0:60d829a0353a	388
tushki7	0:60d829a0353a	389	/** @defgroup FMC_NORSRAM_Data_Width
tushki7	0:60d829a0353a	390	* @{
tushki7	0:60d829a0353a	391	*/
tushki7	0:60d829a0353a	392	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	393	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	394	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	395
tushki7	0:60d829a0353a	396	#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
tushki7	0:60d829a0353a	397	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
tushki7	0:60d829a0353a	398	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
tushki7	0:60d829a0353a	399	/**
tushki7	0:60d829a0353a	400	* @}
tushki7	0:60d829a0353a	401	*/
tushki7	0:60d829a0353a	402
tushki7	0:60d829a0353a	403	/** @defgroup FMC_NORSRAM_Flash_Access
tushki7	0:60d829a0353a	404	* @{
tushki7	0:60d829a0353a	405	*/
tushki7	0:60d829a0353a	406	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	407	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	408	/**
tushki7	0:60d829a0353a	409	* @}
tushki7	0:60d829a0353a	410	*/
tushki7	0:60d829a0353a	411
tushki7	0:60d829a0353a	412	/** @defgroup FMC_Burst_Access_Mode
tushki7	0:60d829a0353a	413	* @{
tushki7	0:60d829a0353a	414	*/
tushki7	0:60d829a0353a	415	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	416	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	417
tushki7	0:60d829a0353a	418	#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
tushki7	0:60d829a0353a	419	((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
tushki7	0:60d829a0353a	420	/**
tushki7	0:60d829a0353a	421	* @}
tushki7	0:60d829a0353a	422	*/
tushki7	0:60d829a0353a	423
tushki7	0:60d829a0353a	424
tushki7	0:60d829a0353a	425	/** @defgroup FMC_Wait_Signal_Polarity
tushki7	0:60d829a0353a	426	* @{
tushki7	0:60d829a0353a	427	*/
tushki7	0:60d829a0353a	428	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	429	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	430
tushki7	0:60d829a0353a	431	#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
tushki7	0:60d829a0353a	432	((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
tushki7	0:60d829a0353a	433	/**
tushki7	0:60d829a0353a	434	* @}
tushki7	0:60d829a0353a	435	*/
tushki7	0:60d829a0353a	436
tushki7	0:60d829a0353a	437	/** @defgroup FMC_Wrap_Mode
tushki7	0:60d829a0353a	438	* @{
tushki7	0:60d829a0353a	439	*/
tushki7	0:60d829a0353a	440	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	441	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
tushki7	0:60d829a0353a	442
tushki7	0:60d829a0353a	443	#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) \|\| \
tushki7	0:60d829a0353a	444	((MODE) == FMC_WRAP_MODE_ENABLE))
tushki7	0:60d829a0353a	445	/**
tushki7	0:60d829a0353a	446	* @}
tushki7	0:60d829a0353a	447	*/
tushki7	0:60d829a0353a	448
tushki7	0:60d829a0353a	449	/** @defgroup FMC_Wait_Timing
tushki7	0:60d829a0353a	450	* @{
tushki7	0:60d829a0353a	451	*/
tushki7	0:60d829a0353a	452	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	453	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	454
tushki7	0:60d829a0353a	455	#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
tushki7	0:60d829a0353a	456	((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
tushki7	0:60d829a0353a	457	/**
tushki7	0:60d829a0353a	458	* @}
tushki7	0:60d829a0353a	459	*/
tushki7	0:60d829a0353a	460
tushki7	0:60d829a0353a	461	/** @defgroup FMC_Write_Operation
tushki7	0:60d829a0353a	462	* @{
tushki7	0:60d829a0353a	463	*/
tushki7	0:60d829a0353a	464	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	465	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	466
tushki7	0:60d829a0353a	467	#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) \|\| \
tushki7	0:60d829a0353a	468	((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
tushki7	0:60d829a0353a	469	/**
tushki7	0:60d829a0353a	470	* @}
tushki7	0:60d829a0353a	471	*/
tushki7	0:60d829a0353a	472
tushki7	0:60d829a0353a	473	/** @defgroup FMC_Wait_Signal
tushki7	0:60d829a0353a	474	* @{
tushki7	0:60d829a0353a	475	*/
tushki7	0:60d829a0353a	476	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	477	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	478
tushki7	0:60d829a0353a	479	#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
tushki7	0:60d829a0353a	480	((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
tushki7	0:60d829a0353a	481	/**
tushki7	0:60d829a0353a	482	* @}
tushki7	0:60d829a0353a	483	*/
tushki7	0:60d829a0353a	484
tushki7	0:60d829a0353a	485	/** @defgroup FMC_Extended_Mode
tushki7	0:60d829a0353a	486	* @{
tushki7	0:60d829a0353a	487	*/
tushki7	0:60d829a0353a	488	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	489	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	490
tushki7	0:60d829a0353a	491	#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) \|\| \
tushki7	0:60d829a0353a	492	((MODE) == FMC_EXTENDED_MODE_ENABLE))
tushki7	0:60d829a0353a	493	/**
tushki7	0:60d829a0353a	494	* @}
tushki7	0:60d829a0353a	495	*/
tushki7	0:60d829a0353a	496
tushki7	0:60d829a0353a	497	/** @defgroup FMC_AsynchronousWait
tushki7	0:60d829a0353a	498	* @{
tushki7	0:60d829a0353a	499	*/
tushki7	0:60d829a0353a	500	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	501	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
tushki7	0:60d829a0353a	502
tushki7	0:60d829a0353a	503	#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
tushki7	0:60d829a0353a	504	((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
tushki7	0:60d829a0353a	505	/**
tushki7	0:60d829a0353a	506	* @}
tushki7	0:60d829a0353a	507	*/
tushki7	0:60d829a0353a	508
tushki7	0:60d829a0353a	509	/** @defgroup FMC_Write_Burst
tushki7	0:60d829a0353a	510	* @{
tushki7	0:60d829a0353a	511	*/
tushki7	0:60d829a0353a	512	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	513	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
tushki7	0:60d829a0353a	514
tushki7	0:60d829a0353a	515	#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) \|\| \
tushki7	0:60d829a0353a	516	((BURST) == FMC_WRITE_BURST_ENABLE))
tushki7	0:60d829a0353a	517	/**
tushki7	0:60d829a0353a	518	* @}
tushki7	0:60d829a0353a	519	*/
tushki7	0:60d829a0353a	520
tushki7	0:60d829a0353a	521	/** @defgroup FMC_Continous_Clock
tushki7	0:60d829a0353a	522	* @{
tushki7	0:60d829a0353a	523	*/
tushki7	0:60d829a0353a	524	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	525	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
tushki7	0:60d829a0353a	526
tushki7	0:60d829a0353a	527	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
tushki7	0:60d829a0353a	528	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
tushki7	0:60d829a0353a	529	/**
tushki7	0:60d829a0353a	530	* @}
tushki7	0:60d829a0353a	531	*/
tushki7	0:60d829a0353a	532
tushki7	0:60d829a0353a	533	/** @defgroup FMC_Address_Setup_Time
tushki7	0:60d829a0353a	534	* @{
tushki7	0:60d829a0353a	535	*/
tushki7	0:60d829a0353a	536	#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
tushki7	0:60d829a0353a	537	/**
tushki7	0:60d829a0353a	538	* @}
tushki7	0:60d829a0353a	539	*/
tushki7	0:60d829a0353a	540
tushki7	0:60d829a0353a	541	/** @defgroup FMC_Address_Hold_Time
tushki7	0:60d829a0353a	542	* @{
tushki7	0:60d829a0353a	543	*/
tushki7	0:60d829a0353a	544	#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
tushki7	0:60d829a0353a	545	/**
tushki7	0:60d829a0353a	546	* @}
tushki7	0:60d829a0353a	547	*/
tushki7	0:60d829a0353a	548
tushki7	0:60d829a0353a	549	/** @defgroup FMC_Data_Setup_Time
tushki7	0:60d829a0353a	550	* @{
tushki7	0:60d829a0353a	551	*/
tushki7	0:60d829a0353a	552	#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
tushki7	0:60d829a0353a	553	/**
tushki7	0:60d829a0353a	554	* @}
tushki7	0:60d829a0353a	555	*/
tushki7	0:60d829a0353a	556
tushki7	0:60d829a0353a	557	/** @defgroup FMC_Bus_Turn_around_Duration
tushki7	0:60d829a0353a	558	* @{
tushki7	0:60d829a0353a	559	*/
tushki7	0:60d829a0353a	560	#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
tushki7	0:60d829a0353a	561	/**
tushki7	0:60d829a0353a	562	* @}
tushki7	0:60d829a0353a	563	*/
tushki7	0:60d829a0353a	564
tushki7	0:60d829a0353a	565	/** @defgroup FMC_CLK_Division
tushki7	0:60d829a0353a	566	* @{
tushki7	0:60d829a0353a	567	*/
tushki7	0:60d829a0353a	568	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
tushki7	0:60d829a0353a	569	/**
tushki7	0:60d829a0353a	570	* @}
tushki7	0:60d829a0353a	571	*/
tushki7	0:60d829a0353a	572
tushki7	0:60d829a0353a	573	/** @defgroup FMC_Data_Latency
tushki7	0:60d829a0353a	574	* @{
tushki7	0:60d829a0353a	575	*/
tushki7	0:60d829a0353a	576	#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
tushki7	0:60d829a0353a	577	/**
tushki7	0:60d829a0353a	578	* @}
tushki7	0:60d829a0353a	579	*/
tushki7	0:60d829a0353a	580
tushki7	0:60d829a0353a	581	/** @defgroup FMC_Access_Mode
tushki7	0:60d829a0353a	582	* @{
tushki7	0:60d829a0353a	583	*/
tushki7	0:60d829a0353a	584	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	585	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
tushki7	0:60d829a0353a	586	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
tushki7	0:60d829a0353a	587	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
tushki7	0:60d829a0353a	588
tushki7	0:60d829a0353a	589	#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) \|\| \
tushki7	0:60d829a0353a	590	((MODE) == FMC_ACCESS_MODE_B) \|\| \
tushki7	0:60d829a0353a	591	((MODE) == FMC_ACCESS_MODE_C) \|\| \
tushki7	0:60d829a0353a	592	((MODE) == FMC_ACCESS_MODE_D))
tushki7	0:60d829a0353a	593	/**
tushki7	0:60d829a0353a	594	* @}
tushki7	0:60d829a0353a	595	*/
tushki7	0:60d829a0353a	596
tushki7	0:60d829a0353a	597	/**
tushki7	0:60d829a0353a	598	* @}
tushki7	0:60d829a0353a	599	*/
tushki7	0:60d829a0353a	600
tushki7	0:60d829a0353a	601	/** @defgroup FMC_NAND_Controller
tushki7	0:60d829a0353a	602	* @{
tushki7	0:60d829a0353a	603	*/
tushki7	0:60d829a0353a	604
tushki7	0:60d829a0353a	605	/** @defgroup FMC_NAND_Bank
tushki7	0:60d829a0353a	606	* @{
tushki7	0:60d829a0353a	607	*/
tushki7	0:60d829a0353a	608	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	609	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	610
tushki7	0:60d829a0353a	611	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
tushki7	0:60d829a0353a	612	((BANK) == FMC_NAND_BANK3))
tushki7	0:60d829a0353a	613	/**
tushki7	0:60d829a0353a	614	* @}
tushki7	0:60d829a0353a	615	*/
tushki7	0:60d829a0353a	616
tushki7	0:60d829a0353a	617	/** @defgroup FMC_Wait_feature
tushki7	0:60d829a0353a	618	* @{
tushki7	0:60d829a0353a	619	*/
tushki7	0:60d829a0353a	620	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	621	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	622
tushki7	0:60d829a0353a	623	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
tushki7	0:60d829a0353a	624	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
tushki7	0:60d829a0353a	625	/**
tushki7	0:60d829a0353a	626	* @}
tushki7	0:60d829a0353a	627	*/
tushki7	0:60d829a0353a	628
tushki7	0:60d829a0353a	629	/** @defgroup FMC_PCR_Memory_Type
tushki7	0:60d829a0353a	630	* @{
tushki7	0:60d829a0353a	631	*/
tushki7	0:60d829a0353a	632	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	633	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	634	/**
tushki7	0:60d829a0353a	635	* @}
tushki7	0:60d829a0353a	636	*/
tushki7	0:60d829a0353a	637
tushki7	0:60d829a0353a	638	/** @defgroup FMC_NAND_Data_Width
tushki7	0:60d829a0353a	639	* @{
tushki7	0:60d829a0353a	640	*/
tushki7	0:60d829a0353a	641	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	642	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	643
tushki7	0:60d829a0353a	644	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
tushki7	0:60d829a0353a	645	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
tushki7	0:60d829a0353a	646	/**
tushki7	0:60d829a0353a	647	* @}
tushki7	0:60d829a0353a	648	*/
tushki7	0:60d829a0353a	649
tushki7	0:60d829a0353a	650	/** @defgroup FMC_ECC
tushki7	0:60d829a0353a	651	* @{
tushki7	0:60d829a0353a	652	*/
tushki7	0:60d829a0353a	653	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	654	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	655
tushki7	0:60d829a0353a	656	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
tushki7	0:60d829a0353a	657	((STATE) == FMC_NAND_ECC_ENABLE))
tushki7	0:60d829a0353a	658	/**
tushki7	0:60d829a0353a	659	* @}
tushki7	0:60d829a0353a	660	*/
tushki7	0:60d829a0353a	661
tushki7	0:60d829a0353a	662	/** @defgroup FMC_ECC_Page_Size
tushki7	0:60d829a0353a	663	* @{
tushki7	0:60d829a0353a	664	*/
tushki7	0:60d829a0353a	665	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	666	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
tushki7	0:60d829a0353a	667	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
tushki7	0:60d829a0353a	668	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
tushki7	0:60d829a0353a	669	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
tushki7	0:60d829a0353a	670	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
tushki7	0:60d829a0353a	671
tushki7	0:60d829a0353a	672	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
tushki7	0:60d829a0353a	673	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
tushki7	0:60d829a0353a	674	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
tushki7	0:60d829a0353a	675	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
tushki7	0:60d829a0353a	676	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
tushki7	0:60d829a0353a	677	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
tushki7	0:60d829a0353a	678	/**
tushki7	0:60d829a0353a	679	* @}
tushki7	0:60d829a0353a	680	*/
tushki7	0:60d829a0353a	681
tushki7	0:60d829a0353a	682	/** @defgroup FMC_TCLR_Setup_Time
tushki7	0:60d829a0353a	683	* @{
tushki7	0:60d829a0353a	684	*/
tushki7	0:60d829a0353a	685	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
tushki7	0:60d829a0353a	686	/**
tushki7	0:60d829a0353a	687	* @}
tushki7	0:60d829a0353a	688	*/
tushki7	0:60d829a0353a	689
tushki7	0:60d829a0353a	690	/** @defgroup FMC_TAR_Setup_Time
tushki7	0:60d829a0353a	691	* @{
tushki7	0:60d829a0353a	692	*/
tushki7	0:60d829a0353a	693	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
tushki7	0:60d829a0353a	694	/**
tushki7	0:60d829a0353a	695	* @}
tushki7	0:60d829a0353a	696	*/
tushki7	0:60d829a0353a	697
tushki7	0:60d829a0353a	698	/** @defgroup FMC_Setup_Time
tushki7	0:60d829a0353a	699	* @{
tushki7	0:60d829a0353a	700	*/
tushki7	0:60d829a0353a	701	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
tushki7	0:60d829a0353a	702	/**
tushki7	0:60d829a0353a	703	* @}
tushki7	0:60d829a0353a	704	*/
tushki7	0:60d829a0353a	705
tushki7	0:60d829a0353a	706	/** @defgroup FMC_Wait_Setup_Time
tushki7	0:60d829a0353a	707	* @{
tushki7	0:60d829a0353a	708	*/
tushki7	0:60d829a0353a	709	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
tushki7	0:60d829a0353a	710	/**
tushki7	0:60d829a0353a	711	* @}
tushki7	0:60d829a0353a	712	*/
tushki7	0:60d829a0353a	713
tushki7	0:60d829a0353a	714	/** @defgroup FMC_Hold_Setup_Time
tushki7	0:60d829a0353a	715	* @{
tushki7	0:60d829a0353a	716	*/
tushki7	0:60d829a0353a	717	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
tushki7	0:60d829a0353a	718	/**
tushki7	0:60d829a0353a	719	* @}
tushki7	0:60d829a0353a	720	*/
tushki7	0:60d829a0353a	721
tushki7	0:60d829a0353a	722	/** @defgroup FMC_HiZ_Setup_Time
tushki7	0:60d829a0353a	723	* @{
tushki7	0:60d829a0353a	724	*/
tushki7	0:60d829a0353a	725	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
tushki7	0:60d829a0353a	726	/**
tushki7	0:60d829a0353a	727	* @}
tushki7	0:60d829a0353a	728	*/
tushki7	0:60d829a0353a	729
tushki7	0:60d829a0353a	730	/**
tushki7	0:60d829a0353a	731	* @}
tushki7	0:60d829a0353a	732	*/
tushki7	0:60d829a0353a	733
tushki7	0:60d829a0353a	734	/** @defgroup FMC_SDRAM_Controller
tushki7	0:60d829a0353a	735	* @{
tushki7	0:60d829a0353a	736	*/
tushki7	0:60d829a0353a	737
tushki7	0:60d829a0353a	738	/** @defgroup FMC_SDRAM_Bank
tushki7	0:60d829a0353a	739	* @{
tushki7	0:60d829a0353a	740	*/
tushki7	0:60d829a0353a	741	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	742	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	743
tushki7	0:60d829a0353a	744	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
tushki7	0:60d829a0353a	745	((BANK) == FMC_SDRAM_BANK2))
tushki7	0:60d829a0353a	746	/**
tushki7	0:60d829a0353a	747	* @}
tushki7	0:60d829a0353a	748	*/
tushki7	0:60d829a0353a	749
tushki7	0:60d829a0353a	750	/** @defgroup FMC_SDRAM_Column_Bits_number
tushki7	0:60d829a0353a	751	* @{
tushki7	0:60d829a0353a	752	*/
tushki7	0:60d829a0353a	753	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	754	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	755	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	756	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
tushki7	0:60d829a0353a	757
tushki7	0:60d829a0353a	758	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
tushki7	0:60d829a0353a	759	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
tushki7	0:60d829a0353a	760	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
tushki7	0:60d829a0353a	761	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
tushki7	0:60d829a0353a	762	/**
tushki7	0:60d829a0353a	763	* @}
tushki7	0:60d829a0353a	764	*/
tushki7	0:60d829a0353a	765
tushki7	0:60d829a0353a	766	/** @defgroup FMC_SDRAM_Row_Bits_number
tushki7	0:60d829a0353a	767	* @{
tushki7	0:60d829a0353a	768	*/
tushki7	0:60d829a0353a	769	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	770	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	771	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	772
tushki7	0:60d829a0353a	773	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
tushki7	0:60d829a0353a	774	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
tushki7	0:60d829a0353a	775	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
tushki7	0:60d829a0353a	776	/**
tushki7	0:60d829a0353a	777	* @}
tushki7	0:60d829a0353a	778	*/
tushki7	0:60d829a0353a	779
tushki7	0:60d829a0353a	780	/** @defgroup FMC_SDRAM_Memory_Bus_Width
tushki7	0:60d829a0353a	781	* @{
tushki7	0:60d829a0353a	782	*/
tushki7	0:60d829a0353a	783	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	784	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	785	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	786
tushki7	0:60d829a0353a	787	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
tushki7	0:60d829a0353a	788	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
tushki7	0:60d829a0353a	789	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
tushki7	0:60d829a0353a	790	/**
tushki7	0:60d829a0353a	791	* @}
tushki7	0:60d829a0353a	792	*/
tushki7	0:60d829a0353a	793
tushki7	0:60d829a0353a	794	/** @defgroup FMC_SDRAM_Internal_Banks_Number
tushki7	0:60d829a0353a	795	* @{
tushki7	0:60d829a0353a	796	*/
tushki7	0:60d829a0353a	797	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	798	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	799
tushki7	0:60d829a0353a	800	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
tushki7	0:60d829a0353a	801	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
tushki7	0:60d829a0353a	802	/**
tushki7	0:60d829a0353a	803	* @}
tushki7	0:60d829a0353a	804	*/
tushki7	0:60d829a0353a	805
tushki7	0:60d829a0353a	806	/** @defgroup FMC_SDRAM_CAS_Latency
tushki7	0:60d829a0353a	807	* @{
tushki7	0:60d829a0353a	808	*/
tushki7	0:60d829a0353a	809	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
tushki7	0:60d829a0353a	810	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
tushki7	0:60d829a0353a	811	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
tushki7	0:60d829a0353a	812
tushki7	0:60d829a0353a	813	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
tushki7	0:60d829a0353a	814	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
tushki7	0:60d829a0353a	815	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
tushki7	0:60d829a0353a	816	/**
tushki7	0:60d829a0353a	817	* @}
tushki7	0:60d829a0353a	818	*/
tushki7	0:60d829a0353a	819
tushki7	0:60d829a0353a	820	/** @defgroup FMC_SDRAM_Write_Protection
tushki7	0:60d829a0353a	821	* @{
tushki7	0:60d829a0353a	822	*/
tushki7	0:60d829a0353a	823	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	824	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
tushki7	0:60d829a0353a	825
tushki7	0:60d829a0353a	826	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
tushki7	0:60d829a0353a	827	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
tushki7	0:60d829a0353a	828	/**
tushki7	0:60d829a0353a	829	* @}
tushki7	0:60d829a0353a	830	*/
tushki7	0:60d829a0353a	831
tushki7	0:60d829a0353a	832	/** @defgroup FMC_SDRAM_Clock_Period
tushki7	0:60d829a0353a	833	* @{
tushki7	0:60d829a0353a	834	*/
tushki7	0:60d829a0353a	835	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	836	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
tushki7	0:60d829a0353a	837	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
tushki7	0:60d829a0353a	838
tushki7	0:60d829a0353a	839	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
tushki7	0:60d829a0353a	840	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
tushki7	0:60d829a0353a	841	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
tushki7	0:60d829a0353a	842	/**
tushki7	0:60d829a0353a	843	* @}
tushki7	0:60d829a0353a	844	*/
tushki7	0:60d829a0353a	845
tushki7	0:60d829a0353a	846	/** @defgroup FMC_SDRAM_Read_Burst
tushki7	0:60d829a0353a	847	* @{
tushki7	0:60d829a0353a	848	*/
tushki7	0:60d829a0353a	849	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	850	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
tushki7	0:60d829a0353a	851
tushki7	0:60d829a0353a	852	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
tushki7	0:60d829a0353a	853	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
tushki7	0:60d829a0353a	854	/**
tushki7	0:60d829a0353a	855	* @}
tushki7	0:60d829a0353a	856	*/
tushki7	0:60d829a0353a	857
tushki7	0:60d829a0353a	858	/** @defgroup FMC_SDRAM_Read_Pipe_Delay
tushki7	0:60d829a0353a	859	* @{
tushki7	0:60d829a0353a	860	*/
tushki7	0:60d829a0353a	861	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	862	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
tushki7	0:60d829a0353a	863	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	864
tushki7	0:60d829a0353a	865	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
tushki7	0:60d829a0353a	866	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
tushki7	0:60d829a0353a	867	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
tushki7	0:60d829a0353a	868	/**
tushki7	0:60d829a0353a	869	* @}
tushki7	0:60d829a0353a	870	*/
tushki7	0:60d829a0353a	871
tushki7	0:60d829a0353a	872	/** @defgroup FMC_SDRAM_LoadToActive_Delay
tushki7	0:60d829a0353a	873	* @{
tushki7	0:60d829a0353a	874	*/
tushki7	0:60d829a0353a	875	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
tushki7	0:60d829a0353a	876	/**
tushki7	0:60d829a0353a	877	* @}
tushki7	0:60d829a0353a	878	*/
tushki7	0:60d829a0353a	879
tushki7	0:60d829a0353a	880	/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
tushki7	0:60d829a0353a	881	* @{
tushki7	0:60d829a0353a	882	*/
tushki7	0:60d829a0353a	883	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
tushki7	0:60d829a0353a	884	/**
tushki7	0:60d829a0353a	885	* @}
tushki7	0:60d829a0353a	886	*/
tushki7	0:60d829a0353a	887
tushki7	0:60d829a0353a	888	/** @defgroup FMC_SDRAM_SelfRefresh_Time
tushki7	0:60d829a0353a	889	* @{
tushki7	0:60d829a0353a	890	*/
tushki7	0:60d829a0353a	891	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
tushki7	0:60d829a0353a	892	/**
tushki7	0:60d829a0353a	893	* @}
tushki7	0:60d829a0353a	894	*/
tushki7	0:60d829a0353a	895
tushki7	0:60d829a0353a	896	/** @defgroup FMC_SDRAM_RowCycle_Delay
tushki7	0:60d829a0353a	897	* @{
tushki7	0:60d829a0353a	898	*/
tushki7	0:60d829a0353a	899	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
tushki7	0:60d829a0353a	900	/**
tushki7	0:60d829a0353a	901	* @}
tushki7	0:60d829a0353a	902	*/
tushki7	0:60d829a0353a	903
tushki7	0:60d829a0353a	904	/** @defgroup FMC_SDRAM_Write_Recovery_Time
tushki7	0:60d829a0353a	905	* @{
tushki7	0:60d829a0353a	906	*/
tushki7	0:60d829a0353a	907	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
tushki7	0:60d829a0353a	908	/**
tushki7	0:60d829a0353a	909	* @}
tushki7	0:60d829a0353a	910	*/
tushki7	0:60d829a0353a	911
tushki7	0:60d829a0353a	912	/** @defgroup FMC_SDRAM_RP_Delay
tushki7	0:60d829a0353a	913	* @{
tushki7	0:60d829a0353a	914	*/
tushki7	0:60d829a0353a	915	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
tushki7	0:60d829a0353a	916	/**
tushki7	0:60d829a0353a	917	* @}
tushki7	0:60d829a0353a	918	*/
tushki7	0:60d829a0353a	919
tushki7	0:60d829a0353a	920	/** @defgroup FMC_SDRAM_RCD_Delay
tushki7	0:60d829a0353a	921	* @{
tushki7	0:60d829a0353a	922	*/
tushki7	0:60d829a0353a	923	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
tushki7	0:60d829a0353a	924
tushki7	0:60d829a0353a	925	/**
tushki7	0:60d829a0353a	926	* @}
tushki7	0:60d829a0353a	927	*/
tushki7	0:60d829a0353a	928
tushki7	0:60d829a0353a	929	/** @defgroup FMC_SDRAM_Command_Mode
tushki7	0:60d829a0353a	930	* @{
tushki7	0:60d829a0353a	931	*/
tushki7	0:60d829a0353a	932	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	933	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	934	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	935	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
tushki7	0:60d829a0353a	936	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	937	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
tushki7	0:60d829a0353a	938	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
tushki7	0:60d829a0353a	939
tushki7	0:60d829a0353a	940	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
tushki7	0:60d829a0353a	941	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
tushki7	0:60d829a0353a	942	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
tushki7	0:60d829a0353a	943	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
tushki7	0:60d829a0353a	944	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
tushki7	0:60d829a0353a	945	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
tushki7	0:60d829a0353a	946	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
tushki7	0:60d829a0353a	947	/**
tushki7	0:60d829a0353a	948	* @}
tushki7	0:60d829a0353a	949	*/
tushki7	0:60d829a0353a	950
tushki7	0:60d829a0353a	951	/** @defgroup FMC_SDRAM_Command_Target
tushki7	0:60d829a0353a	952	* @{
tushki7	0:60d829a0353a	953	*/
tushki7	0:60d829a0353a	954	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
tushki7	0:60d829a0353a	955	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
tushki7	0:60d829a0353a	956	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
tushki7	0:60d829a0353a	957
tushki7	0:60d829a0353a	958	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
tushki7	0:60d829a0353a	959	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
tushki7	0:60d829a0353a	960	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
tushki7	0:60d829a0353a	961	/**
tushki7	0:60d829a0353a	962	* @}
tushki7	0:60d829a0353a	963	*/
tushki7	0:60d829a0353a	964
tushki7	0:60d829a0353a	965	/** @defgroup FMC_SDRAM_AutoRefresh_Number
tushki7	0:60d829a0353a	966	* @{
tushki7	0:60d829a0353a	967	*/
tushki7	0:60d829a0353a	968	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
tushki7	0:60d829a0353a	969	/**
tushki7	0:60d829a0353a	970	* @}
tushki7	0:60d829a0353a	971	*/
tushki7	0:60d829a0353a	972
tushki7	0:60d829a0353a	973	/** @defgroup FMC_SDRAM_ModeRegister_Definition
tushki7	0:60d829a0353a	974	* @{
tushki7	0:60d829a0353a	975	*/
tushki7	0:60d829a0353a	976	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
tushki7	0:60d829a0353a	977	/**
tushki7	0:60d829a0353a	978	* @}
tushki7	0:60d829a0353a	979	*/
tushki7	0:60d829a0353a	980
tushki7	0:60d829a0353a	981	/** @defgroup FMC_SDRAM_Refresh_rate
tushki7	0:60d829a0353a	982	* @{
tushki7	0:60d829a0353a	983	*/
tushki7	0:60d829a0353a	984	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
tushki7	0:60d829a0353a	985	/**
tushki7	0:60d829a0353a	986	* @}
tushki7	0:60d829a0353a	987	*/
tushki7	0:60d829a0353a	988
tushki7	0:60d829a0353a	989	/** @defgroup FMC_SDRAM_Mode_Status
tushki7	0:60d829a0353a	990	* @{
tushki7	0:60d829a0353a	991	*/
tushki7	0:60d829a0353a	992	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
tushki7	0:60d829a0353a	993	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
tushki7	0:60d829a0353a	994	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
tushki7	0:60d829a0353a	995	/**
tushki7	0:60d829a0353a	996	* @}
tushki7	0:60d829a0353a	997	*/
tushki7	0:60d829a0353a	998
tushki7	0:60d829a0353a	999	/** @defgroup FMC_NORSRAM_Device_Instance
tushki7	0:60d829a0353a	1000	* @{
tushki7	0:60d829a0353a	1001	*/
tushki7	0:60d829a0353a	1002	#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
tushki7	0:60d829a0353a	1003	/**
tushki7	0:60d829a0353a	1004	* @}
tushki7	0:60d829a0353a	1005	*/
tushki7	0:60d829a0353a	1006
tushki7	0:60d829a0353a	1007	/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
tushki7	0:60d829a0353a	1008	* @{
tushki7	0:60d829a0353a	1009	*/
tushki7	0:60d829a0353a	1010	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
tushki7	0:60d829a0353a	1011	/**
tushki7	0:60d829a0353a	1012	* @}
tushki7	0:60d829a0353a	1013	*/
tushki7	0:60d829a0353a	1014
tushki7	0:60d829a0353a	1015	/** @defgroup FMC_NAND_Device_Instance
tushki7	0:60d829a0353a	1016	* @{
tushki7	0:60d829a0353a	1017	*/
tushki7	0:60d829a0353a	1018	#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
tushki7	0:60d829a0353a	1019	/**
tushki7	0:60d829a0353a	1020	* @}
tushki7	0:60d829a0353a	1021	*/
tushki7	0:60d829a0353a	1022
tushki7	0:60d829a0353a	1023	/** @defgroup FMC_PCCARD_Device_Instance
tushki7	0:60d829a0353a	1024	* @{
tushki7	0:60d829a0353a	1025	*/
tushki7	0:60d829a0353a	1026	#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
tushki7	0:60d829a0353a	1027	/**
tushki7	0:60d829a0353a	1028	* @}
tushki7	0:60d829a0353a	1029	*/
tushki7	0:60d829a0353a	1030
tushki7	0:60d829a0353a	1031	/** @defgroup FMC_SDRAM_Device_Instance
tushki7	0:60d829a0353a	1032	* @{
tushki7	0:60d829a0353a	1033	*/
tushki7	0:60d829a0353a	1034	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
tushki7	0:60d829a0353a	1035	/**
tushki7	0:60d829a0353a	1036	* @}
tushki7	0:60d829a0353a	1037	*/
tushki7	0:60d829a0353a	1038
tushki7	0:60d829a0353a	1039	/**
tushki7	0:60d829a0353a	1040	* @}
tushki7	0:60d829a0353a	1041	*/
tushki7	0:60d829a0353a	1042
tushki7	0:60d829a0353a	1043	/** @defgroup FMC_Interrupt_definition
tushki7	0:60d829a0353a	1044	* @brief FMC Interrupt definition
tushki7	0:60d829a0353a	1045	* @{
tushki7	0:60d829a0353a	1046	*/
tushki7	0:60d829a0353a	1047	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
tushki7	0:60d829a0353a	1048	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
tushki7	0:60d829a0353a	1049	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
tushki7	0:60d829a0353a	1050	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
tushki7	0:60d829a0353a	1051
tushki7	0:60d829a0353a	1052	#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
tushki7	0:60d829a0353a	1053
tushki7	0:60d829a0353a	1054	#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) \|\| \
tushki7	0:60d829a0353a	1055	((IT) == FMC_IT_LEVEL) \|\| \
tushki7	0:60d829a0353a	1056	((IT) == FMC_IT_FALLING_EDGE) \|\| \
tushki7	0:60d829a0353a	1057	((IT) == FMC_IT_REFRESH_ERROR))
tushki7	0:60d829a0353a	1058	/**
tushki7	0:60d829a0353a	1059	* @}
tushki7	0:60d829a0353a	1060	*/
tushki7	0:60d829a0353a	1061
tushki7	0:60d829a0353a	1062	/** @defgroup FMC_Flag_definition
tushki7	0:60d829a0353a	1063	* @brief FMC Flag definition
tushki7	0:60d829a0353a	1064	* @{
tushki7	0:60d829a0353a	1065	*/
tushki7	0:60d829a0353a	1066	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
tushki7	0:60d829a0353a	1067	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
tushki7	0:60d829a0353a	1068	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
tushki7	0:60d829a0353a	1069	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
tushki7	0:60d829a0353a	1070	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
tushki7	0:60d829a0353a	1071	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
tushki7	0:60d829a0353a	1072	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
tushki7	0:60d829a0353a	1073
tushki7	0:60d829a0353a	1074	#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) \|\| \
tushki7	0:60d829a0353a	1075	((FLAG) == FMC_FLAG_LEVEL) \|\| \
tushki7	0:60d829a0353a	1076	((FLAG) == FMC_FLAG_FALLING_EDGE) \|\| \
tushki7	0:60d829a0353a	1077	((FLAG) == FMC_FLAG_FEMPT) \|\| \
tushki7	0:60d829a0353a	1078	((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) \|\| \
tushki7	0:60d829a0353a	1079	((FLAG) == FMC_SDRAM_FLAG_BUSY))
tushki7	0:60d829a0353a	1080
tushki7	0:60d829a0353a	1081	#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
tushki7	0:60d829a0353a	1082	/**
tushki7	0:60d829a0353a	1083	* @}
tushki7	0:60d829a0353a	1084	*/
tushki7	0:60d829a0353a	1085
tushki7	0:60d829a0353a	1086	/* Exported macro ------------------------------------------------------------*/
tushki7	0:60d829a0353a	1087
tushki7	0:60d829a0353a	1088	/** @defgroup FMC_NOR_Macros
tushki7	0:60d829a0353a	1089	* @brief macros to handle NOR device enable/disable and read/write operations
tushki7	0:60d829a0353a	1090	* @{
tushki7	0:60d829a0353a	1091	*/
tushki7	0:60d829a0353a	1092
tushki7	0:60d829a0353a	1093	/**
tushki7	0:60d829a0353a	1094	* @brief Enable the NORSRAM device access.
tushki7	0:60d829a0353a	1095	* @param __INSTANCE__: FMC_NORSRAM Instance
tushki7	0:60d829a0353a	1096	* @param __BANK__: FMC_NORSRAM Bank
tushki7	0:60d829a0353a	1097	* @retval None
tushki7	0:60d829a0353a	1098	*/
tushki7	0:60d829a0353a	1099	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
tushki7	0:60d829a0353a	1100
tushki7	0:60d829a0353a	1101	/**
tushki7	0:60d829a0353a	1102	* @brief Disable the NORSRAM device access.
tushki7	0:60d829a0353a	1103	* @param __INSTANCE__: FMC_NORSRAM Instance
tushki7	0:60d829a0353a	1104	* @param __BANK__: FMC_NORSRAM Bank
tushki7	0:60d829a0353a	1105	* @retval None
tushki7	0:60d829a0353a	1106	*/
tushki7	0:60d829a0353a	1107	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
tushki7	0:60d829a0353a	1108
tushki7	0:60d829a0353a	1109	/**
tushki7	0:60d829a0353a	1110	* @}
tushki7	0:60d829a0353a	1111	*/
tushki7	0:60d829a0353a	1112
tushki7	0:60d829a0353a	1113	/** @defgroup FMC_NAND_Macros
tushki7	0:60d829a0353a	1114	* @brief macros to handle NAND device enable/disable
tushki7	0:60d829a0353a	1115	* @{
tushki7	0:60d829a0353a	1116	*/
tushki7	0:60d829a0353a	1117
tushki7	0:60d829a0353a	1118	/**
tushki7	0:60d829a0353a	1119	* @brief Enable the NAND device access.
tushki7	0:60d829a0353a	1120	* @param __INSTANCE__: FMC_NAND Instance
tushki7	0:60d829a0353a	1121	* @param __BANK__: FMC_NAND Bank
tushki7	0:60d829a0353a	1122	* @retval None
tushki7	0:60d829a0353a	1123	*/
tushki7	0:60d829a0353a	1124	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
tushki7	0:60d829a0353a	1125	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
tushki7	0:60d829a0353a	1126
tushki7	0:60d829a0353a	1127	/**
tushki7	0:60d829a0353a	1128	* @brief Disable the NAND device access.
tushki7	0:60d829a0353a	1129	* @param __INSTANCE__: FMC_NAND Instance
tushki7	0:60d829a0353a	1130	* @param __BANK__: FMC_NAND Bank
tushki7	0:60d829a0353a	1131	* @retval None
tushki7	0:60d829a0353a	1132	*/
tushki7	0:60d829a0353a	1133	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
tushki7	0:60d829a0353a	1134	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
tushki7	0:60d829a0353a	1135	/**
tushki7	0:60d829a0353a	1136	* @}
tushki7	0:60d829a0353a	1137	*/
tushki7	0:60d829a0353a	1138
tushki7	0:60d829a0353a	1139	/** @defgroup FMC_PCCARD_Macros
tushki7	0:60d829a0353a	1140	* @brief macros to handle SRAM read/write operations
tushki7	0:60d829a0353a	1141	* @{
tushki7	0:60d829a0353a	1142	*/
tushki7	0:60d829a0353a	1143
tushki7	0:60d829a0353a	1144	/**
tushki7	0:60d829a0353a	1145	* @brief Enable the PCCARD device access.
tushki7	0:60d829a0353a	1146	* @param __INSTANCE__: FMC_PCCARD Instance
tushki7	0:60d829a0353a	1147	* @retval None
tushki7	0:60d829a0353a	1148	*/
tushki7	0:60d829a0353a	1149	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
tushki7	0:60d829a0353a	1150
tushki7	0:60d829a0353a	1151	/**
tushki7	0:60d829a0353a	1152	* @brief Disable the PCCARD device access.
tushki7	0:60d829a0353a	1153	* @param __INSTANCE__: FMC_PCCARD Instance
tushki7	0:60d829a0353a	1154	* @retval None
tushki7	0:60d829a0353a	1155	*/
tushki7	0:60d829a0353a	1156	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
tushki7	0:60d829a0353a	1157	/**
tushki7	0:60d829a0353a	1158	* @}
tushki7	0:60d829a0353a	1159	*/
tushki7	0:60d829a0353a	1160
tushki7	0:60d829a0353a	1161	/** @defgroup FMC_Interrupt
tushki7	0:60d829a0353a	1162	* @brief macros to handle FMC interrupts
tushki7	0:60d829a0353a	1163	* @{
tushki7	0:60d829a0353a	1164	*/
tushki7	0:60d829a0353a	1165
tushki7	0:60d829a0353a	1166	/**
tushki7	0:60d829a0353a	1167	* @brief Enable the NAND device interrupt.
tushki7	0:60d829a0353a	1168	* @param __INSTANCE__: FMC_NAND instance
tushki7	0:60d829a0353a	1169	* @param __BANK__: FMC_NAND Bank
tushki7	0:60d829a0353a	1170	* @param __INTERRUPT__: FMC_NAND interrupt
tushki7	0:60d829a0353a	1171	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1172	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
tushki7	0:60d829a0353a	1173	* @arg FMC_IT_LEVEL: Interrupt level.
tushki7	0:60d829a0353a	1174	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
tushki7	0:60d829a0353a	1175	* @retval None
tushki7	0:60d829a0353a	1176	*/
tushki7	0:60d829a0353a	1177	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
tushki7	0:60d829a0353a	1178	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
tushki7	0:60d829a0353a	1179
tushki7	0:60d829a0353a	1180	/**
tushki7	0:60d829a0353a	1181	* @brief Disable the NAND device interrupt.
tushki7	0:60d829a0353a	1182	* @param __INSTANCE__: FMC_NAND handle
tushki7	0:60d829a0353a	1183	* @param __BANK__: FMC_NAND Bank
tushki7	0:60d829a0353a	1184	* @param __INTERRUPT__: FMC_NAND interrupt
tushki7	0:60d829a0353a	1185	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1186	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
tushki7	0:60d829a0353a	1187	* @arg FMC_IT_LEVEL: Interrupt level.
tushki7	0:60d829a0353a	1188	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
tushki7	0:60d829a0353a	1189	* @retval None
tushki7	0:60d829a0353a	1190	*/
tushki7	0:60d829a0353a	1191	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
tushki7	0:60d829a0353a	1192	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
tushki7	0:60d829a0353a	1193
tushki7	0:60d829a0353a	1194	/**
tushki7	0:60d829a0353a	1195	* @brief Get flag status of the NAND device.
tushki7	0:60d829a0353a	1196	* @param __INSTANCE__: FMC_NAND handle
tushki7	0:60d829a0353a	1197	* @param __BANK__: FMC_NAND Bank
tushki7	0:60d829a0353a	1198	* @param __FLAG__: FMC_NAND flag
tushki7	0:60d829a0353a	1199	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1200	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
tushki7	0:60d829a0353a	1201	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
tushki7	0:60d829a0353a	1202	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
tushki7	0:60d829a0353a	1203	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
tushki7	0:60d829a0353a	1204	* @retval The state of FLAG (SET or RESET).
tushki7	0:60d829a0353a	1205	*/
tushki7	0:60d829a0353a	1206	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
tushki7	0:60d829a0353a	1207	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
tushki7	0:60d829a0353a	1208	/**
tushki7	0:60d829a0353a	1209	* @brief Clear flag status of the NAND device.
tushki7	0:60d829a0353a	1210	* @param __INSTANCE__: FMC_NAND handle
tushki7	0:60d829a0353a	1211	* @param __BANK__: FMC_NAND Bank
tushki7	0:60d829a0353a	1212	* @param __FLAG__: FMC_NAND flag
tushki7	0:60d829a0353a	1213	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1214	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
tushki7	0:60d829a0353a	1215	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
tushki7	0:60d829a0353a	1216	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
tushki7	0:60d829a0353a	1217	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
tushki7	0:60d829a0353a	1218	* @retval None
tushki7	0:60d829a0353a	1219	*/
tushki7	0:60d829a0353a	1220	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
tushki7	0:60d829a0353a	1221	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
tushki7	0:60d829a0353a	1222	/**
tushki7	0:60d829a0353a	1223	* @brief Enable the PCCARD device interrupt.
tushki7	0:60d829a0353a	1224	* @param __INSTANCE__: FMC_PCCARD instance
tushki7	0:60d829a0353a	1225	* @param __INTERRUPT__: FMC_PCCARD interrupt
tushki7	0:60d829a0353a	1226	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1227	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
tushki7	0:60d829a0353a	1228	* @arg FMC_IT_LEVEL: Interrupt level.
tushki7	0:60d829a0353a	1229	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
tushki7	0:60d829a0353a	1230	* @retval None
tushki7	0:60d829a0353a	1231	*/
tushki7	0:60d829a0353a	1232	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
tushki7	0:60d829a0353a	1233
tushki7	0:60d829a0353a	1234	/**
tushki7	0:60d829a0353a	1235	* @brief Disable the PCCARD device interrupt.
tushki7	0:60d829a0353a	1236	* @param __INSTANCE__: FMC_PCCARD instance
tushki7	0:60d829a0353a	1237	* @param __INTERRUPT__: FMC_PCCARD interrupt
tushki7	0:60d829a0353a	1238	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1239	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
tushki7	0:60d829a0353a	1240	* @arg FMC_IT_LEVEL: Interrupt level.
tushki7	0:60d829a0353a	1241	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
tushki7	0:60d829a0353a	1242	* @retval None
tushki7	0:60d829a0353a	1243	*/
tushki7	0:60d829a0353a	1244	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
tushki7	0:60d829a0353a	1245
tushki7	0:60d829a0353a	1246	/**
tushki7	0:60d829a0353a	1247	* @brief Get flag status of the PCCARD device.
tushki7	0:60d829a0353a	1248	* @param __INSTANCE__: FMC_PCCARD instance
tushki7	0:60d829a0353a	1249	* @param __FLAG__: FMC_PCCARD flag
tushki7	0:60d829a0353a	1250	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1251	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
tushki7	0:60d829a0353a	1252	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
tushki7	0:60d829a0353a	1253	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
tushki7	0:60d829a0353a	1254	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
tushki7	0:60d829a0353a	1255	* @retval The state of FLAG (SET or RESET).
tushki7	0:60d829a0353a	1256	*/
tushki7	0:60d829a0353a	1257	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
tushki7	0:60d829a0353a	1258
tushki7	0:60d829a0353a	1259	/**
tushki7	0:60d829a0353a	1260	* @brief Clear flag status of the PCCARD device.
tushki7	0:60d829a0353a	1261	* @param __INSTANCE__: FMC_PCCARD instance
tushki7	0:60d829a0353a	1262	* @param __FLAG__: FMC_PCCARD flag
tushki7	0:60d829a0353a	1263	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1264	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
tushki7	0:60d829a0353a	1265	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
tushki7	0:60d829a0353a	1266	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
tushki7	0:60d829a0353a	1267	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
tushki7	0:60d829a0353a	1268	* @retval None
tushki7	0:60d829a0353a	1269	*/
tushki7	0:60d829a0353a	1270	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
tushki7	0:60d829a0353a	1271
tushki7	0:60d829a0353a	1272	/**
tushki7	0:60d829a0353a	1273	* @brief Enable the SDRAM device interrupt.
tushki7	0:60d829a0353a	1274	* @param __INSTANCE__: FMC_SDRAM instance
tushki7	0:60d829a0353a	1275	* @param __INTERRUPT__: FMC_SDRAM interrupt
tushki7	0:60d829a0353a	1276	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1277	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
tushki7	0:60d829a0353a	1278	* @retval None
tushki7	0:60d829a0353a	1279	*/
tushki7	0:60d829a0353a	1280	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
tushki7	0:60d829a0353a	1281
tushki7	0:60d829a0353a	1282	/**
tushki7	0:60d829a0353a	1283	* @brief Disable the SDRAM device interrupt.
tushki7	0:60d829a0353a	1284	* @param __INSTANCE__: FMC_SDRAM instance
tushki7	0:60d829a0353a	1285	* @param __INTERRUPT__: FMC_SDRAM interrupt
tushki7	0:60d829a0353a	1286	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1287	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
tushki7	0:60d829a0353a	1288	* @retval None
tushki7	0:60d829a0353a	1289	*/
tushki7	0:60d829a0353a	1290	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
tushki7	0:60d829a0353a	1291
tushki7	0:60d829a0353a	1292	/**
tushki7	0:60d829a0353a	1293	* @brief Get flag status of the SDRAM device.
tushki7	0:60d829a0353a	1294	* @param __INSTANCE__: FMC_SDRAM instance
tushki7	0:60d829a0353a	1295	* @param __FLAG__: FMC_SDRAM flag
tushki7	0:60d829a0353a	1296	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1297	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
tushki7	0:60d829a0353a	1298	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
tushki7	0:60d829a0353a	1299	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
tushki7	0:60d829a0353a	1300	* @retval The state of FLAG (SET or RESET).
tushki7	0:60d829a0353a	1301	*/
tushki7	0:60d829a0353a	1302	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
tushki7	0:60d829a0353a	1303
tushki7	0:60d829a0353a	1304	/**
tushki7	0:60d829a0353a	1305	* @brief Clear flag status of the SDRAM device.
tushki7	0:60d829a0353a	1306	* @param __INSTANCE__: FMC_SDRAM instance
tushki7	0:60d829a0353a	1307	* @param __FLAG__: FMC_SDRAM flag
tushki7	0:60d829a0353a	1308	* This parameter can be any combination of the following values:
tushki7	0:60d829a0353a	1309	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
tushki7	0:60d829a0353a	1310	* @retval None
tushki7	0:60d829a0353a	1311	*/
tushki7	0:60d829a0353a	1312	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
tushki7	0:60d829a0353a	1313	/**
tushki7	0:60d829a0353a	1314	* @}
tushki7	0:60d829a0353a	1315	*/
tushki7	0:60d829a0353a	1316
tushki7	0:60d829a0353a	1317	/* Exported functions --------------------------------------------------------*/
tushki7	0:60d829a0353a	1318
tushki7	0:60d829a0353a	1319	/* FMC_NORSRAM Controller functions *******************************************/
tushki7	0:60d829a0353a	1320	/* Initialization/de-initialization functions */
tushki7	0:60d829a0353a	1321	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
tushki7	0:60d829a0353a	1322	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
tushki7	0:60d829a0353a	1323	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
tushki7	0:60d829a0353a	1324	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
tushki7	0:60d829a0353a	1325
tushki7	0:60d829a0353a	1326	/* FMC_NORSRAM Control functions */
tushki7	0:60d829a0353a	1327	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
tushki7	0:60d829a0353a	1328	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
tushki7	0:60d829a0353a	1329
tushki7	0:60d829a0353a	1330	/* FMC_NAND Controller functions **********************************************/
tushki7	0:60d829a0353a	1331	/* Initialization/de-initialization functions */
tushki7	0:60d829a0353a	1332	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
tushki7	0:60d829a0353a	1333	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
tushki7	0:60d829a0353a	1334	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
tushki7	0:60d829a0353a	1335	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
tushki7	0:60d829a0353a	1336
tushki7	0:60d829a0353a	1337	/* FMC_NAND Control functions */
tushki7	0:60d829a0353a	1338	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
tushki7	0:60d829a0353a	1339	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
tushki7	0:60d829a0353a	1340	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
tushki7	0:60d829a0353a	1341
tushki7	0:60d829a0353a	1342	/* FMC_PCCARD Controller functions ********************************************/
tushki7	0:60d829a0353a	1343	/* Initialization/de-initialization functions */
tushki7	0:60d829a0353a	1344	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
tushki7	0:60d829a0353a	1345	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
tushki7	0:60d829a0353a	1346	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
tushki7	0:60d829a0353a	1347	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
tushki7	0:60d829a0353a	1348	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
tushki7	0:60d829a0353a	1349
tushki7	0:60d829a0353a	1350	/* FMC_SDRAM Controller functions *********************************************/
tushki7	0:60d829a0353a	1351	/* Initialization/de-initialization functions */
tushki7	0:60d829a0353a	1352	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
tushki7	0:60d829a0353a	1353	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
tushki7	0:60d829a0353a	1354	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
tushki7	0:60d829a0353a	1355
tushki7	0:60d829a0353a	1356	/* FMC_SDRAM Control functions */
tushki7	0:60d829a0353a	1357	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
tushki7	0:60d829a0353a	1358	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
tushki7	0:60d829a0353a	1359	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
tushki7	0:60d829a0353a	1360	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
tushki7	0:60d829a0353a	1361	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
tushki7	0:60d829a0353a	1362	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
tushki7	0:60d829a0353a	1363
tushki7	0:60d829a0353a	1364	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
tushki7	0:60d829a0353a	1365	/**
tushki7	0:60d829a0353a	1366	* @}
tushki7	0:60d829a0353a	1367	*/
tushki7	0:60d829a0353a	1368
tushki7	0:60d829a0353a	1369	/**
tushki7	0:60d829a0353a	1370	* @}
tushki7	0:60d829a0353a	1371	*/
tushki7	0:60d829a0353a	1372
tushki7	0:60d829a0353a	1373	#ifdef __cplusplus
tushki7	0:60d829a0353a	1374	}
tushki7	0:60d829a0353a	1375	#endif
tushki7	0:60d829a0353a	1376
tushki7	0:60d829a0353a	1377	#endif /* __STM32F4xx_LL_FMC_H */
tushki7	0:60d829a0353a	1378
tushki7	0:60d829a0353a	1379	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Build repository

Repository details

Type:	Program
Created:	11 Apr 2015
Imports:	100
Forks:	0
Commits:	2
Dependents:	0
Dependencies:	1
Followers:	2

mbed/TARGET_MTS_MDOT_F411RE/stm32f4xx_ll_fmc.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning