Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_LPC4088_DM/LPC407x_8x_177x_8x.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a 
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /****************************************************************************************************//**
tushki7 0:60d829a0353a 2 * $Id$ LPC407x_8x_177x_8x.h 2012-04-25
tushki7 0:60d829a0353a 3 *//**
tushki7 0:60d829a0353a 4 * @file LPC407x_8x_177x_8x.h
tushki7 0:60d829a0353a 5 *
tushki7 0:60d829a0353a 6 * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for
tushki7 0:60d829a0353a 7 * NXP LPC407x_8x_177x_8x.
tushki7 0:60d829a0353a 8 * @version V0.7
tushki7 0:60d829a0353a 9 * @date 20. June 2012
tushki7 0:60d829a0353a 10 * @author NXP MCU SW Application Team
tushki7 0:60d829a0353a 11 *
tushki7 0:60d829a0353a 12 * Copyright(C) 2012, NXP Semiconductor
tushki7 0:60d829a0353a 13 * All rights reserved.
tushki7 0:60d829a0353a 14 *
tushki7 0:60d829a0353a 15 ***********************************************************************
tushki7 0:60d829a0353a 16 * Software that is described herein is for illustrative purposes only
tushki7 0:60d829a0353a 17 * which provides customers with programming information regarding the
tushki7 0:60d829a0353a 18 * products. This software is supplied "AS IS" without any warranties.
tushki7 0:60d829a0353a 19 * NXP Semiconductors assumes no responsibility or liability for the
tushki7 0:60d829a0353a 20 * use of the software, conveys no license or title under any patent,
tushki7 0:60d829a0353a 21 * copyright, or mask work right to the product. NXP Semiconductors
tushki7 0:60d829a0353a 22 * reserves the right to make changes in the software without
tushki7 0:60d829a0353a 23 * notification. NXP Semiconductors also make no representation or
tushki7 0:60d829a0353a 24 * warranty that such application will be suitable for the specified
tushki7 0:60d829a0353a 25 * use without further testing or modification.
tushki7 0:60d829a0353a 26 * Permission to use, copy, modify, and distribute this software and its
tushki7 0:60d829a0353a 27 * documentation is hereby granted, under NXP Semiconductors'
tushki7 0:60d829a0353a 28 * relevant copyright in the software, without fee, provided that it
tushki7 0:60d829a0353a 29 * is used in conjunction with NXP Semiconductors microcontrollers. This
tushki7 0:60d829a0353a 30 * copyright, permission, and disclaimer notice must appear in all copies of
tushki7 0:60d829a0353a 31 * this code.
tushki7 0:60d829a0353a 32 **********************************************************************/
tushki7 0:60d829a0353a 33
tushki7 0:60d829a0353a 34 #ifndef __LPC407x_8x_177x_8x_H__
tushki7 0:60d829a0353a 35 #define __LPC407x_8x_177x_8x_H__
tushki7 0:60d829a0353a 36
tushki7 0:60d829a0353a 37 #if defined(__CORTEX_M4) && !defined(CORE_M4)
tushki7 0:60d829a0353a 38 #define CORE_M4
tushki7 0:60d829a0353a 39 #endif
tushki7 0:60d829a0353a 40
tushki7 0:60d829a0353a 41 // ##################
tushki7 0:60d829a0353a 42 // Code Red - excluded extern "C" as unrequired
tushki7 0:60d829a0353a 43 // ##################
tushki7 0:60d829a0353a 44 #if 0
tushki7 0:60d829a0353a 45 #ifdef __cplusplus
tushki7 0:60d829a0353a 46 extern "C" {
tushki7 0:60d829a0353a 47 #endif
tushki7 0:60d829a0353a 48 #endif
tushki7 0:60d829a0353a 49
tushki7 0:60d829a0353a 50
tushki7 0:60d829a0353a 51 /* ------------------------- Interrupt Number Definition ------------------------ */
tushki7 0:60d829a0353a 52
tushki7 0:60d829a0353a 53 typedef enum IRQn
tushki7 0:60d829a0353a 54 {
tushki7 0:60d829a0353a 55 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
tushki7 0:60d829a0353a 56 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
tushki7 0:60d829a0353a 57 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
tushki7 0:60d829a0353a 58 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
tushki7 0:60d829a0353a 59 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
tushki7 0:60d829a0353a 60 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
tushki7 0:60d829a0353a 61 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
tushki7 0:60d829a0353a 62 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
tushki7 0:60d829a0353a 63 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
tushki7 0:60d829a0353a 64 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
tushki7 0:60d829a0353a 65 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
tushki7 0:60d829a0353a 66
tushki7 0:60d829a0353a 67 /****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/
tushki7 0:60d829a0353a 68 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
tushki7 0:60d829a0353a 69 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
tushki7 0:60d829a0353a 70 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
tushki7 0:60d829a0353a 71 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
tushki7 0:60d829a0353a 72 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
tushki7 0:60d829a0353a 73 UART0_IRQn = 5, /*!< UART0 Interrupt */
tushki7 0:60d829a0353a 74 UART1_IRQn = 6, /*!< UART1 Interrupt */
tushki7 0:60d829a0353a 75 UART2_IRQn = 7, /*!< UART2 Interrupt */
tushki7 0:60d829a0353a 76 UART3_IRQn = 8, /*!< UART3 Interrupt */
tushki7 0:60d829a0353a 77 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
tushki7 0:60d829a0353a 78 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
tushki7 0:60d829a0353a 79 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
tushki7 0:60d829a0353a 80 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
tushki7 0:60d829a0353a 81 Reserved0_IRQn = 13, /*!< Reserved */
tushki7 0:60d829a0353a 82 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
tushki7 0:60d829a0353a 83 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
tushki7 0:60d829a0353a 84 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
tushki7 0:60d829a0353a 85 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
tushki7 0:60d829a0353a 86 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
tushki7 0:60d829a0353a 87 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
tushki7 0:60d829a0353a 88 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
tushki7 0:60d829a0353a 89 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
tushki7 0:60d829a0353a 90 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
tushki7 0:60d829a0353a 91 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
tushki7 0:60d829a0353a 92 USB_IRQn = 24, /*!< USB Interrupt */
tushki7 0:60d829a0353a 93 CAN_IRQn = 25, /*!< CAN Interrupt */
tushki7 0:60d829a0353a 94 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
tushki7 0:60d829a0353a 95 I2S_IRQn = 27, /*!< I2S Interrupt */
tushki7 0:60d829a0353a 96 ENET_IRQn = 28, /*!< Ethernet Interrupt */
tushki7 0:60d829a0353a 97 MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */
tushki7 0:60d829a0353a 98 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
tushki7 0:60d829a0353a 99 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
tushki7 0:60d829a0353a 100 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
tushki7 0:60d829a0353a 101 USBActivity_IRQn = 33, /*!< USB Activity interrupt */
tushki7 0:60d829a0353a 102 CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
tushki7 0:60d829a0353a 103 UART4_IRQn = 35, /*!< UART4 Interrupt */
tushki7 0:60d829a0353a 104 SSP2_IRQn = 36, /*!< SSP2 Interrupt */
tushki7 0:60d829a0353a 105 LCD_IRQn = 37, /*!< LCD Interrupt */
tushki7 0:60d829a0353a 106 GPIO_IRQn = 38, /*!< GPIO Interrupt */
tushki7 0:60d829a0353a 107 PWM0_IRQn = 39, /*!< 39 PWM0 */
tushki7 0:60d829a0353a 108 EEPROM_IRQn = 40, /*!< 40 EEPROM */
tushki7 0:60d829a0353a 109 CMP0_IRQn = 41, /*!< 41 CMP0 */
tushki7 0:60d829a0353a 110 CMP1_IRQn = 42 /*!< 42 CMP1 */
tushki7 0:60d829a0353a 111 } IRQn_Type;
tushki7 0:60d829a0353a 112
tushki7 0:60d829a0353a 113 /* ================================================================================ */
tushki7 0:60d829a0353a 114 /* ================ Processor and Core Peripheral Section ================ */
tushki7 0:60d829a0353a 115 /* ================================================================================ */
tushki7 0:60d829a0353a 116 #ifdef CORE_M4
tushki7 0:60d829a0353a 117 /* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */
tushki7 0:60d829a0353a 118 #define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
tushki7 0:60d829a0353a 119 #define __MPU_PRESENT 1 /*!< MPU present or not */
tushki7 0:60d829a0353a 120 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
tushki7 0:60d829a0353a 121 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
tushki7 0:60d829a0353a 122 #define __FPU_PRESENT 1 /*!< FPU present or not */
tushki7 0:60d829a0353a 123
tushki7 0:60d829a0353a 124
tushki7 0:60d829a0353a 125 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
tushki7 0:60d829a0353a 126 #else
tushki7 0:60d829a0353a 127 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
tushki7 0:60d829a0353a 128 #define __MPU_PRESENT 1 /*!< MPU present or not */
tushki7 0:60d829a0353a 129 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
tushki7 0:60d829a0353a 130 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
tushki7 0:60d829a0353a 131
tushki7 0:60d829a0353a 132
tushki7 0:60d829a0353a 133 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
tushki7 0:60d829a0353a 134
tushki7 0:60d829a0353a 135 #endif
tushki7 0:60d829a0353a 136
tushki7 0:60d829a0353a 137 #include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */
tushki7 0:60d829a0353a 138
tushki7 0:60d829a0353a 139
tushki7 0:60d829a0353a 140
tushki7 0:60d829a0353a 141
tushki7 0:60d829a0353a 142
tushki7 0:60d829a0353a 143
tushki7 0:60d829a0353a 144 /* ================================================================================ */
tushki7 0:60d829a0353a 145 /* ================ Device Specific Peripheral Section ================ */
tushki7 0:60d829a0353a 146 /* ================================================================================ */
tushki7 0:60d829a0353a 147
tushki7 0:60d829a0353a 148 #if defined ( __CC_ARM )
tushki7 0:60d829a0353a 149 #pragma anon_unions
tushki7 0:60d829a0353a 150 #endif
tushki7 0:60d829a0353a 151
tushki7 0:60d829a0353a 152 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
tushki7 0:60d829a0353a 153 typedef struct /* Common Registers */
tushki7 0:60d829a0353a 154 {
tushki7 0:60d829a0353a 155 __I uint32_t IntStat;
tushki7 0:60d829a0353a 156 __I uint32_t IntTCStat;
tushki7 0:60d829a0353a 157 __O uint32_t IntTCClear;
tushki7 0:60d829a0353a 158 __I uint32_t IntErrStat;
tushki7 0:60d829a0353a 159 __O uint32_t IntErrClr;
tushki7 0:60d829a0353a 160 __I uint32_t RawIntTCStat;
tushki7 0:60d829a0353a 161 __I uint32_t RawIntErrStat;
tushki7 0:60d829a0353a 162 __I uint32_t EnbldChns;
tushki7 0:60d829a0353a 163 __IO uint32_t SoftBReq;
tushki7 0:60d829a0353a 164 __IO uint32_t SoftSReq;
tushki7 0:60d829a0353a 165 __IO uint32_t SoftLBReq;
tushki7 0:60d829a0353a 166 __IO uint32_t SoftLSReq;
tushki7 0:60d829a0353a 167 __IO uint32_t Config;
tushki7 0:60d829a0353a 168 __IO uint32_t Sync;
tushki7 0:60d829a0353a 169 } LPC_GPDMA_TypeDef;
tushki7 0:60d829a0353a 170
tushki7 0:60d829a0353a 171 typedef struct /* Channel Registers */
tushki7 0:60d829a0353a 172 {
tushki7 0:60d829a0353a 173 __IO uint32_t CSrcAddr;
tushki7 0:60d829a0353a 174 __IO uint32_t CDestAddr;
tushki7 0:60d829a0353a 175 __IO uint32_t CLLI;
tushki7 0:60d829a0353a 176 __IO uint32_t CControl;
tushki7 0:60d829a0353a 177 __IO uint32_t CConfig;
tushki7 0:60d829a0353a 178 } LPC_GPDMACH_TypeDef;
tushki7 0:60d829a0353a 179
tushki7 0:60d829a0353a 180 /*------------- System Control (SC) ------------------------------------------*/
tushki7 0:60d829a0353a 181 typedef struct
tushki7 0:60d829a0353a 182 {
tushki7 0:60d829a0353a 183 __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
tushki7 0:60d829a0353a 184 uint32_t RESERVED0[31];
tushki7 0:60d829a0353a 185 __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
tushki7 0:60d829a0353a 186 __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
tushki7 0:60d829a0353a 187 __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
tushki7 0:60d829a0353a 188 __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
tushki7 0:60d829a0353a 189 uint32_t RESERVED1[4];
tushki7 0:60d829a0353a 190 __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
tushki7 0:60d829a0353a 191 __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
tushki7 0:60d829a0353a 192 __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
tushki7 0:60d829a0353a 193 __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
tushki7 0:60d829a0353a 194 uint32_t RESERVED2[4];
tushki7 0:60d829a0353a 195 __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
tushki7 0:60d829a0353a 196 __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
tushki7 0:60d829a0353a 197 __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */
tushki7 0:60d829a0353a 198 uint32_t RESERVED3[13];
tushki7 0:60d829a0353a 199 __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
tushki7 0:60d829a0353a 200 __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */
tushki7 0:60d829a0353a 201 __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */
tushki7 0:60d829a0353a 202 __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
tushki7 0:60d829a0353a 203 __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
tushki7 0:60d829a0353a 204 __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
tushki7 0:60d829a0353a 205 uint32_t RESERVED4[10];
tushki7 0:60d829a0353a 206 __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
tushki7 0:60d829a0353a 207 uint32_t RESERVED5[1];
tushki7 0:60d829a0353a 208 __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
tushki7 0:60d829a0353a 209 __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
tushki7 0:60d829a0353a 210 uint32_t RESERVED6[12];
tushki7 0:60d829a0353a 211 __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
tushki7 0:60d829a0353a 212 uint32_t RESERVED7[7];
tushki7 0:60d829a0353a 213 __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
tushki7 0:60d829a0353a 214 __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */
tushki7 0:60d829a0353a 215 __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
tushki7 0:60d829a0353a 216 uint32_t RESERVED8;
tushki7 0:60d829a0353a 217 __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */
tushki7 0:60d829a0353a 218 __IO uint32_t SPIFICLKSEL;
tushki7 0:60d829a0353a 219 __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
tushki7 0:60d829a0353a 220 uint32_t RESERVED10[1];
tushki7 0:60d829a0353a 221 __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
tushki7 0:60d829a0353a 222 __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
tushki7 0:60d829a0353a 223 __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
tushki7 0:60d829a0353a 224 __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */
tushki7 0:60d829a0353a 225 __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */
tushki7 0:60d829a0353a 226 uint32_t RESERVED11[2];
tushki7 0:60d829a0353a 227 __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */
tushki7 0:60d829a0353a 228 __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
tushki7 0:60d829a0353a 229 } LPC_SC_TypeDef;
tushki7 0:60d829a0353a 230 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
tushki7 0:60d829a0353a 231 typedef struct
tushki7 0:60d829a0353a 232 {
tushki7 0:60d829a0353a 233 __IO uint32_t MAC1; /* MAC Registers */
tushki7 0:60d829a0353a 234 __IO uint32_t MAC2;
tushki7 0:60d829a0353a 235 __IO uint32_t IPGT;
tushki7 0:60d829a0353a 236 __IO uint32_t IPGR;
tushki7 0:60d829a0353a 237 __IO uint32_t CLRT;
tushki7 0:60d829a0353a 238 __IO uint32_t MAXF;
tushki7 0:60d829a0353a 239 __IO uint32_t SUPP;
tushki7 0:60d829a0353a 240 __IO uint32_t TEST;
tushki7 0:60d829a0353a 241 __IO uint32_t MCFG;
tushki7 0:60d829a0353a 242 __IO uint32_t MCMD;
tushki7 0:60d829a0353a 243 __IO uint32_t MADR;
tushki7 0:60d829a0353a 244 __O uint32_t MWTD;
tushki7 0:60d829a0353a 245 __I uint32_t MRDD;
tushki7 0:60d829a0353a 246 __I uint32_t MIND;
tushki7 0:60d829a0353a 247 uint32_t RESERVED0[2];
tushki7 0:60d829a0353a 248 __IO uint32_t SA0;
tushki7 0:60d829a0353a 249 __IO uint32_t SA1;
tushki7 0:60d829a0353a 250 __IO uint32_t SA2;
tushki7 0:60d829a0353a 251 uint32_t RESERVED1[45];
tushki7 0:60d829a0353a 252 __IO uint32_t Command; /* Control Registers */
tushki7 0:60d829a0353a 253 __I uint32_t Status;
tushki7 0:60d829a0353a 254 __IO uint32_t RxDescriptor;
tushki7 0:60d829a0353a 255 __IO uint32_t RxStatus;
tushki7 0:60d829a0353a 256 __IO uint32_t RxDescriptorNumber;
tushki7 0:60d829a0353a 257 __I uint32_t RxProduceIndex;
tushki7 0:60d829a0353a 258 __IO uint32_t RxConsumeIndex;
tushki7 0:60d829a0353a 259 __IO uint32_t TxDescriptor;
tushki7 0:60d829a0353a 260 __IO uint32_t TxStatus;
tushki7 0:60d829a0353a 261 __IO uint32_t TxDescriptorNumber;
tushki7 0:60d829a0353a 262 __IO uint32_t TxProduceIndex;
tushki7 0:60d829a0353a 263 __I uint32_t TxConsumeIndex;
tushki7 0:60d829a0353a 264 uint32_t RESERVED2[10];
tushki7 0:60d829a0353a 265 __I uint32_t TSV0;
tushki7 0:60d829a0353a 266 __I uint32_t TSV1;
tushki7 0:60d829a0353a 267 __I uint32_t RSV;
tushki7 0:60d829a0353a 268 uint32_t RESERVED3[3];
tushki7 0:60d829a0353a 269 __IO uint32_t FlowControlCounter;
tushki7 0:60d829a0353a 270 __I uint32_t FlowControlStatus;
tushki7 0:60d829a0353a 271 uint32_t RESERVED4[34];
tushki7 0:60d829a0353a 272 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
tushki7 0:60d829a0353a 273 __I uint32_t RxFilterWoLStatus;
tushki7 0:60d829a0353a 274 __O uint32_t RxFilterWoLClear;
tushki7 0:60d829a0353a 275 uint32_t RESERVED5;
tushki7 0:60d829a0353a 276 __IO uint32_t HashFilterL;
tushki7 0:60d829a0353a 277 __IO uint32_t HashFilterH;
tushki7 0:60d829a0353a 278 uint32_t RESERVED6[882];
tushki7 0:60d829a0353a 279 __I uint32_t IntStatus; /* Module Control Registers */
tushki7 0:60d829a0353a 280 __IO uint32_t IntEnable;
tushki7 0:60d829a0353a 281 __O uint32_t IntClear;
tushki7 0:60d829a0353a 282 __O uint32_t IntSet;
tushki7 0:60d829a0353a 283 uint32_t RESERVED7;
tushki7 0:60d829a0353a 284 __IO uint32_t PowerDown;
tushki7 0:60d829a0353a 285 uint32_t RESERVED8;
tushki7 0:60d829a0353a 286 __IO uint32_t Module_ID;
tushki7 0:60d829a0353a 287 } LPC_EMAC_TypeDef;
tushki7 0:60d829a0353a 288
tushki7 0:60d829a0353a 289 /*------------- LCD controller (LCD) -----------------------------------------*/
tushki7 0:60d829a0353a 290 typedef struct
tushki7 0:60d829a0353a 291 {
tushki7 0:60d829a0353a 292 __IO uint32_t TIMH; /* LCD Registers */
tushki7 0:60d829a0353a 293 __IO uint32_t TIMV;
tushki7 0:60d829a0353a 294 __IO uint32_t POL;
tushki7 0:60d829a0353a 295 __IO uint32_t LE;
tushki7 0:60d829a0353a 296 __IO uint32_t UPBASE;
tushki7 0:60d829a0353a 297 __IO uint32_t LPBASE;
tushki7 0:60d829a0353a 298 __IO uint32_t CTRL;
tushki7 0:60d829a0353a 299 __IO uint32_t INTMSK;
tushki7 0:60d829a0353a 300 __I uint32_t INTRAW;
tushki7 0:60d829a0353a 301 __I uint32_t INTSTAT;
tushki7 0:60d829a0353a 302 __O uint32_t INTCLR;
tushki7 0:60d829a0353a 303 __I uint32_t UPCURR;
tushki7 0:60d829a0353a 304 __I uint32_t LPCURR;
tushki7 0:60d829a0353a 305 uint32_t RESERVED0[115];
tushki7 0:60d829a0353a 306 __IO uint32_t PAL[128];
tushki7 0:60d829a0353a 307 uint32_t RESERVED1[256];
tushki7 0:60d829a0353a 308 __IO uint32_t CRSR_IMG[256];
tushki7 0:60d829a0353a 309 __IO uint32_t CRSR_CTRL;
tushki7 0:60d829a0353a 310 __IO uint32_t CRSR_CFG;
tushki7 0:60d829a0353a 311 __IO uint32_t CRSR_PAL0;
tushki7 0:60d829a0353a 312 __IO uint32_t CRSR_PAL1;
tushki7 0:60d829a0353a 313 __IO uint32_t CRSR_XY;
tushki7 0:60d829a0353a 314 __IO uint32_t CRSR_CLIP;
tushki7 0:60d829a0353a 315 uint32_t RESERVED2[2];
tushki7 0:60d829a0353a 316 __IO uint32_t CRSR_INTMSK;
tushki7 0:60d829a0353a 317 __O uint32_t CRSR_INTCLR;
tushki7 0:60d829a0353a 318 __I uint32_t CRSR_INTRAW;
tushki7 0:60d829a0353a 319 __I uint32_t CRSR_INTSTAT;
tushki7 0:60d829a0353a 320 } LPC_LCD_TypeDef;
tushki7 0:60d829a0353a 321
tushki7 0:60d829a0353a 322 /*------------- Universal Serial Bus (USB) -----------------------------------*/
tushki7 0:60d829a0353a 323 typedef struct
tushki7 0:60d829a0353a 324 {
tushki7 0:60d829a0353a 325 __I uint32_t Revision; /* USB Host Registers */
tushki7 0:60d829a0353a 326 __IO uint32_t Control;
tushki7 0:60d829a0353a 327 __IO uint32_t CommandStatus;
tushki7 0:60d829a0353a 328 __IO uint32_t InterruptStatus;
tushki7 0:60d829a0353a 329 __IO uint32_t InterruptEnable;
tushki7 0:60d829a0353a 330 __IO uint32_t InterruptDisable;
tushki7 0:60d829a0353a 331 __IO uint32_t HCCA;
tushki7 0:60d829a0353a 332 __I uint32_t PeriodCurrentED;
tushki7 0:60d829a0353a 333 __IO uint32_t ControlHeadED;
tushki7 0:60d829a0353a 334 __IO uint32_t ControlCurrentED;
tushki7 0:60d829a0353a 335 __IO uint32_t BulkHeadED;
tushki7 0:60d829a0353a 336 __IO uint32_t BulkCurrentED;
tushki7 0:60d829a0353a 337 __I uint32_t DoneHead;
tushki7 0:60d829a0353a 338 __IO uint32_t FmInterval;
tushki7 0:60d829a0353a 339 __I uint32_t FmRemaining;
tushki7 0:60d829a0353a 340 __I uint32_t FmNumber;
tushki7 0:60d829a0353a 341 __IO uint32_t PeriodicStart;
tushki7 0:60d829a0353a 342 __IO uint32_t LSTreshold;
tushki7 0:60d829a0353a 343 __IO uint32_t RhDescriptorA;
tushki7 0:60d829a0353a 344 __IO uint32_t RhDescriptorB;
tushki7 0:60d829a0353a 345 __IO uint32_t RhStatus;
tushki7 0:60d829a0353a 346 __IO uint32_t RhPortStatus1;
tushki7 0:60d829a0353a 347 __IO uint32_t RhPortStatus2;
tushki7 0:60d829a0353a 348 uint32_t RESERVED0[40];
tushki7 0:60d829a0353a 349 __I uint32_t Module_ID;
tushki7 0:60d829a0353a 350
tushki7 0:60d829a0353a 351 __I uint32_t IntSt; /* USB On-The-Go Registers */
tushki7 0:60d829a0353a 352 __IO uint32_t IntEn;
tushki7 0:60d829a0353a 353 __O uint32_t IntSet;
tushki7 0:60d829a0353a 354 __O uint32_t IntClr;
tushki7 0:60d829a0353a 355 __IO uint32_t StCtrl;
tushki7 0:60d829a0353a 356 __IO uint32_t Tmr;
tushki7 0:60d829a0353a 357 uint32_t RESERVED1[58];
tushki7 0:60d829a0353a 358
tushki7 0:60d829a0353a 359 __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
tushki7 0:60d829a0353a 360 __IO uint32_t DevIntEn;
tushki7 0:60d829a0353a 361 __O uint32_t DevIntClr;
tushki7 0:60d829a0353a 362 __O uint32_t DevIntSet;
tushki7 0:60d829a0353a 363
tushki7 0:60d829a0353a 364 __O uint32_t CmdCode; /* USB Device SIE Command Registers */
tushki7 0:60d829a0353a 365 __I uint32_t CmdData;
tushki7 0:60d829a0353a 366
tushki7 0:60d829a0353a 367 __I uint32_t RxData; /* USB Device Transfer Registers */
tushki7 0:60d829a0353a 368 __O uint32_t TxData;
tushki7 0:60d829a0353a 369 __I uint32_t RxPLen;
tushki7 0:60d829a0353a 370 __O uint32_t TxPLen;
tushki7 0:60d829a0353a 371 __IO uint32_t Ctrl;
tushki7 0:60d829a0353a 372 __O uint32_t DevIntPri;
tushki7 0:60d829a0353a 373
tushki7 0:60d829a0353a 374 __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
tushki7 0:60d829a0353a 375 __IO uint32_t EpIntEn;
tushki7 0:60d829a0353a 376 __O uint32_t EpIntClr;
tushki7 0:60d829a0353a 377 __O uint32_t EpIntSet;
tushki7 0:60d829a0353a 378 __O uint32_t EpIntPri;
tushki7 0:60d829a0353a 379
tushki7 0:60d829a0353a 380 __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
tushki7 0:60d829a0353a 381 __O uint32_t EpInd;
tushki7 0:60d829a0353a 382 __IO uint32_t MaxPSize;
tushki7 0:60d829a0353a 383
tushki7 0:60d829a0353a 384 __I uint32_t DMARSt; /* USB Device DMA Registers */
tushki7 0:60d829a0353a 385 __O uint32_t DMARClr;
tushki7 0:60d829a0353a 386 __O uint32_t DMARSet;
tushki7 0:60d829a0353a 387 uint32_t RESERVED2[9];
tushki7 0:60d829a0353a 388 __IO uint32_t UDCAH;
tushki7 0:60d829a0353a 389 __I uint32_t EpDMASt;
tushki7 0:60d829a0353a 390 __O uint32_t EpDMAEn;
tushki7 0:60d829a0353a 391 __O uint32_t EpDMADis;
tushki7 0:60d829a0353a 392 __I uint32_t DMAIntSt;
tushki7 0:60d829a0353a 393 __IO uint32_t DMAIntEn;
tushki7 0:60d829a0353a 394 uint32_t RESERVED3[2];
tushki7 0:60d829a0353a 395 __I uint32_t EoTIntSt;
tushki7 0:60d829a0353a 396 __O uint32_t EoTIntClr;
tushki7 0:60d829a0353a 397 __O uint32_t EoTIntSet;
tushki7 0:60d829a0353a 398 __I uint32_t NDDRIntSt;
tushki7 0:60d829a0353a 399 __O uint32_t NDDRIntClr;
tushki7 0:60d829a0353a 400 __O uint32_t NDDRIntSet;
tushki7 0:60d829a0353a 401 __I uint32_t SysErrIntSt;
tushki7 0:60d829a0353a 402 __O uint32_t SysErrIntClr;
tushki7 0:60d829a0353a 403 __O uint32_t SysErrIntSet;
tushki7 0:60d829a0353a 404 uint32_t RESERVED4[15];
tushki7 0:60d829a0353a 405
tushki7 0:60d829a0353a 406 union {
tushki7 0:60d829a0353a 407 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
tushki7 0:60d829a0353a 408 __O uint32_t I2C_TX;
tushki7 0:60d829a0353a 409 };
tushki7 0:60d829a0353a 410 __IO uint32_t I2C_STS;
tushki7 0:60d829a0353a 411 __IO uint32_t I2C_CTL;
tushki7 0:60d829a0353a 412 __IO uint32_t I2C_CLKHI;
tushki7 0:60d829a0353a 413 __O uint32_t I2C_CLKLO;
tushki7 0:60d829a0353a 414 uint32_t RESERVED5[824];
tushki7 0:60d829a0353a 415
tushki7 0:60d829a0353a 416 union {
tushki7 0:60d829a0353a 417 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
tushki7 0:60d829a0353a 418 __IO uint32_t OTGClkCtrl;
tushki7 0:60d829a0353a 419 };
tushki7 0:60d829a0353a 420 union {
tushki7 0:60d829a0353a 421 __I uint32_t USBClkSt;
tushki7 0:60d829a0353a 422 __I uint32_t OTGClkSt;
tushki7 0:60d829a0353a 423 };
tushki7 0:60d829a0353a 424 } LPC_USB_TypeDef;
tushki7 0:60d829a0353a 425
tushki7 0:60d829a0353a 426 /*------------- CRC Engine (CRC) -----------------------------------------*/
tushki7 0:60d829a0353a 427 typedef struct
tushki7 0:60d829a0353a 428 {
tushki7 0:60d829a0353a 429 __IO uint32_t MODE;
tushki7 0:60d829a0353a 430 __IO uint32_t SEED;
tushki7 0:60d829a0353a 431 union {
tushki7 0:60d829a0353a 432 __I uint32_t SUM;
tushki7 0:60d829a0353a 433 struct {
tushki7 0:60d829a0353a 434 __O uint32_t DATA;
tushki7 0:60d829a0353a 435 } WR_DATA_DWORD;
tushki7 0:60d829a0353a 436
tushki7 0:60d829a0353a 437 struct {
tushki7 0:60d829a0353a 438 __O uint16_t DATA;
tushki7 0:60d829a0353a 439 uint16_t RESERVED;
tushki7 0:60d829a0353a 440 }WR_DATA_WORD;
tushki7 0:60d829a0353a 441
tushki7 0:60d829a0353a 442 struct {
tushki7 0:60d829a0353a 443 __O uint8_t DATA;
tushki7 0:60d829a0353a 444 uint8_t RESERVED[3];
tushki7 0:60d829a0353a 445 }WR_DATA_BYTE;
tushki7 0:60d829a0353a 446 };
tushki7 0:60d829a0353a 447 } LPC_CRC_TypeDef;
tushki7 0:60d829a0353a 448 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
tushki7 0:60d829a0353a 449 typedef struct
tushki7 0:60d829a0353a 450 {
tushki7 0:60d829a0353a 451 __IO uint32_t DIR;
tushki7 0:60d829a0353a 452 uint32_t RESERVED0[3];
tushki7 0:60d829a0353a 453 __IO uint32_t MASK;
tushki7 0:60d829a0353a 454 __IO uint32_t PIN;
tushki7 0:60d829a0353a 455 __IO uint32_t SET;
tushki7 0:60d829a0353a 456 __O uint32_t CLR;
tushki7 0:60d829a0353a 457 } LPC_GPIO_TypeDef;
tushki7 0:60d829a0353a 458
tushki7 0:60d829a0353a 459 typedef struct
tushki7 0:60d829a0353a 460 {
tushki7 0:60d829a0353a 461 __I uint32_t IntStatus;
tushki7 0:60d829a0353a 462 __I uint32_t IO0IntStatR;
tushki7 0:60d829a0353a 463 __I uint32_t IO0IntStatF;
tushki7 0:60d829a0353a 464 __O uint32_t IO0IntClr;
tushki7 0:60d829a0353a 465 __IO uint32_t IO0IntEnR;
tushki7 0:60d829a0353a 466 __IO uint32_t IO0IntEnF;
tushki7 0:60d829a0353a 467 uint32_t RESERVED0[3];
tushki7 0:60d829a0353a 468 __I uint32_t IO2IntStatR;
tushki7 0:60d829a0353a 469 __I uint32_t IO2IntStatF;
tushki7 0:60d829a0353a 470 __O uint32_t IO2IntClr;
tushki7 0:60d829a0353a 471 __IO uint32_t IO2IntEnR;
tushki7 0:60d829a0353a 472 __IO uint32_t IO2IntEnF;
tushki7 0:60d829a0353a 473 } LPC_GPIOINT_TypeDef;
tushki7 0:60d829a0353a 474
tushki7 0:60d829a0353a 475 /*------------- External Memory Controller (EMC) -----------------------------*/
tushki7 0:60d829a0353a 476 typedef struct
tushki7 0:60d829a0353a 477 {
tushki7 0:60d829a0353a 478 __IO uint32_t Control;
tushki7 0:60d829a0353a 479 __I uint32_t Status;
tushki7 0:60d829a0353a 480 __IO uint32_t Config;
tushki7 0:60d829a0353a 481 uint32_t RESERVED0[5];
tushki7 0:60d829a0353a 482 __IO uint32_t DynamicControl;
tushki7 0:60d829a0353a 483 __IO uint32_t DynamicRefresh;
tushki7 0:60d829a0353a 484 __IO uint32_t DynamicReadConfig;
tushki7 0:60d829a0353a 485 uint32_t RESERVED1[1];
tushki7 0:60d829a0353a 486 __IO uint32_t DynamicRP;
tushki7 0:60d829a0353a 487 __IO uint32_t DynamicRAS;
tushki7 0:60d829a0353a 488 __IO uint32_t DynamicSREX;
tushki7 0:60d829a0353a 489 __IO uint32_t DynamicAPR;
tushki7 0:60d829a0353a 490 __IO uint32_t DynamicDAL;
tushki7 0:60d829a0353a 491 __IO uint32_t DynamicWR;
tushki7 0:60d829a0353a 492 __IO uint32_t DynamicRC;
tushki7 0:60d829a0353a 493 __IO uint32_t DynamicRFC;
tushki7 0:60d829a0353a 494 __IO uint32_t DynamicXSR;
tushki7 0:60d829a0353a 495 __IO uint32_t DynamicRRD;
tushki7 0:60d829a0353a 496 __IO uint32_t DynamicMRD;
tushki7 0:60d829a0353a 497 uint32_t RESERVED2[9];
tushki7 0:60d829a0353a 498 __IO uint32_t StaticExtendedWait;
tushki7 0:60d829a0353a 499 uint32_t RESERVED3[31];
tushki7 0:60d829a0353a 500 __IO uint32_t DynamicConfig0;
tushki7 0:60d829a0353a 501 __IO uint32_t DynamicRasCas0;
tushki7 0:60d829a0353a 502 uint32_t RESERVED4[6];
tushki7 0:60d829a0353a 503 __IO uint32_t DynamicConfig1;
tushki7 0:60d829a0353a 504 __IO uint32_t DynamicRasCas1;
tushki7 0:60d829a0353a 505 uint32_t RESERVED5[6];
tushki7 0:60d829a0353a 506 __IO uint32_t DynamicConfig2;
tushki7 0:60d829a0353a 507 __IO uint32_t DynamicRasCas2;
tushki7 0:60d829a0353a 508 uint32_t RESERVED6[6];
tushki7 0:60d829a0353a 509 __IO uint32_t DynamicConfig3;
tushki7 0:60d829a0353a 510 __IO uint32_t DynamicRasCas3;
tushki7 0:60d829a0353a 511 uint32_t RESERVED7[38];
tushki7 0:60d829a0353a 512 __IO uint32_t StaticConfig0;
tushki7 0:60d829a0353a 513 __IO uint32_t StaticWaitWen0;
tushki7 0:60d829a0353a 514 __IO uint32_t StaticWaitOen0;
tushki7 0:60d829a0353a 515 __IO uint32_t StaticWaitRd0;
tushki7 0:60d829a0353a 516 __IO uint32_t StaticWaitPage0;
tushki7 0:60d829a0353a 517 __IO uint32_t StaticWaitWr0;
tushki7 0:60d829a0353a 518 __IO uint32_t StaticWaitTurn0;
tushki7 0:60d829a0353a 519 uint32_t RESERVED8[1];
tushki7 0:60d829a0353a 520 __IO uint32_t StaticConfig1;
tushki7 0:60d829a0353a 521 __IO uint32_t StaticWaitWen1;
tushki7 0:60d829a0353a 522 __IO uint32_t StaticWaitOen1;
tushki7 0:60d829a0353a 523 __IO uint32_t StaticWaitRd1;
tushki7 0:60d829a0353a 524 __IO uint32_t StaticWaitPage1;
tushki7 0:60d829a0353a 525 __IO uint32_t StaticWaitWr1;
tushki7 0:60d829a0353a 526 __IO uint32_t StaticWaitTurn1;
tushki7 0:60d829a0353a 527 uint32_t RESERVED9[1];
tushki7 0:60d829a0353a 528 __IO uint32_t StaticConfig2;
tushki7 0:60d829a0353a 529 __IO uint32_t StaticWaitWen2;
tushki7 0:60d829a0353a 530 __IO uint32_t StaticWaitOen2;
tushki7 0:60d829a0353a 531 __IO uint32_t StaticWaitRd2;
tushki7 0:60d829a0353a 532 __IO uint32_t StaticWaitPage2;
tushki7 0:60d829a0353a 533 __IO uint32_t StaticWaitWr2;
tushki7 0:60d829a0353a 534 __IO uint32_t StaticWaitTurn2;
tushki7 0:60d829a0353a 535 uint32_t RESERVED10[1];
tushki7 0:60d829a0353a 536 __IO uint32_t StaticConfig3;
tushki7 0:60d829a0353a 537 __IO uint32_t StaticWaitWen3;
tushki7 0:60d829a0353a 538 __IO uint32_t StaticWaitOen3;
tushki7 0:60d829a0353a 539 __IO uint32_t StaticWaitRd3;
tushki7 0:60d829a0353a 540 __IO uint32_t StaticWaitPage3;
tushki7 0:60d829a0353a 541 __IO uint32_t StaticWaitWr3;
tushki7 0:60d829a0353a 542 __IO uint32_t StaticWaitTurn3;
tushki7 0:60d829a0353a 543 } LPC_EMC_TypeDef;
tushki7 0:60d829a0353a 544
tushki7 0:60d829a0353a 545 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
tushki7 0:60d829a0353a 546 typedef struct
tushki7 0:60d829a0353a 547 {
tushki7 0:60d829a0353a 548 __IO uint8_t MOD;
tushki7 0:60d829a0353a 549 uint8_t RESERVED0[3];
tushki7 0:60d829a0353a 550 __IO uint32_t TC;
tushki7 0:60d829a0353a 551 __O uint8_t FEED;
tushki7 0:60d829a0353a 552 uint8_t RESERVED1[3];
tushki7 0:60d829a0353a 553 __I uint32_t TV;
tushki7 0:60d829a0353a 554 uint32_t RESERVED2;
tushki7 0:60d829a0353a 555 __IO uint32_t WARNINT;
tushki7 0:60d829a0353a 556 __IO uint32_t WINDOW;
tushki7 0:60d829a0353a 557 } LPC_WDT_TypeDef;
tushki7 0:60d829a0353a 558
tushki7 0:60d829a0353a 559 /*------------- Timer (TIM) --------------------------------------------------*/
tushki7 0:60d829a0353a 560 typedef struct
tushki7 0:60d829a0353a 561 {
tushki7 0:60d829a0353a 562 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
tushki7 0:60d829a0353a 563 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
tushki7 0:60d829a0353a 564 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
tushki7 0:60d829a0353a 565 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
tushki7 0:60d829a0353a 566 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
tushki7 0:60d829a0353a 567 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
tushki7 0:60d829a0353a 568 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
tushki7 0:60d829a0353a 569 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
tushki7 0:60d829a0353a 570 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
tushki7 0:60d829a0353a 571 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
tushki7 0:60d829a0353a 572 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
tushki7 0:60d829a0353a 573 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
tushki7 0:60d829a0353a 574 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
tushki7 0:60d829a0353a 575 uint32_t RESERVED0[2];
tushki7 0:60d829a0353a 576 __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
tushki7 0:60d829a0353a 577 uint32_t RESERVED1[12];
tushki7 0:60d829a0353a 578 __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
tushki7 0:60d829a0353a 579 } LPC_TIM_TypeDef;
tushki7 0:60d829a0353a 580
tushki7 0:60d829a0353a 581
tushki7 0:60d829a0353a 582 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
tushki7 0:60d829a0353a 583 typedef struct
tushki7 0:60d829a0353a 584 {
tushki7 0:60d829a0353a 585 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
tushki7 0:60d829a0353a 586 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
tushki7 0:60d829a0353a 587 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
tushki7 0:60d829a0353a 588 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
tushki7 0:60d829a0353a 589 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
tushki7 0:60d829a0353a 590 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
tushki7 0:60d829a0353a 591 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
tushki7 0:60d829a0353a 592 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
tushki7 0:60d829a0353a 593 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
tushki7 0:60d829a0353a 594 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
tushki7 0:60d829a0353a 595 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
tushki7 0:60d829a0353a 596 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
tushki7 0:60d829a0353a 597 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
tushki7 0:60d829a0353a 598 __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */
tushki7 0:60d829a0353a 599 __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */
tushki7 0:60d829a0353a 600 uint32_t RESERVED0;
tushki7 0:60d829a0353a 601 __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */
tushki7 0:60d829a0353a 602 __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */
tushki7 0:60d829a0353a 603 __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */
tushki7 0:60d829a0353a 604 __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */
tushki7 0:60d829a0353a 605 __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */
tushki7 0:60d829a0353a 606 uint32_t RESERVED1[7];
tushki7 0:60d829a0353a 607 __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */
tushki7 0:60d829a0353a 608 } LPC_PWM_TypeDef;
tushki7 0:60d829a0353a 609
tushki7 0:60d829a0353a 610 /*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
tushki7 0:60d829a0353a 611 /* There are three types of UARTs on the chip:
tushki7 0:60d829a0353a 612 (1) UART0,UART2, and UART3 are the standard UART.
tushki7 0:60d829a0353a 613 (2) UART1 is the standard with modem capability.
tushki7 0:60d829a0353a 614 (3) USART(UART4) is the sync/async UART with smart card capability.
tushki7 0:60d829a0353a 615 More details can be found on the Users Manual. */
tushki7 0:60d829a0353a 616
tushki7 0:60d829a0353a 617 #if 0
tushki7 0:60d829a0353a 618 typedef struct
tushki7 0:60d829a0353a 619 {
tushki7 0:60d829a0353a 620 union {
tushki7 0:60d829a0353a 621 __I uint8_t RBR;
tushki7 0:60d829a0353a 622 __O uint8_t THR;
tushki7 0:60d829a0353a 623 __IO uint8_t DLL;
tushki7 0:60d829a0353a 624 uint32_t RESERVED0;
tushki7 0:60d829a0353a 625 };
tushki7 0:60d829a0353a 626 union {
tushki7 0:60d829a0353a 627 __IO uint8_t DLM;
tushki7 0:60d829a0353a 628 __IO uint32_t IER;
tushki7 0:60d829a0353a 629 };
tushki7 0:60d829a0353a 630 union {
tushki7 0:60d829a0353a 631 __I uint32_t IIR;
tushki7 0:60d829a0353a 632 __O uint8_t FCR;
tushki7 0:60d829a0353a 633 };
tushki7 0:60d829a0353a 634 __IO uint8_t LCR;
tushki7 0:60d829a0353a 635 uint8_t RESERVED1[7];
tushki7 0:60d829a0353a 636 __I uint8_t LSR;
tushki7 0:60d829a0353a 637 uint8_t RESERVED2[7];
tushki7 0:60d829a0353a 638 __IO uint8_t SCR;
tushki7 0:60d829a0353a 639 uint8_t RESERVED3[3];
tushki7 0:60d829a0353a 640 __IO uint32_t ACR;
tushki7 0:60d829a0353a 641 __IO uint8_t ICR;
tushki7 0:60d829a0353a 642 uint8_t RESERVED4[3];
tushki7 0:60d829a0353a 643 __IO uint8_t FDR;
tushki7 0:60d829a0353a 644 uint8_t RESERVED5[7];
tushki7 0:60d829a0353a 645 __IO uint8_t TER;
tushki7 0:60d829a0353a 646 uint8_t RESERVED6[39];
tushki7 0:60d829a0353a 647 __I uint8_t FIFOLVL;
tushki7 0:60d829a0353a 648 } LPC_UART_TypeDef;
tushki7 0:60d829a0353a 649 #else
tushki7 0:60d829a0353a 650 typedef struct
tushki7 0:60d829a0353a 651 {
tushki7 0:60d829a0353a 652 union
tushki7 0:60d829a0353a 653 {
tushki7 0:60d829a0353a 654 __I uint8_t RBR;
tushki7 0:60d829a0353a 655 __O uint8_t THR;
tushki7 0:60d829a0353a 656 __IO uint8_t DLL;
tushki7 0:60d829a0353a 657 uint32_t RESERVED0;
tushki7 0:60d829a0353a 658 };
tushki7 0:60d829a0353a 659 union
tushki7 0:60d829a0353a 660 {
tushki7 0:60d829a0353a 661 __IO uint8_t DLM;
tushki7 0:60d829a0353a 662 __IO uint32_t IER;
tushki7 0:60d829a0353a 663 };
tushki7 0:60d829a0353a 664 union
tushki7 0:60d829a0353a 665 {
tushki7 0:60d829a0353a 666 __I uint32_t IIR;
tushki7 0:60d829a0353a 667 __O uint8_t FCR;
tushki7 0:60d829a0353a 668 };
tushki7 0:60d829a0353a 669 __IO uint8_t LCR;
tushki7 0:60d829a0353a 670 uint8_t RESERVED1[7];//Reserved
tushki7 0:60d829a0353a 671 __I uint8_t LSR;
tushki7 0:60d829a0353a 672 uint8_t RESERVED2[7];//Reserved
tushki7 0:60d829a0353a 673 __IO uint8_t SCR;
tushki7 0:60d829a0353a 674 uint8_t RESERVED3[3];//Reserved
tushki7 0:60d829a0353a 675 __IO uint32_t ACR;
tushki7 0:60d829a0353a 676 __IO uint8_t ICR;
tushki7 0:60d829a0353a 677 uint8_t RESERVED4[3];//Reserved
tushki7 0:60d829a0353a 678 __IO uint8_t FDR;
tushki7 0:60d829a0353a 679 uint8_t RESERVED5[7];//Reserved
tushki7 0:60d829a0353a 680 __IO uint8_t TER;
tushki7 0:60d829a0353a 681 uint8_t RESERVED8[27];//Reserved
tushki7 0:60d829a0353a 682 __IO uint8_t RS485CTRL;
tushki7 0:60d829a0353a 683 uint8_t RESERVED9[3];//Reserved
tushki7 0:60d829a0353a 684 __IO uint8_t ADRMATCH;
tushki7 0:60d829a0353a 685 uint8_t RESERVED10[3];//Reserved
tushki7 0:60d829a0353a 686 __IO uint8_t RS485DLY;
tushki7 0:60d829a0353a 687 uint8_t RESERVED11[3];//Reserved
tushki7 0:60d829a0353a 688 __I uint8_t FIFOLVL;
tushki7 0:60d829a0353a 689 }LPC_UART_TypeDef;
tushki7 0:60d829a0353a 690 #endif
tushki7 0:60d829a0353a 691
tushki7 0:60d829a0353a 692
tushki7 0:60d829a0353a 693 typedef struct
tushki7 0:60d829a0353a 694 {
tushki7 0:60d829a0353a 695 union {
tushki7 0:60d829a0353a 696 __I uint8_t RBR;
tushki7 0:60d829a0353a 697 __O uint8_t THR;
tushki7 0:60d829a0353a 698 __IO uint8_t DLL;
tushki7 0:60d829a0353a 699 uint32_t RESERVED0;
tushki7 0:60d829a0353a 700 };
tushki7 0:60d829a0353a 701 union {
tushki7 0:60d829a0353a 702 __IO uint8_t DLM;
tushki7 0:60d829a0353a 703 __IO uint32_t IER;
tushki7 0:60d829a0353a 704 };
tushki7 0:60d829a0353a 705 union {
tushki7 0:60d829a0353a 706 __I uint32_t IIR;
tushki7 0:60d829a0353a 707 __O uint8_t FCR;
tushki7 0:60d829a0353a 708 };
tushki7 0:60d829a0353a 709 __IO uint8_t LCR;
tushki7 0:60d829a0353a 710 uint8_t RESERVED1[3];
tushki7 0:60d829a0353a 711 __IO uint8_t MCR;
tushki7 0:60d829a0353a 712 uint8_t RESERVED2[3];
tushki7 0:60d829a0353a 713 __I uint8_t LSR;
tushki7 0:60d829a0353a 714 uint8_t RESERVED3[3];
tushki7 0:60d829a0353a 715 __I uint8_t MSR;
tushki7 0:60d829a0353a 716 uint8_t RESERVED4[3];
tushki7 0:60d829a0353a 717 __IO uint8_t SCR;
tushki7 0:60d829a0353a 718 uint8_t RESERVED5[3];
tushki7 0:60d829a0353a 719 __IO uint32_t ACR;
tushki7 0:60d829a0353a 720 uint32_t RESERVED6;
tushki7 0:60d829a0353a 721 __IO uint32_t FDR;
tushki7 0:60d829a0353a 722 uint32_t RESERVED7;
tushki7 0:60d829a0353a 723 __IO uint8_t TER;
tushki7 0:60d829a0353a 724 uint8_t RESERVED8[27];
tushki7 0:60d829a0353a 725 __IO uint8_t RS485CTRL;
tushki7 0:60d829a0353a 726 uint8_t RESERVED9[3];
tushki7 0:60d829a0353a 727 __IO uint8_t ADRMATCH;
tushki7 0:60d829a0353a 728 uint8_t RESERVED10[3];
tushki7 0:60d829a0353a 729 __IO uint8_t RS485DLY;
tushki7 0:60d829a0353a 730 uint8_t RESERVED11[3];
tushki7 0:60d829a0353a 731 __I uint8_t FIFOLVL;
tushki7 0:60d829a0353a 732 } LPC_UART1_TypeDef;
tushki7 0:60d829a0353a 733
tushki7 0:60d829a0353a 734 typedef struct
tushki7 0:60d829a0353a 735 {
tushki7 0:60d829a0353a 736 union {
tushki7 0:60d829a0353a 737 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
tushki7 0:60d829a0353a 738 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
tushki7 0:60d829a0353a 739 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
tushki7 0:60d829a0353a 740 };
tushki7 0:60d829a0353a 741 union {
tushki7 0:60d829a0353a 742 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
tushki7 0:60d829a0353a 743 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
tushki7 0:60d829a0353a 744 };
tushki7 0:60d829a0353a 745 union {
tushki7 0:60d829a0353a 746 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
tushki7 0:60d829a0353a 747 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
tushki7 0:60d829a0353a 748 };
tushki7 0:60d829a0353a 749 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
tushki7 0:60d829a0353a 750 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
tushki7 0:60d829a0353a 751 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
tushki7 0:60d829a0353a 752 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
tushki7 0:60d829a0353a 753 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
tushki7 0:60d829a0353a 754 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
tushki7 0:60d829a0353a 755 __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */
tushki7 0:60d829a0353a 756 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
tushki7 0:60d829a0353a 757 __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */
tushki7 0:60d829a0353a 758 __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */
tushki7 0:60d829a0353a 759 __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */
tushki7 0:60d829a0353a 760 uint32_t RESERVED0[2];
tushki7 0:60d829a0353a 761 __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
tushki7 0:60d829a0353a 762 uint32_t RESERVED1;
tushki7 0:60d829a0353a 763 __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
tushki7 0:60d829a0353a 764 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
tushki7 0:60d829a0353a 765 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
tushki7 0:60d829a0353a 766 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
tushki7 0:60d829a0353a 767 __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
tushki7 0:60d829a0353a 768 __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */
tushki7 0:60d829a0353a 769 uint32_t RESERVED2[989];
tushki7 0:60d829a0353a 770 __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */
tushki7 0:60d829a0353a 771 __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
tushki7 0:60d829a0353a 772 __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
tushki7 0:60d829a0353a 773 __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */
tushki7 0:60d829a0353a 774 __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
tushki7 0:60d829a0353a 775 __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
tushki7 0:60d829a0353a 776 __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
tushki7 0:60d829a0353a 777 uint32_t RESERVED3[3];
tushki7 0:60d829a0353a 778 __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */
tushki7 0:60d829a0353a 779 } LPC_UART4_TypeDef;
tushki7 0:60d829a0353a 780 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
tushki7 0:60d829a0353a 781 typedef struct
tushki7 0:60d829a0353a 782 {
tushki7 0:60d829a0353a 783 __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
tushki7 0:60d829a0353a 784 __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
tushki7 0:60d829a0353a 785 __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
tushki7 0:60d829a0353a 786 __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
tushki7 0:60d829a0353a 787 __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
tushki7 0:60d829a0353a 788 __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
tushki7 0:60d829a0353a 789 __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
tushki7 0:60d829a0353a 790 __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
tushki7 0:60d829a0353a 791 __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
tushki7 0:60d829a0353a 792 __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
tushki7 0:60d829a0353a 793 __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
tushki7 0:60d829a0353a 794 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
tushki7 0:60d829a0353a 795 __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
tushki7 0:60d829a0353a 796 __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
tushki7 0:60d829a0353a 797 __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
tushki7 0:60d829a0353a 798 __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
tushki7 0:60d829a0353a 799 } LPC_I2C_TypeDef;
tushki7 0:60d829a0353a 800
tushki7 0:60d829a0353a 801 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
tushki7 0:60d829a0353a 802 typedef struct
tushki7 0:60d829a0353a 803 {
tushki7 0:60d829a0353a 804 __IO uint8_t ILR;
tushki7 0:60d829a0353a 805 uint8_t RESERVED0[7];
tushki7 0:60d829a0353a 806 __IO uint8_t CCR;
tushki7 0:60d829a0353a 807 uint8_t RESERVED1[3];
tushki7 0:60d829a0353a 808 __IO uint8_t CIIR;
tushki7 0:60d829a0353a 809 uint8_t RESERVED2[3];
tushki7 0:60d829a0353a 810 __IO uint8_t AMR;
tushki7 0:60d829a0353a 811 uint8_t RESERVED3[3];
tushki7 0:60d829a0353a 812 __I uint32_t CTIME0;
tushki7 0:60d829a0353a 813 __I uint32_t CTIME1;
tushki7 0:60d829a0353a 814 __I uint32_t CTIME2;
tushki7 0:60d829a0353a 815 __IO uint8_t SEC;
tushki7 0:60d829a0353a 816 uint8_t RESERVED4[3];
tushki7 0:60d829a0353a 817 __IO uint8_t MIN;
tushki7 0:60d829a0353a 818 uint8_t RESERVED5[3];
tushki7 0:60d829a0353a 819 __IO uint8_t HOUR;
tushki7 0:60d829a0353a 820 uint8_t RESERVED6[3];
tushki7 0:60d829a0353a 821 __IO uint8_t DOM;
tushki7 0:60d829a0353a 822 uint8_t RESERVED7[3];
tushki7 0:60d829a0353a 823 __IO uint8_t DOW;
tushki7 0:60d829a0353a 824 uint8_t RESERVED8[3];
tushki7 0:60d829a0353a 825 __IO uint16_t DOY;
tushki7 0:60d829a0353a 826 uint16_t RESERVED9;
tushki7 0:60d829a0353a 827 __IO uint8_t MONTH;
tushki7 0:60d829a0353a 828 uint8_t RESERVED10[3];
tushki7 0:60d829a0353a 829 __IO uint16_t YEAR;
tushki7 0:60d829a0353a 830 uint16_t RESERVED11;
tushki7 0:60d829a0353a 831 __IO uint32_t CALIBRATION;
tushki7 0:60d829a0353a 832 __IO uint32_t GPREG0;
tushki7 0:60d829a0353a 833 __IO uint32_t GPREG1;
tushki7 0:60d829a0353a 834 __IO uint32_t GPREG2;
tushki7 0:60d829a0353a 835 __IO uint32_t GPREG3;
tushki7 0:60d829a0353a 836 __IO uint32_t GPREG4;
tushki7 0:60d829a0353a 837 __IO uint8_t RTC_AUXEN;
tushki7 0:60d829a0353a 838 uint8_t RESERVED12[3];
tushki7 0:60d829a0353a 839 __IO uint8_t RTC_AUX;
tushki7 0:60d829a0353a 840 uint8_t RESERVED13[3];
tushki7 0:60d829a0353a 841 __IO uint8_t ALSEC;
tushki7 0:60d829a0353a 842 uint8_t RESERVED14[3];
tushki7 0:60d829a0353a 843 __IO uint8_t ALMIN;
tushki7 0:60d829a0353a 844 uint8_t RESERVED15[3];
tushki7 0:60d829a0353a 845 __IO uint8_t ALHOUR;
tushki7 0:60d829a0353a 846 uint8_t RESERVED16[3];
tushki7 0:60d829a0353a 847 __IO uint8_t ALDOM;
tushki7 0:60d829a0353a 848 uint8_t RESERVED17[3];
tushki7 0:60d829a0353a 849 __IO uint8_t ALDOW;
tushki7 0:60d829a0353a 850 uint8_t RESERVED18[3];
tushki7 0:60d829a0353a 851 __IO uint16_t ALDOY;
tushki7 0:60d829a0353a 852 uint16_t RESERVED19;
tushki7 0:60d829a0353a 853 __IO uint8_t ALMON;
tushki7 0:60d829a0353a 854 uint8_t RESERVED20[3];
tushki7 0:60d829a0353a 855 __IO uint16_t ALYEAR;
tushki7 0:60d829a0353a 856 uint16_t RESERVED21;
tushki7 0:60d829a0353a 857 __IO uint32_t ERSTATUS;
tushki7 0:60d829a0353a 858 __IO uint32_t ERCONTROL;
tushki7 0:60d829a0353a 859 __IO uint32_t ERCOUNTERS;
tushki7 0:60d829a0353a 860 uint32_t RESERVED22;
tushki7 0:60d829a0353a 861 __IO uint32_t ERFIRSTSTAMP0;
tushki7 0:60d829a0353a 862 __IO uint32_t ERFIRSTSTAMP1;
tushki7 0:60d829a0353a 863 __IO uint32_t ERFIRSTSTAMP2;
tushki7 0:60d829a0353a 864 uint32_t RESERVED23;
tushki7 0:60d829a0353a 865 __IO uint32_t ERLASTSTAMP0;
tushki7 0:60d829a0353a 866 __IO uint32_t ERLASTSTAMP1;
tushki7 0:60d829a0353a 867 __IO uint32_t ERLASTSTAMP2;
tushki7 0:60d829a0353a 868 } LPC_RTC_TypeDef;
tushki7 0:60d829a0353a 869
tushki7 0:60d829a0353a 870
tushki7 0:60d829a0353a 871
tushki7 0:60d829a0353a 872 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
tushki7 0:60d829a0353a 873 typedef struct
tushki7 0:60d829a0353a 874 {
tushki7 0:60d829a0353a 875 __IO uint32_t P0_0; /* 0x000 */
tushki7 0:60d829a0353a 876 __IO uint32_t P0_1;
tushki7 0:60d829a0353a 877 __IO uint32_t P0_2;
tushki7 0:60d829a0353a 878 __IO uint32_t P0_3;
tushki7 0:60d829a0353a 879 __IO uint32_t P0_4;
tushki7 0:60d829a0353a 880 __IO uint32_t P0_5;
tushki7 0:60d829a0353a 881 __IO uint32_t P0_6;
tushki7 0:60d829a0353a 882 __IO uint32_t P0_7;
tushki7 0:60d829a0353a 883
tushki7 0:60d829a0353a 884 __IO uint32_t P0_8; /* 0x020 */
tushki7 0:60d829a0353a 885 __IO uint32_t P0_9;
tushki7 0:60d829a0353a 886 __IO uint32_t P0_10;
tushki7 0:60d829a0353a 887 __IO uint32_t P0_11;
tushki7 0:60d829a0353a 888 __IO uint32_t P0_12;
tushki7 0:60d829a0353a 889 __IO uint32_t P0_13;
tushki7 0:60d829a0353a 890 __IO uint32_t P0_14;
tushki7 0:60d829a0353a 891 __IO uint32_t P0_15;
tushki7 0:60d829a0353a 892
tushki7 0:60d829a0353a 893 __IO uint32_t P0_16; /* 0x040 */
tushki7 0:60d829a0353a 894 __IO uint32_t P0_17;
tushki7 0:60d829a0353a 895 __IO uint32_t P0_18;
tushki7 0:60d829a0353a 896 __IO uint32_t P0_19;
tushki7 0:60d829a0353a 897 __IO uint32_t P0_20;
tushki7 0:60d829a0353a 898 __IO uint32_t P0_21;
tushki7 0:60d829a0353a 899 __IO uint32_t P0_22;
tushki7 0:60d829a0353a 900 __IO uint32_t P0_23;
tushki7 0:60d829a0353a 901
tushki7 0:60d829a0353a 902 __IO uint32_t P0_24; /* 0x060 */
tushki7 0:60d829a0353a 903 __IO uint32_t P0_25;
tushki7 0:60d829a0353a 904 __IO uint32_t P0_26;
tushki7 0:60d829a0353a 905 __IO uint32_t P0_27;
tushki7 0:60d829a0353a 906 __IO uint32_t P0_28;
tushki7 0:60d829a0353a 907 __IO uint32_t P0_29;
tushki7 0:60d829a0353a 908 __IO uint32_t P0_30;
tushki7 0:60d829a0353a 909 __IO uint32_t P0_31;
tushki7 0:60d829a0353a 910
tushki7 0:60d829a0353a 911 __IO uint32_t P1_0; /* 0x080 */
tushki7 0:60d829a0353a 912 __IO uint32_t P1_1;
tushki7 0:60d829a0353a 913 __IO uint32_t P1_2;
tushki7 0:60d829a0353a 914 __IO uint32_t P1_3;
tushki7 0:60d829a0353a 915 __IO uint32_t P1_4;
tushki7 0:60d829a0353a 916 __IO uint32_t P1_5;
tushki7 0:60d829a0353a 917 __IO uint32_t P1_6;
tushki7 0:60d829a0353a 918 __IO uint32_t P1_7;
tushki7 0:60d829a0353a 919
tushki7 0:60d829a0353a 920 __IO uint32_t P1_8; /* 0x0A0 */
tushki7 0:60d829a0353a 921 __IO uint32_t P1_9;
tushki7 0:60d829a0353a 922 __IO uint32_t P1_10;
tushki7 0:60d829a0353a 923 __IO uint32_t P1_11;
tushki7 0:60d829a0353a 924 __IO uint32_t P1_12;
tushki7 0:60d829a0353a 925 __IO uint32_t P1_13;
tushki7 0:60d829a0353a 926 __IO uint32_t P1_14;
tushki7 0:60d829a0353a 927 __IO uint32_t P1_15;
tushki7 0:60d829a0353a 928
tushki7 0:60d829a0353a 929 __IO uint32_t P1_16; /* 0x0C0 */
tushki7 0:60d829a0353a 930 __IO uint32_t P1_17;
tushki7 0:60d829a0353a 931 __IO uint32_t P1_18;
tushki7 0:60d829a0353a 932 __IO uint32_t P1_19;
tushki7 0:60d829a0353a 933 __IO uint32_t P1_20;
tushki7 0:60d829a0353a 934 __IO uint32_t P1_21;
tushki7 0:60d829a0353a 935 __IO uint32_t P1_22;
tushki7 0:60d829a0353a 936 __IO uint32_t P1_23;
tushki7 0:60d829a0353a 937
tushki7 0:60d829a0353a 938 __IO uint32_t P1_24; /* 0x0E0 */
tushki7 0:60d829a0353a 939 __IO uint32_t P1_25;
tushki7 0:60d829a0353a 940 __IO uint32_t P1_26;
tushki7 0:60d829a0353a 941 __IO uint32_t P1_27;
tushki7 0:60d829a0353a 942 __IO uint32_t P1_28;
tushki7 0:60d829a0353a 943 __IO uint32_t P1_29;
tushki7 0:60d829a0353a 944 __IO uint32_t P1_30;
tushki7 0:60d829a0353a 945 __IO uint32_t P1_31;
tushki7 0:60d829a0353a 946
tushki7 0:60d829a0353a 947 __IO uint32_t P2_0; /* 0x100 */
tushki7 0:60d829a0353a 948 __IO uint32_t P2_1;
tushki7 0:60d829a0353a 949 __IO uint32_t P2_2;
tushki7 0:60d829a0353a 950 __IO uint32_t P2_3;
tushki7 0:60d829a0353a 951 __IO uint32_t P2_4;
tushki7 0:60d829a0353a 952 __IO uint32_t P2_5;
tushki7 0:60d829a0353a 953 __IO uint32_t P2_6;
tushki7 0:60d829a0353a 954 __IO uint32_t P2_7;
tushki7 0:60d829a0353a 955
tushki7 0:60d829a0353a 956 __IO uint32_t P2_8; /* 0x120 */
tushki7 0:60d829a0353a 957 __IO uint32_t P2_9;
tushki7 0:60d829a0353a 958 __IO uint32_t P2_10;
tushki7 0:60d829a0353a 959 __IO uint32_t P2_11;
tushki7 0:60d829a0353a 960 __IO uint32_t P2_12;
tushki7 0:60d829a0353a 961 __IO uint32_t P2_13;
tushki7 0:60d829a0353a 962 __IO uint32_t P2_14;
tushki7 0:60d829a0353a 963 __IO uint32_t P2_15;
tushki7 0:60d829a0353a 964
tushki7 0:60d829a0353a 965 __IO uint32_t P2_16; /* 0x140 */
tushki7 0:60d829a0353a 966 __IO uint32_t P2_17;
tushki7 0:60d829a0353a 967 __IO uint32_t P2_18;
tushki7 0:60d829a0353a 968 __IO uint32_t P2_19;
tushki7 0:60d829a0353a 969 __IO uint32_t P2_20;
tushki7 0:60d829a0353a 970 __IO uint32_t P2_21;
tushki7 0:60d829a0353a 971 __IO uint32_t P2_22;
tushki7 0:60d829a0353a 972 __IO uint32_t P2_23;
tushki7 0:60d829a0353a 973
tushki7 0:60d829a0353a 974 __IO uint32_t P2_24; /* 0x160 */
tushki7 0:60d829a0353a 975 __IO uint32_t P2_25;
tushki7 0:60d829a0353a 976 __IO uint32_t P2_26;
tushki7 0:60d829a0353a 977 __IO uint32_t P2_27;
tushki7 0:60d829a0353a 978 __IO uint32_t P2_28;
tushki7 0:60d829a0353a 979 __IO uint32_t P2_29;
tushki7 0:60d829a0353a 980 __IO uint32_t P2_30;
tushki7 0:60d829a0353a 981 __IO uint32_t P2_31;
tushki7 0:60d829a0353a 982
tushki7 0:60d829a0353a 983 __IO uint32_t P3_0; /* 0x180 */
tushki7 0:60d829a0353a 984 __IO uint32_t P3_1;
tushki7 0:60d829a0353a 985 __IO uint32_t P3_2;
tushki7 0:60d829a0353a 986 __IO uint32_t P3_3;
tushki7 0:60d829a0353a 987 __IO uint32_t P3_4;
tushki7 0:60d829a0353a 988 __IO uint32_t P3_5;
tushki7 0:60d829a0353a 989 __IO uint32_t P3_6;
tushki7 0:60d829a0353a 990 __IO uint32_t P3_7;
tushki7 0:60d829a0353a 991
tushki7 0:60d829a0353a 992 __IO uint32_t P3_8; /* 0x1A0 */
tushki7 0:60d829a0353a 993 __IO uint32_t P3_9;
tushki7 0:60d829a0353a 994 __IO uint32_t P3_10;
tushki7 0:60d829a0353a 995 __IO uint32_t P3_11;
tushki7 0:60d829a0353a 996 __IO uint32_t P3_12;
tushki7 0:60d829a0353a 997 __IO uint32_t P3_13;
tushki7 0:60d829a0353a 998 __IO uint32_t P3_14;
tushki7 0:60d829a0353a 999 __IO uint32_t P3_15;
tushki7 0:60d829a0353a 1000
tushki7 0:60d829a0353a 1001 __IO uint32_t P3_16; /* 0x1C0 */
tushki7 0:60d829a0353a 1002 __IO uint32_t P3_17;
tushki7 0:60d829a0353a 1003 __IO uint32_t P3_18;
tushki7 0:60d829a0353a 1004 __IO uint32_t P3_19;
tushki7 0:60d829a0353a 1005 __IO uint32_t P3_20;
tushki7 0:60d829a0353a 1006 __IO uint32_t P3_21;
tushki7 0:60d829a0353a 1007 __IO uint32_t P3_22;
tushki7 0:60d829a0353a 1008 __IO uint32_t P3_23;
tushki7 0:60d829a0353a 1009
tushki7 0:60d829a0353a 1010 __IO uint32_t P3_24; /* 0x1E0 */
tushki7 0:60d829a0353a 1011 __IO uint32_t P3_25;
tushki7 0:60d829a0353a 1012 __IO uint32_t P3_26;
tushki7 0:60d829a0353a 1013 __IO uint32_t P3_27;
tushki7 0:60d829a0353a 1014 __IO uint32_t P3_28;
tushki7 0:60d829a0353a 1015 __IO uint32_t P3_29;
tushki7 0:60d829a0353a 1016 __IO uint32_t P3_30;
tushki7 0:60d829a0353a 1017 __IO uint32_t P3_31;
tushki7 0:60d829a0353a 1018
tushki7 0:60d829a0353a 1019 __IO uint32_t P4_0; /* 0x200 */
tushki7 0:60d829a0353a 1020 __IO uint32_t P4_1;
tushki7 0:60d829a0353a 1021 __IO uint32_t P4_2;
tushki7 0:60d829a0353a 1022 __IO uint32_t P4_3;
tushki7 0:60d829a0353a 1023 __IO uint32_t P4_4;
tushki7 0:60d829a0353a 1024 __IO uint32_t P4_5;
tushki7 0:60d829a0353a 1025 __IO uint32_t P4_6;
tushki7 0:60d829a0353a 1026 __IO uint32_t P4_7;
tushki7 0:60d829a0353a 1027
tushki7 0:60d829a0353a 1028 __IO uint32_t P4_8; /* 0x220 */
tushki7 0:60d829a0353a 1029 __IO uint32_t P4_9;
tushki7 0:60d829a0353a 1030 __IO uint32_t P4_10;
tushki7 0:60d829a0353a 1031 __IO uint32_t P4_11;
tushki7 0:60d829a0353a 1032 __IO uint32_t P4_12;
tushki7 0:60d829a0353a 1033 __IO uint32_t P4_13;
tushki7 0:60d829a0353a 1034 __IO uint32_t P4_14;
tushki7 0:60d829a0353a 1035 __IO uint32_t P4_15;
tushki7 0:60d829a0353a 1036
tushki7 0:60d829a0353a 1037 __IO uint32_t P4_16; /* 0x240 */
tushki7 0:60d829a0353a 1038 __IO uint32_t P4_17;
tushki7 0:60d829a0353a 1039 __IO uint32_t P4_18;
tushki7 0:60d829a0353a 1040 __IO uint32_t P4_19;
tushki7 0:60d829a0353a 1041 __IO uint32_t P4_20;
tushki7 0:60d829a0353a 1042 __IO uint32_t P4_21;
tushki7 0:60d829a0353a 1043 __IO uint32_t P4_22;
tushki7 0:60d829a0353a 1044 __IO uint32_t P4_23;
tushki7 0:60d829a0353a 1045
tushki7 0:60d829a0353a 1046 __IO uint32_t P4_24; /* 0x260 */
tushki7 0:60d829a0353a 1047 __IO uint32_t P4_25;
tushki7 0:60d829a0353a 1048 __IO uint32_t P4_26;
tushki7 0:60d829a0353a 1049 __IO uint32_t P4_27;
tushki7 0:60d829a0353a 1050 __IO uint32_t P4_28;
tushki7 0:60d829a0353a 1051 __IO uint32_t P4_29;
tushki7 0:60d829a0353a 1052 __IO uint32_t P4_30;
tushki7 0:60d829a0353a 1053 __IO uint32_t P4_31;
tushki7 0:60d829a0353a 1054
tushki7 0:60d829a0353a 1055 __IO uint32_t P5_0; /* 0x280 */
tushki7 0:60d829a0353a 1056 __IO uint32_t P5_1;
tushki7 0:60d829a0353a 1057 __IO uint32_t P5_2;
tushki7 0:60d829a0353a 1058 __IO uint32_t P5_3;
tushki7 0:60d829a0353a 1059 __IO uint32_t P5_4; /* 0x290 */
tushki7 0:60d829a0353a 1060 } LPC_IOCON_TypeDef;
tushki7 0:60d829a0353a 1061
tushki7 0:60d829a0353a 1062
tushki7 0:60d829a0353a 1063
tushki7 0:60d829a0353a 1064
tushki7 0:60d829a0353a 1065
tushki7 0:60d829a0353a 1066
tushki7 0:60d829a0353a 1067 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
tushki7 0:60d829a0353a 1068 typedef struct
tushki7 0:60d829a0353a 1069 {
tushki7 0:60d829a0353a 1070 __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
tushki7 0:60d829a0353a 1071 __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
tushki7 0:60d829a0353a 1072 __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
tushki7 0:60d829a0353a 1073 __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
tushki7 0:60d829a0353a 1074 __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
tushki7 0:60d829a0353a 1075 __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
tushki7 0:60d829a0353a 1076 __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
tushki7 0:60d829a0353a 1077 __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
tushki7 0:60d829a0353a 1078 __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
tushki7 0:60d829a0353a 1079 __IO uint32_t DMACR;
tushki7 0:60d829a0353a 1080 } LPC_SSP_TypeDef;
tushki7 0:60d829a0353a 1081
tushki7 0:60d829a0353a 1082 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
tushki7 0:60d829a0353a 1083 typedef struct
tushki7 0:60d829a0353a 1084 {
tushki7 0:60d829a0353a 1085 __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
tushki7 0:60d829a0353a 1086 __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
tushki7 0:60d829a0353a 1087 uint32_t RESERVED0;
tushki7 0:60d829a0353a 1088 __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
tushki7 0:60d829a0353a 1089 __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
tushki7 0:60d829a0353a 1090 __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
tushki7 0:60d829a0353a 1091 __IO uint32_t ADTRM;
tushki7 0:60d829a0353a 1092 } LPC_ADC_TypeDef;
tushki7 0:60d829a0353a 1093
tushki7 0:60d829a0353a 1094 /*------------- Controller Area Network (CAN) --------------------------------*/
tushki7 0:60d829a0353a 1095 typedef struct
tushki7 0:60d829a0353a 1096 {
tushki7 0:60d829a0353a 1097 __IO uint32_t mask[512]; /* ID Masks */
tushki7 0:60d829a0353a 1098 } LPC_CANAF_RAM_TypeDef;
tushki7 0:60d829a0353a 1099
tushki7 0:60d829a0353a 1100 typedef struct /* Acceptance Filter Registers */
tushki7 0:60d829a0353a 1101 {
tushki7 0:60d829a0353a 1102 ///Offset: 0x00000000 - Acceptance Filter Register
tushki7 0:60d829a0353a 1103 __IO uint32_t AFMR;
tushki7 0:60d829a0353a 1104
tushki7 0:60d829a0353a 1105 ///Offset: 0x00000004 - Standard Frame Individual Start Address Register
tushki7 0:60d829a0353a 1106 __IO uint32_t SFF_sa;
tushki7 0:60d829a0353a 1107
tushki7 0:60d829a0353a 1108 ///Offset: 0x00000008 - Standard Frame Group Start Address Register
tushki7 0:60d829a0353a 1109 __IO uint32_t SFF_GRP_sa;
tushki7 0:60d829a0353a 1110
tushki7 0:60d829a0353a 1111 ///Offset: 0x0000000C - Extended Frame Start Address Register
tushki7 0:60d829a0353a 1112 __IO uint32_t EFF_sa;
tushki7 0:60d829a0353a 1113
tushki7 0:60d829a0353a 1114 ///Offset: 0x00000010 - Extended Frame Group Start Address Register
tushki7 0:60d829a0353a 1115 __IO uint32_t EFF_GRP_sa;
tushki7 0:60d829a0353a 1116
tushki7 0:60d829a0353a 1117 ///Offset: 0x00000014 - End of AF Tables register
tushki7 0:60d829a0353a 1118 __IO uint32_t ENDofTable;
tushki7 0:60d829a0353a 1119
tushki7 0:60d829a0353a 1120 ///Offset: 0x00000018 - LUT Error Address register
tushki7 0:60d829a0353a 1121 __I uint32_t LUTerrAd;
tushki7 0:60d829a0353a 1122
tushki7 0:60d829a0353a 1123 ///Offset: 0x0000001C - LUT Error Register
tushki7 0:60d829a0353a 1124 __I uint32_t LUTerr;
tushki7 0:60d829a0353a 1125
tushki7 0:60d829a0353a 1126 ///Offset: 0x00000020 - CAN Central Transmit Status Register
tushki7 0:60d829a0353a 1127 __IO uint32_t FCANIE;
tushki7 0:60d829a0353a 1128
tushki7 0:60d829a0353a 1129 ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
tushki7 0:60d829a0353a 1130 __IO uint32_t FCANIC0;
tushki7 0:60d829a0353a 1131
tushki7 0:60d829a0353a 1132 ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
tushki7 0:60d829a0353a 1133 __IO uint32_t FCANIC1;
tushki7 0:60d829a0353a 1134 } LPC_CANAF_TypeDef;
tushki7 0:60d829a0353a 1135
tushki7 0:60d829a0353a 1136 typedef struct /* Central Registers */
tushki7 0:60d829a0353a 1137 {
tushki7 0:60d829a0353a 1138 __I uint32_t TxSR;
tushki7 0:60d829a0353a 1139 __I uint32_t RxSR;
tushki7 0:60d829a0353a 1140 __I uint32_t MSR;
tushki7 0:60d829a0353a 1141 } LPC_CANCR_TypeDef;
tushki7 0:60d829a0353a 1142
tushki7 0:60d829a0353a 1143 typedef struct /* Controller Registers */
tushki7 0:60d829a0353a 1144 {
tushki7 0:60d829a0353a 1145 ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
tushki7 0:60d829a0353a 1146 __IO uint32_t MOD;
tushki7 0:60d829a0353a 1147
tushki7 0:60d829a0353a 1148 ///Offset: 0x00000004 - Command bits that affect the state
tushki7 0:60d829a0353a 1149 __O uint32_t CMR;
tushki7 0:60d829a0353a 1150
tushki7 0:60d829a0353a 1151 ///Offset: 0x00000008 - Global Controller Status and Error Counters
tushki7 0:60d829a0353a 1152 __IO uint32_t GSR;
tushki7 0:60d829a0353a 1153
tushki7 0:60d829a0353a 1154 ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
tushki7 0:60d829a0353a 1155 __I uint32_t ICR;
tushki7 0:60d829a0353a 1156
tushki7 0:60d829a0353a 1157 ///Offset: 0x00000010 - Interrupt Enable Register
tushki7 0:60d829a0353a 1158 __IO uint32_t IER;
tushki7 0:60d829a0353a 1159
tushki7 0:60d829a0353a 1160 ///Offset: 0x00000014 - Bus Timing Register
tushki7 0:60d829a0353a 1161 __IO uint32_t BTR;
tushki7 0:60d829a0353a 1162
tushki7 0:60d829a0353a 1163 ///Offset: 0x00000018 - Error Warning Limit
tushki7 0:60d829a0353a 1164 __IO uint32_t EWL;
tushki7 0:60d829a0353a 1165
tushki7 0:60d829a0353a 1166 ///Offset: 0x0000001C - Status Register
tushki7 0:60d829a0353a 1167 __I uint32_t SR;
tushki7 0:60d829a0353a 1168
tushki7 0:60d829a0353a 1169 ///Offset: 0x00000020 - Receive frame status
tushki7 0:60d829a0353a 1170 __IO uint32_t RFS;
tushki7 0:60d829a0353a 1171
tushki7 0:60d829a0353a 1172 ///Offset: 0x00000024 - Received Identifier
tushki7 0:60d829a0353a 1173 __IO uint32_t RID;
tushki7 0:60d829a0353a 1174
tushki7 0:60d829a0353a 1175 ///Offset: 0x00000028 - Received data bytes 1-4
tushki7 0:60d829a0353a 1176 __IO uint32_t RDA;
tushki7 0:60d829a0353a 1177
tushki7 0:60d829a0353a 1178 ///Offset: 0x0000002C - Received data bytes 5-8
tushki7 0:60d829a0353a 1179 __IO uint32_t RDB;
tushki7 0:60d829a0353a 1180
tushki7 0:60d829a0353a 1181 ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
tushki7 0:60d829a0353a 1182 __IO uint32_t TFI1;
tushki7 0:60d829a0353a 1183
tushki7 0:60d829a0353a 1184 ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
tushki7 0:60d829a0353a 1185 __IO uint32_t TID1;
tushki7 0:60d829a0353a 1186
tushki7 0:60d829a0353a 1187 ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
tushki7 0:60d829a0353a 1188 __IO uint32_t TDA1;
tushki7 0:60d829a0353a 1189
tushki7 0:60d829a0353a 1190 ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
tushki7 0:60d829a0353a 1191 __IO uint32_t TDB1;
tushki7 0:60d829a0353a 1192
tushki7 0:60d829a0353a 1193 ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
tushki7 0:60d829a0353a 1194 __IO uint32_t TFI2;
tushki7 0:60d829a0353a 1195
tushki7 0:60d829a0353a 1196 ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
tushki7 0:60d829a0353a 1197 __IO uint32_t TID2;
tushki7 0:60d829a0353a 1198
tushki7 0:60d829a0353a 1199 ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
tushki7 0:60d829a0353a 1200 __IO uint32_t TDA2;
tushki7 0:60d829a0353a 1201
tushki7 0:60d829a0353a 1202 ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
tushki7 0:60d829a0353a 1203 __IO uint32_t TDB2;
tushki7 0:60d829a0353a 1204
tushki7 0:60d829a0353a 1205 ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
tushki7 0:60d829a0353a 1206 __IO uint32_t TFI3;
tushki7 0:60d829a0353a 1207
tushki7 0:60d829a0353a 1208 ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
tushki7 0:60d829a0353a 1209 __IO uint32_t TID3;
tushki7 0:60d829a0353a 1210
tushki7 0:60d829a0353a 1211 ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
tushki7 0:60d829a0353a 1212 __IO uint32_t TDA3;
tushki7 0:60d829a0353a 1213
tushki7 0:60d829a0353a 1214 ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
tushki7 0:60d829a0353a 1215 __IO uint32_t TDB3;
tushki7 0:60d829a0353a 1216 } LPC_CAN_TypeDef;
tushki7 0:60d829a0353a 1217
tushki7 0:60d829a0353a 1218 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
tushki7 0:60d829a0353a 1219 typedef struct
tushki7 0:60d829a0353a 1220 {
tushki7 0:60d829a0353a 1221 __IO uint32_t CR;
tushki7 0:60d829a0353a 1222 __IO uint32_t CTRL;
tushki7 0:60d829a0353a 1223 __IO uint32_t CNTVAL;
tushki7 0:60d829a0353a 1224 } LPC_DAC_TypeDef;
tushki7 0:60d829a0353a 1225
tushki7 0:60d829a0353a 1226
tushki7 0:60d829a0353a 1227 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
tushki7 0:60d829a0353a 1228 typedef struct
tushki7 0:60d829a0353a 1229 {
tushki7 0:60d829a0353a 1230 __IO uint32_t DAO;
tushki7 0:60d829a0353a 1231 __IO uint32_t DAI;
tushki7 0:60d829a0353a 1232 __O uint32_t TXFIFO;
tushki7 0:60d829a0353a 1233 __I uint32_t RXFIFO;
tushki7 0:60d829a0353a 1234 __I uint32_t STATE;
tushki7 0:60d829a0353a 1235 __IO uint32_t DMA1;
tushki7 0:60d829a0353a 1236 __IO uint32_t DMA2;
tushki7 0:60d829a0353a 1237 __IO uint32_t IRQ;
tushki7 0:60d829a0353a 1238 __IO uint32_t TXRATE;
tushki7 0:60d829a0353a 1239 __IO uint32_t RXRATE;
tushki7 0:60d829a0353a 1240 __IO uint32_t TXBITRATE;
tushki7 0:60d829a0353a 1241 __IO uint32_t RXBITRATE;
tushki7 0:60d829a0353a 1242 __IO uint32_t TXMODE;
tushki7 0:60d829a0353a 1243 __IO uint32_t RXMODE;
tushki7 0:60d829a0353a 1244 } LPC_I2S_TypeDef;
tushki7 0:60d829a0353a 1245
tushki7 0:60d829a0353a 1246
tushki7 0:60d829a0353a 1247
tushki7 0:60d829a0353a 1248
tushki7 0:60d829a0353a 1249
tushki7 0:60d829a0353a 1250
tushki7 0:60d829a0353a 1251 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
tushki7 0:60d829a0353a 1252 typedef struct
tushki7 0:60d829a0353a 1253 {
tushki7 0:60d829a0353a 1254 __I uint32_t CON;
tushki7 0:60d829a0353a 1255 __O uint32_t CON_SET;
tushki7 0:60d829a0353a 1256 __O uint32_t CON_CLR;
tushki7 0:60d829a0353a 1257 __I uint32_t CAPCON;
tushki7 0:60d829a0353a 1258 __O uint32_t CAPCON_SET;
tushki7 0:60d829a0353a 1259 __O uint32_t CAPCON_CLR;
tushki7 0:60d829a0353a 1260 __IO uint32_t TC0;
tushki7 0:60d829a0353a 1261 __IO uint32_t TC1;
tushki7 0:60d829a0353a 1262 __IO uint32_t TC2;
tushki7 0:60d829a0353a 1263 __IO uint32_t LIM0;
tushki7 0:60d829a0353a 1264 __IO uint32_t LIM1;
tushki7 0:60d829a0353a 1265 __IO uint32_t LIM2;
tushki7 0:60d829a0353a 1266 __IO uint32_t MAT0;
tushki7 0:60d829a0353a 1267 __IO uint32_t MAT1;
tushki7 0:60d829a0353a 1268 __IO uint32_t MAT2;
tushki7 0:60d829a0353a 1269 __IO uint32_t DT;
tushki7 0:60d829a0353a 1270 __IO uint32_t CP;
tushki7 0:60d829a0353a 1271 __IO uint32_t CAP0;
tushki7 0:60d829a0353a 1272 __IO uint32_t CAP1;
tushki7 0:60d829a0353a 1273 __IO uint32_t CAP2;
tushki7 0:60d829a0353a 1274 __I uint32_t INTEN;
tushki7 0:60d829a0353a 1275 __O uint32_t INTEN_SET;
tushki7 0:60d829a0353a 1276 __O uint32_t INTEN_CLR;
tushki7 0:60d829a0353a 1277 __I uint32_t CNTCON;
tushki7 0:60d829a0353a 1278 __O uint32_t CNTCON_SET;
tushki7 0:60d829a0353a 1279 __O uint32_t CNTCON_CLR;
tushki7 0:60d829a0353a 1280 __I uint32_t INTF;
tushki7 0:60d829a0353a 1281 __O uint32_t INTF_SET;
tushki7 0:60d829a0353a 1282 __O uint32_t INTF_CLR;
tushki7 0:60d829a0353a 1283 __O uint32_t CAP_CLR;
tushki7 0:60d829a0353a 1284 } LPC_MCPWM_TypeDef;
tushki7 0:60d829a0353a 1285
tushki7 0:60d829a0353a 1286 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
tushki7 0:60d829a0353a 1287 typedef struct
tushki7 0:60d829a0353a 1288 {
tushki7 0:60d829a0353a 1289 __O uint32_t CON;
tushki7 0:60d829a0353a 1290 __I uint32_t STAT;
tushki7 0:60d829a0353a 1291 __IO uint32_t CONF;
tushki7 0:60d829a0353a 1292 __I uint32_t POS;
tushki7 0:60d829a0353a 1293 __IO uint32_t MAXPOS;
tushki7 0:60d829a0353a 1294 __IO uint32_t CMPOS0;
tushki7 0:60d829a0353a 1295 __IO uint32_t CMPOS1;
tushki7 0:60d829a0353a 1296 __IO uint32_t CMPOS2;
tushki7 0:60d829a0353a 1297 __I uint32_t INXCNT;
tushki7 0:60d829a0353a 1298 __IO uint32_t INXCMP0;
tushki7 0:60d829a0353a 1299 __IO uint32_t LOAD;
tushki7 0:60d829a0353a 1300 __I uint32_t TIME;
tushki7 0:60d829a0353a 1301 __I uint32_t VEL;
tushki7 0:60d829a0353a 1302 __I uint32_t CAP;
tushki7 0:60d829a0353a 1303 __IO uint32_t VELCOMP;
tushki7 0:60d829a0353a 1304 __IO uint32_t FILTERPHA;
tushki7 0:60d829a0353a 1305 __IO uint32_t FILTERPHB;
tushki7 0:60d829a0353a 1306 __IO uint32_t FILTERINX;
tushki7 0:60d829a0353a 1307 __IO uint32_t WINDOW;
tushki7 0:60d829a0353a 1308 __IO uint32_t INXCMP1;
tushki7 0:60d829a0353a 1309 __IO uint32_t INXCMP2;
tushki7 0:60d829a0353a 1310 uint32_t RESERVED0[993];
tushki7 0:60d829a0353a 1311 __O uint32_t IEC;
tushki7 0:60d829a0353a 1312 __O uint32_t IES;
tushki7 0:60d829a0353a 1313 __I uint32_t INTSTAT;
tushki7 0:60d829a0353a 1314 __I uint32_t IE;
tushki7 0:60d829a0353a 1315 __O uint32_t CLR;
tushki7 0:60d829a0353a 1316 __O uint32_t SET;
tushki7 0:60d829a0353a 1317 } LPC_QEI_TypeDef;
tushki7 0:60d829a0353a 1318
tushki7 0:60d829a0353a 1319 /*------------- SD/MMC card Interface (MCI)-----------------------------------*/
tushki7 0:60d829a0353a 1320 typedef struct
tushki7 0:60d829a0353a 1321 {
tushki7 0:60d829a0353a 1322 __IO uint32_t POWER;
tushki7 0:60d829a0353a 1323 __IO uint32_t CLOCK;
tushki7 0:60d829a0353a 1324 __IO uint32_t ARGUMENT;
tushki7 0:60d829a0353a 1325 __IO uint32_t COMMAND;
tushki7 0:60d829a0353a 1326 __I uint32_t RESP_CMD;
tushki7 0:60d829a0353a 1327 __I uint32_t RESP0;
tushki7 0:60d829a0353a 1328 __I uint32_t RESP1;
tushki7 0:60d829a0353a 1329 __I uint32_t RESP2;
tushki7 0:60d829a0353a 1330 __I uint32_t RESP3;
tushki7 0:60d829a0353a 1331 __IO uint32_t DATATMR;
tushki7 0:60d829a0353a 1332 __IO uint32_t DATALEN;
tushki7 0:60d829a0353a 1333 __IO uint32_t DATACTRL;
tushki7 0:60d829a0353a 1334 __I uint32_t DATACNT;
tushki7 0:60d829a0353a 1335 __I uint32_t STATUS;
tushki7 0:60d829a0353a 1336 __O uint32_t CLEAR;
tushki7 0:60d829a0353a 1337 __IO uint32_t MASK0;
tushki7 0:60d829a0353a 1338 uint32_t RESERVED0[2];
tushki7 0:60d829a0353a 1339 __I uint32_t FIFOCNT;
tushki7 0:60d829a0353a 1340 uint32_t RESERVED1[13];
tushki7 0:60d829a0353a 1341 __IO uint32_t FIFO[16];
tushki7 0:60d829a0353a 1342 } LPC_MCI_TypeDef;
tushki7 0:60d829a0353a 1343
tushki7 0:60d829a0353a 1344
tushki7 0:60d829a0353a 1345
tushki7 0:60d829a0353a 1346
tushki7 0:60d829a0353a 1347
tushki7 0:60d829a0353a 1348
tushki7 0:60d829a0353a 1349
tushki7 0:60d829a0353a 1350
tushki7 0:60d829a0353a 1351
tushki7 0:60d829a0353a 1352
tushki7 0:60d829a0353a 1353 /*------------- EEPROM Controller (EEPROM) -----------------------------------*/
tushki7 0:60d829a0353a 1354 typedef struct
tushki7 0:60d829a0353a 1355 {
tushki7 0:60d829a0353a 1356 __IO uint32_t CMD; /* 0x0080 */
tushki7 0:60d829a0353a 1357 __IO uint32_t ADDR;
tushki7 0:60d829a0353a 1358 __IO uint32_t WDATA;
tushki7 0:60d829a0353a 1359 __IO uint32_t RDATA;
tushki7 0:60d829a0353a 1360 __IO uint32_t WSTATE; /* 0x0090 */
tushki7 0:60d829a0353a 1361 __IO uint32_t CLKDIV;
tushki7 0:60d829a0353a 1362 __IO uint32_t PWRDWN; /* 0x0098 */
tushki7 0:60d829a0353a 1363 uint32_t RESERVED0[975];
tushki7 0:60d829a0353a 1364 __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */
tushki7 0:60d829a0353a 1365 __IO uint32_t INT_SET_ENABLE;
tushki7 0:60d829a0353a 1366 __IO uint32_t INT_STATUS; /* 0x0FE0 */
tushki7 0:60d829a0353a 1367 __IO uint32_t INT_ENABLE;
tushki7 0:60d829a0353a 1368 __IO uint32_t INT_CLR_STATUS;
tushki7 0:60d829a0353a 1369 __IO uint32_t INT_SET_STATUS;
tushki7 0:60d829a0353a 1370 } LPC_EEPROM_TypeDef;
tushki7 0:60d829a0353a 1371
tushki7 0:60d829a0353a 1372
tushki7 0:60d829a0353a 1373 /*------------- COMPARATOR ----------------------------------------------------*/
tushki7 0:60d829a0353a 1374
tushki7 0:60d829a0353a 1375 typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */
tushki7 0:60d829a0353a 1376 __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */
tushki7 0:60d829a0353a 1377 __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */
tushki7 0:60d829a0353a 1378 __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */
tushki7 0:60d829a0353a 1379 } LPC_COMPARATOR_Type;
tushki7 0:60d829a0353a 1380
tushki7 0:60d829a0353a 1381
tushki7 0:60d829a0353a 1382 #if defined ( __CC_ARM )
tushki7 0:60d829a0353a 1383 #pragma no_anon_unions
tushki7 0:60d829a0353a 1384 #endif
tushki7 0:60d829a0353a 1385
tushki7 0:60d829a0353a 1386 /******************************************************************************/
tushki7 0:60d829a0353a 1387 /* Peripheral memory map */
tushki7 0:60d829a0353a 1388 /******************************************************************************/
tushki7 0:60d829a0353a 1389 /* Base addresses */
tushki7 0:60d829a0353a 1390 #define LPC_FLASH_BASE (0x00000000UL)
tushki7 0:60d829a0353a 1391 #define LPC_RAM_BASE (0x10000000UL)
tushki7 0:60d829a0353a 1392 #define LPC_PERI_RAM_BASE (0x20000000UL)
tushki7 0:60d829a0353a 1393 #define LPC_APB0_BASE (0x40000000UL)
tushki7 0:60d829a0353a 1394 #define LPC_APB1_BASE (0x40080000UL)
tushki7 0:60d829a0353a 1395 #define LPC_AHBRAM1_BASE (0x20004000UL)
tushki7 0:60d829a0353a 1396 #define LPC_AHB_BASE (0x20080000UL)
tushki7 0:60d829a0353a 1397 #define LPC_CM3_BASE (0xE0000000UL)
tushki7 0:60d829a0353a 1398
tushki7 0:60d829a0353a 1399 /* APB0 peripherals */
tushki7 0:60d829a0353a 1400 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
tushki7 0:60d829a0353a 1401 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
tushki7 0:60d829a0353a 1402 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
tushki7 0:60d829a0353a 1403 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
tushki7 0:60d829a0353a 1404 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
tushki7 0:60d829a0353a 1405 #define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000)
tushki7 0:60d829a0353a 1406 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
tushki7 0:60d829a0353a 1407 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
tushki7 0:60d829a0353a 1408 #define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000)
tushki7 0:60d829a0353a 1409 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
tushki7 0:60d829a0353a 1410 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
tushki7 0:60d829a0353a 1411 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000)
tushki7 0:60d829a0353a 1412 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
tushki7 0:60d829a0353a 1413 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
tushki7 0:60d829a0353a 1414 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
tushki7 0:60d829a0353a 1415 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
tushki7 0:60d829a0353a 1416 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
tushki7 0:60d829a0353a 1417 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
tushki7 0:60d829a0353a 1418 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
tushki7 0:60d829a0353a 1419 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
tushki7 0:60d829a0353a 1420
tushki7 0:60d829a0353a 1421 /* APB1 peripherals */
tushki7 0:60d829a0353a 1422 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
tushki7 0:60d829a0353a 1423 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
tushki7 0:60d829a0353a 1424 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
tushki7 0:60d829a0353a 1425 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
tushki7 0:60d829a0353a 1426 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
tushki7 0:60d829a0353a 1427 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
tushki7 0:60d829a0353a 1428 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
tushki7 0:60d829a0353a 1429 #define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000)
tushki7 0:60d829a0353a 1430 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
tushki7 0:60d829a0353a 1431 #define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000)
tushki7 0:60d829a0353a 1432 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
tushki7 0:60d829a0353a 1433 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
tushki7 0:60d829a0353a 1434 #define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000)
tushki7 0:60d829a0353a 1435 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
tushki7 0:60d829a0353a 1436
tushki7 0:60d829a0353a 1437 /* AHB peripherals */
tushki7 0:60d829a0353a 1438 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000)
tushki7 0:60d829a0353a 1439 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100)
tushki7 0:60d829a0353a 1440 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120)
tushki7 0:60d829a0353a 1441 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140)
tushki7 0:60d829a0353a 1442 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160)
tushki7 0:60d829a0353a 1443 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180)
tushki7 0:60d829a0353a 1444 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0)
tushki7 0:60d829a0353a 1445 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0)
tushki7 0:60d829a0353a 1446 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0)
tushki7 0:60d829a0353a 1447 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000)
tushki7 0:60d829a0353a 1448 #define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000)
tushki7 0:60d829a0353a 1449 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
tushki7 0:60d829a0353a 1450 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000)
tushki7 0:60d829a0353a 1451 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000)
tushki7 0:60d829a0353a 1452 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020)
tushki7 0:60d829a0353a 1453 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040)
tushki7 0:60d829a0353a 1454 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060)
tushki7 0:60d829a0353a 1455 #define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080)
tushki7 0:60d829a0353a 1456 #define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0)
tushki7 0:60d829a0353a 1457 #define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000)
tushki7 0:60d829a0353a 1458
tushki7 0:60d829a0353a 1459 #define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080)
tushki7 0:60d829a0353a 1460
tushki7 0:60d829a0353a 1461
tushki7 0:60d829a0353a 1462 /******************************************************************************/
tushki7 0:60d829a0353a 1463 /* Peripheral declaration */
tushki7 0:60d829a0353a 1464 /******************************************************************************/
tushki7 0:60d829a0353a 1465 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
tushki7 0:60d829a0353a 1466 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
tushki7 0:60d829a0353a 1467 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
tushki7 0:60d829a0353a 1468 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
tushki7 0:60d829a0353a 1469 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
tushki7 0:60d829a0353a 1470 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
tushki7 0:60d829a0353a 1471 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
tushki7 0:60d829a0353a 1472 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
tushki7 0:60d829a0353a 1473 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
tushki7 0:60d829a0353a 1474 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
tushki7 0:60d829a0353a 1475 #define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE )
tushki7 0:60d829a0353a 1476 #define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
tushki7 0:60d829a0353a 1477 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
tushki7 0:60d829a0353a 1478 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
tushki7 0:60d829a0353a 1479 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
tushki7 0:60d829a0353a 1480 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
tushki7 0:60d829a0353a 1481 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
tushki7 0:60d829a0353a 1482 #define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE)
tushki7 0:60d829a0353a 1483 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
tushki7 0:60d829a0353a 1484 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
tushki7 0:60d829a0353a 1485 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
tushki7 0:60d829a0353a 1486 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
tushki7 0:60d829a0353a 1487 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
tushki7 0:60d829a0353a 1488 #define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )
tushki7 0:60d829a0353a 1489 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
tushki7 0:60d829a0353a 1490 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
tushki7 0:60d829a0353a 1491 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
tushki7 0:60d829a0353a 1492 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
tushki7 0:60d829a0353a 1493 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
tushki7 0:60d829a0353a 1494 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
tushki7 0:60d829a0353a 1495 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
tushki7 0:60d829a0353a 1496 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
tushki7 0:60d829a0353a 1497 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
tushki7 0:60d829a0353a 1498 #define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
tushki7 0:60d829a0353a 1499 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
tushki7 0:60d829a0353a 1500 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
tushki7 0:60d829a0353a 1501 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
tushki7 0:60d829a0353a 1502 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
tushki7 0:60d829a0353a 1503 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
tushki7 0:60d829a0353a 1504 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
tushki7 0:60d829a0353a 1505 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
tushki7 0:60d829a0353a 1506 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
tushki7 0:60d829a0353a 1507 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
tushki7 0:60d829a0353a 1508 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
tushki7 0:60d829a0353a 1509 #define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE )
tushki7 0:60d829a0353a 1510 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
tushki7 0:60d829a0353a 1511 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
tushki7 0:60d829a0353a 1512 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
tushki7 0:60d829a0353a 1513 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
tushki7 0:60d829a0353a 1514 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
tushki7 0:60d829a0353a 1515 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
tushki7 0:60d829a0353a 1516 #define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )
tushki7 0:60d829a0353a 1517 #define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
tushki7 0:60d829a0353a 1518 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
tushki7 0:60d829a0353a 1519 #define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )
tushki7 0:60d829a0353a 1520
tushki7 0:60d829a0353a 1521
tushki7 0:60d829a0353a 1522
tushki7 0:60d829a0353a 1523 #endif // __LPC407x_8x_177x_8x_H__