Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_LPC1768/LPC17xx.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a 
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /**************************************************************************//**
tushki7 0:60d829a0353a 2 * @file LPC17xx.h
tushki7 0:60d829a0353a 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
tushki7 0:60d829a0353a 4 * NXP LPC17xx Device Series
tushki7 0:60d829a0353a 5 * @version: V1.09
tushki7 0:60d829a0353a 6 * @date: 17. March 2010
tushki7 0:60d829a0353a 7
tushki7 0:60d829a0353a 8 *
tushki7 0:60d829a0353a 9 * @note
tushki7 0:60d829a0353a 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
tushki7 0:60d829a0353a 11 *
tushki7 0:60d829a0353a 12 * @par
tushki7 0:60d829a0353a 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
tushki7 0:60d829a0353a 14 * processor based microcontrollers. This file can be freely distributed
tushki7 0:60d829a0353a 15 * within development tools that are supporting such ARM based processors.
tushki7 0:60d829a0353a 16 *
tushki7 0:60d829a0353a 17 * @par
tushki7 0:60d829a0353a 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
tushki7 0:60d829a0353a 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
tushki7 0:60d829a0353a 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
tushki7 0:60d829a0353a 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
tushki7 0:60d829a0353a 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
tushki7 0:60d829a0353a 23 *
tushki7 0:60d829a0353a 24 ******************************************************************************/
tushki7 0:60d829a0353a 25
tushki7 0:60d829a0353a 26
tushki7 0:60d829a0353a 27 #ifndef __LPC17xx_H__
tushki7 0:60d829a0353a 28 #define __LPC17xx_H__
tushki7 0:60d829a0353a 29
tushki7 0:60d829a0353a 30 /*
tushki7 0:60d829a0353a 31 * ==========================================================================
tushki7 0:60d829a0353a 32 * ---------- Interrupt Number Definition -----------------------------------
tushki7 0:60d829a0353a 33 * ==========================================================================
tushki7 0:60d829a0353a 34 */
tushki7 0:60d829a0353a 35
tushki7 0:60d829a0353a 36 typedef enum IRQn
tushki7 0:60d829a0353a 37 {
tushki7 0:60d829a0353a 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
tushki7 0:60d829a0353a 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
tushki7 0:60d829a0353a 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
tushki7 0:60d829a0353a 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
tushki7 0:60d829a0353a 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
tushki7 0:60d829a0353a 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
tushki7 0:60d829a0353a 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
tushki7 0:60d829a0353a 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
tushki7 0:60d829a0353a 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
tushki7 0:60d829a0353a 47
tushki7 0:60d829a0353a 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
tushki7 0:60d829a0353a 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
tushki7 0:60d829a0353a 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
tushki7 0:60d829a0353a 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
tushki7 0:60d829a0353a 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
tushki7 0:60d829a0353a 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
tushki7 0:60d829a0353a 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
tushki7 0:60d829a0353a 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
tushki7 0:60d829a0353a 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
tushki7 0:60d829a0353a 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
tushki7 0:60d829a0353a 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
tushki7 0:60d829a0353a 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
tushki7 0:60d829a0353a 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
tushki7 0:60d829a0353a 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
tushki7 0:60d829a0353a 62 SPI_IRQn = 13, /*!< SPI Interrupt */
tushki7 0:60d829a0353a 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
tushki7 0:60d829a0353a 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
tushki7 0:60d829a0353a 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
tushki7 0:60d829a0353a 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
tushki7 0:60d829a0353a 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
tushki7 0:60d829a0353a 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
tushki7 0:60d829a0353a 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
tushki7 0:60d829a0353a 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
tushki7 0:60d829a0353a 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
tushki7 0:60d829a0353a 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
tushki7 0:60d829a0353a 73 USB_IRQn = 24, /*!< USB Interrupt */
tushki7 0:60d829a0353a 74 CAN_IRQn = 25, /*!< CAN Interrupt */
tushki7 0:60d829a0353a 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
tushki7 0:60d829a0353a 76 I2S_IRQn = 27, /*!< I2S Interrupt */
tushki7 0:60d829a0353a 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
tushki7 0:60d829a0353a 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
tushki7 0:60d829a0353a 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
tushki7 0:60d829a0353a 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
tushki7 0:60d829a0353a 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
tushki7 0:60d829a0353a 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
tushki7 0:60d829a0353a 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
tushki7 0:60d829a0353a 84 } IRQn_Type;
tushki7 0:60d829a0353a 85
tushki7 0:60d829a0353a 86
tushki7 0:60d829a0353a 87 /*
tushki7 0:60d829a0353a 88 * ==========================================================================
tushki7 0:60d829a0353a 89 * ----------- Processor and Core Peripheral Section ------------------------
tushki7 0:60d829a0353a 90 * ==========================================================================
tushki7 0:60d829a0353a 91 */
tushki7 0:60d829a0353a 92
tushki7 0:60d829a0353a 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
tushki7 0:60d829a0353a 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
tushki7 0:60d829a0353a 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
tushki7 0:60d829a0353a 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
tushki7 0:60d829a0353a 97
tushki7 0:60d829a0353a 98
tushki7 0:60d829a0353a 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
tushki7 0:60d829a0353a 100 #include "system_LPC17xx.h" /* System Header */
tushki7 0:60d829a0353a 101
tushki7 0:60d829a0353a 102
tushki7 0:60d829a0353a 103 /******************************************************************************/
tushki7 0:60d829a0353a 104 /* Device Specific Peripheral registers structures */
tushki7 0:60d829a0353a 105 /******************************************************************************/
tushki7 0:60d829a0353a 106
tushki7 0:60d829a0353a 107 #if defined ( __CC_ARM )
tushki7 0:60d829a0353a 108 #pragma anon_unions
tushki7 0:60d829a0353a 109 #endif
tushki7 0:60d829a0353a 110
tushki7 0:60d829a0353a 111 /*------------- System Control (SC) ------------------------------------------*/
tushki7 0:60d829a0353a 112 typedef struct
tushki7 0:60d829a0353a 113 {
tushki7 0:60d829a0353a 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
tushki7 0:60d829a0353a 115 uint32_t RESERVED0[31];
tushki7 0:60d829a0353a 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
tushki7 0:60d829a0353a 117 __IO uint32_t PLL0CFG;
tushki7 0:60d829a0353a 118 __I uint32_t PLL0STAT;
tushki7 0:60d829a0353a 119 __O uint32_t PLL0FEED;
tushki7 0:60d829a0353a 120 uint32_t RESERVED1[4];
tushki7 0:60d829a0353a 121 __IO uint32_t PLL1CON;
tushki7 0:60d829a0353a 122 __IO uint32_t PLL1CFG;
tushki7 0:60d829a0353a 123 __I uint32_t PLL1STAT;
tushki7 0:60d829a0353a 124 __O uint32_t PLL1FEED;
tushki7 0:60d829a0353a 125 uint32_t RESERVED2[4];
tushki7 0:60d829a0353a 126 __IO uint32_t PCON;
tushki7 0:60d829a0353a 127 __IO uint32_t PCONP;
tushki7 0:60d829a0353a 128 uint32_t RESERVED3[15];
tushki7 0:60d829a0353a 129 __IO uint32_t CCLKCFG;
tushki7 0:60d829a0353a 130 __IO uint32_t USBCLKCFG;
tushki7 0:60d829a0353a 131 __IO uint32_t CLKSRCSEL;
tushki7 0:60d829a0353a 132 __IO uint32_t CANSLEEPCLR;
tushki7 0:60d829a0353a 133 __IO uint32_t CANWAKEFLAGS;
tushki7 0:60d829a0353a 134 uint32_t RESERVED4[10];
tushki7 0:60d829a0353a 135 __IO uint32_t EXTINT; /* External Interrupts */
tushki7 0:60d829a0353a 136 uint32_t RESERVED5;
tushki7 0:60d829a0353a 137 __IO uint32_t EXTMODE;
tushki7 0:60d829a0353a 138 __IO uint32_t EXTPOLAR;
tushki7 0:60d829a0353a 139 uint32_t RESERVED6[12];
tushki7 0:60d829a0353a 140 __IO uint32_t RSID; /* Reset */
tushki7 0:60d829a0353a 141 uint32_t RESERVED7[7];
tushki7 0:60d829a0353a 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
tushki7 0:60d829a0353a 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
tushki7 0:60d829a0353a 144 __IO uint32_t PCLKSEL0;
tushki7 0:60d829a0353a 145 __IO uint32_t PCLKSEL1;
tushki7 0:60d829a0353a 146 uint32_t RESERVED8[4];
tushki7 0:60d829a0353a 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
tushki7 0:60d829a0353a 148 __IO uint32_t DMAREQSEL;
tushki7 0:60d829a0353a 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
tushki7 0:60d829a0353a 150 } LPC_SC_TypeDef;
tushki7 0:60d829a0353a 151
tushki7 0:60d829a0353a 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
tushki7 0:60d829a0353a 153 typedef struct
tushki7 0:60d829a0353a 154 {
tushki7 0:60d829a0353a 155 __IO uint32_t PINSEL0;
tushki7 0:60d829a0353a 156 __IO uint32_t PINSEL1;
tushki7 0:60d829a0353a 157 __IO uint32_t PINSEL2;
tushki7 0:60d829a0353a 158 __IO uint32_t PINSEL3;
tushki7 0:60d829a0353a 159 __IO uint32_t PINSEL4;
tushki7 0:60d829a0353a 160 __IO uint32_t PINSEL5;
tushki7 0:60d829a0353a 161 __IO uint32_t PINSEL6;
tushki7 0:60d829a0353a 162 __IO uint32_t PINSEL7;
tushki7 0:60d829a0353a 163 __IO uint32_t PINSEL8;
tushki7 0:60d829a0353a 164 __IO uint32_t PINSEL9;
tushki7 0:60d829a0353a 165 __IO uint32_t PINSEL10;
tushki7 0:60d829a0353a 166 uint32_t RESERVED0[5];
tushki7 0:60d829a0353a 167 __IO uint32_t PINMODE0;
tushki7 0:60d829a0353a 168 __IO uint32_t PINMODE1;
tushki7 0:60d829a0353a 169 __IO uint32_t PINMODE2;
tushki7 0:60d829a0353a 170 __IO uint32_t PINMODE3;
tushki7 0:60d829a0353a 171 __IO uint32_t PINMODE4;
tushki7 0:60d829a0353a 172 __IO uint32_t PINMODE5;
tushki7 0:60d829a0353a 173 __IO uint32_t PINMODE6;
tushki7 0:60d829a0353a 174 __IO uint32_t PINMODE7;
tushki7 0:60d829a0353a 175 __IO uint32_t PINMODE8;
tushki7 0:60d829a0353a 176 __IO uint32_t PINMODE9;
tushki7 0:60d829a0353a 177 __IO uint32_t PINMODE_OD0;
tushki7 0:60d829a0353a 178 __IO uint32_t PINMODE_OD1;
tushki7 0:60d829a0353a 179 __IO uint32_t PINMODE_OD2;
tushki7 0:60d829a0353a 180 __IO uint32_t PINMODE_OD3;
tushki7 0:60d829a0353a 181 __IO uint32_t PINMODE_OD4;
tushki7 0:60d829a0353a 182 __IO uint32_t I2CPADCFG;
tushki7 0:60d829a0353a 183 } LPC_PINCON_TypeDef;
tushki7 0:60d829a0353a 184
tushki7 0:60d829a0353a 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
tushki7 0:60d829a0353a 186 typedef struct
tushki7 0:60d829a0353a 187 {
tushki7 0:60d829a0353a 188 union {
tushki7 0:60d829a0353a 189 __IO uint32_t FIODIR;
tushki7 0:60d829a0353a 190 struct {
tushki7 0:60d829a0353a 191 __IO uint16_t FIODIRL;
tushki7 0:60d829a0353a 192 __IO uint16_t FIODIRH;
tushki7 0:60d829a0353a 193 };
tushki7 0:60d829a0353a 194 struct {
tushki7 0:60d829a0353a 195 __IO uint8_t FIODIR0;
tushki7 0:60d829a0353a 196 __IO uint8_t FIODIR1;
tushki7 0:60d829a0353a 197 __IO uint8_t FIODIR2;
tushki7 0:60d829a0353a 198 __IO uint8_t FIODIR3;
tushki7 0:60d829a0353a 199 };
tushki7 0:60d829a0353a 200 };
tushki7 0:60d829a0353a 201 uint32_t RESERVED0[3];
tushki7 0:60d829a0353a 202 union {
tushki7 0:60d829a0353a 203 __IO uint32_t FIOMASK;
tushki7 0:60d829a0353a 204 struct {
tushki7 0:60d829a0353a 205 __IO uint16_t FIOMASKL;
tushki7 0:60d829a0353a 206 __IO uint16_t FIOMASKH;
tushki7 0:60d829a0353a 207 };
tushki7 0:60d829a0353a 208 struct {
tushki7 0:60d829a0353a 209 __IO uint8_t FIOMASK0;
tushki7 0:60d829a0353a 210 __IO uint8_t FIOMASK1;
tushki7 0:60d829a0353a 211 __IO uint8_t FIOMASK2;
tushki7 0:60d829a0353a 212 __IO uint8_t FIOMASK3;
tushki7 0:60d829a0353a 213 };
tushki7 0:60d829a0353a 214 };
tushki7 0:60d829a0353a 215 union {
tushki7 0:60d829a0353a 216 __IO uint32_t FIOPIN;
tushki7 0:60d829a0353a 217 struct {
tushki7 0:60d829a0353a 218 __IO uint16_t FIOPINL;
tushki7 0:60d829a0353a 219 __IO uint16_t FIOPINH;
tushki7 0:60d829a0353a 220 };
tushki7 0:60d829a0353a 221 struct {
tushki7 0:60d829a0353a 222 __IO uint8_t FIOPIN0;
tushki7 0:60d829a0353a 223 __IO uint8_t FIOPIN1;
tushki7 0:60d829a0353a 224 __IO uint8_t FIOPIN2;
tushki7 0:60d829a0353a 225 __IO uint8_t FIOPIN3;
tushki7 0:60d829a0353a 226 };
tushki7 0:60d829a0353a 227 };
tushki7 0:60d829a0353a 228 union {
tushki7 0:60d829a0353a 229 __IO uint32_t FIOSET;
tushki7 0:60d829a0353a 230 struct {
tushki7 0:60d829a0353a 231 __IO uint16_t FIOSETL;
tushki7 0:60d829a0353a 232 __IO uint16_t FIOSETH;
tushki7 0:60d829a0353a 233 };
tushki7 0:60d829a0353a 234 struct {
tushki7 0:60d829a0353a 235 __IO uint8_t FIOSET0;
tushki7 0:60d829a0353a 236 __IO uint8_t FIOSET1;
tushki7 0:60d829a0353a 237 __IO uint8_t FIOSET2;
tushki7 0:60d829a0353a 238 __IO uint8_t FIOSET3;
tushki7 0:60d829a0353a 239 };
tushki7 0:60d829a0353a 240 };
tushki7 0:60d829a0353a 241 union {
tushki7 0:60d829a0353a 242 __O uint32_t FIOCLR;
tushki7 0:60d829a0353a 243 struct {
tushki7 0:60d829a0353a 244 __O uint16_t FIOCLRL;
tushki7 0:60d829a0353a 245 __O uint16_t FIOCLRH;
tushki7 0:60d829a0353a 246 };
tushki7 0:60d829a0353a 247 struct {
tushki7 0:60d829a0353a 248 __O uint8_t FIOCLR0;
tushki7 0:60d829a0353a 249 __O uint8_t FIOCLR1;
tushki7 0:60d829a0353a 250 __O uint8_t FIOCLR2;
tushki7 0:60d829a0353a 251 __O uint8_t FIOCLR3;
tushki7 0:60d829a0353a 252 };
tushki7 0:60d829a0353a 253 };
tushki7 0:60d829a0353a 254 } LPC_GPIO_TypeDef;
tushki7 0:60d829a0353a 255
tushki7 0:60d829a0353a 256 typedef struct
tushki7 0:60d829a0353a 257 {
tushki7 0:60d829a0353a 258 __I uint32_t IntStatus;
tushki7 0:60d829a0353a 259 __I uint32_t IO0IntStatR;
tushki7 0:60d829a0353a 260 __I uint32_t IO0IntStatF;
tushki7 0:60d829a0353a 261 __O uint32_t IO0IntClr;
tushki7 0:60d829a0353a 262 __IO uint32_t IO0IntEnR;
tushki7 0:60d829a0353a 263 __IO uint32_t IO0IntEnF;
tushki7 0:60d829a0353a 264 uint32_t RESERVED0[3];
tushki7 0:60d829a0353a 265 __I uint32_t IO2IntStatR;
tushki7 0:60d829a0353a 266 __I uint32_t IO2IntStatF;
tushki7 0:60d829a0353a 267 __O uint32_t IO2IntClr;
tushki7 0:60d829a0353a 268 __IO uint32_t IO2IntEnR;
tushki7 0:60d829a0353a 269 __IO uint32_t IO2IntEnF;
tushki7 0:60d829a0353a 270 } LPC_GPIOINT_TypeDef;
tushki7 0:60d829a0353a 271
tushki7 0:60d829a0353a 272 /*------------- Timer (TIM) --------------------------------------------------*/
tushki7 0:60d829a0353a 273 typedef struct
tushki7 0:60d829a0353a 274 {
tushki7 0:60d829a0353a 275 __IO uint32_t IR;
tushki7 0:60d829a0353a 276 __IO uint32_t TCR;
tushki7 0:60d829a0353a 277 __IO uint32_t TC;
tushki7 0:60d829a0353a 278 __IO uint32_t PR;
tushki7 0:60d829a0353a 279 __IO uint32_t PC;
tushki7 0:60d829a0353a 280 __IO uint32_t MCR;
tushki7 0:60d829a0353a 281 __IO uint32_t MR0;
tushki7 0:60d829a0353a 282 __IO uint32_t MR1;
tushki7 0:60d829a0353a 283 __IO uint32_t MR2;
tushki7 0:60d829a0353a 284 __IO uint32_t MR3;
tushki7 0:60d829a0353a 285 __IO uint32_t CCR;
tushki7 0:60d829a0353a 286 __I uint32_t CR0;
tushki7 0:60d829a0353a 287 __I uint32_t CR1;
tushki7 0:60d829a0353a 288 uint32_t RESERVED0[2];
tushki7 0:60d829a0353a 289 __IO uint32_t EMR;
tushki7 0:60d829a0353a 290 uint32_t RESERVED1[12];
tushki7 0:60d829a0353a 291 __IO uint32_t CTCR;
tushki7 0:60d829a0353a 292 } LPC_TIM_TypeDef;
tushki7 0:60d829a0353a 293
tushki7 0:60d829a0353a 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
tushki7 0:60d829a0353a 295 typedef struct
tushki7 0:60d829a0353a 296 {
tushki7 0:60d829a0353a 297 __IO uint32_t IR;
tushki7 0:60d829a0353a 298 __IO uint32_t TCR;
tushki7 0:60d829a0353a 299 __IO uint32_t TC;
tushki7 0:60d829a0353a 300 __IO uint32_t PR;
tushki7 0:60d829a0353a 301 __IO uint32_t PC;
tushki7 0:60d829a0353a 302 __IO uint32_t MCR;
tushki7 0:60d829a0353a 303 __IO uint32_t MR0;
tushki7 0:60d829a0353a 304 __IO uint32_t MR1;
tushki7 0:60d829a0353a 305 __IO uint32_t MR2;
tushki7 0:60d829a0353a 306 __IO uint32_t MR3;
tushki7 0:60d829a0353a 307 __IO uint32_t CCR;
tushki7 0:60d829a0353a 308 __I uint32_t CR0;
tushki7 0:60d829a0353a 309 __I uint32_t CR1;
tushki7 0:60d829a0353a 310 __I uint32_t CR2;
tushki7 0:60d829a0353a 311 __I uint32_t CR3;
tushki7 0:60d829a0353a 312 uint32_t RESERVED0;
tushki7 0:60d829a0353a 313 __IO uint32_t MR4;
tushki7 0:60d829a0353a 314 __IO uint32_t MR5;
tushki7 0:60d829a0353a 315 __IO uint32_t MR6;
tushki7 0:60d829a0353a 316 __IO uint32_t PCR;
tushki7 0:60d829a0353a 317 __IO uint32_t LER;
tushki7 0:60d829a0353a 318 uint32_t RESERVED1[7];
tushki7 0:60d829a0353a 319 __IO uint32_t CTCR;
tushki7 0:60d829a0353a 320 } LPC_PWM_TypeDef;
tushki7 0:60d829a0353a 321
tushki7 0:60d829a0353a 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
tushki7 0:60d829a0353a 323 typedef struct
tushki7 0:60d829a0353a 324 {
tushki7 0:60d829a0353a 325 union {
tushki7 0:60d829a0353a 326 __I uint8_t RBR;
tushki7 0:60d829a0353a 327 __O uint8_t THR;
tushki7 0:60d829a0353a 328 __IO uint8_t DLL;
tushki7 0:60d829a0353a 329 uint32_t RESERVED0;
tushki7 0:60d829a0353a 330 };
tushki7 0:60d829a0353a 331 union {
tushki7 0:60d829a0353a 332 __IO uint8_t DLM;
tushki7 0:60d829a0353a 333 __IO uint32_t IER;
tushki7 0:60d829a0353a 334 };
tushki7 0:60d829a0353a 335 union {
tushki7 0:60d829a0353a 336 __I uint32_t IIR;
tushki7 0:60d829a0353a 337 __O uint8_t FCR;
tushki7 0:60d829a0353a 338 };
tushki7 0:60d829a0353a 339 __IO uint8_t LCR;
tushki7 0:60d829a0353a 340 uint8_t RESERVED1[7];
tushki7 0:60d829a0353a 341 __I uint8_t LSR;
tushki7 0:60d829a0353a 342 uint8_t RESERVED2[7];
tushki7 0:60d829a0353a 343 __IO uint8_t SCR;
tushki7 0:60d829a0353a 344 uint8_t RESERVED3[3];
tushki7 0:60d829a0353a 345 __IO uint32_t ACR;
tushki7 0:60d829a0353a 346 __IO uint8_t ICR;
tushki7 0:60d829a0353a 347 uint8_t RESERVED4[3];
tushki7 0:60d829a0353a 348 __IO uint8_t FDR;
tushki7 0:60d829a0353a 349 uint8_t RESERVED5[7];
tushki7 0:60d829a0353a 350 __IO uint8_t TER;
tushki7 0:60d829a0353a 351 uint8_t RESERVED6[39];
tushki7 0:60d829a0353a 352 __IO uint32_t FIFOLVL;
tushki7 0:60d829a0353a 353 } LPC_UART_TypeDef;
tushki7 0:60d829a0353a 354
tushki7 0:60d829a0353a 355 typedef struct
tushki7 0:60d829a0353a 356 {
tushki7 0:60d829a0353a 357 union {
tushki7 0:60d829a0353a 358 __I uint8_t RBR;
tushki7 0:60d829a0353a 359 __O uint8_t THR;
tushki7 0:60d829a0353a 360 __IO uint8_t DLL;
tushki7 0:60d829a0353a 361 uint32_t RESERVED0;
tushki7 0:60d829a0353a 362 };
tushki7 0:60d829a0353a 363 union {
tushki7 0:60d829a0353a 364 __IO uint8_t DLM;
tushki7 0:60d829a0353a 365 __IO uint32_t IER;
tushki7 0:60d829a0353a 366 };
tushki7 0:60d829a0353a 367 union {
tushki7 0:60d829a0353a 368 __I uint32_t IIR;
tushki7 0:60d829a0353a 369 __O uint8_t FCR;
tushki7 0:60d829a0353a 370 };
tushki7 0:60d829a0353a 371 __IO uint8_t LCR;
tushki7 0:60d829a0353a 372 uint8_t RESERVED1[7];
tushki7 0:60d829a0353a 373 __I uint8_t LSR;
tushki7 0:60d829a0353a 374 uint8_t RESERVED2[7];
tushki7 0:60d829a0353a 375 __IO uint8_t SCR;
tushki7 0:60d829a0353a 376 uint8_t RESERVED3[3];
tushki7 0:60d829a0353a 377 __IO uint32_t ACR;
tushki7 0:60d829a0353a 378 __IO uint8_t ICR;
tushki7 0:60d829a0353a 379 uint8_t RESERVED4[3];
tushki7 0:60d829a0353a 380 __IO uint8_t FDR;
tushki7 0:60d829a0353a 381 uint8_t RESERVED5[7];
tushki7 0:60d829a0353a 382 __IO uint8_t TER;
tushki7 0:60d829a0353a 383 uint8_t RESERVED6[39];
tushki7 0:60d829a0353a 384 __IO uint32_t FIFOLVL;
tushki7 0:60d829a0353a 385 } LPC_UART0_TypeDef;
tushki7 0:60d829a0353a 386
tushki7 0:60d829a0353a 387 typedef struct
tushki7 0:60d829a0353a 388 {
tushki7 0:60d829a0353a 389 union {
tushki7 0:60d829a0353a 390 __I uint8_t RBR;
tushki7 0:60d829a0353a 391 __O uint8_t THR;
tushki7 0:60d829a0353a 392 __IO uint8_t DLL;
tushki7 0:60d829a0353a 393 uint32_t RESERVED0;
tushki7 0:60d829a0353a 394 };
tushki7 0:60d829a0353a 395 union {
tushki7 0:60d829a0353a 396 __IO uint8_t DLM;
tushki7 0:60d829a0353a 397 __IO uint32_t IER;
tushki7 0:60d829a0353a 398 };
tushki7 0:60d829a0353a 399 union {
tushki7 0:60d829a0353a 400 __I uint32_t IIR;
tushki7 0:60d829a0353a 401 __O uint8_t FCR;
tushki7 0:60d829a0353a 402 };
tushki7 0:60d829a0353a 403 __IO uint8_t LCR;
tushki7 0:60d829a0353a 404 uint8_t RESERVED1[3];
tushki7 0:60d829a0353a 405 __IO uint8_t MCR;
tushki7 0:60d829a0353a 406 uint8_t RESERVED2[3];
tushki7 0:60d829a0353a 407 __I uint8_t LSR;
tushki7 0:60d829a0353a 408 uint8_t RESERVED3[3];
tushki7 0:60d829a0353a 409 __I uint8_t MSR;
tushki7 0:60d829a0353a 410 uint8_t RESERVED4[3];
tushki7 0:60d829a0353a 411 __IO uint8_t SCR;
tushki7 0:60d829a0353a 412 uint8_t RESERVED5[3];
tushki7 0:60d829a0353a 413 __IO uint32_t ACR;
tushki7 0:60d829a0353a 414 uint32_t RESERVED6;
tushki7 0:60d829a0353a 415 __IO uint32_t FDR;
tushki7 0:60d829a0353a 416 uint32_t RESERVED7;
tushki7 0:60d829a0353a 417 __IO uint8_t TER;
tushki7 0:60d829a0353a 418 uint8_t RESERVED8[27];
tushki7 0:60d829a0353a 419 __IO uint8_t RS485CTRL;
tushki7 0:60d829a0353a 420 uint8_t RESERVED9[3];
tushki7 0:60d829a0353a 421 __IO uint8_t ADRMATCH;
tushki7 0:60d829a0353a 422 uint8_t RESERVED10[3];
tushki7 0:60d829a0353a 423 __IO uint8_t RS485DLY;
tushki7 0:60d829a0353a 424 uint8_t RESERVED11[3];
tushki7 0:60d829a0353a 425 __IO uint32_t FIFOLVL;
tushki7 0:60d829a0353a 426 } LPC_UART1_TypeDef;
tushki7 0:60d829a0353a 427
tushki7 0:60d829a0353a 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
tushki7 0:60d829a0353a 429 typedef struct
tushki7 0:60d829a0353a 430 {
tushki7 0:60d829a0353a 431 __IO uint32_t SPCR;
tushki7 0:60d829a0353a 432 __I uint32_t SPSR;
tushki7 0:60d829a0353a 433 __IO uint32_t SPDR;
tushki7 0:60d829a0353a 434 __IO uint32_t SPCCR;
tushki7 0:60d829a0353a 435 uint32_t RESERVED0[3];
tushki7 0:60d829a0353a 436 __IO uint32_t SPINT;
tushki7 0:60d829a0353a 437 } LPC_SPI_TypeDef;
tushki7 0:60d829a0353a 438
tushki7 0:60d829a0353a 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
tushki7 0:60d829a0353a 440 typedef struct
tushki7 0:60d829a0353a 441 {
tushki7 0:60d829a0353a 442 __IO uint32_t CR0;
tushki7 0:60d829a0353a 443 __IO uint32_t CR1;
tushki7 0:60d829a0353a 444 __IO uint32_t DR;
tushki7 0:60d829a0353a 445 __I uint32_t SR;
tushki7 0:60d829a0353a 446 __IO uint32_t CPSR;
tushki7 0:60d829a0353a 447 __IO uint32_t IMSC;
tushki7 0:60d829a0353a 448 __IO uint32_t RIS;
tushki7 0:60d829a0353a 449 __IO uint32_t MIS;
tushki7 0:60d829a0353a 450 __IO uint32_t ICR;
tushki7 0:60d829a0353a 451 __IO uint32_t DMACR;
tushki7 0:60d829a0353a 452 } LPC_SSP_TypeDef;
tushki7 0:60d829a0353a 453
tushki7 0:60d829a0353a 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
tushki7 0:60d829a0353a 455 typedef struct
tushki7 0:60d829a0353a 456 {
tushki7 0:60d829a0353a 457 __IO uint32_t I2CONSET;
tushki7 0:60d829a0353a 458 __I uint32_t I2STAT;
tushki7 0:60d829a0353a 459 __IO uint32_t I2DAT;
tushki7 0:60d829a0353a 460 __IO uint32_t I2ADR0;
tushki7 0:60d829a0353a 461 __IO uint32_t I2SCLH;
tushki7 0:60d829a0353a 462 __IO uint32_t I2SCLL;
tushki7 0:60d829a0353a 463 __O uint32_t I2CONCLR;
tushki7 0:60d829a0353a 464 __IO uint32_t MMCTRL;
tushki7 0:60d829a0353a 465 __IO uint32_t I2ADR1;
tushki7 0:60d829a0353a 466 __IO uint32_t I2ADR2;
tushki7 0:60d829a0353a 467 __IO uint32_t I2ADR3;
tushki7 0:60d829a0353a 468 __I uint32_t I2DATA_BUFFER;
tushki7 0:60d829a0353a 469 __IO uint32_t I2MASK0;
tushki7 0:60d829a0353a 470 __IO uint32_t I2MASK1;
tushki7 0:60d829a0353a 471 __IO uint32_t I2MASK2;
tushki7 0:60d829a0353a 472 __IO uint32_t I2MASK3;
tushki7 0:60d829a0353a 473 } LPC_I2C_TypeDef;
tushki7 0:60d829a0353a 474
tushki7 0:60d829a0353a 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
tushki7 0:60d829a0353a 476 typedef struct
tushki7 0:60d829a0353a 477 {
tushki7 0:60d829a0353a 478 __IO uint32_t I2SDAO;
tushki7 0:60d829a0353a 479 __IO uint32_t I2SDAI;
tushki7 0:60d829a0353a 480 __O uint32_t I2STXFIFO;
tushki7 0:60d829a0353a 481 __I uint32_t I2SRXFIFO;
tushki7 0:60d829a0353a 482 __I uint32_t I2SSTATE;
tushki7 0:60d829a0353a 483 __IO uint32_t I2SDMA1;
tushki7 0:60d829a0353a 484 __IO uint32_t I2SDMA2;
tushki7 0:60d829a0353a 485 __IO uint32_t I2SIRQ;
tushki7 0:60d829a0353a 486 __IO uint32_t I2STXRATE;
tushki7 0:60d829a0353a 487 __IO uint32_t I2SRXRATE;
tushki7 0:60d829a0353a 488 __IO uint32_t I2STXBITRATE;
tushki7 0:60d829a0353a 489 __IO uint32_t I2SRXBITRATE;
tushki7 0:60d829a0353a 490 __IO uint32_t I2STXMODE;
tushki7 0:60d829a0353a 491 __IO uint32_t I2SRXMODE;
tushki7 0:60d829a0353a 492 } LPC_I2S_TypeDef;
tushki7 0:60d829a0353a 493
tushki7 0:60d829a0353a 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
tushki7 0:60d829a0353a 495 typedef struct
tushki7 0:60d829a0353a 496 {
tushki7 0:60d829a0353a 497 __IO uint32_t RICOMPVAL;
tushki7 0:60d829a0353a 498 __IO uint32_t RIMASK;
tushki7 0:60d829a0353a 499 __IO uint8_t RICTRL;
tushki7 0:60d829a0353a 500 uint8_t RESERVED0[3];
tushki7 0:60d829a0353a 501 __IO uint32_t RICOUNTER;
tushki7 0:60d829a0353a 502 } LPC_RIT_TypeDef;
tushki7 0:60d829a0353a 503
tushki7 0:60d829a0353a 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
tushki7 0:60d829a0353a 505 typedef struct
tushki7 0:60d829a0353a 506 {
tushki7 0:60d829a0353a 507 __IO uint8_t ILR;
tushki7 0:60d829a0353a 508 uint8_t RESERVED0[7];
tushki7 0:60d829a0353a 509 __IO uint8_t CCR;
tushki7 0:60d829a0353a 510 uint8_t RESERVED1[3];
tushki7 0:60d829a0353a 511 __IO uint8_t CIIR;
tushki7 0:60d829a0353a 512 uint8_t RESERVED2[3];
tushki7 0:60d829a0353a 513 __IO uint8_t AMR;
tushki7 0:60d829a0353a 514 uint8_t RESERVED3[3];
tushki7 0:60d829a0353a 515 __I uint32_t CTIME0;
tushki7 0:60d829a0353a 516 __I uint32_t CTIME1;
tushki7 0:60d829a0353a 517 __I uint32_t CTIME2;
tushki7 0:60d829a0353a 518 __IO uint8_t SEC;
tushki7 0:60d829a0353a 519 uint8_t RESERVED4[3];
tushki7 0:60d829a0353a 520 __IO uint8_t MIN;
tushki7 0:60d829a0353a 521 uint8_t RESERVED5[3];
tushki7 0:60d829a0353a 522 __IO uint8_t HOUR;
tushki7 0:60d829a0353a 523 uint8_t RESERVED6[3];
tushki7 0:60d829a0353a 524 __IO uint8_t DOM;
tushki7 0:60d829a0353a 525 uint8_t RESERVED7[3];
tushki7 0:60d829a0353a 526 __IO uint8_t DOW;
tushki7 0:60d829a0353a 527 uint8_t RESERVED8[3];
tushki7 0:60d829a0353a 528 __IO uint16_t DOY;
tushki7 0:60d829a0353a 529 uint16_t RESERVED9;
tushki7 0:60d829a0353a 530 __IO uint8_t MONTH;
tushki7 0:60d829a0353a 531 uint8_t RESERVED10[3];
tushki7 0:60d829a0353a 532 __IO uint16_t YEAR;
tushki7 0:60d829a0353a 533 uint16_t RESERVED11;
tushki7 0:60d829a0353a 534 __IO uint32_t CALIBRATION;
tushki7 0:60d829a0353a 535 __IO uint32_t GPREG0;
tushki7 0:60d829a0353a 536 __IO uint32_t GPREG1;
tushki7 0:60d829a0353a 537 __IO uint32_t GPREG2;
tushki7 0:60d829a0353a 538 __IO uint32_t GPREG3;
tushki7 0:60d829a0353a 539 __IO uint32_t GPREG4;
tushki7 0:60d829a0353a 540 __IO uint8_t RTC_AUXEN;
tushki7 0:60d829a0353a 541 uint8_t RESERVED12[3];
tushki7 0:60d829a0353a 542 __IO uint8_t RTC_AUX;
tushki7 0:60d829a0353a 543 uint8_t RESERVED13[3];
tushki7 0:60d829a0353a 544 __IO uint8_t ALSEC;
tushki7 0:60d829a0353a 545 uint8_t RESERVED14[3];
tushki7 0:60d829a0353a 546 __IO uint8_t ALMIN;
tushki7 0:60d829a0353a 547 uint8_t RESERVED15[3];
tushki7 0:60d829a0353a 548 __IO uint8_t ALHOUR;
tushki7 0:60d829a0353a 549 uint8_t RESERVED16[3];
tushki7 0:60d829a0353a 550 __IO uint8_t ALDOM;
tushki7 0:60d829a0353a 551 uint8_t RESERVED17[3];
tushki7 0:60d829a0353a 552 __IO uint8_t ALDOW;
tushki7 0:60d829a0353a 553 uint8_t RESERVED18[3];
tushki7 0:60d829a0353a 554 __IO uint16_t ALDOY;
tushki7 0:60d829a0353a 555 uint16_t RESERVED19;
tushki7 0:60d829a0353a 556 __IO uint8_t ALMON;
tushki7 0:60d829a0353a 557 uint8_t RESERVED20[3];
tushki7 0:60d829a0353a 558 __IO uint16_t ALYEAR;
tushki7 0:60d829a0353a 559 uint16_t RESERVED21;
tushki7 0:60d829a0353a 560 } LPC_RTC_TypeDef;
tushki7 0:60d829a0353a 561
tushki7 0:60d829a0353a 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
tushki7 0:60d829a0353a 563 typedef struct
tushki7 0:60d829a0353a 564 {
tushki7 0:60d829a0353a 565 __IO uint8_t WDMOD;
tushki7 0:60d829a0353a 566 uint8_t RESERVED0[3];
tushki7 0:60d829a0353a 567 __IO uint32_t WDTC;
tushki7 0:60d829a0353a 568 __O uint8_t WDFEED;
tushki7 0:60d829a0353a 569 uint8_t RESERVED1[3];
tushki7 0:60d829a0353a 570 __I uint32_t WDTV;
tushki7 0:60d829a0353a 571 __IO uint32_t WDCLKSEL;
tushki7 0:60d829a0353a 572 } LPC_WDT_TypeDef;
tushki7 0:60d829a0353a 573
tushki7 0:60d829a0353a 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
tushki7 0:60d829a0353a 575 typedef struct
tushki7 0:60d829a0353a 576 {
tushki7 0:60d829a0353a 577 __IO uint32_t ADCR;
tushki7 0:60d829a0353a 578 __IO uint32_t ADGDR;
tushki7 0:60d829a0353a 579 uint32_t RESERVED0;
tushki7 0:60d829a0353a 580 __IO uint32_t ADINTEN;
tushki7 0:60d829a0353a 581 __I uint32_t ADDR0;
tushki7 0:60d829a0353a 582 __I uint32_t ADDR1;
tushki7 0:60d829a0353a 583 __I uint32_t ADDR2;
tushki7 0:60d829a0353a 584 __I uint32_t ADDR3;
tushki7 0:60d829a0353a 585 __I uint32_t ADDR4;
tushki7 0:60d829a0353a 586 __I uint32_t ADDR5;
tushki7 0:60d829a0353a 587 __I uint32_t ADDR6;
tushki7 0:60d829a0353a 588 __I uint32_t ADDR7;
tushki7 0:60d829a0353a 589 __I uint32_t ADSTAT;
tushki7 0:60d829a0353a 590 __IO uint32_t ADTRM;
tushki7 0:60d829a0353a 591 } LPC_ADC_TypeDef;
tushki7 0:60d829a0353a 592
tushki7 0:60d829a0353a 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
tushki7 0:60d829a0353a 594 typedef struct
tushki7 0:60d829a0353a 595 {
tushki7 0:60d829a0353a 596 __IO uint32_t DACR;
tushki7 0:60d829a0353a 597 __IO uint32_t DACCTRL;
tushki7 0:60d829a0353a 598 __IO uint16_t DACCNTVAL;
tushki7 0:60d829a0353a 599 } LPC_DAC_TypeDef;
tushki7 0:60d829a0353a 600
tushki7 0:60d829a0353a 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
tushki7 0:60d829a0353a 602 typedef struct
tushki7 0:60d829a0353a 603 {
tushki7 0:60d829a0353a 604 __I uint32_t MCCON;
tushki7 0:60d829a0353a 605 __O uint32_t MCCON_SET;
tushki7 0:60d829a0353a 606 __O uint32_t MCCON_CLR;
tushki7 0:60d829a0353a 607 __I uint32_t MCCAPCON;
tushki7 0:60d829a0353a 608 __O uint32_t MCCAPCON_SET;
tushki7 0:60d829a0353a 609 __O uint32_t MCCAPCON_CLR;
tushki7 0:60d829a0353a 610 __IO uint32_t MCTIM0;
tushki7 0:60d829a0353a 611 __IO uint32_t MCTIM1;
tushki7 0:60d829a0353a 612 __IO uint32_t MCTIM2;
tushki7 0:60d829a0353a 613 __IO uint32_t MCPER0;
tushki7 0:60d829a0353a 614 __IO uint32_t MCPER1;
tushki7 0:60d829a0353a 615 __IO uint32_t MCPER2;
tushki7 0:60d829a0353a 616 __IO uint32_t MCPW0;
tushki7 0:60d829a0353a 617 __IO uint32_t MCPW1;
tushki7 0:60d829a0353a 618 __IO uint32_t MCPW2;
tushki7 0:60d829a0353a 619 __IO uint32_t MCDEADTIME;
tushki7 0:60d829a0353a 620 __IO uint32_t MCCCP;
tushki7 0:60d829a0353a 621 __IO uint32_t MCCR0;
tushki7 0:60d829a0353a 622 __IO uint32_t MCCR1;
tushki7 0:60d829a0353a 623 __IO uint32_t MCCR2;
tushki7 0:60d829a0353a 624 __I uint32_t MCINTEN;
tushki7 0:60d829a0353a 625 __O uint32_t MCINTEN_SET;
tushki7 0:60d829a0353a 626 __O uint32_t MCINTEN_CLR;
tushki7 0:60d829a0353a 627 __I uint32_t MCCNTCON;
tushki7 0:60d829a0353a 628 __O uint32_t MCCNTCON_SET;
tushki7 0:60d829a0353a 629 __O uint32_t MCCNTCON_CLR;
tushki7 0:60d829a0353a 630 __I uint32_t MCINTFLAG;
tushki7 0:60d829a0353a 631 __O uint32_t MCINTFLAG_SET;
tushki7 0:60d829a0353a 632 __O uint32_t MCINTFLAG_CLR;
tushki7 0:60d829a0353a 633 __O uint32_t MCCAP_CLR;
tushki7 0:60d829a0353a 634 } LPC_MCPWM_TypeDef;
tushki7 0:60d829a0353a 635
tushki7 0:60d829a0353a 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
tushki7 0:60d829a0353a 637 typedef struct
tushki7 0:60d829a0353a 638 {
tushki7 0:60d829a0353a 639 __O uint32_t QEICON;
tushki7 0:60d829a0353a 640 __I uint32_t QEISTAT;
tushki7 0:60d829a0353a 641 __IO uint32_t QEICONF;
tushki7 0:60d829a0353a 642 __I uint32_t QEIPOS;
tushki7 0:60d829a0353a 643 __IO uint32_t QEIMAXPOS;
tushki7 0:60d829a0353a 644 __IO uint32_t CMPOS0;
tushki7 0:60d829a0353a 645 __IO uint32_t CMPOS1;
tushki7 0:60d829a0353a 646 __IO uint32_t CMPOS2;
tushki7 0:60d829a0353a 647 __I uint32_t INXCNT;
tushki7 0:60d829a0353a 648 __IO uint32_t INXCMP;
tushki7 0:60d829a0353a 649 __IO uint32_t QEILOAD;
tushki7 0:60d829a0353a 650 __I uint32_t QEITIME;
tushki7 0:60d829a0353a 651 __I uint32_t QEIVEL;
tushki7 0:60d829a0353a 652 __I uint32_t QEICAP;
tushki7 0:60d829a0353a 653 __IO uint32_t VELCOMP;
tushki7 0:60d829a0353a 654 __IO uint32_t FILTER;
tushki7 0:60d829a0353a 655 uint32_t RESERVED0[998];
tushki7 0:60d829a0353a 656 __O uint32_t QEIIEC;
tushki7 0:60d829a0353a 657 __O uint32_t QEIIES;
tushki7 0:60d829a0353a 658 __I uint32_t QEIINTSTAT;
tushki7 0:60d829a0353a 659 __I uint32_t QEIIE;
tushki7 0:60d829a0353a 660 __O uint32_t QEICLR;
tushki7 0:60d829a0353a 661 __O uint32_t QEISET;
tushki7 0:60d829a0353a 662 } LPC_QEI_TypeDef;
tushki7 0:60d829a0353a 663
tushki7 0:60d829a0353a 664 /*------------- Controller Area Network (CAN) --------------------------------*/
tushki7 0:60d829a0353a 665 typedef struct
tushki7 0:60d829a0353a 666 {
tushki7 0:60d829a0353a 667 __IO uint32_t mask[512]; /* ID Masks */
tushki7 0:60d829a0353a 668 } LPC_CANAF_RAM_TypeDef;
tushki7 0:60d829a0353a 669
tushki7 0:60d829a0353a 670 typedef struct /* Acceptance Filter Registers */
tushki7 0:60d829a0353a 671 {
tushki7 0:60d829a0353a 672 __IO uint32_t AFMR;
tushki7 0:60d829a0353a 673 __IO uint32_t SFF_sa;
tushki7 0:60d829a0353a 674 __IO uint32_t SFF_GRP_sa;
tushki7 0:60d829a0353a 675 __IO uint32_t EFF_sa;
tushki7 0:60d829a0353a 676 __IO uint32_t EFF_GRP_sa;
tushki7 0:60d829a0353a 677 __IO uint32_t ENDofTable;
tushki7 0:60d829a0353a 678 __I uint32_t LUTerrAd;
tushki7 0:60d829a0353a 679 __I uint32_t LUTerr;
tushki7 0:60d829a0353a 680 __IO uint32_t FCANIE;
tushki7 0:60d829a0353a 681 __IO uint32_t FCANIC0;
tushki7 0:60d829a0353a 682 __IO uint32_t FCANIC1;
tushki7 0:60d829a0353a 683 } LPC_CANAF_TypeDef;
tushki7 0:60d829a0353a 684
tushki7 0:60d829a0353a 685 typedef struct /* Central Registers */
tushki7 0:60d829a0353a 686 {
tushki7 0:60d829a0353a 687 __I uint32_t CANTxSR;
tushki7 0:60d829a0353a 688 __I uint32_t CANRxSR;
tushki7 0:60d829a0353a 689 __I uint32_t CANMSR;
tushki7 0:60d829a0353a 690 } LPC_CANCR_TypeDef;
tushki7 0:60d829a0353a 691
tushki7 0:60d829a0353a 692 typedef struct /* Controller Registers */
tushki7 0:60d829a0353a 693 {
tushki7 0:60d829a0353a 694 __IO uint32_t MOD;
tushki7 0:60d829a0353a 695 __O uint32_t CMR;
tushki7 0:60d829a0353a 696 __IO uint32_t GSR;
tushki7 0:60d829a0353a 697 __I uint32_t ICR;
tushki7 0:60d829a0353a 698 __IO uint32_t IER;
tushki7 0:60d829a0353a 699 __IO uint32_t BTR;
tushki7 0:60d829a0353a 700 __IO uint32_t EWL;
tushki7 0:60d829a0353a 701 __I uint32_t SR;
tushki7 0:60d829a0353a 702 __IO uint32_t RFS;
tushki7 0:60d829a0353a 703 __IO uint32_t RID;
tushki7 0:60d829a0353a 704 __IO uint32_t RDA;
tushki7 0:60d829a0353a 705 __IO uint32_t RDB;
tushki7 0:60d829a0353a 706 __IO uint32_t TFI1;
tushki7 0:60d829a0353a 707 __IO uint32_t TID1;
tushki7 0:60d829a0353a 708 __IO uint32_t TDA1;
tushki7 0:60d829a0353a 709 __IO uint32_t TDB1;
tushki7 0:60d829a0353a 710 __IO uint32_t TFI2;
tushki7 0:60d829a0353a 711 __IO uint32_t TID2;
tushki7 0:60d829a0353a 712 __IO uint32_t TDA2;
tushki7 0:60d829a0353a 713 __IO uint32_t TDB2;
tushki7 0:60d829a0353a 714 __IO uint32_t TFI3;
tushki7 0:60d829a0353a 715 __IO uint32_t TID3;
tushki7 0:60d829a0353a 716 __IO uint32_t TDA3;
tushki7 0:60d829a0353a 717 __IO uint32_t TDB3;
tushki7 0:60d829a0353a 718 } LPC_CAN_TypeDef;
tushki7 0:60d829a0353a 719
tushki7 0:60d829a0353a 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
tushki7 0:60d829a0353a 721 typedef struct /* Common Registers */
tushki7 0:60d829a0353a 722 {
tushki7 0:60d829a0353a 723 __I uint32_t DMACIntStat;
tushki7 0:60d829a0353a 724 __I uint32_t DMACIntTCStat;
tushki7 0:60d829a0353a 725 __O uint32_t DMACIntTCClear;
tushki7 0:60d829a0353a 726 __I uint32_t DMACIntErrStat;
tushki7 0:60d829a0353a 727 __O uint32_t DMACIntErrClr;
tushki7 0:60d829a0353a 728 __I uint32_t DMACRawIntTCStat;
tushki7 0:60d829a0353a 729 __I uint32_t DMACRawIntErrStat;
tushki7 0:60d829a0353a 730 __I uint32_t DMACEnbldChns;
tushki7 0:60d829a0353a 731 __IO uint32_t DMACSoftBReq;
tushki7 0:60d829a0353a 732 __IO uint32_t DMACSoftSReq;
tushki7 0:60d829a0353a 733 __IO uint32_t DMACSoftLBReq;
tushki7 0:60d829a0353a 734 __IO uint32_t DMACSoftLSReq;
tushki7 0:60d829a0353a 735 __IO uint32_t DMACConfig;
tushki7 0:60d829a0353a 736 __IO uint32_t DMACSync;
tushki7 0:60d829a0353a 737 } LPC_GPDMA_TypeDef;
tushki7 0:60d829a0353a 738
tushki7 0:60d829a0353a 739 typedef struct /* Channel Registers */
tushki7 0:60d829a0353a 740 {
tushki7 0:60d829a0353a 741 __IO uint32_t DMACCSrcAddr;
tushki7 0:60d829a0353a 742 __IO uint32_t DMACCDestAddr;
tushki7 0:60d829a0353a 743 __IO uint32_t DMACCLLI;
tushki7 0:60d829a0353a 744 __IO uint32_t DMACCControl;
tushki7 0:60d829a0353a 745 __IO uint32_t DMACCConfig;
tushki7 0:60d829a0353a 746 } LPC_GPDMACH_TypeDef;
tushki7 0:60d829a0353a 747
tushki7 0:60d829a0353a 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
tushki7 0:60d829a0353a 749 typedef struct
tushki7 0:60d829a0353a 750 {
tushki7 0:60d829a0353a 751 __I uint32_t HcRevision; /* USB Host Registers */
tushki7 0:60d829a0353a 752 __IO uint32_t HcControl;
tushki7 0:60d829a0353a 753 __IO uint32_t HcCommandStatus;
tushki7 0:60d829a0353a 754 __IO uint32_t HcInterruptStatus;
tushki7 0:60d829a0353a 755 __IO uint32_t HcInterruptEnable;
tushki7 0:60d829a0353a 756 __IO uint32_t HcInterruptDisable;
tushki7 0:60d829a0353a 757 __IO uint32_t HcHCCA;
tushki7 0:60d829a0353a 758 __I uint32_t HcPeriodCurrentED;
tushki7 0:60d829a0353a 759 __IO uint32_t HcControlHeadED;
tushki7 0:60d829a0353a 760 __IO uint32_t HcControlCurrentED;
tushki7 0:60d829a0353a 761 __IO uint32_t HcBulkHeadED;
tushki7 0:60d829a0353a 762 __IO uint32_t HcBulkCurrentED;
tushki7 0:60d829a0353a 763 __I uint32_t HcDoneHead;
tushki7 0:60d829a0353a 764 __IO uint32_t HcFmInterval;
tushki7 0:60d829a0353a 765 __I uint32_t HcFmRemaining;
tushki7 0:60d829a0353a 766 __I uint32_t HcFmNumber;
tushki7 0:60d829a0353a 767 __IO uint32_t HcPeriodicStart;
tushki7 0:60d829a0353a 768 __IO uint32_t HcLSTreshold;
tushki7 0:60d829a0353a 769 __IO uint32_t HcRhDescriptorA;
tushki7 0:60d829a0353a 770 __IO uint32_t HcRhDescriptorB;
tushki7 0:60d829a0353a 771 __IO uint32_t HcRhStatus;
tushki7 0:60d829a0353a 772 __IO uint32_t HcRhPortStatus1;
tushki7 0:60d829a0353a 773 __IO uint32_t HcRhPortStatus2;
tushki7 0:60d829a0353a 774 uint32_t RESERVED0[40];
tushki7 0:60d829a0353a 775 __I uint32_t Module_ID;
tushki7 0:60d829a0353a 776
tushki7 0:60d829a0353a 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
tushki7 0:60d829a0353a 778 __IO uint32_t OTGIntEn;
tushki7 0:60d829a0353a 779 __O uint32_t OTGIntSet;
tushki7 0:60d829a0353a 780 __O uint32_t OTGIntClr;
tushki7 0:60d829a0353a 781 __IO uint32_t OTGStCtrl;
tushki7 0:60d829a0353a 782 __IO uint32_t OTGTmr;
tushki7 0:60d829a0353a 783 uint32_t RESERVED1[58];
tushki7 0:60d829a0353a 784
tushki7 0:60d829a0353a 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
tushki7 0:60d829a0353a 786 __IO uint32_t USBDevIntEn;
tushki7 0:60d829a0353a 787 __O uint32_t USBDevIntClr;
tushki7 0:60d829a0353a 788 __O uint32_t USBDevIntSet;
tushki7 0:60d829a0353a 789
tushki7 0:60d829a0353a 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
tushki7 0:60d829a0353a 791 __I uint32_t USBCmdData;
tushki7 0:60d829a0353a 792
tushki7 0:60d829a0353a 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
tushki7 0:60d829a0353a 794 __O uint32_t USBTxData;
tushki7 0:60d829a0353a 795 __I uint32_t USBRxPLen;
tushki7 0:60d829a0353a 796 __O uint32_t USBTxPLen;
tushki7 0:60d829a0353a 797 __IO uint32_t USBCtrl;
tushki7 0:60d829a0353a 798 __O uint32_t USBDevIntPri;
tushki7 0:60d829a0353a 799
tushki7 0:60d829a0353a 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
tushki7 0:60d829a0353a 801 __IO uint32_t USBEpIntEn;
tushki7 0:60d829a0353a 802 __O uint32_t USBEpIntClr;
tushki7 0:60d829a0353a 803 __O uint32_t USBEpIntSet;
tushki7 0:60d829a0353a 804 __O uint32_t USBEpIntPri;
tushki7 0:60d829a0353a 805
tushki7 0:60d829a0353a 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
tushki7 0:60d829a0353a 807 __O uint32_t USBEpInd;
tushki7 0:60d829a0353a 808 __IO uint32_t USBMaxPSize;
tushki7 0:60d829a0353a 809
tushki7 0:60d829a0353a 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
tushki7 0:60d829a0353a 811 __O uint32_t USBDMARClr;
tushki7 0:60d829a0353a 812 __O uint32_t USBDMARSet;
tushki7 0:60d829a0353a 813 uint32_t RESERVED2[9];
tushki7 0:60d829a0353a 814 __IO uint32_t USBUDCAH;
tushki7 0:60d829a0353a 815 __I uint32_t USBEpDMASt;
tushki7 0:60d829a0353a 816 __O uint32_t USBEpDMAEn;
tushki7 0:60d829a0353a 817 __O uint32_t USBEpDMADis;
tushki7 0:60d829a0353a 818 __I uint32_t USBDMAIntSt;
tushki7 0:60d829a0353a 819 __IO uint32_t USBDMAIntEn;
tushki7 0:60d829a0353a 820 uint32_t RESERVED3[2];
tushki7 0:60d829a0353a 821 __I uint32_t USBEoTIntSt;
tushki7 0:60d829a0353a 822 __O uint32_t USBEoTIntClr;
tushki7 0:60d829a0353a 823 __O uint32_t USBEoTIntSet;
tushki7 0:60d829a0353a 824 __I uint32_t USBNDDRIntSt;
tushki7 0:60d829a0353a 825 __O uint32_t USBNDDRIntClr;
tushki7 0:60d829a0353a 826 __O uint32_t USBNDDRIntSet;
tushki7 0:60d829a0353a 827 __I uint32_t USBSysErrIntSt;
tushki7 0:60d829a0353a 828 __O uint32_t USBSysErrIntClr;
tushki7 0:60d829a0353a 829 __O uint32_t USBSysErrIntSet;
tushki7 0:60d829a0353a 830 uint32_t RESERVED4[15];
tushki7 0:60d829a0353a 831
tushki7 0:60d829a0353a 832 union {
tushki7 0:60d829a0353a 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
tushki7 0:60d829a0353a 834 __O uint32_t I2C_TX;
tushki7 0:60d829a0353a 835 };
tushki7 0:60d829a0353a 836 __I uint32_t I2C_STS;
tushki7 0:60d829a0353a 837 __IO uint32_t I2C_CTL;
tushki7 0:60d829a0353a 838 __IO uint32_t I2C_CLKHI;
tushki7 0:60d829a0353a 839 __O uint32_t I2C_CLKLO;
tushki7 0:60d829a0353a 840 uint32_t RESERVED5[824];
tushki7 0:60d829a0353a 841
tushki7 0:60d829a0353a 842 union {
tushki7 0:60d829a0353a 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
tushki7 0:60d829a0353a 844 __IO uint32_t OTGClkCtrl;
tushki7 0:60d829a0353a 845 };
tushki7 0:60d829a0353a 846 union {
tushki7 0:60d829a0353a 847 __I uint32_t USBClkSt;
tushki7 0:60d829a0353a 848 __I uint32_t OTGClkSt;
tushki7 0:60d829a0353a 849 };
tushki7 0:60d829a0353a 850 } LPC_USB_TypeDef;
tushki7 0:60d829a0353a 851
tushki7 0:60d829a0353a 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
tushki7 0:60d829a0353a 853 typedef struct
tushki7 0:60d829a0353a 854 {
tushki7 0:60d829a0353a 855 __IO uint32_t MAC1; /* MAC Registers */
tushki7 0:60d829a0353a 856 __IO uint32_t MAC2;
tushki7 0:60d829a0353a 857 __IO uint32_t IPGT;
tushki7 0:60d829a0353a 858 __IO uint32_t IPGR;
tushki7 0:60d829a0353a 859 __IO uint32_t CLRT;
tushki7 0:60d829a0353a 860 __IO uint32_t MAXF;
tushki7 0:60d829a0353a 861 __IO uint32_t SUPP;
tushki7 0:60d829a0353a 862 __IO uint32_t TEST;
tushki7 0:60d829a0353a 863 __IO uint32_t MCFG;
tushki7 0:60d829a0353a 864 __IO uint32_t MCMD;
tushki7 0:60d829a0353a 865 __IO uint32_t MADR;
tushki7 0:60d829a0353a 866 __O uint32_t MWTD;
tushki7 0:60d829a0353a 867 __I uint32_t MRDD;
tushki7 0:60d829a0353a 868 __I uint32_t MIND;
tushki7 0:60d829a0353a 869 uint32_t RESERVED0[2];
tushki7 0:60d829a0353a 870 __IO uint32_t SA0;
tushki7 0:60d829a0353a 871 __IO uint32_t SA1;
tushki7 0:60d829a0353a 872 __IO uint32_t SA2;
tushki7 0:60d829a0353a 873 uint32_t RESERVED1[45];
tushki7 0:60d829a0353a 874 __IO uint32_t Command; /* Control Registers */
tushki7 0:60d829a0353a 875 __I uint32_t Status;
tushki7 0:60d829a0353a 876 __IO uint32_t RxDescriptor;
tushki7 0:60d829a0353a 877 __IO uint32_t RxStatus;
tushki7 0:60d829a0353a 878 __IO uint32_t RxDescriptorNumber;
tushki7 0:60d829a0353a 879 __I uint32_t RxProduceIndex;
tushki7 0:60d829a0353a 880 __IO uint32_t RxConsumeIndex;
tushki7 0:60d829a0353a 881 __IO uint32_t TxDescriptor;
tushki7 0:60d829a0353a 882 __IO uint32_t TxStatus;
tushki7 0:60d829a0353a 883 __IO uint32_t TxDescriptorNumber;
tushki7 0:60d829a0353a 884 __IO uint32_t TxProduceIndex;
tushki7 0:60d829a0353a 885 __I uint32_t TxConsumeIndex;
tushki7 0:60d829a0353a 886 uint32_t RESERVED2[10];
tushki7 0:60d829a0353a 887 __I uint32_t TSV0;
tushki7 0:60d829a0353a 888 __I uint32_t TSV1;
tushki7 0:60d829a0353a 889 __I uint32_t RSV;
tushki7 0:60d829a0353a 890 uint32_t RESERVED3[3];
tushki7 0:60d829a0353a 891 __IO uint32_t FlowControlCounter;
tushki7 0:60d829a0353a 892 __I uint32_t FlowControlStatus;
tushki7 0:60d829a0353a 893 uint32_t RESERVED4[34];
tushki7 0:60d829a0353a 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
tushki7 0:60d829a0353a 895 __IO uint32_t RxFilterWoLStatus;
tushki7 0:60d829a0353a 896 __IO uint32_t RxFilterWoLClear;
tushki7 0:60d829a0353a 897 uint32_t RESERVED5;
tushki7 0:60d829a0353a 898 __IO uint32_t HashFilterL;
tushki7 0:60d829a0353a 899 __IO uint32_t HashFilterH;
tushki7 0:60d829a0353a 900 uint32_t RESERVED6[882];
tushki7 0:60d829a0353a 901 __I uint32_t IntStatus; /* Module Control Registers */
tushki7 0:60d829a0353a 902 __IO uint32_t IntEnable;
tushki7 0:60d829a0353a 903 __O uint32_t IntClear;
tushki7 0:60d829a0353a 904 __O uint32_t IntSet;
tushki7 0:60d829a0353a 905 uint32_t RESERVED7;
tushki7 0:60d829a0353a 906 __IO uint32_t PowerDown;
tushki7 0:60d829a0353a 907 uint32_t RESERVED8;
tushki7 0:60d829a0353a 908 __IO uint32_t Module_ID;
tushki7 0:60d829a0353a 909 } LPC_EMAC_TypeDef;
tushki7 0:60d829a0353a 910
tushki7 0:60d829a0353a 911 #if defined ( __CC_ARM )
tushki7 0:60d829a0353a 912 #pragma no_anon_unions
tushki7 0:60d829a0353a 913 #endif
tushki7 0:60d829a0353a 914
tushki7 0:60d829a0353a 915
tushki7 0:60d829a0353a 916 /******************************************************************************/
tushki7 0:60d829a0353a 917 /* Peripheral memory map */
tushki7 0:60d829a0353a 918 /******************************************************************************/
tushki7 0:60d829a0353a 919 /* Base addresses */
tushki7 0:60d829a0353a 920 #define LPC_FLASH_BASE (0x00000000UL)
tushki7 0:60d829a0353a 921 #define LPC_RAM_BASE (0x10000000UL)
tushki7 0:60d829a0353a 922 #define LPC_GPIO_BASE (0x2009C000UL)
tushki7 0:60d829a0353a 923 #define LPC_APB0_BASE (0x40000000UL)
tushki7 0:60d829a0353a 924 #define LPC_APB1_BASE (0x40080000UL)
tushki7 0:60d829a0353a 925 #define LPC_AHB_BASE (0x50000000UL)
tushki7 0:60d829a0353a 926 #define LPC_CM3_BASE (0xE0000000UL)
tushki7 0:60d829a0353a 927
tushki7 0:60d829a0353a 928 /* APB0 peripherals */
tushki7 0:60d829a0353a 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
tushki7 0:60d829a0353a 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
tushki7 0:60d829a0353a 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
tushki7 0:60d829a0353a 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
tushki7 0:60d829a0353a 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
tushki7 0:60d829a0353a 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
tushki7 0:60d829a0353a 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
tushki7 0:60d829a0353a 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
tushki7 0:60d829a0353a 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
tushki7 0:60d829a0353a 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
tushki7 0:60d829a0353a 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
tushki7 0:60d829a0353a 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
tushki7 0:60d829a0353a 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
tushki7 0:60d829a0353a 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
tushki7 0:60d829a0353a 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
tushki7 0:60d829a0353a 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
tushki7 0:60d829a0353a 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
tushki7 0:60d829a0353a 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
tushki7 0:60d829a0353a 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
tushki7 0:60d829a0353a 948
tushki7 0:60d829a0353a 949 /* APB1 peripherals */
tushki7 0:60d829a0353a 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
tushki7 0:60d829a0353a 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
tushki7 0:60d829a0353a 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
tushki7 0:60d829a0353a 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
tushki7 0:60d829a0353a 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
tushki7 0:60d829a0353a 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
tushki7 0:60d829a0353a 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
tushki7 0:60d829a0353a 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
tushki7 0:60d829a0353a 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
tushki7 0:60d829a0353a 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
tushki7 0:60d829a0353a 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
tushki7 0:60d829a0353a 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
tushki7 0:60d829a0353a 962
tushki7 0:60d829a0353a 963 /* AHB peripherals */
tushki7 0:60d829a0353a 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
tushki7 0:60d829a0353a 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
tushki7 0:60d829a0353a 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
tushki7 0:60d829a0353a 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
tushki7 0:60d829a0353a 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
tushki7 0:60d829a0353a 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
tushki7 0:60d829a0353a 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
tushki7 0:60d829a0353a 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
tushki7 0:60d829a0353a 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
tushki7 0:60d829a0353a 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
tushki7 0:60d829a0353a 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
tushki7 0:60d829a0353a 975
tushki7 0:60d829a0353a 976 /* GPIOs */
tushki7 0:60d829a0353a 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
tushki7 0:60d829a0353a 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
tushki7 0:60d829a0353a 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
tushki7 0:60d829a0353a 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
tushki7 0:60d829a0353a 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
tushki7 0:60d829a0353a 982
tushki7 0:60d829a0353a 983
tushki7 0:60d829a0353a 984 /******************************************************************************/
tushki7 0:60d829a0353a 985 /* Peripheral declaration */
tushki7 0:60d829a0353a 986 /******************************************************************************/
tushki7 0:60d829a0353a 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
tushki7 0:60d829a0353a 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
tushki7 0:60d829a0353a 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
tushki7 0:60d829a0353a 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
tushki7 0:60d829a0353a 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
tushki7 0:60d829a0353a 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
tushki7 0:60d829a0353a 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
tushki7 0:60d829a0353a 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
tushki7 0:60d829a0353a 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
tushki7 0:60d829a0353a 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
tushki7 0:60d829a0353a 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
tushki7 0:60d829a0353a 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
tushki7 0:60d829a0353a 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
tushki7 0:60d829a0353a 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
tushki7 0:60d829a0353a 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
tushki7 0:60d829a0353a 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
tushki7 0:60d829a0353a 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
tushki7 0:60d829a0353a 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
tushki7 0:60d829a0353a 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
tushki7 0:60d829a0353a 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
tushki7 0:60d829a0353a 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
tushki7 0:60d829a0353a 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
tushki7 0:60d829a0353a 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
tushki7 0:60d829a0353a 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
tushki7 0:60d829a0353a 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
tushki7 0:60d829a0353a 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
tushki7 0:60d829a0353a 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
tushki7 0:60d829a0353a 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
tushki7 0:60d829a0353a 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
tushki7 0:60d829a0353a 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
tushki7 0:60d829a0353a 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
tushki7 0:60d829a0353a 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
tushki7 0:60d829a0353a 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
tushki7 0:60d829a0353a 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
tushki7 0:60d829a0353a 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
tushki7 0:60d829a0353a 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
tushki7 0:60d829a0353a 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
tushki7 0:60d829a0353a 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
tushki7 0:60d829a0353a 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
tushki7 0:60d829a0353a 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
tushki7 0:60d829a0353a 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
tushki7 0:60d829a0353a 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
tushki7 0:60d829a0353a 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
tushki7 0:60d829a0353a 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
tushki7 0:60d829a0353a 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
tushki7 0:60d829a0353a 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
tushki7 0:60d829a0353a 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
tushki7 0:60d829a0353a 1034
tushki7 0:60d829a0353a 1035 #endif // __LPC17xx_H__