FRDM_K64F_LCD - A simple 128x32 graphical LCD program to quicksta…

Users » tushki7 » Code » FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies: C12832

mbed/TARGET_LPC1549/LPC15xx.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:: tushki7
Date:: Sun Apr 12 15:45:52 2015 +0000
Revision:: 1:eb68c94a8ee5
Parent:: 0:60d829a0353a

A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

User	Revision	Line number	New contents of line
tushki7	0:60d829a0353a	1
tushki7	0:60d829a0353a	2	/**************************************************************************************************//
tushki7	0:60d829a0353a	3	* @file LPC15xx.h
tushki7	0:60d829a0353a	4	*
tushki7	0:60d829a0353a	5	* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
tushki7	0:60d829a0353a	6	* LPC15xx from .
tushki7	0:60d829a0353a	7	*
tushki7	0:60d829a0353a	8	* @version V0.3
tushki7	0:60d829a0353a	9	* @date 17. July 2013
tushki7	0:60d829a0353a	10	*
tushki7	0:60d829a0353a	11	* @note Generated with SVDConv V2.80
tushki7	0:60d829a0353a	12	* from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
tushki7	0:60d829a0353a	13	*
tushki7	0:60d829a0353a	14	* modified by Keil
tushki7	0:60d829a0353a	15	* modified by ytsuboi
tushki7	0:60d829a0353a	16	*******************************************************************************************************/
tushki7	0:60d829a0353a	17
tushki7	0:60d829a0353a	18
tushki7	0:60d829a0353a	19
tushki7	0:60d829a0353a	20	/** @addtogroup (null)
tushki7	0:60d829a0353a	21	* @{
tushki7	0:60d829a0353a	22	*/
tushki7	0:60d829a0353a	23
tushki7	0:60d829a0353a	24	/** @addtogroup LPC15xx
tushki7	0:60d829a0353a	25	* @{
tushki7	0:60d829a0353a	26	*/
tushki7	0:60d829a0353a	27
tushki7	0:60d829a0353a	28	#ifndef LPC15XX_H
tushki7	0:60d829a0353a	29	#define LPC15XX_H
tushki7	0:60d829a0353a	30
tushki7	0:60d829a0353a	31	#ifdef __cplusplus
tushki7	0:60d829a0353a	32	extern "C" {
tushki7	0:60d829a0353a	33	#endif
tushki7	0:60d829a0353a	34
tushki7	0:60d829a0353a	35
tushki7	0:60d829a0353a	36	/* ------------------------- Interrupt Number Definition ------------------------ */
tushki7	0:60d829a0353a	37
tushki7	0:60d829a0353a	38	typedef enum {
tushki7	0:60d829a0353a	39	/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
tushki7	0:60d829a0353a	40	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
tushki7	0:60d829a0353a	41	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
tushki7	0:60d829a0353a	42	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
tushki7	0:60d829a0353a	43	MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
tushki7	0:60d829a0353a	44	and No Match */
tushki7	0:60d829a0353a	45	BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
tushki7	0:60d829a0353a	46	related Fault */
tushki7	0:60d829a0353a	47	UsageFault_IRQn = -10, /!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition /
tushki7	0:60d829a0353a	48	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
tushki7	0:60d829a0353a	49	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
tushki7	0:60d829a0353a	50	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
tushki7	0:60d829a0353a	51	SysTick_IRQn = -1, /!< 15 System Tick Timer /
tushki7	0:60d829a0353a	52	/* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
tushki7	0:60d829a0353a	53	WDT_IRQn = 0, /!< 0 WDT /
tushki7	0:60d829a0353a	54	BOD_IRQn = 1, /!< 1 BOD /
tushki7	0:60d829a0353a	55	FLASH_IRQn = 2, /!< 2 FLASH /
tushki7	0:60d829a0353a	56	EE_IRQn = 3, /!< 3 EE /
tushki7	0:60d829a0353a	57	DMA_IRQn = 4, /!< 4 DMA /
tushki7	0:60d829a0353a	58	GINT0_IRQn = 5, /!< 5 GINT0 /
tushki7	0:60d829a0353a	59	GINT1_IRQn = 6, /!< 6 GINT1 /
tushki7	0:60d829a0353a	60	PIN_INT0_IRQn = 7, /!< 7 PIN_INT0 /
tushki7	0:60d829a0353a	61	PIN_INT1_IRQn = 8, /!< 8 PIN_INT1 /
tushki7	0:60d829a0353a	62	PIN_INT2_IRQn = 9, /!< 9 PIN_INT2 /
tushki7	0:60d829a0353a	63	PIN_INT3_IRQn = 10, /!< 10 PIN_INT3 /
tushki7	0:60d829a0353a	64	PIN_INT4_IRQn = 11, /!< 11 PIN_INT4 /
tushki7	0:60d829a0353a	65	PIN_INT5_IRQn = 12, /!< 12 PIN_INT5 /
tushki7	0:60d829a0353a	66	PIN_INT6_IRQn = 13, /!< 13 PIN_INT6 /
tushki7	0:60d829a0353a	67	PIN_INT7_IRQn = 14, /!< 14 PIN_INT7 /
tushki7	0:60d829a0353a	68	RIT_IRQn = 15, /!< 15 RIT /
tushki7	0:60d829a0353a	69	SCT0_IRQn = 16, /!< 16 SCT0 /
tushki7	0:60d829a0353a	70	SCT1_IRQn = 17, /!< 17 SCT1 /
tushki7	0:60d829a0353a	71	SCT2_IRQn = 18, /!< 18 SCT2 /
tushki7	0:60d829a0353a	72	SCT3_IRQn = 19, /!< 19 SCT3 /
tushki7	0:60d829a0353a	73	MRT_IRQn = 20, /!< 20 MRT /
tushki7	0:60d829a0353a	74	UART0_IRQn = 21, /!< 21 UART0 /
tushki7	0:60d829a0353a	75	UART1_IRQn = 22, /!< 22 UART1 /
tushki7	0:60d829a0353a	76	UART2_IRQn = 23, /!< 23 UART2 /
tushki7	0:60d829a0353a	77	I2C0_IRQn = 24, /!< 24 I2C0 /
tushki7	0:60d829a0353a	78	SPI0_IRQn = 25, /!< 25 SPI0 /
tushki7	0:60d829a0353a	79	SPI1_IRQn = 26, /!< 26 SPI1 /
tushki7	0:60d829a0353a	80	C_CAN0_IRQn = 27, /!< 27 C_CAN0 /
tushki7	0:60d829a0353a	81	USB_IRQ_IRQn = 28, /!< 28 USB_IRQ /
tushki7	0:60d829a0353a	82	USB_FIQ_IRQn = 29, /!< 29 USB_FIQ /
tushki7	0:60d829a0353a	83	USBWAKEUP_IRQn = 30, /!< 30 USBWAKEUP /
tushki7	0:60d829a0353a	84	ADC0_SEQA_IRQn = 31, /!< 31 ADC0_SEQA /
tushki7	0:60d829a0353a	85	ADC0_SEQB_IRQn = 32, /!< 32 ADC0_SEQB /
tushki7	0:60d829a0353a	86	ADC0_THCMP_IRQn = 33, /!< 33 ADC0_THCMP /
tushki7	0:60d829a0353a	87	ADC0_OVR_IRQn = 34, /!< 34 ADC0_OVR /
tushki7	0:60d829a0353a	88	ADC1_SEQA_IRQn = 35, /!< 35 ADC1_SEQA /
tushki7	0:60d829a0353a	89	ADC1_SEQB_IRQn = 36, /!< 36 ADC1_SEQB /
tushki7	0:60d829a0353a	90	ADC1_THCMP_IRQn = 37, /!< 37 ADC1_THCMP /
tushki7	0:60d829a0353a	91	ADC1_OVR_IRQn = 38, /!< 38 ADC1_OVR /
tushki7	0:60d829a0353a	92	DAC_IRQn = 39, /!< 39 DAC /
tushki7	0:60d829a0353a	93	CMP0_IRQn = 40, /!< 40 CMP0 /
tushki7	0:60d829a0353a	94	CMP1_IRQn = 41, /!< 41 CMP1 /
tushki7	0:60d829a0353a	95	CMP2_IRQn = 42, /!< 42 CMP2 /
tushki7	0:60d829a0353a	96	CMP3_IRQn = 43, /!< 43 CMP3 /
tushki7	0:60d829a0353a	97	QEI_IRQn = 44, /!< 44 QEI /
tushki7	0:60d829a0353a	98	RTC_ALARM_IRQn = 45, /!< 45 RTC_ALARM /
tushki7	0:60d829a0353a	99	RTC_WAKE_IRQn = 46 /!< 46 RTC_WAKE /
tushki7	0:60d829a0353a	100	} IRQn_Type;
tushki7	0:60d829a0353a	101
tushki7	0:60d829a0353a	102
tushki7	0:60d829a0353a	103	/** @addtogroup Configuration_of_CMSIS
tushki7	0:60d829a0353a	104	* @{
tushki7	0:60d829a0353a	105	*/
tushki7	0:60d829a0353a	106
tushki7	0:60d829a0353a	107
tushki7	0:60d829a0353a	108	/* ================================================================================ */
tushki7	0:60d829a0353a	109	/* ================ Processor and Core Peripheral Section ================ */
tushki7	0:60d829a0353a	110	/* ================================================================================ */
tushki7	0:60d829a0353a	111
tushki7	0:60d829a0353a	112	/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
tushki7	0:60d829a0353a	113	#define __CM3_REV 0x0201 /!< Cortex-M3 Core Revision /
tushki7	0:60d829a0353a	114	#define __MPU_PRESENT 0 /!< MPU present or not /
tushki7	0:60d829a0353a	115	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
tushki7	0:60d829a0353a	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
tushki7	0:60d829a0353a	117	/** @} / / End of group Configuration_of_CMSIS */
tushki7	0:60d829a0353a	118
tushki7	0:60d829a0353a	119	#include "core_cm3.h" /!< Cortex-M3 processor and core peripherals /
tushki7	0:60d829a0353a	120	#include "system_LPC15xx.h" /!< LPC15xx System /
tushki7	0:60d829a0353a	121
tushki7	0:60d829a0353a	122
tushki7	0:60d829a0353a	123	/* ================================================================================ */
tushki7	0:60d829a0353a	124	/* ================ Device Specific Peripheral Section ================ */
tushki7	0:60d829a0353a	125	/* ================================================================================ */
tushki7	0:60d829a0353a	126
tushki7	0:60d829a0353a	127
tushki7	0:60d829a0353a	128	/** @addtogroup Device_Peripheral_Registers
tushki7	0:60d829a0353a	129	* @{
tushki7	0:60d829a0353a	130	*/
tushki7	0:60d829a0353a	131
tushki7	0:60d829a0353a	132
tushki7	0:60d829a0353a	133	/* ------------------- Start of section using anonymous unions ------------------ */
tushki7	0:60d829a0353a	134	#if defined(__CC_ARM)
tushki7	0:60d829a0353a	135	#pragma push
tushki7	0:60d829a0353a	136	#pragma anon_unions
tushki7	0:60d829a0353a	137	#elif defined(__ICCARM__)
tushki7	0:60d829a0353a	138	#pragma language=extended
tushki7	0:60d829a0353a	139	#elif defined(__GNUC__)
tushki7	0:60d829a0353a	140	/* anonymous unions are enabled by default */
tushki7	0:60d829a0353a	141	#elif defined(__TMS470__)
tushki7	0:60d829a0353a	142	/* anonymous unions are enabled by default */
tushki7	0:60d829a0353a	143	#elif defined(__TASKING__)
tushki7	0:60d829a0353a	144	#pragma warning 586
tushki7	0:60d829a0353a	145	#else
tushki7	0:60d829a0353a	146	#warning Not supported compiler type
tushki7	0:60d829a0353a	147	#endif
tushki7	0:60d829a0353a	148
tushki7	0:60d829a0353a	149
tushki7	0:60d829a0353a	150
tushki7	0:60d829a0353a	151	/* ================================================================================ */
tushki7	0:60d829a0353a	152	/* ================ GPIO_PORT ================ */
tushki7	0:60d829a0353a	153	/* ================================================================================ */
tushki7	0:60d829a0353a	154
tushki7	0:60d829a0353a	155
tushki7	0:60d829a0353a	156	/**
tushki7	0:60d829a0353a	157	* @brief General Purpose I/O (GPIO) (GPIO_PORT)
tushki7	0:60d829a0353a	158	*/
tushki7	0:60d829a0353a	159
tushki7	0:60d829a0353a	160	typedef struct { /!< GPIO_PORT Structure /
tushki7	0:60d829a0353a	161	__IO uint8_t B[76]; /!< Byte pin registers /
tushki7	0:60d829a0353a	162	__I uint32_t RESERVED0[45];
tushki7	0:60d829a0353a	163	__IO uint32_t W[76]; /!< Word pin registers /
tushki7	0:60d829a0353a	164	__I uint32_t RESERVED1[1908];
tushki7	0:60d829a0353a	165	__IO uint32_t DIR[3]; /!< Port Direction registers /
tushki7	0:60d829a0353a	166	__I uint32_t RESERVED2[29];
tushki7	0:60d829a0353a	167	__IO uint32_t MASK[3]; /!< Port Mask register /
tushki7	0:60d829a0353a	168	__I uint32_t RESERVED3[29];
tushki7	0:60d829a0353a	169	__IO uint32_t PIN[3]; /!< Port pin register /
tushki7	0:60d829a0353a	170	__I uint32_t RESERVED4[29];
tushki7	0:60d829a0353a	171	__IO uint32_t MPIN[3]; /!< Masked port register /
tushki7	0:60d829a0353a	172	__I uint32_t RESERVED5[29];
tushki7	0:60d829a0353a	173	__IO uint32_t SET[3]; /!< Write: Set port register Read: port output bits /
tushki7	0:60d829a0353a	174	__I uint32_t RESERVED6[29];
tushki7	0:60d829a0353a	175	__O uint32_t CLR[3]; /!< Clear port /
tushki7	0:60d829a0353a	176	__I uint32_t RESERVED7[29];
tushki7	0:60d829a0353a	177	__O uint32_t NOT[3]; /!< Toggle port /
tushki7	0:60d829a0353a	178	} LPC_GPIO_PORT_Type;
tushki7	0:60d829a0353a	179
tushki7	0:60d829a0353a	180
tushki7	0:60d829a0353a	181	/* ================================================================================ */
tushki7	0:60d829a0353a	182	/* ================ DMA ================ */
tushki7	0:60d829a0353a	183	/* ================================================================================ */
tushki7	0:60d829a0353a	184
tushki7	0:60d829a0353a	185
tushki7	0:60d829a0353a	186	/**
tushki7	0:60d829a0353a	187	* @brief DMA controller (DMA)
tushki7	0:60d829a0353a	188	*/
tushki7	0:60d829a0353a	189
tushki7	0:60d829a0353a	190	typedef struct { /!< DMA Structure /
tushki7	0:60d829a0353a	191	__IO uint32_t CTRL; /!< DMA control. /
tushki7	0:60d829a0353a	192	__I uint32_t INTSTAT; /!< Interrupt status. /
tushki7	0:60d829a0353a	193	__IO uint32_t SRAMBASE; /!< SRAM address of the channel configuration table. /
tushki7	0:60d829a0353a	194	__I uint32_t RESERVED0[5];
tushki7	0:60d829a0353a	195	__IO uint32_t ENABLESET0; /!< Channel Enable read and Set for all DMA channels. /
tushki7	0:60d829a0353a	196	__I uint32_t RESERVED1;
tushki7	0:60d829a0353a	197	__O uint32_t ENABLECLR0; /!< Channel Enable Clear for all DMA channels. /
tushki7	0:60d829a0353a	198	__I uint32_t RESERVED2;
tushki7	0:60d829a0353a	199	__I uint32_t ACTIVE0; /!< Channel Active status for all DMA channels. /
tushki7	0:60d829a0353a	200	__I uint32_t RESERVED3;
tushki7	0:60d829a0353a	201	__I uint32_t BUSY0; /!< Channel Busy status for all DMA channels. /
tushki7	0:60d829a0353a	202	__I uint32_t RESERVED4;
tushki7	0:60d829a0353a	203	__IO uint32_t ERRINT0; /!< Error Interrupt status for all DMA channels. /
tushki7	0:60d829a0353a	204	__I uint32_t RESERVED5;
tushki7	0:60d829a0353a	205	__IO uint32_t INTENSET0; /!< Interrupt Enable read and Set for all DMA channels. /
tushki7	0:60d829a0353a	206	__I uint32_t RESERVED6;
tushki7	0:60d829a0353a	207	__O uint32_t INTENCLR0; /!< Interrupt Enable Clear for all DMA channels. /
tushki7	0:60d829a0353a	208	__I uint32_t RESERVED7;
tushki7	0:60d829a0353a	209	__IO uint32_t INTA0; /!< Interrupt A status for all DMA channels. /
tushki7	0:60d829a0353a	210	__I uint32_t RESERVED8;
tushki7	0:60d829a0353a	211	__IO uint32_t INTB0; /!< Interrupt B status for all DMA channels. /
tushki7	0:60d829a0353a	212	__I uint32_t RESERVED9;
tushki7	0:60d829a0353a	213	__O uint32_t SETVALID0; /!< Set ValidPending control bits for all DMA channels. /
tushki7	0:60d829a0353a	214	__I uint32_t RESERVED10;
tushki7	0:60d829a0353a	215	__O uint32_t SETTRIG0; /!< Set Trigger control bits for all DMA channels. /
tushki7	0:60d829a0353a	216	__I uint32_t RESERVED11;
tushki7	0:60d829a0353a	217	__O uint32_t ABORT0; /!< Channel Abort control for all DMA channels. /
tushki7	0:60d829a0353a	218	__I uint32_t RESERVED12[225];
tushki7	0:60d829a0353a	219	__IO uint32_t CFG0; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	220	__I uint32_t CTLSTAT0; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	221	__IO uint32_t XFERCFG0; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	222	__I uint32_t RESERVED13;
tushki7	0:60d829a0353a	223	__IO uint32_t CFG1; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	224	__I uint32_t CTLSTAT1; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	225	__IO uint32_t XFERCFG1; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	226	__I uint32_t RESERVED14;
tushki7	0:60d829a0353a	227	__IO uint32_t CFG2; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	228	__I uint32_t CTLSTAT2; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	229	__IO uint32_t XFERCFG2; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	230	__I uint32_t RESERVED15;
tushki7	0:60d829a0353a	231	__IO uint32_t CFG3; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	232	__I uint32_t CTLSTAT3; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	233	__IO uint32_t XFERCFG3; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	234	__I uint32_t RESERVED16;
tushki7	0:60d829a0353a	235	__IO uint32_t CFG4; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	236	__I uint32_t CTLSTAT4; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	237	__IO uint32_t XFERCFG4; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	238	__I uint32_t RESERVED17;
tushki7	0:60d829a0353a	239	__IO uint32_t CFG5; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	240	__I uint32_t CTLSTAT5; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	241	__IO uint32_t XFERCFG5; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	242	__I uint32_t RESERVED18;
tushki7	0:60d829a0353a	243	__IO uint32_t CFG6; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	244	__I uint32_t CTLSTAT6; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	245	__IO uint32_t XFERCFG6; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	246	__I uint32_t RESERVED19;
tushki7	0:60d829a0353a	247	__IO uint32_t CFG7; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	248	__I uint32_t CTLSTAT7; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	249	__IO uint32_t XFERCFG7; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	250	__I uint32_t RESERVED20;
tushki7	0:60d829a0353a	251	__IO uint32_t CFG8; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	252	__I uint32_t CTLSTAT8; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	253	__IO uint32_t XFERCFG8; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	254	__I uint32_t RESERVED21;
tushki7	0:60d829a0353a	255	__IO uint32_t CFG9; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	256	__I uint32_t CTLSTAT9; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	257	__IO uint32_t XFERCFG9; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	258	__I uint32_t RESERVED22;
tushki7	0:60d829a0353a	259	__IO uint32_t CFG10; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	260	__I uint32_t CTLSTAT10; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	261	__IO uint32_t XFERCFG10; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	262	__I uint32_t RESERVED23;
tushki7	0:60d829a0353a	263	__IO uint32_t CFG11; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	264	__I uint32_t CTLSTAT11; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	265	__IO uint32_t XFERCFG11; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	266	__I uint32_t RESERVED24;
tushki7	0:60d829a0353a	267	__IO uint32_t CFG12; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	268	__I uint32_t CTLSTAT12; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	269	__IO uint32_t XFERCFG12; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	270	__I uint32_t RESERVED25;
tushki7	0:60d829a0353a	271	__IO uint32_t CFG13; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	272	__I uint32_t CTLSTAT13; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	273	__IO uint32_t XFERCFG13; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	274	__I uint32_t RESERVED26;
tushki7	0:60d829a0353a	275	__IO uint32_t CFG14; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	276	__I uint32_t CTLSTAT14; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	277	__IO uint32_t XFERCFG14; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	278	__I uint32_t RESERVED27;
tushki7	0:60d829a0353a	279	__IO uint32_t CFG15; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	280	__I uint32_t CTLSTAT15; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	281	__IO uint32_t XFERCFG15; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	282	__I uint32_t RESERVED28;
tushki7	0:60d829a0353a	283	__IO uint32_t CFG16; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	284	__I uint32_t CTLSTAT16; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	285	__IO uint32_t XFERCFG16; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	286	__I uint32_t RESERVED29;
tushki7	0:60d829a0353a	287	__IO uint32_t CFG17; /!< Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	288	__I uint32_t CTLSTAT17; /!< Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	289	__IO uint32_t XFERCFG17; /!< Transfer configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	290	} LPC_DMA_Type;
tushki7	0:60d829a0353a	291
tushki7	0:60d829a0353a	292
tushki7	0:60d829a0353a	293	/* ================================================================================ */
tushki7	0:60d829a0353a	294	/* ================ USB ================ */
tushki7	0:60d829a0353a	295	/* ================================================================================ */
tushki7	0:60d829a0353a	296
tushki7	0:60d829a0353a	297
tushki7	0:60d829a0353a	298	/**
tushki7	0:60d829a0353a	299	* @brief USB device controller (USB)
tushki7	0:60d829a0353a	300	*/
tushki7	0:60d829a0353a	301
tushki7	0:60d829a0353a	302	typedef struct { /!< USB Structure /
tushki7	0:60d829a0353a	303	__IO uint32_t DEVCMDSTAT; /!< USB Device Command/Status register /
tushki7	0:60d829a0353a	304	__IO uint32_t INFO; /!< USB Info register /
tushki7	0:60d829a0353a	305	__IO uint32_t EPLISTSTART; /!< USB EP Command/Status List start address /
tushki7	0:60d829a0353a	306	__IO uint32_t DATABUFSTART; /!< USB Data buffer start address /
tushki7	0:60d829a0353a	307	__IO uint32_t LPM; /!< Link Power Management register /
tushki7	0:60d829a0353a	308	__IO uint32_t EPSKIP; /!< USB Endpoint skip /
tushki7	0:60d829a0353a	309	__IO uint32_t EPINUSE; /!< USB Endpoint Buffer in use /
tushki7	0:60d829a0353a	310	__IO uint32_t EPBUFCFG; /!< USB Endpoint Buffer Configuration register /
tushki7	0:60d829a0353a	311	__IO uint32_t INTSTAT; /!< USB interrupt status register /
tushki7	0:60d829a0353a	312	__IO uint32_t INTEN; /!< USB interrupt enable register /
tushki7	0:60d829a0353a	313	__IO uint32_t INTSETSTAT; /!< USB set interrupt status register /
tushki7	0:60d829a0353a	314	__IO uint32_t INTROUTING; /!< USB interrupt routing register /
tushki7	0:60d829a0353a	315	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	316	__I uint32_t EPTOGGLE; /!< USB Endpoint toggle register /
tushki7	0:60d829a0353a	317	} LPC_USB_Type;
tushki7	0:60d829a0353a	318
tushki7	0:60d829a0353a	319
tushki7	0:60d829a0353a	320	/* ================================================================================ */
tushki7	0:60d829a0353a	321	/* ================ CRC ================ */
tushki7	0:60d829a0353a	322	/* ================================================================================ */
tushki7	0:60d829a0353a	323
tushki7	0:60d829a0353a	324
tushki7	0:60d829a0353a	325	/**
tushki7	0:60d829a0353a	326	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
tushki7	0:60d829a0353a	327	*/
tushki7	0:60d829a0353a	328
tushki7	0:60d829a0353a	329	typedef struct { /!< CRC Structure /
tushki7	0:60d829a0353a	330	__IO uint32_t MODE; /!< CRC mode register /
tushki7	0:60d829a0353a	331	__IO uint32_t SEED; /!< CRC seed register /
tushki7	0:60d829a0353a	332
tushki7	0:60d829a0353a	333	union {
tushki7	0:60d829a0353a	334	__O uint32_t WR_DATA; /!< CRC data register /
tushki7	0:60d829a0353a	335	__I uint32_t SUM; /!< CRC checksum register /
tushki7	0:60d829a0353a	336	};
tushki7	0:60d829a0353a	337	} LPC_CRC_Type;
tushki7	0:60d829a0353a	338
tushki7	0:60d829a0353a	339
tushki7	0:60d829a0353a	340	/* ================================================================================ */
tushki7	0:60d829a0353a	341	/* ================ SCT0 ================ */
tushki7	0:60d829a0353a	342	/* ================================================================================ */
tushki7	0:60d829a0353a	343
tushki7	0:60d829a0353a	344
tushki7	0:60d829a0353a	345	/**
tushki7	0:60d829a0353a	346	* @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
tushki7	0:60d829a0353a	347	*/
tushki7	0:60d829a0353a	348
tushki7	0:60d829a0353a	349	typedef struct { /!< SCT0 Structure /
tushki7	0:60d829a0353a	350	__IO uint32_t CONFIG; /!< SCT configuration register /
tushki7	0:60d829a0353a	351	__IO uint32_t CTRL; /!< SCT control register /
tushki7	0:60d829a0353a	352	__IO uint32_t LIMIT; /!< SCT limit register /
tushki7	0:60d829a0353a	353	__IO uint32_t HALT; /!< SCT halt condition register /
tushki7	0:60d829a0353a	354	__IO uint32_t STOP; /!< SCT stop condition register /
tushki7	0:60d829a0353a	355	__IO uint32_t START; /!< SCT start condition register /
tushki7	0:60d829a0353a	356	__IO uint32_t DITHER; /!< SCT dither condition register /
tushki7	0:60d829a0353a	357	__I uint32_t RESERVED0[9];
tushki7	0:60d829a0353a	358	__IO uint32_t COUNT; /!< SCT counter register /
tushki7	0:60d829a0353a	359	__IO uint32_t STATE; /!< SCT state register /
tushki7	0:60d829a0353a	360	__I uint32_t INPUT; /!< SCT input register /
tushki7	0:60d829a0353a	361	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
tushki7	0:60d829a0353a	362	__IO uint32_t OUTPUT; /!< SCT output register /
tushki7	0:60d829a0353a	363	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
tushki7	0:60d829a0353a	364	__IO uint32_t RES; /!< SCT conflict resolution register /
tushki7	0:60d829a0353a	365	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
tushki7	0:60d829a0353a	366	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
tushki7	0:60d829a0353a	367	__I uint32_t RESERVED1[35];
tushki7	0:60d829a0353a	368	__IO uint32_t EVEN; /!< SCT event enable register /
tushki7	0:60d829a0353a	369	__IO uint32_t EVFLAG; /!< SCT event flag register /
tushki7	0:60d829a0353a	370	__IO uint32_t CONEN; /!< SCT conflict enable register /
tushki7	0:60d829a0353a	371	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
tushki7	0:60d829a0353a	372
tushki7	0:60d829a0353a	373	union {
tushki7	0:60d829a0353a	374	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	375	REGMODE15 = 1 */
tushki7	0:60d829a0353a	376	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	377	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	378	};
tushki7	0:60d829a0353a	379
tushki7	0:60d829a0353a	380	union {
tushki7	0:60d829a0353a	381	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	382	REGMODE15 = 1 */
tushki7	0:60d829a0353a	383	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	384	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	385	};
tushki7	0:60d829a0353a	386
tushki7	0:60d829a0353a	387	union {
tushki7	0:60d829a0353a	388	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	389	REGMODE15 = 1 */
tushki7	0:60d829a0353a	390	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	391	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	392	};
tushki7	0:60d829a0353a	393
tushki7	0:60d829a0353a	394	union {
tushki7	0:60d829a0353a	395	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	396	REGMODE15 = 1 */
tushki7	0:60d829a0353a	397	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	398	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	399	};
tushki7	0:60d829a0353a	400
tushki7	0:60d829a0353a	401	union {
tushki7	0:60d829a0353a	402	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	403	REGMODE15 = 1 */
tushki7	0:60d829a0353a	404	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	405	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	406	};
tushki7	0:60d829a0353a	407
tushki7	0:60d829a0353a	408	union {
tushki7	0:60d829a0353a	409	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	410	REGMODE15 = 1 */
tushki7	0:60d829a0353a	411	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	412	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	413	};
tushki7	0:60d829a0353a	414
tushki7	0:60d829a0353a	415	union {
tushki7	0:60d829a0353a	416	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	417	REGMODE15 = 1 */
tushki7	0:60d829a0353a	418	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	419	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	420	};
tushki7	0:60d829a0353a	421
tushki7	0:60d829a0353a	422	union {
tushki7	0:60d829a0353a	423	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	424	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	425	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	426	REGMODE15 = 1 */
tushki7	0:60d829a0353a	427	};
tushki7	0:60d829a0353a	428
tushki7	0:60d829a0353a	429	union {
tushki7	0:60d829a0353a	430	__I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	431	REGMODE15 = 1 */
tushki7	0:60d829a0353a	432	__IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	433	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	434	};
tushki7	0:60d829a0353a	435
tushki7	0:60d829a0353a	436	union {
tushki7	0:60d829a0353a	437	__IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	438	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	439	__I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	440	REGMODE15 = 1 */
tushki7	0:60d829a0353a	441	};
tushki7	0:60d829a0353a	442
tushki7	0:60d829a0353a	443	union {
tushki7	0:60d829a0353a	444	__IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	445	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	446	__I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	447	REGMODE15 = 1 */
tushki7	0:60d829a0353a	448	};
tushki7	0:60d829a0353a	449
tushki7	0:60d829a0353a	450	union {
tushki7	0:60d829a0353a	451	__IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	452	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	453	__I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	454	REGMODE15 = 1 */
tushki7	0:60d829a0353a	455	};
tushki7	0:60d829a0353a	456
tushki7	0:60d829a0353a	457	union {
tushki7	0:60d829a0353a	458	__IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	459	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	460	__I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	461	REGMODE15 = 1 */
tushki7	0:60d829a0353a	462	};
tushki7	0:60d829a0353a	463
tushki7	0:60d829a0353a	464	union {
tushki7	0:60d829a0353a	465	__IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	466	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	467	__I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	468	REGMODE15 = 1 */
tushki7	0:60d829a0353a	469	};
tushki7	0:60d829a0353a	470
tushki7	0:60d829a0353a	471	union {
tushki7	0:60d829a0353a	472	__I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	473	REGMODE15 = 1 */
tushki7	0:60d829a0353a	474	__IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	475	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	476	};
tushki7	0:60d829a0353a	477
tushki7	0:60d829a0353a	478	union {
tushki7	0:60d829a0353a	479	__IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
tushki7	0:60d829a0353a	480	to REGMODE15 = 0 */
tushki7	0:60d829a0353a	481	__I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
tushki7	0:60d829a0353a	482	REGMODE15 = 1 */
tushki7	0:60d829a0353a	483	};
tushki7	0:60d829a0353a	484	__IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
tushki7	0:60d829a0353a	485	0 to 5. */
tushki7	0:60d829a0353a	486	__IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
tushki7	0:60d829a0353a	487	0 to 5. */
tushki7	0:60d829a0353a	488	__IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
tushki7	0:60d829a0353a	489	0 to 5. */
tushki7	0:60d829a0353a	490	__IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
tushki7	0:60d829a0353a	491	0 to 5. */
tushki7	0:60d829a0353a	492	__IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
tushki7	0:60d829a0353a	493	0 to 5. */
tushki7	0:60d829a0353a	494	__IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
tushki7	0:60d829a0353a	495	0 to 5. */
tushki7	0:60d829a0353a	496	__I uint32_t RESERVED2[42];
tushki7	0:60d829a0353a	497
tushki7	0:60d829a0353a	498	union {
tushki7	0:60d829a0353a	499	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	500	= 1 */
tushki7	0:60d829a0353a	501	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	502	= 0 */
tushki7	0:60d829a0353a	503	};
tushki7	0:60d829a0353a	504
tushki7	0:60d829a0353a	505	union {
tushki7	0:60d829a0353a	506	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	507	= 0 */
tushki7	0:60d829a0353a	508	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	509	= 1 */
tushki7	0:60d829a0353a	510	};
tushki7	0:60d829a0353a	511
tushki7	0:60d829a0353a	512	union {
tushki7	0:60d829a0353a	513	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	514	= 0 */
tushki7	0:60d829a0353a	515	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	516	= 1 */
tushki7	0:60d829a0353a	517	};
tushki7	0:60d829a0353a	518
tushki7	0:60d829a0353a	519	union {
tushki7	0:60d829a0353a	520	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	521	= 1 */
tushki7	0:60d829a0353a	522	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	523	= 0 */
tushki7	0:60d829a0353a	524	};
tushki7	0:60d829a0353a	525
tushki7	0:60d829a0353a	526	union {
tushki7	0:60d829a0353a	527	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	528	= 1 */
tushki7	0:60d829a0353a	529	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	530	= 0 */
tushki7	0:60d829a0353a	531	};
tushki7	0:60d829a0353a	532
tushki7	0:60d829a0353a	533	union {
tushki7	0:60d829a0353a	534	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	535	= 1 */
tushki7	0:60d829a0353a	536	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	537	= 0 */
tushki7	0:60d829a0353a	538	};
tushki7	0:60d829a0353a	539
tushki7	0:60d829a0353a	540	union {
tushki7	0:60d829a0353a	541	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	542	= 0 */
tushki7	0:60d829a0353a	543	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	544	= 1 */
tushki7	0:60d829a0353a	545	};
tushki7	0:60d829a0353a	546
tushki7	0:60d829a0353a	547	union {
tushki7	0:60d829a0353a	548	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	549	= 0 */
tushki7	0:60d829a0353a	550	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	551	= 1 */
tushki7	0:60d829a0353a	552	};
tushki7	0:60d829a0353a	553
tushki7	0:60d829a0353a	554	union {
tushki7	0:60d829a0353a	555	__IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	556	= 1 */
tushki7	0:60d829a0353a	557	__IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	558	= 0 */
tushki7	0:60d829a0353a	559	};
tushki7	0:60d829a0353a	560
tushki7	0:60d829a0353a	561	union {
tushki7	0:60d829a0353a	562	__IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	563	= 1 */
tushki7	0:60d829a0353a	564	__IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	565	= 0 */
tushki7	0:60d829a0353a	566	};
tushki7	0:60d829a0353a	567
tushki7	0:60d829a0353a	568	union {
tushki7	0:60d829a0353a	569	__IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	570	= 1 */
tushki7	0:60d829a0353a	571	__IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	572	= 0 */
tushki7	0:60d829a0353a	573	};
tushki7	0:60d829a0353a	574
tushki7	0:60d829a0353a	575	union {
tushki7	0:60d829a0353a	576	__IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	577	= 1 */
tushki7	0:60d829a0353a	578	__IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	579	= 0 */
tushki7	0:60d829a0353a	580	};
tushki7	0:60d829a0353a	581
tushki7	0:60d829a0353a	582	union {
tushki7	0:60d829a0353a	583	__IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	584	= 0 */
tushki7	0:60d829a0353a	585	__IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	586	= 1 */
tushki7	0:60d829a0353a	587	};
tushki7	0:60d829a0353a	588
tushki7	0:60d829a0353a	589	union {
tushki7	0:60d829a0353a	590	__IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	591	= 0 */
tushki7	0:60d829a0353a	592	__IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	593	= 1 */
tushki7	0:60d829a0353a	594	};
tushki7	0:60d829a0353a	595
tushki7	0:60d829a0353a	596	union {
tushki7	0:60d829a0353a	597	__IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	598	= 1 */
tushki7	0:60d829a0353a	599	__IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	600	= 0 */
tushki7	0:60d829a0353a	601	};
tushki7	0:60d829a0353a	602
tushki7	0:60d829a0353a	603	union {
tushki7	0:60d829a0353a	604	__IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
tushki7	0:60d829a0353a	605	= 1 */
tushki7	0:60d829a0353a	606	__IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
tushki7	0:60d829a0353a	607	= 0 */
tushki7	0:60d829a0353a	608	};
tushki7	0:60d829a0353a	609	__IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
tushki7	0:60d829a0353a	610	registers 0 to 5. */
tushki7	0:60d829a0353a	611	__IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
tushki7	0:60d829a0353a	612	registers 0 to 5. */
tushki7	0:60d829a0353a	613	__IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
tushki7	0:60d829a0353a	614	registers 0 to 5. */
tushki7	0:60d829a0353a	615	__IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
tushki7	0:60d829a0353a	616	registers 0 to 5. */
tushki7	0:60d829a0353a	617	__IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
tushki7	0:60d829a0353a	618	registers 0 to 5. */
tushki7	0:60d829a0353a	619	__IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
tushki7	0:60d829a0353a	620	registers 0 to 5. */
tushki7	0:60d829a0353a	621	__I uint32_t RESERVED3[42];
tushki7	0:60d829a0353a	622	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	623	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	624	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	625	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	626	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	627	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	628	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	629	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	630	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	631	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	632	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	633	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	634	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	635	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	636	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	637	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	638	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	639	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	640	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	641	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	642	__IO uint32_t EV10_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	643	__IO uint32_t EV10_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	644	__IO uint32_t EV11_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	645	__IO uint32_t EV11_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	646	__IO uint32_t EV12_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	647	__IO uint32_t EV12_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	648	__IO uint32_t EV13_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	649	__IO uint32_t EV13_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	650	__IO uint32_t EV14_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	651	__IO uint32_t EV14_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	652	__IO uint32_t EV15_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	653	__IO uint32_t EV15_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	654	__I uint32_t RESERVED4[96];
tushki7	0:60d829a0353a	655	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	656	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	657	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	658	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	659	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	660	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	661	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	662	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	663	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	664	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	665	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	666	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	667	__IO uint32_t OUT6_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	668	__IO uint32_t OUT6_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	669	__IO uint32_t OUT7_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	670	__IO uint32_t OUT7_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	671	__IO uint32_t OUT8_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	672	__IO uint32_t OUT8_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	673	__IO uint32_t OUT9_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	674	__IO uint32_t OUT9_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	675	} LPC_SCT0_Type;
tushki7	0:60d829a0353a	676
tushki7	0:60d829a0353a	677
tushki7	0:60d829a0353a	678	/* ================================================================================ */
tushki7	0:60d829a0353a	679	/* ================ SCT2 ================ */
tushki7	0:60d829a0353a	680	/* ================================================================================ */
tushki7	0:60d829a0353a	681
tushki7	0:60d829a0353a	682
tushki7	0:60d829a0353a	683	/**
tushki7	0:60d829a0353a	684	* @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
tushki7	0:60d829a0353a	685	*/
tushki7	0:60d829a0353a	686
tushki7	0:60d829a0353a	687	typedef struct { /!< SCT2 Structure /
tushki7	0:60d829a0353a	688	__IO uint32_t CONFIG; /!< SCT configuration register /
tushki7	0:60d829a0353a	689	__IO uint32_t CTRL; /!< SCT control register /
tushki7	0:60d829a0353a	690	__IO uint32_t LIMIT; /!< SCT limit register /
tushki7	0:60d829a0353a	691	__IO uint32_t HALT; /!< SCT halt condition register /
tushki7	0:60d829a0353a	692	__IO uint32_t STOP; /!< SCT stop condition register /
tushki7	0:60d829a0353a	693	__IO uint32_t START; /!< SCT start condition register /
tushki7	0:60d829a0353a	694	__I uint32_t RESERVED0[10];
tushki7	0:60d829a0353a	695	__IO uint32_t COUNT; /!< SCT counter register /
tushki7	0:60d829a0353a	696	__IO uint32_t STATE; /!< SCT state register /
tushki7	0:60d829a0353a	697	__I uint32_t INPUT; /!< SCT input register /
tushki7	0:60d829a0353a	698	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
tushki7	0:60d829a0353a	699	__IO uint32_t OUTPUT; /!< SCT output register /
tushki7	0:60d829a0353a	700	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
tushki7	0:60d829a0353a	701	__IO uint32_t RES; /!< SCT conflict resolution register /
tushki7	0:60d829a0353a	702	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
tushki7	0:60d829a0353a	703	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
tushki7	0:60d829a0353a	704	__I uint32_t RESERVED1[35];
tushki7	0:60d829a0353a	705	__IO uint32_t EVEN; /!< SCT event enable register /
tushki7	0:60d829a0353a	706	__IO uint32_t EVFLAG; /!< SCT event flag register /
tushki7	0:60d829a0353a	707	__IO uint32_t CONEN; /!< SCT conflict enable register /
tushki7	0:60d829a0353a	708	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
tushki7	0:60d829a0353a	709
tushki7	0:60d829a0353a	710	union {
tushki7	0:60d829a0353a	711	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
tushki7	0:60d829a0353a	712	= 1 */
tushki7	0:60d829a0353a	713	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
tushki7	0:60d829a0353a	714	REGMODE7 = 0 */
tushki7	0:60d829a0353a	715	};
tushki7	0:60d829a0353a	716
tushki7	0:60d829a0353a	717	union {
tushki7	0:60d829a0353a	718	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
tushki7	0:60d829a0353a	719	= 1 */
tushki7	0:60d829a0353a	720	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
tushki7	0:60d829a0353a	721	REGMODE7 = 0 */
tushki7	0:60d829a0353a	722	};
tushki7	0:60d829a0353a	723
tushki7	0:60d829a0353a	724	union {
tushki7	0:60d829a0353a	725	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
tushki7	0:60d829a0353a	726	= 1 */
tushki7	0:60d829a0353a	727	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
tushki7	0:60d829a0353a	728	REGMODE7 = 0 */
tushki7	0:60d829a0353a	729	};
tushki7	0:60d829a0353a	730
tushki7	0:60d829a0353a	731	union {
tushki7	0:60d829a0353a	732	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
tushki7	0:60d829a0353a	733	REGMODE7 = 0 */
tushki7	0:60d829a0353a	734	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
tushki7	0:60d829a0353a	735	= 1 */
tushki7	0:60d829a0353a	736	};
tushki7	0:60d829a0353a	737
tushki7	0:60d829a0353a	738	union {
tushki7	0:60d829a0353a	739	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
tushki7	0:60d829a0353a	740	= 1 */
tushki7	0:60d829a0353a	741	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
tushki7	0:60d829a0353a	742	REGMODE7 = 0 */
tushki7	0:60d829a0353a	743	};
tushki7	0:60d829a0353a	744
tushki7	0:60d829a0353a	745	union {
tushki7	0:60d829a0353a	746	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
tushki7	0:60d829a0353a	747	REGMODE7 = 0 */
tushki7	0:60d829a0353a	748	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
tushki7	0:60d829a0353a	749	= 1 */
tushki7	0:60d829a0353a	750	};
tushki7	0:60d829a0353a	751
tushki7	0:60d829a0353a	752	union {
tushki7	0:60d829a0353a	753	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
tushki7	0:60d829a0353a	754	= 1 */
tushki7	0:60d829a0353a	755	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
tushki7	0:60d829a0353a	756	REGMODE7 = 0 */
tushki7	0:60d829a0353a	757	};
tushki7	0:60d829a0353a	758
tushki7	0:60d829a0353a	759	union {
tushki7	0:60d829a0353a	760	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
tushki7	0:60d829a0353a	761	= 1 */
tushki7	0:60d829a0353a	762	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
tushki7	0:60d829a0353a	763	REGMODE7 = 0 */
tushki7	0:60d829a0353a	764	};
tushki7	0:60d829a0353a	765	__I uint32_t RESERVED2[56];
tushki7	0:60d829a0353a	766
tushki7	0:60d829a0353a	767	union {
tushki7	0:60d829a0353a	768	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
tushki7	0:60d829a0353a	769	= 1 */
tushki7	0:60d829a0353a	770	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
tushki7	0:60d829a0353a	771	= 0 */
tushki7	0:60d829a0353a	772	};
tushki7	0:60d829a0353a	773
tushki7	0:60d829a0353a	774	union {
tushki7	0:60d829a0353a	775	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
tushki7	0:60d829a0353a	776	= 1 */
tushki7	0:60d829a0353a	777	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
tushki7	0:60d829a0353a	778	= 0 */
tushki7	0:60d829a0353a	779	};
tushki7	0:60d829a0353a	780
tushki7	0:60d829a0353a	781	union {
tushki7	0:60d829a0353a	782	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
tushki7	0:60d829a0353a	783	= 1 */
tushki7	0:60d829a0353a	784	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
tushki7	0:60d829a0353a	785	= 0 */
tushki7	0:60d829a0353a	786	};
tushki7	0:60d829a0353a	787
tushki7	0:60d829a0353a	788	union {
tushki7	0:60d829a0353a	789	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
tushki7	0:60d829a0353a	790	= 0 */
tushki7	0:60d829a0353a	791	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
tushki7	0:60d829a0353a	792	= 1 */
tushki7	0:60d829a0353a	793	};
tushki7	0:60d829a0353a	794
tushki7	0:60d829a0353a	795	union {
tushki7	0:60d829a0353a	796	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
tushki7	0:60d829a0353a	797	= 1 */
tushki7	0:60d829a0353a	798	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
tushki7	0:60d829a0353a	799	= 0 */
tushki7	0:60d829a0353a	800	};
tushki7	0:60d829a0353a	801
tushki7	0:60d829a0353a	802	union {
tushki7	0:60d829a0353a	803	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
tushki7	0:60d829a0353a	804	= 0 */
tushki7	0:60d829a0353a	805	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
tushki7	0:60d829a0353a	806	= 1 */
tushki7	0:60d829a0353a	807	};
tushki7	0:60d829a0353a	808
tushki7	0:60d829a0353a	809	union {
tushki7	0:60d829a0353a	810	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
tushki7	0:60d829a0353a	811	= 1 */
tushki7	0:60d829a0353a	812	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
tushki7	0:60d829a0353a	813	= 0 */
tushki7	0:60d829a0353a	814	};
tushki7	0:60d829a0353a	815
tushki7	0:60d829a0353a	816	union {
tushki7	0:60d829a0353a	817	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
tushki7	0:60d829a0353a	818	= 1 */
tushki7	0:60d829a0353a	819	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
tushki7	0:60d829a0353a	820	= 0 */
tushki7	0:60d829a0353a	821	};
tushki7	0:60d829a0353a	822	__I uint32_t RESERVED3[56];
tushki7	0:60d829a0353a	823	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	824	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	825	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	826	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	827	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	828	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	829	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	830	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	831	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	832	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	833	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	834	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	835	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	836	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	837	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	838	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	839	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	840	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	841	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
tushki7	0:60d829a0353a	842	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
tushki7	0:60d829a0353a	843	__I uint32_t RESERVED4[108];
tushki7	0:60d829a0353a	844	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	845	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	846	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	847	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	848	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	849	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	850	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	851	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	852	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	853	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	854	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
tushki7	0:60d829a0353a	855	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
tushki7	0:60d829a0353a	856	} LPC_SCT2_Type;
tushki7	0:60d829a0353a	857
tushki7	0:60d829a0353a	858
tushki7	0:60d829a0353a	859	/* ================================================================================ */
tushki7	0:60d829a0353a	860	/* ================ ADC0 ================ */
tushki7	0:60d829a0353a	861	/* ================================================================================ */
tushki7	0:60d829a0353a	862
tushki7	0:60d829a0353a	863
tushki7	0:60d829a0353a	864	/**
tushki7	0:60d829a0353a	865	* @brief 12-bit ADC controller ADC0/1 (ADC0)
tushki7	0:60d829a0353a	866	*/
tushki7	0:60d829a0353a	867
tushki7	0:60d829a0353a	868	typedef struct { /!< ADC0 Structure /
tushki7	0:60d829a0353a	869	__IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
tushki7	0:60d829a0353a	870	bits for each sequence and the A/D power-down bit. */
tushki7	0:60d829a0353a	871	__IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
tushki7	0:60d829a0353a	872	internal source for various channels */
tushki7	0:60d829a0353a	873	__IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
tushki7	0:60d829a0353a	874	and channel selection for conversion sequence-A. Also specifies
tushki7	0:60d829a0353a	875	interrupt mode for sequence-A. */
tushki7	0:60d829a0353a	876	__IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
tushki7	0:60d829a0353a	877	and channel selection for conversion sequence-B. Also specifies
tushki7	0:60d829a0353a	878	interrupt mode for sequence-B. */
tushki7	0:60d829a0353a	879	__IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
tushki7	0:60d829a0353a	880	the result of the most recent A/D conversion performed under
tushki7	0:60d829a0353a	881	sequence-A */
tushki7	0:60d829a0353a	882	__IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
tushki7	0:60d829a0353a	883	the result of the most recent A/D conversion performed under
tushki7	0:60d829a0353a	884	sequence-B */
tushki7	0:60d829a0353a	885	__I uint32_t RESERVED0[2];
tushki7	0:60d829a0353a	886	__I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
tushki7	0:60d829a0353a	887	of the most recent conversion completed on channel 0. */
tushki7	0:60d829a0353a	888	__IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
tushki7	0:60d829a0353a	889	level for automatic threshold comparison for any channels linked
tushki7	0:60d829a0353a	890	to threshold pair 0. */
tushki7	0:60d829a0353a	891	__IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
tushki7	0:60d829a0353a	892	level for automatic threshold comparison for any channels linked
tushki7	0:60d829a0353a	893	to threshold pair 1. */
tushki7	0:60d829a0353a	894	__IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
tushki7	0:60d829a0353a	895	level for automatic threshold comparison for any channels linked
tushki7	0:60d829a0353a	896	to threshold pair 0. */
tushki7	0:60d829a0353a	897	__IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
tushki7	0:60d829a0353a	898	level for automatic threshold comparison for any channels linked
tushki7	0:60d829a0353a	899	to threshold pair 1. */
tushki7	0:60d829a0353a	900	__I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
tushki7	0:60d829a0353a	901	threshold compare registers are to be used for each channel */
tushki7	0:60d829a0353a	902	__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
tushki7	0:60d829a0353a	903	bits that enable the sequence-A, sequence-B, threshold compare
tushki7	0:60d829a0353a	904	and data overrun interrupts to be generated. */
tushki7	0:60d829a0353a	905	__I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
tushki7	0:60d829a0353a	906	and the individual component overrun and threshold-compare flags.
tushki7	0:60d829a0353a	907	(The overrun bits replicate information stored in the result
tushki7	0:60d829a0353a	908	registers). */
tushki7	0:60d829a0353a	909	__IO uint32_t TRM; /!< ADC trim register. /
tushki7	0:60d829a0353a	910	} LPC_ADC0_Type;
tushki7	0:60d829a0353a	911
tushki7	0:60d829a0353a	912
tushki7	0:60d829a0353a	913	/* ================================================================================ */
tushki7	0:60d829a0353a	914	/* ================ DAC ================ */
tushki7	0:60d829a0353a	915	/* ================================================================================ */
tushki7	0:60d829a0353a	916
tushki7	0:60d829a0353a	917
tushki7	0:60d829a0353a	918	/**
tushki7	0:60d829a0353a	919	* @brief 12-bit DAC Modification (DAC)
tushki7	0:60d829a0353a	920	*/
tushki7	0:60d829a0353a	921
tushki7	0:60d829a0353a	922	typedef struct { /!< DAC Structure /
tushki7	0:60d829a0353a	923	__IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
tushki7	0:60d829a0353a	924	value to be converted to analog. */
tushki7	0:60d829a0353a	925	__IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
tushki7	0:60d829a0353a	926	DAC operation and the interrupt/dma request flag. */
tushki7	0:60d829a0353a	927	__IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
tushki7	0:60d829a0353a	928	value for the internal DAC DMA/Interrupt timer. */
tushki7	0:60d829a0353a	929	} LPC_DAC_Type;
tushki7	0:60d829a0353a	930
tushki7	0:60d829a0353a	931
tushki7	0:60d829a0353a	932	/* ================================================================================ */
tushki7	0:60d829a0353a	933	/* ================ ACMP ================ */
tushki7	0:60d829a0353a	934	/* ================================================================================ */
tushki7	0:60d829a0353a	935
tushki7	0:60d829a0353a	936
tushki7	0:60d829a0353a	937	/**
tushki7	0:60d829a0353a	938	* @brief Analog comparators ACMP0/1/2/3 (ACMP)
tushki7	0:60d829a0353a	939	*/
tushki7	0:60d829a0353a	940
tushki7	0:60d829a0353a	941	typedef struct { /!< ACMP Structure /
tushki7	0:60d829a0353a	942	__IO uint32_t CTRL; /!< Comparator block control register /
tushki7	0:60d829a0353a	943	__IO uint32_t CMP0; /!< Comparator 0 source control /
tushki7	0:60d829a0353a	944	__IO uint32_t CMPFILTR0; /!< Comparator 0 pin filter set-up /
tushki7	0:60d829a0353a	945	__IO uint32_t CMP1; /!< Comparator 1 source control /
tushki7	0:60d829a0353a	946	__IO uint32_t CMPFILTR1; /!< Comparator 0 pin filter set-up /
tushki7	0:60d829a0353a	947	__IO uint32_t CMP2; /!< Comparator 2 source control /
tushki7	0:60d829a0353a	948	__IO uint32_t CMPFILTR2; /!< Comparator 0 pin filter set-up /
tushki7	0:60d829a0353a	949	__IO uint32_t CMP3; /!< Comparator 3 source control /
tushki7	0:60d829a0353a	950	__IO uint32_t CMPFILTR3; /!< Comparator 0 pin filter set-up /
tushki7	0:60d829a0353a	951	} LPC_ACMP_Type;
tushki7	0:60d829a0353a	952
tushki7	0:60d829a0353a	953
tushki7	0:60d829a0353a	954	/* ================================================================================ */
tushki7	0:60d829a0353a	955	/* ================ INMUX ================ */
tushki7	0:60d829a0353a	956	/* ================================================================================ */
tushki7	0:60d829a0353a	957
tushki7	0:60d829a0353a	958
tushki7	0:60d829a0353a	959	/**
tushki7	0:60d829a0353a	960	* @brief Input multiplexing (INMUX) (INMUX)
tushki7	0:60d829a0353a	961	*/
tushki7	0:60d829a0353a	962
tushki7	0:60d829a0353a	963	typedef struct { /!< INMUX Structure /
tushki7	0:60d829a0353a	964	__IO uint32_t SCT0_INMUX[7]; /!< Pinmux register for SCT0 input 0 /
tushki7	0:60d829a0353a	965	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	966	__IO uint32_t SCT1_INMUX[7]; /!< Pinmux register for SCT1 input 0 /
tushki7	0:60d829a0353a	967	__I uint32_t RESERVED1;
tushki7	0:60d829a0353a	968	__IO uint32_t SCT2_INMUX[3]; /!< Pinmux register for SCT2 input 0 /
tushki7	0:60d829a0353a	969	__I uint32_t RESERVED2[5];
tushki7	0:60d829a0353a	970	__IO uint32_t SCT3_INMUX[3]; /!< Pinmux register for SCT3 input 0 /
tushki7	0:60d829a0353a	971	__I uint32_t RESERVED3[21];
tushki7	0:60d829a0353a	972	__IO uint32_t PINTSEL[8]; /!< Pin interrupt select register 0 /
tushki7	0:60d829a0353a	973	__IO uint32_t DMA_ITRIG_INMUX[18]; /!< Trigger input for DMA channel 0 select register. /
tushki7	0:60d829a0353a	974	__I uint32_t RESERVED4[14];
tushki7	0:60d829a0353a	975	__IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
tushki7	0:60d829a0353a	976	clock */
tushki7	0:60d829a0353a	977	__IO uint32_t FREQMEAS_TARGET; /!< Clock selection for frequency measurement function target clock /
tushki7	0:60d829a0353a	978	} LPC_INMUX_Type;
tushki7	0:60d829a0353a	979
tushki7	0:60d829a0353a	980
tushki7	0:60d829a0353a	981	/* ================================================================================ */
tushki7	0:60d829a0353a	982	/* ================ RTC ================ */
tushki7	0:60d829a0353a	983	/* ================================================================================ */
tushki7	0:60d829a0353a	984
tushki7	0:60d829a0353a	985
tushki7	0:60d829a0353a	986	/**
tushki7	0:60d829a0353a	987	* @brief Real-Time Clock (RTC) (RTC)
tushki7	0:60d829a0353a	988	*/
tushki7	0:60d829a0353a	989
tushki7	0:60d829a0353a	990	typedef struct { /!< RTC Structure /
tushki7	0:60d829a0353a	991	__IO uint32_t CTRL; /!< RTC control register /
tushki7	0:60d829a0353a	992	__IO uint32_t MATCH; /!< RTC match register /
tushki7	0:60d829a0353a	993	__IO uint32_t COUNT; /!< RTC counter register /
tushki7	0:60d829a0353a	994	__IO uint32_t WAKE; /!< RTC high-resolution/wake-up timer control register /
tushki7	0:60d829a0353a	995	} LPC_RTC_Type;
tushki7	0:60d829a0353a	996
tushki7	0:60d829a0353a	997
tushki7	0:60d829a0353a	998	/* ================================================================================ */
tushki7	0:60d829a0353a	999	/* ================ WWDT ================ */
tushki7	0:60d829a0353a	1000	/* ================================================================================ */
tushki7	0:60d829a0353a	1001
tushki7	0:60d829a0353a	1002
tushki7	0:60d829a0353a	1003	/**
tushki7	0:60d829a0353a	1004	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
tushki7	0:60d829a0353a	1005	*/
tushki7	0:60d829a0353a	1006
tushki7	0:60d829a0353a	1007	typedef struct { /!< WWDT Structure /
tushki7	0:60d829a0353a	1008	__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
tushki7	0:60d829a0353a	1009	and status of the Watchdog Timer. */
tushki7	0:60d829a0353a	1010	__IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
tushki7	0:60d829a0353a	1011	the time-out value. */
tushki7	0:60d829a0353a	1012	__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
tushki7	0:60d829a0353a	1013	to this register reloads the Watchdog timer with the value contained
tushki7	0:60d829a0353a	1014	in WDTC. */
tushki7	0:60d829a0353a	1015	__I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
tushki7	0:60d829a0353a	1016	the current value of the Watchdog timer. */
tushki7	0:60d829a0353a	1017	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	1018	__IO uint32_t WARNINT; /!< Watchdog Warning Interrupt compare value. /
tushki7	0:60d829a0353a	1019	__IO uint32_t WINDOW; /!< Watchdog Window compare value. /
tushki7	0:60d829a0353a	1020	} LPC_WWDT_Type;
tushki7	0:60d829a0353a	1021
tushki7	0:60d829a0353a	1022
tushki7	0:60d829a0353a	1023	/* ================================================================================ */
tushki7	0:60d829a0353a	1024	/* ================ SWM ================ */
tushki7	0:60d829a0353a	1025	/* ================================================================================ */
tushki7	0:60d829a0353a	1026
tushki7	0:60d829a0353a	1027
tushki7	0:60d829a0353a	1028	/**
tushki7	0:60d829a0353a	1029	* @brief Switch Matrix (SWM) (SWM)
tushki7	0:60d829a0353a	1030	*/
tushki7	0:60d829a0353a	1031
tushki7	0:60d829a0353a	1032	typedef struct { /!< SWM Structure /
tushki7	0:60d829a0353a	1033	union {
tushki7	0:60d829a0353a	1034	__IO uint32_t PINASSIGN[16];
tushki7	0:60d829a0353a	1035	struct {
tushki7	0:60d829a0353a	1036	__IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
tushki7	0:60d829a0353a	1037	U0_RTS, U0_CTS. */
tushki7	0:60d829a0353a	1038	__IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
tushki7	0:60d829a0353a	1039	U1_RXD, U1_RTS. */
tushki7	0:60d829a0353a	1040	__IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
tushki7	0:60d829a0353a	1041	U2_TXD, U2_RXD. */
tushki7	0:60d829a0353a	1042	__IO uint32_t PINASSIGN3; /!< Pin assign register 3. Assign movable function . /
tushki7	0:60d829a0353a	1043	__IO uint32_t PINASSIGN4; /!< Pin assign register 4. Assign movable functions /
tushki7	0:60d829a0353a	1044	__IO uint32_t PINASSIGN5; /!< Pin assign register 5. Assign movable functions /
tushki7	0:60d829a0353a	1045	__IO uint32_t PINASSIGN6; /!< Pin assign register 6. Assign movable functions /
tushki7	0:60d829a0353a	1046	__IO uint32_t PINASSIGN7; /!< Pin assign register 7. Assign movable functions /
tushki7	0:60d829a0353a	1047	__IO uint32_t PINASSIGN8; /!< Pin assign register 8. Assign movable functions /
tushki7	0:60d829a0353a	1048	__IO uint32_t PINASSIGN9; /!< Pin assign register 9. Assign movable functions /
tushki7	0:60d829a0353a	1049	__IO uint32_t PINASSIGN10; /!< Pin assign register 10. Assign movable functions /
tushki7	0:60d829a0353a	1050	__IO uint32_t PINASSIGN11; /!< Pin assign register 11. Assign movable functions /
tushki7	0:60d829a0353a	1051	__IO uint32_t PINASSIGN12; /!< Pin assign register 12. Assign movable functions /
tushki7	0:60d829a0353a	1052	__IO uint32_t PINASSIGN13; /!< Pin assign register 13. Assign movable functions /
tushki7	0:60d829a0353a	1053	__IO uint32_t PINASSIGN14; /!< Pin assign register 14. Assign movable functions /
tushki7	0:60d829a0353a	1054	__IO uint32_t PINASSIGN15; /!< Pin assign register 15. Assign movable functions /
tushki7	0:60d829a0353a	1055	};
tushki7	0:60d829a0353a	1056	};
tushki7	0:60d829a0353a	1057	__I uint32_t RESERVED0[96];
tushki7	0:60d829a0353a	1058	__IO uint32_t PINENABLE0; /!< Pin enable register 0. Enables fixed-pin functions /
tushki7	0:60d829a0353a	1059	__IO uint32_t PINENABLE1; /!< Pin enable register 0. Enables fixed-pin functions /
tushki7	0:60d829a0353a	1060	} LPC_SWM_Type;
tushki7	0:60d829a0353a	1061
tushki7	0:60d829a0353a	1062
tushki7	0:60d829a0353a	1063	/* ================================================================================ */
tushki7	0:60d829a0353a	1064	/* ================ PMU ================ */
tushki7	0:60d829a0353a	1065	/* ================================================================================ */
tushki7	0:60d829a0353a	1066
tushki7	0:60d829a0353a	1067
tushki7	0:60d829a0353a	1068	/**
tushki7	0:60d829a0353a	1069	* @brief Power Management Unit (PMU) (PMU)
tushki7	0:60d829a0353a	1070	*/
tushki7	0:60d829a0353a	1071
tushki7	0:60d829a0353a	1072	typedef struct { /!< PMU Structure /
tushki7	0:60d829a0353a	1073	__IO uint32_t PCON; /!< Power control register /
tushki7	0:60d829a0353a	1074	__IO uint32_t GPREG0; /!< General purpose register 0 /
tushki7	0:60d829a0353a	1075	__IO uint32_t GPREG1; /!< General purpose register 0 /
tushki7	0:60d829a0353a	1076	__IO uint32_t GPREG2; /!< General purpose register 0 /
tushki7	0:60d829a0353a	1077	__IO uint32_t GPREG3; /!< General purpose register 0 /
tushki7	0:60d829a0353a	1078	__IO uint32_t DPDCTRL; /!< Deep power-down control register /
tushki7	0:60d829a0353a	1079	} LPC_PMU_Type;
tushki7	0:60d829a0353a	1080
tushki7	0:60d829a0353a	1081
tushki7	0:60d829a0353a	1082	/* ================================================================================ */
tushki7	0:60d829a0353a	1083	/* ================ USART0 ================ */
tushki7	0:60d829a0353a	1084	/* ================================================================================ */
tushki7	0:60d829a0353a	1085
tushki7	0:60d829a0353a	1086
tushki7	0:60d829a0353a	1087	/**
tushki7	0:60d829a0353a	1088	* @brief USART0 (USART0)
tushki7	0:60d829a0353a	1089	*/
tushki7	0:60d829a0353a	1090
tushki7	0:60d829a0353a	1091	typedef struct { /!< USART0 Structure /
tushki7	0:60d829a0353a	1092	__IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
tushki7	0:60d829a0353a	1093	that typically are not changed during operation. */
tushki7	0:60d829a0353a	1094	__IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
tushki7	0:60d829a0353a	1095	likely to change during operation. */
tushki7	0:60d829a0353a	1096	__IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
tushki7	0:60d829a0353a	1097	here. Writing ones clears some bits in the register. Some bits
tushki7	0:60d829a0353a	1098	can be cleared by writing a 1 to them. */
tushki7	0:60d829a0353a	1099	__IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
tushki7	0:60d829a0353a	1100	interrupt enable bit for each potential USART interrupt. A complete
tushki7	0:60d829a0353a	1101	value may be read from this register. Writing a 1 to any implemented
tushki7	0:60d829a0353a	1102	bit position causes that bit to be set. */
tushki7	0:60d829a0353a	1103	__O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
tushki7	0:60d829a0353a	1104	of bits in the INTENSET register. Writing a 1 to any implemented
tushki7	0:60d829a0353a	1105	bit position causes the corresponding bit to be cleared. */
tushki7	0:60d829a0353a	1106	__I uint32_t RXDATA; /!< Receiver Data register. Contains the last character received. /
tushki7	0:60d829a0353a	1107	__I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
tushki7	0:60d829a0353a	1108	received with the current USART receive status. Allows DMA or
tushki7	0:60d829a0353a	1109	software to recover incoming data and status together. */
tushki7	0:60d829a0353a	1110	__IO uint32_t TXDATA; /!< Transmit Data register. Data to be transmitted is written here. /
tushki7	0:60d829a0353a	1111	__IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
tushki7	0:60d829a0353a	1112	value. */
tushki7	0:60d829a0353a	1113	__I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
tushki7	0:60d829a0353a	1114	enabled. */
tushki7	0:60d829a0353a	1115	} LPC_USART0_Type;
tushki7	0:60d829a0353a	1116
tushki7	0:60d829a0353a	1117
tushki7	0:60d829a0353a	1118	/* ================================================================================ */
tushki7	0:60d829a0353a	1119	/* ================ SPI0 ================ */
tushki7	0:60d829a0353a	1120	/* ================================================================================ */
tushki7	0:60d829a0353a	1121
tushki7	0:60d829a0353a	1122
tushki7	0:60d829a0353a	1123	/**
tushki7	0:60d829a0353a	1124	* @brief SPI0 (SPI0)
tushki7	0:60d829a0353a	1125	*/
tushki7	0:60d829a0353a	1126
tushki7	0:60d829a0353a	1127	typedef struct { /!< SPI0 Structure /
tushki7	0:60d829a0353a	1128	__IO uint32_t CFG; /!< SPI Configuration register /
tushki7	0:60d829a0353a	1129	__IO uint32_t DLY; /!< SPI Delay register /
tushki7	0:60d829a0353a	1130	__IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
tushki7	0:60d829a0353a	1131	to that bit position */
tushki7	0:60d829a0353a	1132	__IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
tushki7	0:60d829a0353a	1133	from this register. Writing a 1 to any implemented bit position
tushki7	0:60d829a0353a	1134	causes that bit to be set. */
tushki7	0:60d829a0353a	1135	__O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
tushki7	0:60d829a0353a	1136	position causes the corresponding bit in INTENSET to be cleared. */
tushki7	0:60d829a0353a	1137	__I uint32_t RXDAT; /!< SPI Receive Data /
tushki7	0:60d829a0353a	1138	__IO uint32_t TXDATCTL; /!< SPI Transmit Data with Control /
tushki7	0:60d829a0353a	1139	__IO uint32_t TXDAT; /!< SPI Transmit Data with Control /
tushki7	0:60d829a0353a	1140	__IO uint32_t TXCTL; /!< SPI Transmit Control /
tushki7	0:60d829a0353a	1141	__IO uint32_t DIV; /!< SPI clock Divider /
tushki7	0:60d829a0353a	1142	__I uint32_t INTSTAT; /!< SPI Interrupt Status /
tushki7	0:60d829a0353a	1143	} LPC_SPI0_Type;
tushki7	0:60d829a0353a	1144
tushki7	0:60d829a0353a	1145
tushki7	0:60d829a0353a	1146	/* ================================================================================ */
tushki7	0:60d829a0353a	1147	/* ================ I2C0 ================ */
tushki7	0:60d829a0353a	1148	/* ================================================================================ */
tushki7	0:60d829a0353a	1149
tushki7	0:60d829a0353a	1150
tushki7	0:60d829a0353a	1151	/**
tushki7	0:60d829a0353a	1152	* @brief I2C-bus interface (I2C0)
tushki7	0:60d829a0353a	1153	*/
tushki7	0:60d829a0353a	1154
tushki7	0:60d829a0353a	1155	typedef struct { /!< I2C0 Structure /
tushki7	0:60d829a0353a	1156	__IO uint32_t CFG; /!< Configuration for shared functions. /
tushki7	0:60d829a0353a	1157	__IO uint32_t STAT; /!< Status register for Master, Slave, and Monitor functions. /
tushki7	0:60d829a0353a	1158	__IO uint32_t INTENSET; /!< Interrupt Enable Set and read register. /
tushki7	0:60d829a0353a	1159	__O uint32_t INTENCLR; /!< Interrupt Enable Clear register. /
tushki7	0:60d829a0353a	1160	__IO uint32_t TIMEOUT; /!< Time-out value register. /
tushki7	0:60d829a0353a	1161	__IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
tushki7	0:60d829a0353a	1162	what time increments are used for the MSTTIME and SLVTIME registers. */
tushki7	0:60d829a0353a	1163	__I uint32_t INTSTAT; /!< Interrupt Status register for Master, Slave, and Monitor functions. /
tushki7	0:60d829a0353a	1164	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	1165	__IO uint32_t MSTCTL; /!< Master control register. /
tushki7	0:60d829a0353a	1166	__IO uint32_t MSTTIME; /!< Master timing configuration. /
tushki7	0:60d829a0353a	1167	__IO uint32_t MSTDAT; /!< Combined Master receiver and transmitter data register. /
tushki7	0:60d829a0353a	1168	__I uint32_t RESERVED1[5];
tushki7	0:60d829a0353a	1169	__IO uint32_t SLVCTL; /!< Slave control register. /
tushki7	0:60d829a0353a	1170	__IO uint32_t SLVDAT; /!< Combined Slave receiver and transmitter data register. /
tushki7	0:60d829a0353a	1171	__IO uint32_t SLVADR0; /!< Slave address 0. /
tushki7	0:60d829a0353a	1172	__IO uint32_t SLVADR1; /!< Slave address 0. /
tushki7	0:60d829a0353a	1173	__IO uint32_t SLVADR2; /!< Slave address 0. /
tushki7	0:60d829a0353a	1174	__IO uint32_t SLVADR3; /!< Slave address 0. /
tushki7	0:60d829a0353a	1175	__IO uint32_t SLVQUAL0; /!< Slave Qualification for address 0. /
tushki7	0:60d829a0353a	1176	__I uint32_t RESERVED2[9];
tushki7	0:60d829a0353a	1177	__I uint32_t MONRXDAT; /!< Monitor receiver data register. /
tushki7	0:60d829a0353a	1178	} LPC_I2C0_Type;
tushki7	0:60d829a0353a	1179
tushki7	0:60d829a0353a	1180
tushki7	0:60d829a0353a	1181	/* ================================================================================ */
tushki7	0:60d829a0353a	1182	/* ================ QEI ================ */
tushki7	0:60d829a0353a	1183	/* ================================================================================ */
tushki7	0:60d829a0353a	1184
tushki7	0:60d829a0353a	1185
tushki7	0:60d829a0353a	1186	/**
tushki7	0:60d829a0353a	1187	* @brief Quadrature Encoder Interface (QEI) (QEI)
tushki7	0:60d829a0353a	1188	*/
tushki7	0:60d829a0353a	1189
tushki7	0:60d829a0353a	1190	typedef struct { /!< QEI Structure /
tushki7	0:60d829a0353a	1191	__O uint32_t CON; /!< Control register /
tushki7	0:60d829a0353a	1192	__I uint32_t STAT; /!< Encoder status register /
tushki7	0:60d829a0353a	1193	__IO uint32_t CONF; /!< Configuration register /
tushki7	0:60d829a0353a	1194	__I uint32_t POS; /!< Position register /
tushki7	0:60d829a0353a	1195	__IO uint32_t MAXPOS; /!< Maximum position register /
tushki7	0:60d829a0353a	1196	__IO uint32_t CMPOS0; /!< position compare register 0 /
tushki7	0:60d829a0353a	1197	__IO uint32_t CMPOS1; /!< position compare register 1 /
tushki7	0:60d829a0353a	1198	__IO uint32_t CMPOS2; /!< position compare register 2 /
tushki7	0:60d829a0353a	1199	__I uint32_t INXCNT; /!< Index count register /
tushki7	0:60d829a0353a	1200	__IO uint32_t INXCMP0; /!< Index compare register 0 /
tushki7	0:60d829a0353a	1201	__IO uint32_t LOAD; /!< Velocity timer reload register /
tushki7	0:60d829a0353a	1202	__I uint32_t TIME; /!< Velocity timer register /
tushki7	0:60d829a0353a	1203	__I uint32_t VEL; /!< Velocity counter register /
tushki7	0:60d829a0353a	1204	__I uint32_t CAP; /!< Velocity capture register /
tushki7	0:60d829a0353a	1205	__IO uint32_t VELCOMP; /!< Velocity compare register /
tushki7	0:60d829a0353a	1206	__IO uint32_t FILTERPHA; /!< Digital filter register on input phase A (QEI_A) /
tushki7	0:60d829a0353a	1207	__IO uint32_t FILTERPHB; /!< Digital filter register on input phase B (QEI_B) /
tushki7	0:60d829a0353a	1208	__IO uint32_t FILTERINX; /!< Digital filter register on input index (QEI_IDX) /
tushki7	0:60d829a0353a	1209	__IO uint32_t WINDOW; /!< Index acceptance window register /
tushki7	0:60d829a0353a	1210	__IO uint32_t INXCMP1; /!< Index compare register 1 /
tushki7	0:60d829a0353a	1211	__IO uint32_t INXCMP2; /!< Index compare register 2 /
tushki7	0:60d829a0353a	1212	__I uint32_t RESERVED0[993];
tushki7	0:60d829a0353a	1213	__O uint32_t IEC; /!< Interrupt enable clear register /
tushki7	0:60d829a0353a	1214	__O uint32_t IES; /!< Interrupt enable set register /
tushki7	0:60d829a0353a	1215	__I uint32_t INTSTAT; /!< Interrupt status register /
tushki7	0:60d829a0353a	1216	__O uint32_t IE; /!< Interrupt enable clear register /
tushki7	0:60d829a0353a	1217	__O uint32_t CLR; /!< Interrupt status clear register /
tushki7	0:60d829a0353a	1218	__O uint32_t SET; /!< Interrupt status set register /
tushki7	0:60d829a0353a	1219	} LPC_QEI_Type;
tushki7	0:60d829a0353a	1220
tushki7	0:60d829a0353a	1221
tushki7	0:60d829a0353a	1222	/* ================================================================================ */
tushki7	0:60d829a0353a	1223	/* ================ SYSCON ================ */
tushki7	0:60d829a0353a	1224	/* ================================================================================ */
tushki7	0:60d829a0353a	1225
tushki7	0:60d829a0353a	1226
tushki7	0:60d829a0353a	1227	/**
tushki7	0:60d829a0353a	1228	* @brief System configuration (SYSCON) (SYSCON)
tushki7	0:60d829a0353a	1229	*/
tushki7	0:60d829a0353a	1230
tushki7	0:60d829a0353a	1231	typedef struct { /!< SYSCON Structure /
tushki7	0:60d829a0353a	1232	__IO uint32_t SYSMEMREMAP; /!< System memory remap /
tushki7	0:60d829a0353a	1233	__I uint32_t RESERVED0[4];
tushki7	0:60d829a0353a	1234	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration /
tushki7	0:60d829a0353a	1235	__I uint32_t RESERVED1;
tushki7	0:60d829a0353a	1236	__IO uint32_t NMISRC; /!< NMI Source Control /
tushki7	0:60d829a0353a	1237	__I uint32_t RESERVED2[8];
tushki7	0:60d829a0353a	1238	__IO uint32_t SYSRSTSTAT; /!< System reset status register /
tushki7	0:60d829a0353a	1239	__IO uint32_t PRESETCTRL0; /!< Peripheral reset control 0 /
tushki7	0:60d829a0353a	1240	__IO uint32_t PRESETCTRL1; /!< Peripheral reset control 1 /
tushki7	0:60d829a0353a	1241	__I uint32_t PIOPORCAP0; /!< POR captured PIO status 0 /
tushki7	0:60d829a0353a	1242	__I uint32_t PIOPORCAP1; /!< POR captured PIO status 1 /
tushki7	0:60d829a0353a	1243	__I uint32_t PIOPORCAP2; /!< POR captured PIO status 2 /
tushki7	0:60d829a0353a	1244	__I uint32_t RESERVED3[10];
tushki7	0:60d829a0353a	1245	__IO uint32_t MAINCLKSELA; /!< Main clock source select A /
tushki7	0:60d829a0353a	1246	__IO uint32_t MAINCLKSELB; /!< Main clock source select B /
tushki7	0:60d829a0353a	1247	__IO uint32_t USBCLKSEL; /!< USB clock source select /
tushki7	0:60d829a0353a	1248	__IO uint32_t ADCASYNCCLKSEL; /!< ADC asynchronous clock source select /
tushki7	0:60d829a0353a	1249	__I uint32_t RESERVED4;
tushki7	0:60d829a0353a	1250	__IO uint32_t CLKOUTSELA; /!< CLKOUT clock source select A /
tushki7	0:60d829a0353a	1251	__IO uint32_t CLKOUTSELB; /!< CLKOUT clock source select B /
tushki7	0:60d829a0353a	1252	__I uint32_t RESERVED5;
tushki7	0:60d829a0353a	1253	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select /
tushki7	0:60d829a0353a	1254	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select /
tushki7	0:60d829a0353a	1255	__IO uint32_t SCTPLLCLKSEL; /!< SCT PLL clock source select /
tushki7	0:60d829a0353a	1256	__I uint32_t RESERVED6[5];
tushki7	0:60d829a0353a	1257	__IO uint32_t SYSAHBCLKDIV; /!< System clock divider /
tushki7	0:60d829a0353a	1258	__IO uint32_t SYSAHBCLKCTRL0; /!< System clock control 0 /
tushki7	0:60d829a0353a	1259	__IO uint32_t SYSAHBCLKCTRL1; /!< System clock control 1 /
tushki7	0:60d829a0353a	1260	__IO uint32_t SYSTICKCLKDIV; /!< SYSTICK clock divider /
tushki7	0:60d829a0353a	1261	__IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
tushki7	0:60d829a0353a	1262	baud rate generator. */
tushki7	0:60d829a0353a	1263	__IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
tushki7	0:60d829a0353a	1264	filter */
tushki7	0:60d829a0353a	1265	__IO uint32_t TRACECLKDIV; /!< ARM trace clock divider /
tushki7	0:60d829a0353a	1266	__I uint32_t RESERVED7[4];
tushki7	0:60d829a0353a	1267	__IO uint32_t USBCLKDIV; /!< USB clock divider /
tushki7	0:60d829a0353a	1268	__IO uint32_t ADCASYNCCLKDIV; /!< Asynchronous ADC clock divider /
tushki7	0:60d829a0353a	1269	__I uint32_t RESERVED8;
tushki7	0:60d829a0353a	1270	__IO uint32_t CLKOUTDIV; /!< CLKOUT clock divider /
tushki7	0:60d829a0353a	1271	__I uint32_t RESERVED9[11];
tushki7	0:60d829a0353a	1272	__IO uint32_t FRGCTRL; /!< USART fractional baud rate generator control /
tushki7	0:60d829a0353a	1273	__IO uint32_t USBCLKCTRL; /!< USB clock control /
tushki7	0:60d829a0353a	1274	__IO uint32_t USBCLKST; /!< USB clock status /
tushki7	0:60d829a0353a	1275	__I uint32_t RESERVED10[19];
tushki7	0:60d829a0353a	1276	__IO uint32_t BODCTRL; /!< Brown-Out Detect /
tushki7	0:60d829a0353a	1277	__I uint32_t RESERVED11;
tushki7	0:60d829a0353a	1278	__IO uint32_t SYSOSCCTRL; /!< System oscillator control /
tushki7	0:60d829a0353a	1279	__I uint32_t RESERVED12;
tushki7	0:60d829a0353a	1280	__IO uint32_t RTCOSCCTRL; /!< RTC oscillator control /
tushki7	0:60d829a0353a	1281	__I uint32_t RESERVED13;
tushki7	0:60d829a0353a	1282	__IO uint32_t SYSPLLCTRL; /!< System PLL control /
tushki7	0:60d829a0353a	1283	__I uint32_t SYSPLLSTAT; /!< System PLL status /
tushki7	0:60d829a0353a	1284	__IO uint32_t USBPLLCTRL; /!< USB PLL control /
tushki7	0:60d829a0353a	1285	__I uint32_t USBPLLSTAT; /!< USB PLL status /
tushki7	0:60d829a0353a	1286	__IO uint32_t SCTPLLCTRL; /!< SCT PLL control /
tushki7	0:60d829a0353a	1287	__I uint32_t SCTPLLSTAT; /!< SCT PLL status /
tushki7	0:60d829a0353a	1288	__I uint32_t RESERVED14[21];
tushki7	0:60d829a0353a	1289	__IO uint32_t PDAWAKECFG; /!< Power-down states for wake-up from deep-sleep /
tushki7	0:60d829a0353a	1290	__IO uint32_t PDRUNCFG; /!< Power configuration register /
tushki7	0:60d829a0353a	1291	__I uint32_t RESERVED15[3];
tushki7	0:60d829a0353a	1292	__IO uint32_t STARTERP0; /!< Start logic 0 wake-up enable register /
tushki7	0:60d829a0353a	1293	__IO uint32_t STARTERP1; /!< Start logic 1 wake-up enable register /
tushki7	0:60d829a0353a	1294	} LPC_SYSCON_Type;
tushki7	0:60d829a0353a	1295
tushki7	0:60d829a0353a	1296
tushki7	0:60d829a0353a	1297	/* ================================================================================ */
tushki7	0:60d829a0353a	1298	/* ================ MRT ================ */
tushki7	0:60d829a0353a	1299	/* ================================================================================ */
tushki7	0:60d829a0353a	1300
tushki7	0:60d829a0353a	1301
tushki7	0:60d829a0353a	1302	/**
tushki7	0:60d829a0353a	1303	* @brief Multi-Rate Timer (MRT) (MRT)
tushki7	0:60d829a0353a	1304	*/
tushki7	0:60d829a0353a	1305
tushki7	0:60d829a0353a	1306	typedef struct { /!< MRT Structure /
tushki7	0:60d829a0353a	1307	__IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
tushki7	0:60d829a0353a	1308	the TIMER0 register. */
tushki7	0:60d829a0353a	1309	__I uint32_t TIMER0; /!< MRT0 Timer register. This register reads the value of the down-counter. /
tushki7	0:60d829a0353a	1310	__IO uint32_t CTRL0; /!< MRT0 Control register. This register controls the MRT0 modes. /
tushki7	0:60d829a0353a	1311	__IO uint32_t STAT0; /!< MRT0 Status register. /
tushki7	0:60d829a0353a	1312	__IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
tushki7	0:60d829a0353a	1313	the TIMER0 register. */
tushki7	0:60d829a0353a	1314	__I uint32_t TIMER1; /!< MRT0 Timer register. This register reads the value of the down-counter. /
tushki7	0:60d829a0353a	1315	__IO uint32_t CTRL1; /!< MRT0 Control register. This register controls the MRT0 modes. /
tushki7	0:60d829a0353a	1316	__IO uint32_t STAT1; /!< MRT0 Status register. /
tushki7	0:60d829a0353a	1317	__IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
tushki7	0:60d829a0353a	1318	the TIMER0 register. */
tushki7	0:60d829a0353a	1319	__I uint32_t TIMER2; /!< MRT0 Timer register. This register reads the value of the down-counter. /
tushki7	0:60d829a0353a	1320	__IO uint32_t CTRL2; /!< MRT0 Control register. This register controls the MRT0 modes. /
tushki7	0:60d829a0353a	1321	__IO uint32_t STAT2; /!< MRT0 Status register. /
tushki7	0:60d829a0353a	1322	__IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
tushki7	0:60d829a0353a	1323	the TIMER0 register. */
tushki7	0:60d829a0353a	1324	__I uint32_t TIMER3; /!< MRT0 Timer register. This register reads the value of the down-counter. /
tushki7	0:60d829a0353a	1325	__IO uint32_t CTRL3; /!< MRT0 Control register. This register controls the MRT0 modes. /
tushki7	0:60d829a0353a	1326	__IO uint32_t STAT3; /!< MRT0 Status register. /
tushki7	0:60d829a0353a	1327	__I uint32_t RESERVED0[45];
tushki7	0:60d829a0353a	1328	__I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
tushki7	0:60d829a0353a	1329	first idle channel. */
tushki7	0:60d829a0353a	1330	__IO uint32_t IRQ_FLAG; /!< Global interrupt flag register /
tushki7	0:60d829a0353a	1331	} LPC_MRT_Type;
tushki7	0:60d829a0353a	1332
tushki7	0:60d829a0353a	1333
tushki7	0:60d829a0353a	1334	/* ================================================================================ */
tushki7	0:60d829a0353a	1335	/* ================ PINT ================ */
tushki7	0:60d829a0353a	1336	/* ================================================================================ */
tushki7	0:60d829a0353a	1337
tushki7	0:60d829a0353a	1338
tushki7	0:60d829a0353a	1339	/**
tushki7	0:60d829a0353a	1340	* @brief Pin interruptand pattern match (PINT) (PINT)
tushki7	0:60d829a0353a	1341	*/
tushki7	0:60d829a0353a	1342
tushki7	0:60d829a0353a	1343	typedef struct { /!< PINT Structure /
tushki7	0:60d829a0353a	1344	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
tushki7	0:60d829a0353a	1345	__IO uint32_t IENR; /!< Pin interrupt level or rising edge interrupt enable register /
tushki7	0:60d829a0353a	1346	__O uint32_t SIENR; /!< Pin interrupt level or rising edge interrupt set register /
tushki7	0:60d829a0353a	1347	__O uint32_t CIENR; /!< Pin interrupt level (rising edge interrupt) clear register /
tushki7	0:60d829a0353a	1348	__IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
tushki7	0:60d829a0353a	1349	register */
tushki7	0:60d829a0353a	1350	__O uint32_t SIENF; /!< Pin interrupt active level or falling edge interrupt set register /
tushki7	0:60d829a0353a	1351	__O uint32_t CIENF; /!< Pin interrupt active level or falling edge interrupt clear register /
tushki7	0:60d829a0353a	1352	__IO uint32_t RISE; /!< Pin interrupt rising edge register /
tushki7	0:60d829a0353a	1353	__IO uint32_t FALL; /!< Pin interrupt falling edge register /
tushki7	0:60d829a0353a	1354	__IO uint32_t IST; /!< Pin interrupt status register /
tushki7	0:60d829a0353a	1355	__IO uint32_t PMCTRL; /!< Pattern match interrupt control register /
tushki7	0:60d829a0353a	1356	__IO uint32_t PMSRC; /!< Pattern match interrupt bit-slice source register /
tushki7	0:60d829a0353a	1357	__IO uint32_t PMCFG; /!< Pattern match interrupt bit slice configuration register /
tushki7	0:60d829a0353a	1358	} LPC_PINT_Type;
tushki7	0:60d829a0353a	1359
tushki7	0:60d829a0353a	1360
tushki7	0:60d829a0353a	1361	/* ================================================================================ */
tushki7	0:60d829a0353a	1362	/* ================ GINT0 ================ */
tushki7	0:60d829a0353a	1363	/* ================================================================================ */
tushki7	0:60d829a0353a	1364
tushki7	0:60d829a0353a	1365
tushki7	0:60d829a0353a	1366	/**
tushki7	0:60d829a0353a	1367	* @brief Group interrupt 0/1 (GINT0/1) (GINT0)
tushki7	0:60d829a0353a	1368	*/
tushki7	0:60d829a0353a	1369
tushki7	0:60d829a0353a	1370	typedef struct { /!< GINT0 Structure /
tushki7	0:60d829a0353a	1371	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
tushki7	0:60d829a0353a	1372	__I uint32_t RESERVED0[7];
tushki7	0:60d829a0353a	1373	__IO uint32_t PORT_POL[3]; /!< GPIO grouped interrupt port 0 polarity register /
tushki7	0:60d829a0353a	1374	__I uint32_t RESERVED1[5];
tushki7	0:60d829a0353a	1375	__IO uint32_t PORT_ENA[3]; /!< GPIO grouped interrupt port 0 enable register /
tushki7	0:60d829a0353a	1376	} LPC_GINT0_Type;
tushki7	0:60d829a0353a	1377
tushki7	0:60d829a0353a	1378
tushki7	0:60d829a0353a	1379	/* ================================================================================ */
tushki7	0:60d829a0353a	1380	/* ================ RIT ================ */
tushki7	0:60d829a0353a	1381	/* ================================================================================ */
tushki7	0:60d829a0353a	1382
tushki7	0:60d829a0353a	1383
tushki7	0:60d829a0353a	1384	/**
tushki7	0:60d829a0353a	1385	* @brief Repetitive Interrupt Timer (RIT) (RIT)
tushki7	0:60d829a0353a	1386	*/
tushki7	0:60d829a0353a	1387
tushki7	0:60d829a0353a	1388	typedef struct { /!< RIT Structure /
tushki7	0:60d829a0353a	1389	__IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
tushki7	0:60d829a0353a	1390	value. */
tushki7	0:60d829a0353a	1391	__IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
tushki7	0:60d829a0353a	1392	value. A 1 written to any bit will force a compare on the corresponding
tushki7	0:60d829a0353a	1393	bit of the counter and compare register. */
tushki7	0:60d829a0353a	1394	__IO uint32_t CTRL; /!< Control register. /
tushki7	0:60d829a0353a	1395	__IO uint32_t COUNTER; /!< Counter LSB register. 32 LSBs of the counter. /
tushki7	0:60d829a0353a	1396	__IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
tushki7	0:60d829a0353a	1397	value. */
tushki7	0:60d829a0353a	1398	__IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
tushki7	0:60d829a0353a	1399	value. A 1 written to any bit will force a compare on the corresponding
tushki7	0:60d829a0353a	1400	bit of the counter and compare register. */
tushki7	0:60d829a0353a	1401	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	1402	__IO uint32_t COUNTER_H; /!< Counter MSB register. 16 MSBs of the counter. /
tushki7	0:60d829a0353a	1403	} LPC_RIT_Type;
tushki7	0:60d829a0353a	1404
tushki7	0:60d829a0353a	1405
tushki7	0:60d829a0353a	1406	/* ================================================================================ */
tushki7	0:60d829a0353a	1407	/* ================ SCTIPU ================ */
tushki7	0:60d829a0353a	1408	/* ================================================================================ */
tushki7	0:60d829a0353a	1409
tushki7	0:60d829a0353a	1410
tushki7	0:60d829a0353a	1411	/**
tushki7	0:60d829a0353a	1412	* @brief SCT Input Processing Unit (IPU) (SCTIPU)
tushki7	0:60d829a0353a	1413	*/
tushki7	0:60d829a0353a	1414
tushki7	0:60d829a0353a	1415	typedef struct { /!< SCTIPU Structure /
tushki7	0:60d829a0353a	1416	__IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
tushki7	0:60d829a0353a	1417	latch/sample-enable mux selects, and sample overrride bits for
tushki7	0:60d829a0353a	1418	the SAMPLE module. */
tushki7	0:60d829a0353a	1419	__I uint32_t RESERVED0[7];
tushki7	0:60d829a0353a	1420	__IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
tushki7	0:60d829a0353a	1421	to ORed Abort Output 0. */
tushki7	0:60d829a0353a	1422	__IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
tushki7	0:60d829a0353a	1423	input source caused abort output 0. */
tushki7	0:60d829a0353a	1424	__I uint32_t RESERVED1[6];
tushki7	0:60d829a0353a	1425	__IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
tushki7	0:60d829a0353a	1426	to ORed Abort Output 0. */
tushki7	0:60d829a0353a	1427	__IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
tushki7	0:60d829a0353a	1428	input source caused abort output 0. */
tushki7	0:60d829a0353a	1429	__I uint32_t RESERVED2[6];
tushki7	0:60d829a0353a	1430	__IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
tushki7	0:60d829a0353a	1431	to ORed Abort Output 0. */
tushki7	0:60d829a0353a	1432	__IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
tushki7	0:60d829a0353a	1433	input source caused abort output 0. */
tushki7	0:60d829a0353a	1434	__I uint32_t RESERVED3[6];
tushki7	0:60d829a0353a	1435	__IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
tushki7	0:60d829a0353a	1436	to ORed Abort Output 0. */
tushki7	0:60d829a0353a	1437	__IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
tushki7	0:60d829a0353a	1438	input source caused abort output 0. */
tushki7	0:60d829a0353a	1439	} LPC_SCTIPU_Type;
tushki7	0:60d829a0353a	1440
tushki7	0:60d829a0353a	1441
tushki7	0:60d829a0353a	1442	/* ================================================================================ */
tushki7	0:60d829a0353a	1443	/* ================ FLASHCTRL ================ */
tushki7	0:60d829a0353a	1444	/* ================================================================================ */
tushki7	0:60d829a0353a	1445
tushki7	0:60d829a0353a	1446
tushki7	0:60d829a0353a	1447	/**
tushki7	0:60d829a0353a	1448	* @brief Flash controller (FLASHCTRL)
tushki7	0:60d829a0353a	1449	*/
tushki7	0:60d829a0353a	1450
tushki7	0:60d829a0353a	1451	typedef struct { /!< FLASHCTRL Structure /
tushki7	0:60d829a0353a	1452	__I uint32_t RESERVED0[8];
tushki7	0:60d829a0353a	1453	__IO uint32_t FMSSTART; /!< Signature start address register /
tushki7	0:60d829a0353a	1454	__IO uint32_t FMSSTOP; /!< Signature stop-address register /
tushki7	0:60d829a0353a	1455	__I uint32_t RESERVED1;
tushki7	0:60d829a0353a	1456	__I uint32_t FMSW0; /!< Signature word /
tushki7	0:60d829a0353a	1457	} LPC_FLASHCTRL_Type;
tushki7	0:60d829a0353a	1458
tushki7	0:60d829a0353a	1459
tushki7	0:60d829a0353a	1460	/* ================================================================================ */
tushki7	0:60d829a0353a	1461	/* ================ C_CAN0 ================ */
tushki7	0:60d829a0353a	1462	/* ================================================================================ */
tushki7	0:60d829a0353a	1463
tushki7	0:60d829a0353a	1464
tushki7	0:60d829a0353a	1465	/**
tushki7	0:60d829a0353a	1466	* @brief Controller Area Network C_CAN0 (C_CAN0)
tushki7	0:60d829a0353a	1467	*/
tushki7	0:60d829a0353a	1468
tushki7	0:60d829a0353a	1469	typedef struct { /!< C_CAN0 Structure /
tushki7	0:60d829a0353a	1470	__IO uint32_t CANCNTL; /!< CAN control /
tushki7	0:60d829a0353a	1471	__IO uint32_t CANSTAT; /!< Status register /
tushki7	0:60d829a0353a	1472	__I uint32_t CANEC; /!< Error counter /
tushki7	0:60d829a0353a	1473	__IO uint32_t CANBT; /!< Bit timing register /
tushki7	0:60d829a0353a	1474	__I uint32_t CANINT; /!< Interrupt register /
tushki7	0:60d829a0353a	1475	__IO uint32_t CANTEST; /!< Test register /
tushki7	0:60d829a0353a	1476	__IO uint32_t CANBRPE; /!< Baud rate prescaler extension register /
tushki7	0:60d829a0353a	1477	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	1478	__IO uint32_t CANIF1_CMDREQ; /!< Message interface 1 command request /
tushki7	0:60d829a0353a	1479
tushki7	0:60d829a0353a	1480	union {
tushki7	0:60d829a0353a	1481	__IO uint32_t CANIF1_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
tushki7	0:60d829a0353a	1482	__IO uint32_t CANIF1_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
tushki7	0:60d829a0353a	1483	};
tushki7	0:60d829a0353a	1484	__IO uint32_t CANIF1_MSK1; /!< Message interface 1 mask 1 /
tushki7	0:60d829a0353a	1485	__IO uint32_t CANIF1_MSK2; /!< Message interface 1 mask 2 /
tushki7	0:60d829a0353a	1486	__IO uint32_t CANIF1_ARB1; /!< Message interface 1 arbitration 1 /
tushki7	0:60d829a0353a	1487	__IO uint32_t CANIF1_ARB2; /!< Message interface 1 arbitration 2 /
tushki7	0:60d829a0353a	1488	__IO uint32_t CANIF1_MCTRL; /!< Message interface 1 message control /
tushki7	0:60d829a0353a	1489	__IO uint32_t CANIF1_DA1; /!< Message interface 1 data A1 /
tushki7	0:60d829a0353a	1490	__IO uint32_t CANIF1_DA2; /!< Message interface 1 data A2 /
tushki7	0:60d829a0353a	1491	__IO uint32_t CANIF1_DB1; /!< Message interface 1 data B1 /
tushki7	0:60d829a0353a	1492	__IO uint32_t CANIF1_DB2; /!< Message interface 1 data B2 /
tushki7	0:60d829a0353a	1493	__I uint32_t RESERVED1[13];
tushki7	0:60d829a0353a	1494	__IO uint32_t CANIF2_CMDREQ; /!< Message interface 1 command request /
tushki7	0:60d829a0353a	1495
tushki7	0:60d829a0353a	1496	union {
tushki7	0:60d829a0353a	1497	__IO uint32_t CANIF2_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
tushki7	0:60d829a0353a	1498	__IO uint32_t CANIF2_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
tushki7	0:60d829a0353a	1499	};
tushki7	0:60d829a0353a	1500	__IO uint32_t CANIF2_MSK1; /!< Message interface 1 mask 1 /
tushki7	0:60d829a0353a	1501	__IO uint32_t CANIF2_MSK2; /!< Message interface 1 mask 2 /
tushki7	0:60d829a0353a	1502	__IO uint32_t CANIF2_ARB1; /!< Message interface 1 arbitration 1 /
tushki7	0:60d829a0353a	1503	__IO uint32_t CANIF2_ARB2; /!< Message interface 1 arbitration 2 /
tushki7	0:60d829a0353a	1504	__IO uint32_t CANIF2_MCTRL; /!< Message interface 1 message control /
tushki7	0:60d829a0353a	1505	__IO uint32_t CANIF2_DA1; /!< Message interface 2 data A1 /
tushki7	0:60d829a0353a	1506	__IO uint32_t CANIF2_DA2; /!< Message interface 2 data A2 /
tushki7	0:60d829a0353a	1507	__IO uint32_t CANIF2_DB1; /!< Message interface 2 data B1 /
tushki7	0:60d829a0353a	1508	__IO uint32_t CANIF2_DB2; /!< Message interface 2 data B2 /
tushki7	0:60d829a0353a	1509	__I uint32_t RESERVED2[21];
tushki7	0:60d829a0353a	1510	__I uint32_t CANTXREQ1; /!< Transmission request 1 /
tushki7	0:60d829a0353a	1511	__I uint32_t CANTXREQ2; /!< Transmission request 2 /
tushki7	0:60d829a0353a	1512	__I uint32_t RESERVED3[6];
tushki7	0:60d829a0353a	1513	__I uint32_t CANND1; /!< New data 1 /
tushki7	0:60d829a0353a	1514	__I uint32_t CANND2; /!< New data 2 /
tushki7	0:60d829a0353a	1515	__I uint32_t RESERVED4[6];
tushki7	0:60d829a0353a	1516	__I uint32_t CANIR1; /!< Interrupt pending 1 /
tushki7	0:60d829a0353a	1517	__I uint32_t CANIR2; /!< Interrupt pending 2 /
tushki7	0:60d829a0353a	1518	__I uint32_t RESERVED5[6];
tushki7	0:60d829a0353a	1519	__I uint32_t CANMSGV1; /!< Message valid 1 /
tushki7	0:60d829a0353a	1520	__I uint32_t CANMSGV2; /!< Message valid 2 /
tushki7	0:60d829a0353a	1521	__I uint32_t RESERVED6[6];
tushki7	0:60d829a0353a	1522	__IO uint32_t CANCLKDIV; /!< Can clock divider register /
tushki7	0:60d829a0353a	1523	} LPC_C_CAN0_Type;
tushki7	0:60d829a0353a	1524
tushki7	0:60d829a0353a	1525
tushki7	0:60d829a0353a	1526	/* ================================================================================ */
tushki7	0:60d829a0353a	1527	/* ================ IOCON ================ */
tushki7	0:60d829a0353a	1528	/* ================================================================================ */
tushki7	0:60d829a0353a	1529
tushki7	0:60d829a0353a	1530
tushki7	0:60d829a0353a	1531	/**
tushki7	0:60d829a0353a	1532	* @brief I/O pin configuration (IOCON) (IOCON)
tushki7	0:60d829a0353a	1533	*/
tushki7	0:60d829a0353a	1534
tushki7	0:60d829a0353a	1535	typedef struct { /!< IOCON Structure /
tushki7	0:60d829a0353a	1536	__IO uint32_t PIO0_0; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1537	__IO uint32_t PIO0_1; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1538	__IO uint32_t PIO0_2; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1539	__IO uint32_t PIO0_3; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1540	__IO uint32_t PIO0_4; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1541	__IO uint32_t PIO0_5; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1542	__IO uint32_t PIO0_6; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1543	__IO uint32_t PIO0_7; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1544	__IO uint32_t PIO0_8; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1545	__IO uint32_t PIO0_9; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1546	__IO uint32_t PIO0_10; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1547	__IO uint32_t PIO0_11; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1548	__IO uint32_t PIO0_12; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1549	__IO uint32_t PIO0_13; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1550	__IO uint32_t PIO0_14; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1551	__IO uint32_t PIO0_15; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1552	__IO uint32_t PIO0_16; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1553	__IO uint32_t PIO0_17; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1554	__IO uint32_t PIO0_18; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1555	__IO uint32_t PIO0_19; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1556	__IO uint32_t PIO0_20; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1557	__IO uint32_t PIO0_21; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
tushki7	0:60d829a0353a	1558	__IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
tushki7	0:60d829a0353a	1559	the I2C-bus SCL function. */
tushki7	0:60d829a0353a	1560	__IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
tushki7	0:60d829a0353a	1561	the I2C-bus SCL function. */
tushki7	0:60d829a0353a	1562	__IO uint32_t PIO0_24; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
tushki7	0:60d829a0353a	1563	__IO uint32_t PIO0_25; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
tushki7	0:60d829a0353a	1564	__IO uint32_t PIO0_26; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
tushki7	0:60d829a0353a	1565	__IO uint32_t PIO0_27; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
tushki7	0:60d829a0353a	1566	__IO uint32_t PIO0_28; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
tushki7	0:60d829a0353a	1567	__IO uint32_t PIO0_29; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
tushki7	0:60d829a0353a	1568	__IO uint32_t PIO0_30; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
tushki7	0:60d829a0353a	1569	__IO uint32_t PIO0_31; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
tushki7	0:60d829a0353a	1570	__IO uint32_t PIO1_0; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1571	__IO uint32_t PIO1_1; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1572	__IO uint32_t PIO1_2; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1573	__IO uint32_t PIO1_3; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1574	__IO uint32_t PIO1_4; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1575	__IO uint32_t PIO1_5; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1576	__IO uint32_t PIO1_6; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1577	__IO uint32_t PIO1_7; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1578	__IO uint32_t PIO1_8; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1579	__IO uint32_t PIO1_9; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1580	__IO uint32_t PIO1_10; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1581	__IO uint32_t PIO1_11; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1582	__IO uint32_t PIO1_12; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1583	__IO uint32_t PIO1_13; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1584	__IO uint32_t PIO1_14; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1585	__IO uint32_t PIO1_15; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1586	__IO uint32_t PIO1_16; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1587	__IO uint32_t PIO1_17; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1588	__IO uint32_t PIO1_18; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1589	__IO uint32_t PIO1_19; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1590	__IO uint32_t PIO1_20; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1591	__IO uint32_t PIO1_21; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1592	__IO uint32_t PIO1_22; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1593	__IO uint32_t PIO1_23; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1594	__IO uint32_t PIO1_24; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1595	__IO uint32_t PIO1_25; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1596	__IO uint32_t PIO1_26; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1597	__IO uint32_t PIO1_27; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1598	__IO uint32_t PIO1_28; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1599	__IO uint32_t PIO1_29; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1600	__IO uint32_t PIO1_30; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1601	__IO uint32_t PIO1_31; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
tushki7	0:60d829a0353a	1602	__IO uint32_t PIO2_0; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
tushki7	0:60d829a0353a	1603	__IO uint32_t PIO2_1; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
tushki7	0:60d829a0353a	1604	__IO uint32_t PIO2_2; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
tushki7	0:60d829a0353a	1605	__IO uint32_t PIO2_3; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
tushki7	0:60d829a0353a	1606	__IO uint32_t PIO2_4; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
tushki7	0:60d829a0353a	1607	__IO uint32_t PIO2_5; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
tushki7	0:60d829a0353a	1608	__IO uint32_t PIO2_6; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
tushki7	0:60d829a0353a	1609	__IO uint32_t PIO2_7; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
tushki7	0:60d829a0353a	1610	__IO uint32_t PIO2_8; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
tushki7	0:60d829a0353a	1611	__IO uint32_t PIO2_9; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
tushki7	0:60d829a0353a	1612	__IO uint32_t PIO2_10; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
tushki7	0:60d829a0353a	1613	__IO uint32_t PIO2_11; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
tushki7	0:60d829a0353a	1614	} LPC_IOCON_Type;
tushki7	0:60d829a0353a	1615
tushki7	0:60d829a0353a	1616
tushki7	0:60d829a0353a	1617	/* -------------------- End of section using anonymous unions ------------------- */
tushki7	0:60d829a0353a	1618	#if defined(__CC_ARM)
tushki7	0:60d829a0353a	1619	#pragma pop
tushki7	0:60d829a0353a	1620	#elif defined(__ICCARM__)
tushki7	0:60d829a0353a	1621	/* leave anonymous unions enabled */
tushki7	0:60d829a0353a	1622	#elif defined(__GNUC__)
tushki7	0:60d829a0353a	1623	/* anonymous unions are enabled by default */
tushki7	0:60d829a0353a	1624	#elif defined(__TMS470__)
tushki7	0:60d829a0353a	1625	/* anonymous unions are enabled by default */
tushki7	0:60d829a0353a	1626	#elif defined(__TASKING__)
tushki7	0:60d829a0353a	1627	#pragma warning restore
tushki7	0:60d829a0353a	1628	#else
tushki7	0:60d829a0353a	1629	#warning Not supported compiler type
tushki7	0:60d829a0353a	1630	#endif
tushki7	0:60d829a0353a	1631
tushki7	0:60d829a0353a	1632
tushki7	0:60d829a0353a	1633
tushki7	0:60d829a0353a	1634
tushki7	0:60d829a0353a	1635	/* ================================================================================ */
tushki7	0:60d829a0353a	1636	/* ================ Peripheral memory map ================ */
tushki7	0:60d829a0353a	1637	/* ================================================================================ */
tushki7	0:60d829a0353a	1638
tushki7	0:60d829a0353a	1639	#define LPC_GPIO_PORT_BASE 0x1C000000UL
tushki7	0:60d829a0353a	1640	#define LPC_DMA_BASE 0x1C004000UL
tushki7	0:60d829a0353a	1641	#define LPC_USB_BASE 0x1C00C000UL
tushki7	0:60d829a0353a	1642	#define LPC_CRC_BASE 0x1C010000UL
tushki7	0:60d829a0353a	1643	#define LPC_SCT0_BASE 0x1C018000UL
tushki7	0:60d829a0353a	1644	#define LPC_SCT1_BASE 0x1C01C000UL
tushki7	0:60d829a0353a	1645	#define LPC_SCT2_BASE 0x1C020000UL
tushki7	0:60d829a0353a	1646	#define LPC_SCT3_BASE 0x1C024000UL
tushki7	0:60d829a0353a	1647	#define LPC_ADC0_BASE 0x40000000UL
tushki7	0:60d829a0353a	1648	#define LPC_DAC_BASE 0x40004000UL
tushki7	0:60d829a0353a	1649	#define LPC_ACMP_BASE 0x40008000UL
tushki7	0:60d829a0353a	1650	#define LPC_INMUX_BASE 0x40014000UL
tushki7	0:60d829a0353a	1651	#define LPC_RTC_BASE 0x40028000UL
tushki7	0:60d829a0353a	1652	#define LPC_WWDT_BASE 0x4002C000UL
tushki7	0:60d829a0353a	1653	#define LPC_SWM_BASE 0x40038000UL
tushki7	0:60d829a0353a	1654	#define LPC_PMU_BASE 0x4003C000UL
tushki7	0:60d829a0353a	1655	#define LPC_USART0_BASE 0x40040000UL
tushki7	0:60d829a0353a	1656	#define LPC_USART1_BASE 0x40044000UL
tushki7	0:60d829a0353a	1657	#define LPC_SPI0_BASE 0x40048000UL
tushki7	0:60d829a0353a	1658	#define LPC_SPI1_BASE 0x4004C000UL
tushki7	0:60d829a0353a	1659	#define LPC_I2C0_BASE 0x40050000UL
tushki7	0:60d829a0353a	1660	#define LPC_QEI_BASE 0x40058000UL
tushki7	0:60d829a0353a	1661	#define LPC_SYSCON_BASE 0x40074000UL
tushki7	0:60d829a0353a	1662	#define LPC_ADC1_BASE 0x40080000UL
tushki7	0:60d829a0353a	1663	#define LPC_MRT_BASE 0x400A0000UL
tushki7	0:60d829a0353a	1664	#define LPC_PINT_BASE 0x400A4000UL
tushki7	0:60d829a0353a	1665	#define LPC_GINT0_BASE 0x400A8000UL
tushki7	0:60d829a0353a	1666	#define LPC_GINT1_BASE 0x400AC000UL
tushki7	0:60d829a0353a	1667	#define LPC_RIT_BASE 0x400B4000UL
tushki7	0:60d829a0353a	1668	#define LPC_SCTIPU_BASE 0x400B8000UL
tushki7	0:60d829a0353a	1669	#define LPC_FLASHCTRL_BASE 0x400BC000UL
tushki7	0:60d829a0353a	1670	#define LPC_USART2_BASE 0x400C0000UL
tushki7	0:60d829a0353a	1671	#define LPC_C_CAN0_BASE 0x400F0000UL
tushki7	0:60d829a0353a	1672	#define LPC_IOCON_BASE 0x400F8000UL
tushki7	0:60d829a0353a	1673
tushki7	0:60d829a0353a	1674
tushki7	0:60d829a0353a	1675	/* ================================================================================ */
tushki7	0:60d829a0353a	1676	/* ================ Peripheral declaration ================ */
tushki7	0:60d829a0353a	1677	/* ================================================================================ */
tushki7	0:60d829a0353a	1678
tushki7	0:60d829a0353a	1679	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
tushki7	0:60d829a0353a	1680	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
tushki7	0:60d829a0353a	1681	#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
tushki7	0:60d829a0353a	1682	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
tushki7	0:60d829a0353a	1683	#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
tushki7	0:60d829a0353a	1684	#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
tushki7	0:60d829a0353a	1685	#define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
tushki7	0:60d829a0353a	1686	#define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
tushki7	0:60d829a0353a	1687	#define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
tushki7	0:60d829a0353a	1688	#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
tushki7	0:60d829a0353a	1689	#define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
tushki7	0:60d829a0353a	1690	#define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
tushki7	0:60d829a0353a	1691	#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
tushki7	0:60d829a0353a	1692	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
tushki7	0:60d829a0353a	1693	#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
tushki7	0:60d829a0353a	1694	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
tushki7	0:60d829a0353a	1695	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
tushki7	0:60d829a0353a	1696	#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
tushki7	0:60d829a0353a	1697	#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
tushki7	0:60d829a0353a	1698	#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
tushki7	0:60d829a0353a	1699	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
tushki7	0:60d829a0353a	1700	#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
tushki7	0:60d829a0353a	1701	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
tushki7	0:60d829a0353a	1702	#define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
tushki7	0:60d829a0353a	1703	#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
tushki7	0:60d829a0353a	1704	#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
tushki7	0:60d829a0353a	1705	#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
tushki7	0:60d829a0353a	1706	#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
tushki7	0:60d829a0353a	1707	#define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
tushki7	0:60d829a0353a	1708	#define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
tushki7	0:60d829a0353a	1709	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
tushki7	0:60d829a0353a	1710	#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
tushki7	0:60d829a0353a	1711	#define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
tushki7	0:60d829a0353a	1712	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
tushki7	0:60d829a0353a	1713
tushki7	0:60d829a0353a	1714
tushki7	0:60d829a0353a	1715	/** @} / / End of group Device_Peripheral_Registers */
tushki7	0:60d829a0353a	1716	/** @} / / End of group LPC15xx */
tushki7	0:60d829a0353a	1717	/** @} / / End of group (null) */
tushki7	0:60d829a0353a	1718
tushki7	0:60d829a0353a	1719	#ifdef __cplusplus
tushki7	0:60d829a0353a	1720	}
tushki7	0:60d829a0353a	1721	#endif
tushki7	0:60d829a0353a	1722
tushki7	0:60d829a0353a	1723
tushki7	0:60d829a0353a	1724	#endif /* LPC15XX_H */
tushki7	0:60d829a0353a	1725

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Type:	Program
Created:	11 Apr 2015
Imports:	100
Forks:	0
Commits:	2
Dependents:	0
Dependencies:	1
Followers:	2

mbed/TARGET_LPC1549/LPC15xx.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

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