Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_LPC1114/LPC11xx.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a 
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /****************************************************************************
tushki7 0:60d829a0353a 2 * $Id:: LPC11xx.h 9198 2012-05-29 usb00175 $
tushki7 0:60d829a0353a 3 * Project: NXP LPC11xx software example
tushki7 0:60d829a0353a 4 *
tushki7 0:60d829a0353a 5 * Description:
tushki7 0:60d829a0353a 6 * CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
tushki7 0:60d829a0353a 7 * NXP LPC11xx Device Series
tushki7 0:60d829a0353a 8
tushki7 0:60d829a0353a 9 ****************************************************************************
tushki7 0:60d829a0353a 10 * Software that is described herein is for illustrative purposes only
tushki7 0:60d829a0353a 11 * which provides customers with programming information regarding the
tushki7 0:60d829a0353a 12 * products. This software is supplied "AS IS" without any warranties.
tushki7 0:60d829a0353a 13 * NXP Semiconductors assumes no responsibility or liability for the
tushki7 0:60d829a0353a 14 * use of the software, conveys no license or title under any patent,
tushki7 0:60d829a0353a 15 * copyright, or mask work right to the product. NXP Semiconductors
tushki7 0:60d829a0353a 16 * reserves the right to make changes in the software without
tushki7 0:60d829a0353a 17 * notification. NXP Semiconductors also make no representation or
tushki7 0:60d829a0353a 18 * warranty that such application will be suitable for the specified
tushki7 0:60d829a0353a 19 * use without further testing or modification.
tushki7 0:60d829a0353a 20
tushki7 0:60d829a0353a 21 * Permission to use, copy, modify, and distribute this software and its
tushki7 0:60d829a0353a 22 * documentation is hereby granted, under NXP Semiconductors'
tushki7 0:60d829a0353a 23 * relevant copyright in the software, without fee, provided that it
tushki7 0:60d829a0353a 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
tushki7 0:60d829a0353a 25 * copyright, permission, and disclaimer notice must appear in all copies of
tushki7 0:60d829a0353a 26 * this code.
tushki7 0:60d829a0353a 27
tushki7 0:60d829a0353a 28 ****************************************************************************/
tushki7 0:60d829a0353a 29 #ifndef __LPC11xx_H__
tushki7 0:60d829a0353a 30 #define __LPC11xx_H__
tushki7 0:60d829a0353a 31
tushki7 0:60d829a0353a 32 #ifdef __cplusplus
tushki7 0:60d829a0353a 33 extern "C" {
tushki7 0:60d829a0353a 34 #endif
tushki7 0:60d829a0353a 35
tushki7 0:60d829a0353a 36 /** @addtogroup LPC11xx_Definitions LPC11xx Definitions
tushki7 0:60d829a0353a 37 This file defines all structures and symbols for LPC11xx:
tushki7 0:60d829a0353a 38 - Registers and bitfields
tushki7 0:60d829a0353a 39 - peripheral base address
tushki7 0:60d829a0353a 40 - peripheral ID
tushki7 0:60d829a0353a 41 - PIO definitions
tushki7 0:60d829a0353a 42 @{
tushki7 0:60d829a0353a 43 */
tushki7 0:60d829a0353a 44
tushki7 0:60d829a0353a 45
tushki7 0:60d829a0353a 46 /******************************************************************************/
tushki7 0:60d829a0353a 47 /* Processor and Core Peripherals */
tushki7 0:60d829a0353a 48 /******************************************************************************/
tushki7 0:60d829a0353a 49 /** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions
tushki7 0:60d829a0353a 50 Configuration of the Cortex-M0 Processor and Core Peripherals
tushki7 0:60d829a0353a 51 @{
tushki7 0:60d829a0353a 52 */
tushki7 0:60d829a0353a 53
tushki7 0:60d829a0353a 54 /*
tushki7 0:60d829a0353a 55 * ==========================================================================
tushki7 0:60d829a0353a 56 * ---------- Interrupt Number Definition -----------------------------------
tushki7 0:60d829a0353a 57 * ==========================================================================
tushki7 0:60d829a0353a 58 */
tushki7 0:60d829a0353a 59 typedef enum IRQn
tushki7 0:60d829a0353a 60 {
tushki7 0:60d829a0353a 61 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
tushki7 0:60d829a0353a 62 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
tushki7 0:60d829a0353a 63 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
tushki7 0:60d829a0353a 64 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
tushki7 0:60d829a0353a 65 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
tushki7 0:60d829a0353a 66 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
tushki7 0:60d829a0353a 67
tushki7 0:60d829a0353a 68 /****** LPC11Cxx or LPC11xx Specific Interrupt Numbers *******************************************************/
tushki7 0:60d829a0353a 69 WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
tushki7 0:60d829a0353a 70 WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */
tushki7 0:60d829a0353a 71 WAKEUP2_IRQn = 2,
tushki7 0:60d829a0353a 72 WAKEUP3_IRQn = 3,
tushki7 0:60d829a0353a 73 WAKEUP4_IRQn = 4,
tushki7 0:60d829a0353a 74 WAKEUP5_IRQn = 5,
tushki7 0:60d829a0353a 75 WAKEUP6_IRQn = 6,
tushki7 0:60d829a0353a 76 WAKEUP7_IRQn = 7,
tushki7 0:60d829a0353a 77 WAKEUP8_IRQn = 8,
tushki7 0:60d829a0353a 78 WAKEUP9_IRQn = 9,
tushki7 0:60d829a0353a 79 WAKEUP10_IRQn = 10,
tushki7 0:60d829a0353a 80 WAKEUP11_IRQn = 11,
tushki7 0:60d829a0353a 81 WAKEUP12_IRQn = 12,
tushki7 0:60d829a0353a 82 CAN_IRQn = 13, /*!< CAN Interrupt */
tushki7 0:60d829a0353a 83 SSP1_IRQn = 14, /*!< SSP1 Interrupt */
tushki7 0:60d829a0353a 84 I2C_IRQn = 15, /*!< I2C Interrupt */
tushki7 0:60d829a0353a 85 TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
tushki7 0:60d829a0353a 86 TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
tushki7 0:60d829a0353a 87 TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
tushki7 0:60d829a0353a 88 TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
tushki7 0:60d829a0353a 89 SSP0_IRQn = 20, /*!< SSP0 Interrupt */
tushki7 0:60d829a0353a 90 UART_IRQn = 21, /*!< UART Interrupt */
tushki7 0:60d829a0353a 91 Reserved0_IRQn = 22, /*!< Reserved Interrupt */
tushki7 0:60d829a0353a 92 Reserved1_IRQn = 23,
tushki7 0:60d829a0353a 93 ADC_IRQn = 24, /*!< A/D Converter Interrupt */
tushki7 0:60d829a0353a 94 WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
tushki7 0:60d829a0353a 95 BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
tushki7 0:60d829a0353a 96 FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
tushki7 0:60d829a0353a 97 EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */
tushki7 0:60d829a0353a 98 EINT2_IRQn = 29, /*!< External Interrupt 2 Interrupt */
tushki7 0:60d829a0353a 99 EINT1_IRQn = 30, /*!< External Interrupt 1 Interrupt */
tushki7 0:60d829a0353a 100 EINT0_IRQn = 31, /*!< External Interrupt 0 Interrupt */
tushki7 0:60d829a0353a 101 } IRQn_Type;
tushki7 0:60d829a0353a 102
tushki7 0:60d829a0353a 103 /*
tushki7 0:60d829a0353a 104 * ==========================================================================
tushki7 0:60d829a0353a 105 * ----------- Processor and Core Peripheral Section ------------------------
tushki7 0:60d829a0353a 106 * ==========================================================================
tushki7 0:60d829a0353a 107 */
tushki7 0:60d829a0353a 108
tushki7 0:60d829a0353a 109 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
tushki7 0:60d829a0353a 110 #define __MPU_PRESENT 0 /*!< MPU present or not */
tushki7 0:60d829a0353a 111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
tushki7 0:60d829a0353a 112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
tushki7 0:60d829a0353a 113
tushki7 0:60d829a0353a 114 /*@}*/ /* end of group LPC11xx_CMSIS */
tushki7 0:60d829a0353a 115
tushki7 0:60d829a0353a 116
tushki7 0:60d829a0353a 117 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
tushki7 0:60d829a0353a 118 #include "system_LPC11xx.h" /* System Header */
tushki7 0:60d829a0353a 119
tushki7 0:60d829a0353a 120
tushki7 0:60d829a0353a 121 /******************************************************************************/
tushki7 0:60d829a0353a 122 /* Device Specific Peripheral Registers structures */
tushki7 0:60d829a0353a 123 /******************************************************************************/
tushki7 0:60d829a0353a 124
tushki7 0:60d829a0353a 125 #if defined ( __CC_ARM )
tushki7 0:60d829a0353a 126 #pragma anon_unions
tushki7 0:60d829a0353a 127 #endif
tushki7 0:60d829a0353a 128
tushki7 0:60d829a0353a 129 /*------------- System Control (SYSCON) --------------------------------------*/
tushki7 0:60d829a0353a 130 /** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block
tushki7 0:60d829a0353a 131 @{
tushki7 0:60d829a0353a 132 */
tushki7 0:60d829a0353a 133 typedef struct
tushki7 0:60d829a0353a 134 {
tushki7 0:60d829a0353a 135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
tushki7 0:60d829a0353a 136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
tushki7 0:60d829a0353a 137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
tushki7 0:60d829a0353a 138 __I uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/ ) */
tushki7 0:60d829a0353a 139 uint32_t RESERVED0[4];
tushki7 0:60d829a0353a 140
tushki7 0:60d829a0353a 141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
tushki7 0:60d829a0353a 142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
tushki7 0:60d829a0353a 143 __IO uint32_t IRCCTRL; /*!< Offset: 0x028 IRC control (R/W) */
tushki7 0:60d829a0353a 144 uint32_t RESERVED1[1];
tushki7 0:60d829a0353a 145 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/ ) */
tushki7 0:60d829a0353a 146 uint32_t RESERVED2[3];
tushki7 0:60d829a0353a 147 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
tushki7 0:60d829a0353a 148 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
tushki7 0:60d829a0353a 149 uint32_t RESERVED3[10];
tushki7 0:60d829a0353a 150
tushki7 0:60d829a0353a 151 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
tushki7 0:60d829a0353a 152 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
tushki7 0:60d829a0353a 153 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
tushki7 0:60d829a0353a 154 uint32_t RESERVED4[1];
tushki7 0:60d829a0353a 155
tushki7 0:60d829a0353a 156 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
tushki7 0:60d829a0353a 157 uint32_t RESERVED5[4];
tushki7 0:60d829a0353a 158 __IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */
tushki7 0:60d829a0353a 159 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x098 UART clock divider (R/W) */
tushki7 0:60d829a0353a 160 __IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */
tushki7 0:60d829a0353a 161 uint32_t RESERVED6[12];
tushki7 0:60d829a0353a 162
tushki7 0:60d829a0353a 163 __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 WDT clock source select (R/W) */
tushki7 0:60d829a0353a 164 __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */
tushki7 0:60d829a0353a 165 __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 WDT clock divider (R/W) */
tushki7 0:60d829a0353a 166 uint32_t RESERVED8[1];
tushki7 0:60d829a0353a 167 __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
tushki7 0:60d829a0353a 168 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
tushki7 0:60d829a0353a 169 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
tushki7 0:60d829a0353a 170 uint32_t RESERVED9[5];
tushki7 0:60d829a0353a 171
tushki7 0:60d829a0353a 172 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
tushki7 0:60d829a0353a 173 __IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */
tushki7 0:60d829a0353a 174 uint32_t RESERVED10[18];
tushki7 0:60d829a0353a 175 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
tushki7 0:60d829a0353a 176 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
tushki7 0:60d829a0353a 177
tushki7 0:60d829a0353a 178 uint32_t RESERVED13[7];
tushki7 0:60d829a0353a 179 __IO uint32_t NMISRC; /*!< Offset: 0x174 NMI source selection register (R/W) */
tushki7 0:60d829a0353a 180 uint32_t RESERVED14[34];
tushki7 0:60d829a0353a 181
tushki7 0:60d829a0353a 182 __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */
tushki7 0:60d829a0353a 183 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
tushki7 0:60d829a0353a 184 __O uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 Start logic reset Register 0 ( /W) */
tushki7 0:60d829a0353a 185 __I uint32_t STARTSRP0; /*!< Offset: 0x20C Start logic status Register 0 (R/) */
tushki7 0:60d829a0353a 186 __IO uint32_t STARTAPRP1; /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */
tushki7 0:60d829a0353a 187 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */
tushki7 0:60d829a0353a 188 __O uint32_t STARTRSRP1CLR; /*!< Offset: 0x218 Start logic reset Register 0 ( /W). (LPC11UXX only) */
tushki7 0:60d829a0353a 189 __IO uint32_t STARTSRP1; /*!< Offset: 0x21C Start logic status Register 0 (R/W). (LPC11UXX only) */
tushki7 0:60d829a0353a 190 uint32_t RESERVED17[4];
tushki7 0:60d829a0353a 191
tushki7 0:60d829a0353a 192 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
tushki7 0:60d829a0353a 193 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
tushki7 0:60d829a0353a 194 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
tushki7 0:60d829a0353a 195 uint32_t RESERVED15[110];
tushki7 0:60d829a0353a 196 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
tushki7 0:60d829a0353a 197 } LPC_SYSCON_TypeDef;
tushki7 0:60d829a0353a 198 /*@}*/ /* end of group LPC11xx_SYSCON */
tushki7 0:60d829a0353a 199
tushki7 0:60d829a0353a 200
tushki7 0:60d829a0353a 201 /*------------- Pin Connect Block (IOCON) --------------------------------*/
tushki7 0:60d829a0353a 202 /** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block
tushki7 0:60d829a0353a 203 @{
tushki7 0:60d829a0353a 204 */
tushki7 0:60d829a0353a 205 typedef struct
tushki7 0:60d829a0353a 206 {
tushki7 0:60d829a0353a 207 __IO uint32_t PIO2_6; /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */
tushki7 0:60d829a0353a 208 uint32_t RESERVED0[1];
tushki7 0:60d829a0353a 209 __IO uint32_t PIO2_0; /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */
tushki7 0:60d829a0353a 210 __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0 (R/W) */
tushki7 0:60d829a0353a 211 __IO uint32_t PIO0_1; /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */
tushki7 0:60d829a0353a 212 __IO uint32_t PIO1_8; /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */
tushki7 0:60d829a0353a 213 __IO uint32_t SSEL1_LOC; /*!< Offset: 0x018 IOCON SSEL1 location register (IOCON_SSEL1_LOC, address 0x4004 4018) */
tushki7 0:60d829a0353a 214 __IO uint32_t PIO0_2; /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */
tushki7 0:60d829a0353a 215
tushki7 0:60d829a0353a 216 __IO uint32_t PIO2_7; /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */
tushki7 0:60d829a0353a 217 __IO uint32_t PIO2_8; /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */
tushki7 0:60d829a0353a 218 __IO uint32_t PIO2_1; /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */
tushki7 0:60d829a0353a 219 __IO uint32_t PIO0_3; /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */
tushki7 0:60d829a0353a 220 __IO uint32_t PIO0_4; /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */
tushki7 0:60d829a0353a 221 __IO uint32_t PIO0_5; /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */
tushki7 0:60d829a0353a 222 __IO uint32_t PIO1_9; /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */
tushki7 0:60d829a0353a 223 __IO uint32_t PIO3_4; /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */
tushki7 0:60d829a0353a 224
tushki7 0:60d829a0353a 225 __IO uint32_t PIO2_4; /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */
tushki7 0:60d829a0353a 226 __IO uint32_t PIO2_5; /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */
tushki7 0:60d829a0353a 227 __IO uint32_t PIO3_5; /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */
tushki7 0:60d829a0353a 228 __IO uint32_t PIO0_6; /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */
tushki7 0:60d829a0353a 229 __IO uint32_t PIO0_7; /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */
tushki7 0:60d829a0353a 230 __IO uint32_t PIO2_9; /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */
tushki7 0:60d829a0353a 231 __IO uint32_t PIO2_10; /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */
tushki7 0:60d829a0353a 232 __IO uint32_t PIO2_2; /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */
tushki7 0:60d829a0353a 233
tushki7 0:60d829a0353a 234 __IO uint32_t PIO0_8; /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */
tushki7 0:60d829a0353a 235 __IO uint32_t PIO0_9; /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */
tushki7 0:60d829a0353a 236 __IO uint32_t SWCLK_PIO0_10; /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */
tushki7 0:60d829a0353a 237 __IO uint32_t PIO1_10; /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */
tushki7 0:60d829a0353a 238 __IO uint32_t PIO2_11; /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */
tushki7 0:60d829a0353a 239 __IO uint32_t R_PIO0_11; /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */
tushki7 0:60d829a0353a 240 __IO uint32_t R_PIO1_0; /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */
tushki7 0:60d829a0353a 241 __IO uint32_t R_PIO1_1; /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */
tushki7 0:60d829a0353a 242
tushki7 0:60d829a0353a 243 __IO uint32_t R_PIO1_2; /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */
tushki7 0:60d829a0353a 244 __IO uint32_t PIO3_0; /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */
tushki7 0:60d829a0353a 245 __IO uint32_t PIO3_1; /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */
tushki7 0:60d829a0353a 246 __IO uint32_t PIO2_3; /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */
tushki7 0:60d829a0353a 247 __IO uint32_t SWDIO_PIO1_3; /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */
tushki7 0:60d829a0353a 248 __IO uint32_t PIO1_4; /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */
tushki7 0:60d829a0353a 249 __IO uint32_t PIO1_11; /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */
tushki7 0:60d829a0353a 250 __IO uint32_t PIO3_2; /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */
tushki7 0:60d829a0353a 251
tushki7 0:60d829a0353a 252 __IO uint32_t PIO1_5; /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */
tushki7 0:60d829a0353a 253 __IO uint32_t PIO1_6; /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */
tushki7 0:60d829a0353a 254 __IO uint32_t PIO1_7; /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */
tushki7 0:60d829a0353a 255 __IO uint32_t PIO3_3; /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */
tushki7 0:60d829a0353a 256 __IO uint32_t SCK_LOC; /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */
tushki7 0:60d829a0353a 257 __IO uint32_t DSR_LOC; /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */
tushki7 0:60d829a0353a 258 __IO uint32_t DCD_LOC; /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */
tushki7 0:60d829a0353a 259 __IO uint32_t RI_LOC; /*!< Offset: 0x0BC RI pin location Register (R/W) */
tushki7 0:60d829a0353a 260
tushki7 0:60d829a0353a 261 __IO uint32_t CT16B0_CAP0_LOC; /*!< Offset: 0x0C0 IOCON CT16B0_CAP0 location register (IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0) */
tushki7 0:60d829a0353a 262 __IO uint32_t SCK1_LOC; /*!< Offset: 0x0C4 IOCON SCK1 location register (IOCON_SCK1_LOC, address 0x4004 40C4) */
tushki7 0:60d829a0353a 263 __IO uint32_t MISO1_LOC; /*!< Offset: 0x0C8 IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) */
tushki7 0:60d829a0353a 264 __IO uint32_t MOSI1_LOC; /*!< Offset: 0x0CC IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) */
tushki7 0:60d829a0353a 265 __IO uint32_t CT32B0_CAP0_LOC; /*!< Offset: 0x0D0 IOCON CT32B0_CAP0 location register (IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0) */
tushki7 0:60d829a0353a 266 __IO uint32_t RXD_LOC; /*!< Offset: 0x0D4 IOCON RXD location register (IOCON_RXD_LOC, address 0x4004 40D4) */
tushki7 0:60d829a0353a 267 } LPC_IOCON_TypeDef;
tushki7 0:60d829a0353a 268 /*@}*/ /* end of group LPC11xx_IOCON */
tushki7 0:60d829a0353a 269
tushki7 0:60d829a0353a 270
tushki7 0:60d829a0353a 271 /*------------- Power Management Unit (PMU) --------------------------*/
tushki7 0:60d829a0353a 272 /** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit
tushki7 0:60d829a0353a 273 @{
tushki7 0:60d829a0353a 274 */
tushki7 0:60d829a0353a 275 typedef struct
tushki7 0:60d829a0353a 276 {
tushki7 0:60d829a0353a 277 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
tushki7 0:60d829a0353a 278 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
tushki7 0:60d829a0353a 279 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
tushki7 0:60d829a0353a 280 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
tushki7 0:60d829a0353a 281 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
tushki7 0:60d829a0353a 282 __IO uint32_t GPREG4; /*!< Offset: 0x014 General purpose Register 4 (R/W) */
tushki7 0:60d829a0353a 283 } LPC_PMU_TypeDef;
tushki7 0:60d829a0353a 284 /*@}*/ /* end of group LPC11xx_PMU */
tushki7 0:60d829a0353a 285
tushki7 0:60d829a0353a 286
tushki7 0:60d829a0353a 287
tushki7 0:60d829a0353a 288 // ------------------------------------------------------------------------------------------------
tushki7 0:60d829a0353a 289 // ----- FLASHCTRL -----
tushki7 0:60d829a0353a 290 // ------------------------------------------------------------------------------------------------
tushki7 0:60d829a0353a 291
tushki7 0:60d829a0353a 292 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
tushki7 0:60d829a0353a 293 __I uint32_t RESERVED0[4];
tushki7 0:60d829a0353a 294 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
tushki7 0:60d829a0353a 295 __I uint32_t RESERVED1[3];
tushki7 0:60d829a0353a 296 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
tushki7 0:60d829a0353a 297 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
tushki7 0:60d829a0353a 298 __I uint32_t RESERVED2[1];
tushki7 0:60d829a0353a 299 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
tushki7 0:60d829a0353a 300 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
tushki7 0:60d829a0353a 301 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
tushki7 0:60d829a0353a 302 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
tushki7 0:60d829a0353a 303 __I uint32_t RESERVED3[1001];
tushki7 0:60d829a0353a 304 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
tushki7 0:60d829a0353a 305 __I uint32_t RESERVED4[1];
tushki7 0:60d829a0353a 306 __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
tushki7 0:60d829a0353a 307 } LPC_FLASHCTRL_Type;
tushki7 0:60d829a0353a 308
tushki7 0:60d829a0353a 309
tushki7 0:60d829a0353a 310 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
tushki7 0:60d829a0353a 311 /** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output
tushki7 0:60d829a0353a 312 @{
tushki7 0:60d829a0353a 313 */
tushki7 0:60d829a0353a 314 typedef struct
tushki7 0:60d829a0353a 315 {
tushki7 0:60d829a0353a 316 union {
tushki7 0:60d829a0353a 317 __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */
tushki7 0:60d829a0353a 318 struct {
tushki7 0:60d829a0353a 319 uint32_t RESERVED0[4095];
tushki7 0:60d829a0353a 320 __IO uint32_t DATA; /*!< Offset: 0x3FFC Port data Register (R/W) */
tushki7 0:60d829a0353a 321 };
tushki7 0:60d829a0353a 322 };
tushki7 0:60d829a0353a 323 uint32_t RESERVED1[4096];
tushki7 0:60d829a0353a 324 __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction Register (R/W) */
tushki7 0:60d829a0353a 325 __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense Register (R/W) */
tushki7 0:60d829a0353a 326 __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */
tushki7 0:60d829a0353a 327 __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event Register (R/W) */
tushki7 0:60d829a0353a 328 __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask Register (R/W) */
tushki7 0:60d829a0353a 329 __I uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */
tushki7 0:60d829a0353a 330 __I uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */
tushki7 0:60d829a0353a 331 __O uint32_t IC; /*!< Offset: 0x801C Interrupt clear Register (/W) */
tushki7 0:60d829a0353a 332 } LPC_GPIO_TypeDef;
tushki7 0:60d829a0353a 333 /*@}*/ /* end of group LPC11xx_GPIO */
tushki7 0:60d829a0353a 334
tushki7 0:60d829a0353a 335 /*------------- Timer (TMR) --------------------------------------------------*/
tushki7 0:60d829a0353a 336 /** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer
tushki7 0:60d829a0353a 337 @{
tushki7 0:60d829a0353a 338 */
tushki7 0:60d829a0353a 339 typedef struct
tushki7 0:60d829a0353a 340 {
tushki7 0:60d829a0353a 341 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
tushki7 0:60d829a0353a 342 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
tushki7 0:60d829a0353a 343 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
tushki7 0:60d829a0353a 344 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
tushki7 0:60d829a0353a 345 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
tushki7 0:60d829a0353a 346 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
tushki7 0:60d829a0353a 347 union {
tushki7 0:60d829a0353a 348 __IO uint32_t MR[4]; /*!< Offset: Match Register base */
tushki7 0:60d829a0353a 349 struct{
tushki7 0:60d829a0353a 350 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
tushki7 0:60d829a0353a 351 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
tushki7 0:60d829a0353a 352 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
tushki7 0:60d829a0353a 353 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
tushki7 0:60d829a0353a 354 };
tushki7 0:60d829a0353a 355 };
tushki7 0:60d829a0353a 356 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
tushki7 0:60d829a0353a 357 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
tushki7 0:60d829a0353a 358 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
tushki7 0:60d829a0353a 359 uint32_t RESERVED1[2];
tushki7 0:60d829a0353a 360 __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
tushki7 0:60d829a0353a 361 uint32_t RESERVED2[12];
tushki7 0:60d829a0353a 362 __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
tushki7 0:60d829a0353a 363 __IO uint32_t PWMC; /*!< Offset: 0x074 PWM Control Register (R/W) */
tushki7 0:60d829a0353a 364 } LPC_TMR_TypeDef;
tushki7 0:60d829a0353a 365 /*@}*/ /* end of group LPC11xx_TMR */
tushki7 0:60d829a0353a 366
tushki7 0:60d829a0353a 367
tushki7 0:60d829a0353a 368 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
tushki7 0:60d829a0353a 369 /** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter
tushki7 0:60d829a0353a 370 @{
tushki7 0:60d829a0353a 371 */
tushki7 0:60d829a0353a 372 typedef struct
tushki7 0:60d829a0353a 373 {
tushki7 0:60d829a0353a 374 union {
tushki7 0:60d829a0353a 375 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
tushki7 0:60d829a0353a 376 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
tushki7 0:60d829a0353a 377 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
tushki7 0:60d829a0353a 378 };
tushki7 0:60d829a0353a 379 union {
tushki7 0:60d829a0353a 380 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
tushki7 0:60d829a0353a 381 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
tushki7 0:60d829a0353a 382 };
tushki7 0:60d829a0353a 383 union {
tushki7 0:60d829a0353a 384 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
tushki7 0:60d829a0353a 385 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
tushki7 0:60d829a0353a 386 };
tushki7 0:60d829a0353a 387 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
tushki7 0:60d829a0353a 388 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
tushki7 0:60d829a0353a 389 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
tushki7 0:60d829a0353a 390 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
tushki7 0:60d829a0353a 391 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
tushki7 0:60d829a0353a 392 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
tushki7 0:60d829a0353a 393 uint32_t RESERVED0;
tushki7 0:60d829a0353a 394 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
tushki7 0:60d829a0353a 395 uint32_t RESERVED1;
tushki7 0:60d829a0353a 396 __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */
tushki7 0:60d829a0353a 397 uint32_t RESERVED2[6];
tushki7 0:60d829a0353a 398 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
tushki7 0:60d829a0353a 399 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
tushki7 0:60d829a0353a 400 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
tushki7 0:60d829a0353a 401 __I uint32_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register (R) */
tushki7 0:60d829a0353a 402 } LPC_UART_TypeDef;
tushki7 0:60d829a0353a 403 /*@}*/ /* end of group LPC11xx_UART */
tushki7 0:60d829a0353a 404
tushki7 0:60d829a0353a 405
tushki7 0:60d829a0353a 406 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
tushki7 0:60d829a0353a 407 /** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port
tushki7 0:60d829a0353a 408 @{
tushki7 0:60d829a0353a 409 */
tushki7 0:60d829a0353a 410 typedef struct
tushki7 0:60d829a0353a 411 {
tushki7 0:60d829a0353a 412 __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
tushki7 0:60d829a0353a 413 __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
tushki7 0:60d829a0353a 414 __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
tushki7 0:60d829a0353a 415 __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
tushki7 0:60d829a0353a 416 __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
tushki7 0:60d829a0353a 417 __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
tushki7 0:60d829a0353a 418 __I uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/) */
tushki7 0:60d829a0353a 419 __I uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/) */
tushki7 0:60d829a0353a 420 __O uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (/W) */
tushki7 0:60d829a0353a 421 } LPC_SSP_TypeDef;
tushki7 0:60d829a0353a 422 /*@}*/ /* end of group LPC11xx_SSP */
tushki7 0:60d829a0353a 423
tushki7 0:60d829a0353a 424
tushki7 0:60d829a0353a 425 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
tushki7 0:60d829a0353a 426 /** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface
tushki7 0:60d829a0353a 427 @{
tushki7 0:60d829a0353a 428 */
tushki7 0:60d829a0353a 429 typedef struct
tushki7 0:60d829a0353a 430 {
tushki7 0:60d829a0353a 431 __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
tushki7 0:60d829a0353a 432 __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
tushki7 0:60d829a0353a 433 __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
tushki7 0:60d829a0353a 434 __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
tushki7 0:60d829a0353a 435 __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
tushki7 0:60d829a0353a 436 __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
tushki7 0:60d829a0353a 437 __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
tushki7 0:60d829a0353a 438 __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
tushki7 0:60d829a0353a 439 __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
tushki7 0:60d829a0353a 440 __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
tushki7 0:60d829a0353a 441 __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
tushki7 0:60d829a0353a 442 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
tushki7 0:60d829a0353a 443 __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
tushki7 0:60d829a0353a 444 __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
tushki7 0:60d829a0353a 445 __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
tushki7 0:60d829a0353a 446 __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
tushki7 0:60d829a0353a 447 } LPC_I2C_TypeDef;
tushki7 0:60d829a0353a 448 /*@}*/ /* end of group LPC11xx_I2C */
tushki7 0:60d829a0353a 449
tushki7 0:60d829a0353a 450
tushki7 0:60d829a0353a 451 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
tushki7 0:60d829a0353a 452 /** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer
tushki7 0:60d829a0353a 453 @{
tushki7 0:60d829a0353a 454 */
tushki7 0:60d829a0353a 455 typedef struct
tushki7 0:60d829a0353a 456 {
tushki7 0:60d829a0353a 457 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
tushki7 0:60d829a0353a 458 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
tushki7 0:60d829a0353a 459 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
tushki7 0:60d829a0353a 460 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
tushki7 0:60d829a0353a 461 uint32_t RESERVED0;
tushki7 0:60d829a0353a 462 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
tushki7 0:60d829a0353a 463 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
tushki7 0:60d829a0353a 464 } LPC_WDT_TypeDef;
tushki7 0:60d829a0353a 465 /*@}*/ /* end of group LPC11xx_WDT */
tushki7 0:60d829a0353a 466
tushki7 0:60d829a0353a 467
tushki7 0:60d829a0353a 468 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
tushki7 0:60d829a0353a 469 /** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter
tushki7 0:60d829a0353a 470 @{
tushki7 0:60d829a0353a 471 */
tushki7 0:60d829a0353a 472 typedef struct
tushki7 0:60d829a0353a 473 {
tushki7 0:60d829a0353a 474 __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
tushki7 0:60d829a0353a 475 __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
tushki7 0:60d829a0353a 476 uint32_t RESERVED0;
tushki7 0:60d829a0353a 477 __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
tushki7 0:60d829a0353a 478 __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
tushki7 0:60d829a0353a 479 __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
tushki7 0:60d829a0353a 480 } LPC_ADC_TypeDef;
tushki7 0:60d829a0353a 481 /*@}*/ /* end of group LPC11xx_ADC */
tushki7 0:60d829a0353a 482
tushki7 0:60d829a0353a 483
tushki7 0:60d829a0353a 484 /*------------- CAN Controller (CAN) ----------------------------*/
tushki7 0:60d829a0353a 485 /** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN)
tushki7 0:60d829a0353a 486 @{
tushki7 0:60d829a0353a 487 */
tushki7 0:60d829a0353a 488 typedef struct
tushki7 0:60d829a0353a 489 {
tushki7 0:60d829a0353a 490 __IO uint32_t CNTL; /* 0x000 */
tushki7 0:60d829a0353a 491 __IO uint32_t STAT;
tushki7 0:60d829a0353a 492 __IO uint32_t EC;
tushki7 0:60d829a0353a 493 __IO uint32_t BT;
tushki7 0:60d829a0353a 494 __IO uint32_t INT;
tushki7 0:60d829a0353a 495 __IO uint32_t TEST;
tushki7 0:60d829a0353a 496 __IO uint32_t BRPE;
tushki7 0:60d829a0353a 497 uint32_t RESERVED0;
tushki7 0:60d829a0353a 498 __IO uint32_t IF1_CMDREQ; /* 0x020 */
tushki7 0:60d829a0353a 499 __IO uint32_t IF1_CMDMSK;
tushki7 0:60d829a0353a 500 __IO uint32_t IF1_MSK1;
tushki7 0:60d829a0353a 501 __IO uint32_t IF1_MSK2;
tushki7 0:60d829a0353a 502 __IO uint32_t IF1_ARB1;
tushki7 0:60d829a0353a 503 __IO uint32_t IF1_ARB2;
tushki7 0:60d829a0353a 504 __IO uint32_t IF1_MCTRL;
tushki7 0:60d829a0353a 505 __IO uint32_t IF1_DA1;
tushki7 0:60d829a0353a 506 __IO uint32_t IF1_DA2;
tushki7 0:60d829a0353a 507 __IO uint32_t IF1_DB1;
tushki7 0:60d829a0353a 508 __IO uint32_t IF1_DB2;
tushki7 0:60d829a0353a 509 uint32_t RESERVED1[13];
tushki7 0:60d829a0353a 510 __IO uint32_t IF2_CMDREQ; /* 0x080 */
tushki7 0:60d829a0353a 511 __IO uint32_t IF2_CMDMSK;
tushki7 0:60d829a0353a 512 __IO uint32_t IF2_MSK1;
tushki7 0:60d829a0353a 513 __IO uint32_t IF2_MSK2;
tushki7 0:60d829a0353a 514 __IO uint32_t IF2_ARB1;
tushki7 0:60d829a0353a 515 __IO uint32_t IF2_ARB2;
tushki7 0:60d829a0353a 516 __IO uint32_t IF2_MCTRL;
tushki7 0:60d829a0353a 517 __IO uint32_t IF2_DA1;
tushki7 0:60d829a0353a 518 __IO uint32_t IF2_DA2;
tushki7 0:60d829a0353a 519 __IO uint32_t IF2_DB1;
tushki7 0:60d829a0353a 520 __IO uint32_t IF2_DB2;
tushki7 0:60d829a0353a 521 uint32_t RESERVED2[21];
tushki7 0:60d829a0353a 522 __I uint32_t TXREQ1; /* 0x100 */
tushki7 0:60d829a0353a 523 __I uint32_t TXREQ2;
tushki7 0:60d829a0353a 524 uint32_t RESERVED3[6];
tushki7 0:60d829a0353a 525 __I uint32_t ND1; /* 0x120 */
tushki7 0:60d829a0353a 526 __I uint32_t ND2;
tushki7 0:60d829a0353a 527 uint32_t RESERVED4[6];
tushki7 0:60d829a0353a 528 __I uint32_t IR1; /* 0x140 */
tushki7 0:60d829a0353a 529 __I uint32_t IR2;
tushki7 0:60d829a0353a 530 uint32_t RESERVED5[6];
tushki7 0:60d829a0353a 531 __I uint32_t MSGV1; /* 0x160 */
tushki7 0:60d829a0353a 532 __I uint32_t MSGV2;
tushki7 0:60d829a0353a 533 uint32_t RESERVED6[6];
tushki7 0:60d829a0353a 534 __IO uint32_t CLKDIV; /* 0x180 */
tushki7 0:60d829a0353a 535 } LPC_CAN_TypeDef;
tushki7 0:60d829a0353a 536 /*@}*/ /* end of group LPC11xx_CAN */
tushki7 0:60d829a0353a 537
tushki7 0:60d829a0353a 538 #if defined ( __CC_ARM )
tushki7 0:60d829a0353a 539 #pragma no_anon_unions
tushki7 0:60d829a0353a 540 #endif
tushki7 0:60d829a0353a 541
tushki7 0:60d829a0353a 542 /******************************************************************************/
tushki7 0:60d829a0353a 543 /* Peripheral memory map */
tushki7 0:60d829a0353a 544 /******************************************************************************/
tushki7 0:60d829a0353a 545 /* Base addresses */
tushki7 0:60d829a0353a 546 #define LPC_FLASH_BASE (0x00000000UL)
tushki7 0:60d829a0353a 547 #define LPC_RAM_BASE (0x10000000UL)
tushki7 0:60d829a0353a 548 #define LPC_APB0_BASE (0x40000000UL)
tushki7 0:60d829a0353a 549 #define LPC_AHB_BASE (0x50000000UL)
tushki7 0:60d829a0353a 550
tushki7 0:60d829a0353a 551 /* APB0 peripherals */
tushki7 0:60d829a0353a 552 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
tushki7 0:60d829a0353a 553 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
tushki7 0:60d829a0353a 554 #define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
tushki7 0:60d829a0353a 555 #define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
tushki7 0:60d829a0353a 556 #define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
tushki7 0:60d829a0353a 557 #define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
tushki7 0:60d829a0353a 558 #define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
tushki7 0:60d829a0353a 559 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
tushki7 0:60d829a0353a 560 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
tushki7 0:60d829a0353a 561 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x3C000)
tushki7 0:60d829a0353a 562 #define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000)
tushki7 0:60d829a0353a 563 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
tushki7 0:60d829a0353a 564 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
tushki7 0:60d829a0353a 565 #define LPC_CAN_BASE (LPC_APB0_BASE + 0x50000)
tushki7 0:60d829a0353a 566 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000)
tushki7 0:60d829a0353a 567
tushki7 0:60d829a0353a 568 /* AHB peripherals */
tushki7 0:60d829a0353a 569 #define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
tushki7 0:60d829a0353a 570 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
tushki7 0:60d829a0353a 571 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
tushki7 0:60d829a0353a 572 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
tushki7 0:60d829a0353a 573 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
tushki7 0:60d829a0353a 574
tushki7 0:60d829a0353a 575 /******************************************************************************/
tushki7 0:60d829a0353a 576 /* Peripheral declaration */
tushki7 0:60d829a0353a 577 /******************************************************************************/
tushki7 0:60d829a0353a 578 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
tushki7 0:60d829a0353a 579 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
tushki7 0:60d829a0353a 580 #define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
tushki7 0:60d829a0353a 581 #define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
tushki7 0:60d829a0353a 582 #define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
tushki7 0:60d829a0353a 583 #define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
tushki7 0:60d829a0353a 584 #define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
tushki7 0:60d829a0353a 585 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
tushki7 0:60d829a0353a 586 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
tushki7 0:60d829a0353a 587 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
tushki7 0:60d829a0353a 588 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
tushki7 0:60d829a0353a 589 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
tushki7 0:60d829a0353a 590 #define LPC_CAN ((LPC_CAN_TypeDef *) LPC_CAN_BASE )
tushki7 0:60d829a0353a 591 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
tushki7 0:60d829a0353a 592 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
tushki7 0:60d829a0353a 593 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
tushki7 0:60d829a0353a 594 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
tushki7 0:60d829a0353a 595 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
tushki7 0:60d829a0353a 596 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
tushki7 0:60d829a0353a 597
tushki7 0:60d829a0353a 598 #ifdef __cplusplus
tushki7 0:60d829a0353a 599 }
tushki7 0:60d829a0353a 600 #endif
tushki7 0:60d829a0353a 601
tushki7 0:60d829a0353a 602 #endif /* __LPC11xx_H__ */