Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_KL43Z/system_MKL43Z4.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a 
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /*
tushki7 0:60d829a0353a 2 ** ###################################################################
tushki7 0:60d829a0353a 3 ** Processors: MKL43Z256VLH4
tushki7 0:60d829a0353a 4 ** MKL43Z128VLH4
tushki7 0:60d829a0353a 5 ** MKL43Z64VLH4
tushki7 0:60d829a0353a 6 ** MKL43Z256VMP4
tushki7 0:60d829a0353a 7 ** MKL43Z128VMP4
tushki7 0:60d829a0353a 8 ** MKL43Z64VMP4
tushki7 0:60d829a0353a 9 **
tushki7 0:60d829a0353a 10 ** Compilers: Keil ARM C/C++ Compiler
tushki7 0:60d829a0353a 11 ** Freescale C/C++ for Embedded ARM
tushki7 0:60d829a0353a 12 ** GNU C Compiler
tushki7 0:60d829a0353a 13 ** GNU C Compiler - CodeSourcery Sourcery G++
tushki7 0:60d829a0353a 14 ** IAR ANSI C/C++ Compiler for ARM
tushki7 0:60d829a0353a 15 **
tushki7 0:60d829a0353a 16 ** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
tushki7 0:60d829a0353a 17 ** Version: rev. 1.4, 2014-09-01
tushki7 0:60d829a0353a 18 ** Build: b140904
tushki7 0:60d829a0353a 19 **
tushki7 0:60d829a0353a 20 ** Abstract:
tushki7 0:60d829a0353a 21 ** Provides a system configuration function and a global variable that
tushki7 0:60d829a0353a 22 ** contains the system frequency. It configures the device and initializes
tushki7 0:60d829a0353a 23 ** the oscillator (PLL) that is part of the microcontroller device.
tushki7 0:60d829a0353a 24 **
tushki7 0:60d829a0353a 25 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
tushki7 0:60d829a0353a 26 ** All rights reserved.
tushki7 0:60d829a0353a 27 **
tushki7 0:60d829a0353a 28 ** Redistribution and use in source and binary forms, with or without modification,
tushki7 0:60d829a0353a 29 ** are permitted provided that the following conditions are met:
tushki7 0:60d829a0353a 30 **
tushki7 0:60d829a0353a 31 ** o Redistributions of source code must retain the above copyright notice, this list
tushki7 0:60d829a0353a 32 ** of conditions and the following disclaimer.
tushki7 0:60d829a0353a 33 **
tushki7 0:60d829a0353a 34 ** o Redistributions in binary form must reproduce the above copyright notice, this
tushki7 0:60d829a0353a 35 ** list of conditions and the following disclaimer in the documentation and/or
tushki7 0:60d829a0353a 36 ** other materials provided with the distribution.
tushki7 0:60d829a0353a 37 **
tushki7 0:60d829a0353a 38 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
tushki7 0:60d829a0353a 39 ** contributors may be used to endorse or promote products derived from this
tushki7 0:60d829a0353a 40 ** software without specific prior written permission.
tushki7 0:60d829a0353a 41 **
tushki7 0:60d829a0353a 42 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
tushki7 0:60d829a0353a 43 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
tushki7 0:60d829a0353a 44 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
tushki7 0:60d829a0353a 45 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
tushki7 0:60d829a0353a 46 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
tushki7 0:60d829a0353a 47 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
tushki7 0:60d829a0353a 48 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
tushki7 0:60d829a0353a 49 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
tushki7 0:60d829a0353a 50 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
tushki7 0:60d829a0353a 51 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
tushki7 0:60d829a0353a 52 **
tushki7 0:60d829a0353a 53 ** http: www.freescale.com
tushki7 0:60d829a0353a 54 ** mail: support@freescale.com
tushki7 0:60d829a0353a 55 **
tushki7 0:60d829a0353a 56 ** Revisions:
tushki7 0:60d829a0353a 57 ** - rev. 1.0 (2014-03-27)
tushki7 0:60d829a0353a 58 ** Initial version.
tushki7 0:60d829a0353a 59 ** - rev. 1.1 (2014-05-26)
tushki7 0:60d829a0353a 60 ** I2S registers TCR2/RCR2 and others were changed.
tushki7 0:60d829a0353a 61 ** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
tushki7 0:60d829a0353a 62 ** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
tushki7 0:60d829a0353a 63 ** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
tushki7 0:60d829a0353a 64 ** Clock configuration for high range external oscillator has been added.
tushki7 0:60d829a0353a 65 ** RFSYS module access has been added.
tushki7 0:60d829a0353a 66 ** - rev. 1.2 (2014-07-10)
tushki7 0:60d829a0353a 67 ** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
tushki7 0:60d829a0353a 68 ** UART0 - UART0 module renamed to UART2.
tushki7 0:60d829a0353a 69 ** I2S - removed MDR register.
tushki7 0:60d829a0353a 70 ** - rev. 1.3 (2014-08-21)
tushki7 0:60d829a0353a 71 ** UART2 - Removed ED register.
tushki7 0:60d829a0353a 72 ** UART2 - Removed MODEM register.
tushki7 0:60d829a0353a 73 ** UART2 - Removed IR register.
tushki7 0:60d829a0353a 74 ** UART2 - Removed PFIFO register.
tushki7 0:60d829a0353a 75 ** UART2 - Removed CFIFO register.
tushki7 0:60d829a0353a 76 ** UART2 - Removed SFIFO register.
tushki7 0:60d829a0353a 77 ** UART2 - Removed TWFIFO register.
tushki7 0:60d829a0353a 78 ** UART2 - Removed TCFIFO register.
tushki7 0:60d829a0353a 79 ** UART2 - Removed RWFIFO register.
tushki7 0:60d829a0353a 80 ** UART2 - Removed RCFIFO register.
tushki7 0:60d829a0353a 81 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
tushki7 0:60d829a0353a 82 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
tushki7 0:60d829a0353a 83 ** SIM - Removed bitfield DIEID in SDID register.
tushki7 0:60d829a0353a 84 ** - rev. 1.4 (2014-09-01)
tushki7 0:60d829a0353a 85 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
tushki7 0:60d829a0353a 86 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
tushki7 0:60d829a0353a 87 **
tushki7 0:60d829a0353a 88 ** ###################################################################
tushki7 0:60d829a0353a 89 */
tushki7 0:60d829a0353a 90
tushki7 0:60d829a0353a 91 /*!
tushki7 0:60d829a0353a 92 * @file MKL43Z4
tushki7 0:60d829a0353a 93 * @version 1.4
tushki7 0:60d829a0353a 94 * @date 2014-09-01
tushki7 0:60d829a0353a 95 * @brief Device specific configuration file for MKL43Z4 (header file)
tushki7 0:60d829a0353a 96 *
tushki7 0:60d829a0353a 97 * Provides a system configuration function and a global variable that contains
tushki7 0:60d829a0353a 98 * the system frequency. It configures the device and initializes the oscillator
tushki7 0:60d829a0353a 99 * (PLL) that is part of the microcontroller device.
tushki7 0:60d829a0353a 100 */
tushki7 0:60d829a0353a 101
tushki7 0:60d829a0353a 102 #ifndef SYSTEM_MKL43Z4_H_
tushki7 0:60d829a0353a 103 #define SYSTEM_MKL43Z4_H_ /**< Symbol preventing repeated inclusion */
tushki7 0:60d829a0353a 104
tushki7 0:60d829a0353a 105 #ifdef __cplusplus
tushki7 0:60d829a0353a 106 extern "C" {
tushki7 0:60d829a0353a 107 #endif
tushki7 0:60d829a0353a 108
tushki7 0:60d829a0353a 109 #include <stdint.h>
tushki7 0:60d829a0353a 110
tushki7 0:60d829a0353a 111
tushki7 0:60d829a0353a 112 #ifndef DISABLE_WDOG
tushki7 0:60d829a0353a 113 #define DISABLE_WDOG 1
tushki7 0:60d829a0353a 114 #endif
tushki7 0:60d829a0353a 115
tushki7 0:60d829a0353a 116 #define ACK_ISOLATION 1
tushki7 0:60d829a0353a 117
tushki7 0:60d829a0353a 118 #ifndef CLOCK_SETUP
tushki7 0:60d829a0353a 119 #define CLOCK_SETUP 1
tushki7 0:60d829a0353a 120 #endif
tushki7 0:60d829a0353a 121
tushki7 0:60d829a0353a 122 /* MCG_Lite mode constants */
tushki7 0:60d829a0353a 123
tushki7 0:60d829a0353a 124 #define MCG_MODE_LIRC_8M 0U
tushki7 0:60d829a0353a 125 #define MCG_MODE_HIRC 1U
tushki7 0:60d829a0353a 126 #define MCG_MODE_LIRC_2M 2U
tushki7 0:60d829a0353a 127 #define MCG_MODE_EXT 3U
tushki7 0:60d829a0353a 128
tushki7 0:60d829a0353a 129 /* Predefined clock setups
tushki7 0:60d829a0353a 130 0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode
tushki7 0:60d829a0353a 131 Default part configuration.
tushki7 0:60d829a0353a 132 Core clock/Bus clock derived from the internal clock source 8 MHz
tushki7 0:60d829a0353a 133 Core clock = 4MHz, BusClock = 2MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
tushki7 0:60d829a0353a 134 1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
tushki7 0:60d829a0353a 135 Maximum achievable clock frequency configuration using internal clock.
tushki7 0:60d829a0353a 136 Core clock/Bus clock derived from the internal clock source 48MHz
tushki7 0:60d829a0353a 137 Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
tushki7 0:60d829a0353a 138 2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
tushki7 0:60d829a0353a 139 Core clock/Bus clock derived directly from the external crystal 32.768kHz
tushki7 0:60d829a0353a 140 The clock settings is ready for Very Low Power Run mode.
tushki7 0:60d829a0353a 141 Core clock = 32.768kHz, BusClock = 32.768kHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
tushki7 0:60d829a0353a 142 3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode
tushki7 0:60d829a0353a 143 Core clock/Bus clock derived from the internal clock source 2 MHz
tushki7 0:60d829a0353a 144 The clock settings is ready for Very Low Power Run mode.
tushki7 0:60d829a0353a 145 Core clock = 2MHz, BusClock = 1MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
tushki7 0:60d829a0353a 146 4 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
tushki7 0:60d829a0353a 147 USB clock setup - for USB to receive internal 48MHz clock derived from HIRC.
tushki7 0:60d829a0353a 148 Core clock/Bus clock derived from the internal clock source 48MHz
tushki7 0:60d829a0353a 149 Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from HIRC (MCGPCLK)
tushki7 0:60d829a0353a 150 5 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
tushki7 0:60d829a0353a 151 Core clock/Bus clock derived directly from the external crystal 8 MHz
tushki7 0:60d829a0353a 152 Core clock = 8MHz, BusClock = 4MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
tushki7 0:60d829a0353a 153 */
tushki7 0:60d829a0353a 154
tushki7 0:60d829a0353a 155 /* Define clock source values */
tushki7 0:60d829a0353a 156
tushki7 0:60d829a0353a 157 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 158 #define CPU_INT_FAST_CLK_HZ 48000000u /* Value of the fast internal oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 159 #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 160
tushki7 0:60d829a0353a 161 /* Low power mode enable */
tushki7 0:60d829a0353a 162 /* SMC_PMPROT: AVLP=1,AVLLS=1 */
tushki7 0:60d829a0353a 163 #define SMC_PMPROT_VALUE 0x22u /* SMC_PMPROT */
tushki7 0:60d829a0353a 164
tushki7 0:60d829a0353a 165 #if (CLOCK_SETUP == 0)
tushki7 0:60d829a0353a 166 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
tushki7 0:60d829a0353a 167 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 168 #define MCG_MODE MCG_MODE_LIRC_8M /* Clock generator mode */
tushki7 0:60d829a0353a 169 /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
tushki7 0:60d829a0353a 170 #define MCG_C1_VALUE 0x42u /* MCG_C1 */
tushki7 0:60d829a0353a 171 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
tushki7 0:60d829a0353a 172 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
tushki7 0:60d829a0353a 173 /* MCG_SC: FCRDIV=0 */
tushki7 0:60d829a0353a 174 #define MCG_SC_VALUE 0x00u /* MCG_SC */
tushki7 0:60d829a0353a 175 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
tushki7 0:60d829a0353a 176 #define MCG_MC_VALUE 0x00u /* MCG_MC */
tushki7 0:60d829a0353a 177 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
tushki7 0:60d829a0353a 178 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
tushki7 0:60d829a0353a 179 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
tushki7 0:60d829a0353a 180 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
tushki7 0:60d829a0353a 181 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
tushki7 0:60d829a0353a 182 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000u /* SIM_CLKDIV1 */
tushki7 0:60d829a0353a 183 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
tushki7 0:60d829a0353a 184 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
tushki7 0:60d829a0353a 185 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
tushki7 0:60d829a0353a 186 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
tushki7 0:60d829a0353a 187 #elif (CLOCK_SETUP == 1)
tushki7 0:60d829a0353a 188 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
tushki7 0:60d829a0353a 189 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 190 #define MCG_MODE MCG_MODE_HIRC /* Clock generator mode */
tushki7 0:60d829a0353a 191 /* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
tushki7 0:60d829a0353a 192 #define MCG_C1_VALUE 0x00u /* MCG_C1 */
tushki7 0:60d829a0353a 193 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
tushki7 0:60d829a0353a 194 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
tushki7 0:60d829a0353a 195 /* MCG_SC: FCRDIV=0 */
tushki7 0:60d829a0353a 196 #define MCG_SC_VALUE 0x00u /* MCG_SC */
tushki7 0:60d829a0353a 197 /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
tushki7 0:60d829a0353a 198 #define MCG_MC_VALUE 0x80u /* MCG_MC */
tushki7 0:60d829a0353a 199 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
tushki7 0:60d829a0353a 200 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
tushki7 0:60d829a0353a 201 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
tushki7 0:60d829a0353a 202 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
tushki7 0:60d829a0353a 203 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
tushki7 0:60d829a0353a 204 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
tushki7 0:60d829a0353a 205 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
tushki7 0:60d829a0353a 206 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
tushki7 0:60d829a0353a 207 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
tushki7 0:60d829a0353a 208 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000U /* SIM_SOPT2 */
tushki7 0:60d829a0353a 209 #elif (CLOCK_SETUP == 2)
tushki7 0:60d829a0353a 210 #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
tushki7 0:60d829a0353a 211 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 212 #define MCG_MODE MCG_MODE_EXT /* Clock generator mode */
tushki7 0:60d829a0353a 213 /* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */
tushki7 0:60d829a0353a 214 #define MCG_C1_VALUE 0x82u /* MCG_C1 */
tushki7 0:60d829a0353a 215 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */
tushki7 0:60d829a0353a 216 #define MCG_C2_VALUE 0x05u /* MCG_C2 */
tushki7 0:60d829a0353a 217 /* MCG_SC: FCRDIV=0 */
tushki7 0:60d829a0353a 218 #define MCG_SC_VALUE 0x00u /* MCG_SC */
tushki7 0:60d829a0353a 219 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
tushki7 0:60d829a0353a 220 #define MCG_MC_VALUE 0x00u /* MCG_MC */
tushki7 0:60d829a0353a 221 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
tushki7 0:60d829a0353a 222 #define OSC0_CR_VALUE 0x80u /* OSC0_CR */
tushki7 0:60d829a0353a 223 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
tushki7 0:60d829a0353a 224 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
tushki7 0:60d829a0353a 225 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
tushki7 0:60d829a0353a 226 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00u /* SIM_CLKDIV1 */
tushki7 0:60d829a0353a 227 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
tushki7 0:60d829a0353a 228 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
tushki7 0:60d829a0353a 229 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=2,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
tushki7 0:60d829a0353a 230 #define SYSTEM_SIM_SOPT2_VALUE 0x02000000u /* SIM_SOPT2 */
tushki7 0:60d829a0353a 231 #elif (CLOCK_SETUP == 3)
tushki7 0:60d829a0353a 232 #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
tushki7 0:60d829a0353a 233 #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 234 #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
tushki7 0:60d829a0353a 235 /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
tushki7 0:60d829a0353a 236 #define MCG_C1_VALUE 0x42u /* MCG_C1 */
tushki7 0:60d829a0353a 237 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */
tushki7 0:60d829a0353a 238 #define MCG_C2_VALUE 0x00u /* MCG_C2 */
tushki7 0:60d829a0353a 239 /* MCG_SC: FCRDIV=0 */
tushki7 0:60d829a0353a 240 #define MCG_SC_VALUE 0x00u /* MCG_SC */
tushki7 0:60d829a0353a 241 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
tushki7 0:60d829a0353a 242 #define MCG_MC_VALUE 0x00u /* MCG_MC */
tushki7 0:60d829a0353a 243 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
tushki7 0:60d829a0353a 244 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
tushki7 0:60d829a0353a 245 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
tushki7 0:60d829a0353a 246 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
tushki7 0:60d829a0353a 247 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
tushki7 0:60d829a0353a 248 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
tushki7 0:60d829a0353a 249 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
tushki7 0:60d829a0353a 250 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
tushki7 0:60d829a0353a 251 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
tushki7 0:60d829a0353a 252 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
tushki7 0:60d829a0353a 253 #elif (CLOCK_SETUP == 4)
tushki7 0:60d829a0353a 254 #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
tushki7 0:60d829a0353a 255 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 256 #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
tushki7 0:60d829a0353a 257 /* MCG_C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
tushki7 0:60d829a0353a 258 #define MCG_C1_VALUE 0x02u /* MCG_C1 */
tushki7 0:60d829a0353a 259 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
tushki7 0:60d829a0353a 260 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
tushki7 0:60d829a0353a 261 /* MCG_SC: FCRDIV=0 */
tushki7 0:60d829a0353a 262 #define MCG_SC_VALUE 0x00u /* MCG_SC */
tushki7 0:60d829a0353a 263 /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
tushki7 0:60d829a0353a 264 #define MCG_MC_VALUE 0x80u /* MCG_MC */
tushki7 0:60d829a0353a 265 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
tushki7 0:60d829a0353a 266 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
tushki7 0:60d829a0353a 267 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
tushki7 0:60d829a0353a 268 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
tushki7 0:60d829a0353a 269 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
tushki7 0:60d829a0353a 270 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
tushki7 0:60d829a0353a 271 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
tushki7 0:60d829a0353a 272 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
tushki7 0:60d829a0353a 273 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
tushki7 0:60d829a0353a 274 #define SYSTEM_SIM_SOPT2_VALUE 0x03040000u /* SIM_SOPT2 */
tushki7 0:60d829a0353a 275 #elif (CLOCK_SETUP == 5)
tushki7 0:60d829a0353a 276 #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
tushki7 0:60d829a0353a 277 #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
tushki7 0:60d829a0353a 278 #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
tushki7 0:60d829a0353a 279 /* MCG_C1: CLKS=2,IRCLKEN=0,IREFSTEN=0 */
tushki7 0:60d829a0353a 280 #define MCG_C1_VALUE 0x80u /* MCG_C1 */
tushki7 0:60d829a0353a 281 /* MCG_C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */
tushki7 0:60d829a0353a 282 #define MCG_C2_VALUE 0x15u /* MCG_C2 */
tushki7 0:60d829a0353a 283 /* MCG_SC: FCRDIV=0 */
tushki7 0:60d829a0353a 284 #define MCG_SC_VALUE 0x00u /* MCG_SC */
tushki7 0:60d829a0353a 285 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
tushki7 0:60d829a0353a 286 #define MCG_MC_VALUE 0x00u /* MCG_MC */
tushki7 0:60d829a0353a 287 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
tushki7 0:60d829a0353a 288 #define OSC0_CR_VALUE 0x80u /* OSC0_CR */
tushki7 0:60d829a0353a 289 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
tushki7 0:60d829a0353a 290 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
tushki7 0:60d829a0353a 291 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
tushki7 0:60d829a0353a 292 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
tushki7 0:60d829a0353a 293 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
tushki7 0:60d829a0353a 294 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
tushki7 0:60d829a0353a 295 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
tushki7 0:60d829a0353a 296 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
tushki7 0:60d829a0353a 297 #else
tushki7 0:60d829a0353a 298 #error The selected clock setup is not supported.
tushki7 0:60d829a0353a 299 #endif /* (CLOCK_SETUP == 5) */
tushki7 0:60d829a0353a 300
tushki7 0:60d829a0353a 301
tushki7 0:60d829a0353a 302 /**
tushki7 0:60d829a0353a 303 * @brief System clock frequency (core clock)
tushki7 0:60d829a0353a 304 *
tushki7 0:60d829a0353a 305 * The system clock frequency supplied to the SysTick timer and the processor
tushki7 0:60d829a0353a 306 * core clock. This variable can be used by the user application to setup the
tushki7 0:60d829a0353a 307 * SysTick timer or configure other parameters. It may also be used by debugger to
tushki7 0:60d829a0353a 308 * query the frequency of the debug timer or configure the trace clock speed
tushki7 0:60d829a0353a 309 * SystemCoreClock is initialized with a correct predefined value.
tushki7 0:60d829a0353a 310 */
tushki7 0:60d829a0353a 311 extern uint32_t SystemCoreClock;
tushki7 0:60d829a0353a 312
tushki7 0:60d829a0353a 313 /**
tushki7 0:60d829a0353a 314 * @brief Setup the microcontroller system.
tushki7 0:60d829a0353a 315 *
tushki7 0:60d829a0353a 316 * Typically this function configures the oscillator (PLL) that is part of the
tushki7 0:60d829a0353a 317 * microcontroller device. For systems with variable clock speed it also updates
tushki7 0:60d829a0353a 318 * the variable SystemCoreClock. SystemInit is called from startup_device file.
tushki7 0:60d829a0353a 319 */
tushki7 0:60d829a0353a 320 void SystemInit (void);
tushki7 0:60d829a0353a 321
tushki7 0:60d829a0353a 322 /**
tushki7 0:60d829a0353a 323 * @brief Updates the SystemCoreClock variable.
tushki7 0:60d829a0353a 324 *
tushki7 0:60d829a0353a 325 * It must be called whenever the core clock is changed during program
tushki7 0:60d829a0353a 326 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
tushki7 0:60d829a0353a 327 * the current core clock.
tushki7 0:60d829a0353a 328 */
tushki7 0:60d829a0353a 329 void SystemCoreClockUpdate (void);
tushki7 0:60d829a0353a 330
tushki7 0:60d829a0353a 331 #ifdef __cplusplus
tushki7 0:60d829a0353a 332 }
tushki7 0:60d829a0353a 333 #endif
tushki7 0:60d829a0353a 334
tushki7 0:60d829a0353a 335 #endif /* #if !defined(SYSTEM_MKL43Z4_H_) */