Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_ARCH_GPRS/core_ca_mmu.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a 
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 ;/**************************************************************************//**
tushki7 0:60d829a0353a 2 ; * @file core_ca_mmu.h
tushki7 0:60d829a0353a 3 ; * @brief MMU Startup File for
tushki7 0:60d829a0353a 4 ; * VE_A9_MP Device Series
tushki7 0:60d829a0353a 5 ; * @version V1.01
tushki7 0:60d829a0353a 6 ; * @date 25 March 2013
tushki7 0:60d829a0353a 7 ; *
tushki7 0:60d829a0353a 8 ; * @note
tushki7 0:60d829a0353a 9 ; *
tushki7 0:60d829a0353a 10 ; ******************************************************************************/
tushki7 0:60d829a0353a 11 ;/* Copyright (c) 2012 ARM LIMITED
tushki7 0:60d829a0353a 12 ;
tushki7 0:60d829a0353a 13 ; All rights reserved.
tushki7 0:60d829a0353a 14 ; Redistribution and use in source and binary forms, with or without
tushki7 0:60d829a0353a 15 ; modification, are permitted provided that the following conditions are met:
tushki7 0:60d829a0353a 16 ; - Redistributions of source code must retain the above copyright
tushki7 0:60d829a0353a 17 ; notice, this list of conditions and the following disclaimer.
tushki7 0:60d829a0353a 18 ; - Redistributions in binary form must reproduce the above copyright
tushki7 0:60d829a0353a 19 ; notice, this list of conditions and the following disclaimer in the
tushki7 0:60d829a0353a 20 ; documentation and/or other materials provided with the distribution.
tushki7 0:60d829a0353a 21 ; - Neither the name of ARM nor the names of its contributors may be used
tushki7 0:60d829a0353a 22 ; to endorse or promote products derived from this software without
tushki7 0:60d829a0353a 23 ; specific prior written permission.
tushki7 0:60d829a0353a 24 ; *
tushki7 0:60d829a0353a 25 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
tushki7 0:60d829a0353a 26 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
tushki7 0:60d829a0353a 27 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
tushki7 0:60d829a0353a 28 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
tushki7 0:60d829a0353a 29 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
tushki7 0:60d829a0353a 30 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
tushki7 0:60d829a0353a 31 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
tushki7 0:60d829a0353a 32 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
tushki7 0:60d829a0353a 33 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
tushki7 0:60d829a0353a 34 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
tushki7 0:60d829a0353a 35 ; POSSIBILITY OF SUCH DAMAGE.
tushki7 0:60d829a0353a 36 ; ---------------------------------------------------------------------------*/
tushki7 0:60d829a0353a 37
tushki7 0:60d829a0353a 38 #ifdef __cplusplus
tushki7 0:60d829a0353a 39 extern "C" {
tushki7 0:60d829a0353a 40 #endif
tushki7 0:60d829a0353a 41
tushki7 0:60d829a0353a 42 #ifndef _MMU_FUNC_H
tushki7 0:60d829a0353a 43 #define _MMU_FUNC_H
tushki7 0:60d829a0353a 44
tushki7 0:60d829a0353a 45 #define SECTION_DESCRIPTOR (0x2)
tushki7 0:60d829a0353a 46 #define SECTION_MASK (0xFFFFFFFC)
tushki7 0:60d829a0353a 47
tushki7 0:60d829a0353a 48 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
tushki7 0:60d829a0353a 49 #define SECTION_B_SHIFT (2)
tushki7 0:60d829a0353a 50 #define SECTION_C_SHIFT (3)
tushki7 0:60d829a0353a 51 #define SECTION_TEX0_SHIFT (12)
tushki7 0:60d829a0353a 52 #define SECTION_TEX1_SHIFT (13)
tushki7 0:60d829a0353a 53 #define SECTION_TEX2_SHIFT (14)
tushki7 0:60d829a0353a 54
tushki7 0:60d829a0353a 55 #define SECTION_XN_MASK (0xFFFFFFEF)
tushki7 0:60d829a0353a 56 #define SECTION_XN_SHIFT (4)
tushki7 0:60d829a0353a 57
tushki7 0:60d829a0353a 58 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
tushki7 0:60d829a0353a 59 #define SECTION_DOMAIN_SHIFT (5)
tushki7 0:60d829a0353a 60
tushki7 0:60d829a0353a 61 #define SECTION_P_MASK (0xFFFFFDFF)
tushki7 0:60d829a0353a 62 #define SECTION_P_SHIFT (9)
tushki7 0:60d829a0353a 63
tushki7 0:60d829a0353a 64 #define SECTION_AP_MASK (0xFFFF73FF)
tushki7 0:60d829a0353a 65 #define SECTION_AP_SHIFT (10)
tushki7 0:60d829a0353a 66 #define SECTION_AP2_SHIFT (15)
tushki7 0:60d829a0353a 67
tushki7 0:60d829a0353a 68 #define SECTION_S_MASK (0xFFFEFFFF)
tushki7 0:60d829a0353a 69 #define SECTION_S_SHIFT (16)
tushki7 0:60d829a0353a 70
tushki7 0:60d829a0353a 71 #define SECTION_NG_MASK (0xFFFDFFFF)
tushki7 0:60d829a0353a 72 #define SECTION_NG_SHIFT (17)
tushki7 0:60d829a0353a 73
tushki7 0:60d829a0353a 74 #define SECTION_NS_MASK (0xFFF7FFFF)
tushki7 0:60d829a0353a 75 #define SECTION_NS_SHIFT (19)
tushki7 0:60d829a0353a 76
tushki7 0:60d829a0353a 77
tushki7 0:60d829a0353a 78 #define PAGE_L1_DESCRIPTOR (0x1)
tushki7 0:60d829a0353a 79 #define PAGE_L1_MASK (0xFFFFFFFC)
tushki7 0:60d829a0353a 80
tushki7 0:60d829a0353a 81 #define PAGE_L2_4K_DESC (0x2)
tushki7 0:60d829a0353a 82 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
tushki7 0:60d829a0353a 83
tushki7 0:60d829a0353a 84 #define PAGE_L2_64K_DESC (0x1)
tushki7 0:60d829a0353a 85 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
tushki7 0:60d829a0353a 86
tushki7 0:60d829a0353a 87 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
tushki7 0:60d829a0353a 88 #define PAGE_4K_B_SHIFT (2)
tushki7 0:60d829a0353a 89 #define PAGE_4K_C_SHIFT (3)
tushki7 0:60d829a0353a 90 #define PAGE_4K_TEX0_SHIFT (6)
tushki7 0:60d829a0353a 91 #define PAGE_4K_TEX1_SHIFT (7)
tushki7 0:60d829a0353a 92 #define PAGE_4K_TEX2_SHIFT (8)
tushki7 0:60d829a0353a 93
tushki7 0:60d829a0353a 94 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
tushki7 0:60d829a0353a 95 #define PAGE_64K_B_SHIFT (2)
tushki7 0:60d829a0353a 96 #define PAGE_64K_C_SHIFT (3)
tushki7 0:60d829a0353a 97 #define PAGE_64K_TEX0_SHIFT (12)
tushki7 0:60d829a0353a 98 #define PAGE_64K_TEX1_SHIFT (13)
tushki7 0:60d829a0353a 99 #define PAGE_64K_TEX2_SHIFT (14)
tushki7 0:60d829a0353a 100
tushki7 0:60d829a0353a 101 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
tushki7 0:60d829a0353a 102 #define PAGE_B_SHIFT (2)
tushki7 0:60d829a0353a 103 #define PAGE_C_SHIFT (3)
tushki7 0:60d829a0353a 104 #define PAGE_TEX_SHIFT (12)
tushki7 0:60d829a0353a 105
tushki7 0:60d829a0353a 106 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
tushki7 0:60d829a0353a 107 #define PAGE_XN_4K_SHIFT (0)
tushki7 0:60d829a0353a 108 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
tushki7 0:60d829a0353a 109 #define PAGE_XN_64K_SHIFT (15)
tushki7 0:60d829a0353a 110
tushki7 0:60d829a0353a 111
tushki7 0:60d829a0353a 112 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
tushki7 0:60d829a0353a 113 #define PAGE_DOMAIN_SHIFT (5)
tushki7 0:60d829a0353a 114
tushki7 0:60d829a0353a 115 #define PAGE_P_MASK (0xFFFFFDFF)
tushki7 0:60d829a0353a 116 #define PAGE_P_SHIFT (9)
tushki7 0:60d829a0353a 117
tushki7 0:60d829a0353a 118 #define PAGE_AP_MASK (0xFFFFFDCF)
tushki7 0:60d829a0353a 119 #define PAGE_AP_SHIFT (4)
tushki7 0:60d829a0353a 120 #define PAGE_AP2_SHIFT (9)
tushki7 0:60d829a0353a 121
tushki7 0:60d829a0353a 122 #define PAGE_S_MASK (0xFFFFFBFF)
tushki7 0:60d829a0353a 123 #define PAGE_S_SHIFT (10)
tushki7 0:60d829a0353a 124
tushki7 0:60d829a0353a 125 #define PAGE_NG_MASK (0xFFFFF7FF)
tushki7 0:60d829a0353a 126 #define PAGE_NG_SHIFT (11)
tushki7 0:60d829a0353a 127
tushki7 0:60d829a0353a 128 #define PAGE_NS_MASK (0xFFFFFFF7)
tushki7 0:60d829a0353a 129 #define PAGE_NS_SHIFT (3)
tushki7 0:60d829a0353a 130
tushki7 0:60d829a0353a 131 #define OFFSET_1M (0x00100000)
tushki7 0:60d829a0353a 132 #define OFFSET_64K (0x00010000)
tushki7 0:60d829a0353a 133 #define OFFSET_4K (0x00001000)
tushki7 0:60d829a0353a 134
tushki7 0:60d829a0353a 135 #define DESCRIPTOR_FAULT (0x00000000)
tushki7 0:60d829a0353a 136
tushki7 0:60d829a0353a 137 /* ########################### MMU Function Access ########################### */
tushki7 0:60d829a0353a 138 /** \ingroup MMU_FunctionInterface
tushki7 0:60d829a0353a 139 \defgroup MMU_Functions MMU Functions Interface
tushki7 0:60d829a0353a 140 @{
tushki7 0:60d829a0353a 141 */
tushki7 0:60d829a0353a 142
tushki7 0:60d829a0353a 143 /* Attributes enumerations */
tushki7 0:60d829a0353a 144
tushki7 0:60d829a0353a 145 /* Region size attributes */
tushki7 0:60d829a0353a 146 typedef enum
tushki7 0:60d829a0353a 147 {
tushki7 0:60d829a0353a 148 SECTION,
tushki7 0:60d829a0353a 149 PAGE_4k,
tushki7 0:60d829a0353a 150 PAGE_64k,
tushki7 0:60d829a0353a 151 } mmu_region_size_Type;
tushki7 0:60d829a0353a 152
tushki7 0:60d829a0353a 153 /* Region type attributes */
tushki7 0:60d829a0353a 154 typedef enum
tushki7 0:60d829a0353a 155 {
tushki7 0:60d829a0353a 156 NORMAL,
tushki7 0:60d829a0353a 157 DEVICE,
tushki7 0:60d829a0353a 158 SHARED_DEVICE,
tushki7 0:60d829a0353a 159 NON_SHARED_DEVICE,
tushki7 0:60d829a0353a 160 STRONGLY_ORDERED
tushki7 0:60d829a0353a 161 } mmu_memory_Type;
tushki7 0:60d829a0353a 162
tushki7 0:60d829a0353a 163 /* Region cacheability attributes */
tushki7 0:60d829a0353a 164 typedef enum
tushki7 0:60d829a0353a 165 {
tushki7 0:60d829a0353a 166 NON_CACHEABLE,
tushki7 0:60d829a0353a 167 WB_WA,
tushki7 0:60d829a0353a 168 WT,
tushki7 0:60d829a0353a 169 WB_NO_WA,
tushki7 0:60d829a0353a 170 } mmu_cacheability_Type;
tushki7 0:60d829a0353a 171
tushki7 0:60d829a0353a 172 /* Region parity check attributes */
tushki7 0:60d829a0353a 173 typedef enum
tushki7 0:60d829a0353a 174 {
tushki7 0:60d829a0353a 175 ECC_DISABLED,
tushki7 0:60d829a0353a 176 ECC_ENABLED,
tushki7 0:60d829a0353a 177 } mmu_ecc_check_Type;
tushki7 0:60d829a0353a 178
tushki7 0:60d829a0353a 179 /* Region execution attributes */
tushki7 0:60d829a0353a 180 typedef enum
tushki7 0:60d829a0353a 181 {
tushki7 0:60d829a0353a 182 EXECUTE,
tushki7 0:60d829a0353a 183 NON_EXECUTE,
tushki7 0:60d829a0353a 184 } mmu_execute_Type;
tushki7 0:60d829a0353a 185
tushki7 0:60d829a0353a 186 /* Region global attributes */
tushki7 0:60d829a0353a 187 typedef enum
tushki7 0:60d829a0353a 188 {
tushki7 0:60d829a0353a 189 GLOBAL,
tushki7 0:60d829a0353a 190 NON_GLOBAL,
tushki7 0:60d829a0353a 191 } mmu_global_Type;
tushki7 0:60d829a0353a 192
tushki7 0:60d829a0353a 193 /* Region shareability attributes */
tushki7 0:60d829a0353a 194 typedef enum
tushki7 0:60d829a0353a 195 {
tushki7 0:60d829a0353a 196 NON_SHARED,
tushki7 0:60d829a0353a 197 SHARED,
tushki7 0:60d829a0353a 198 } mmu_shared_Type;
tushki7 0:60d829a0353a 199
tushki7 0:60d829a0353a 200 /* Region security attributes */
tushki7 0:60d829a0353a 201 typedef enum
tushki7 0:60d829a0353a 202 {
tushki7 0:60d829a0353a 203 SECURE,
tushki7 0:60d829a0353a 204 NON_SECURE,
tushki7 0:60d829a0353a 205 } mmu_secure_Type;
tushki7 0:60d829a0353a 206
tushki7 0:60d829a0353a 207 /* Region access attributes */
tushki7 0:60d829a0353a 208 typedef enum
tushki7 0:60d829a0353a 209 {
tushki7 0:60d829a0353a 210 NO_ACCESS,
tushki7 0:60d829a0353a 211 RW,
tushki7 0:60d829a0353a 212 READ,
tushki7 0:60d829a0353a 213 } mmu_access_Type;
tushki7 0:60d829a0353a 214
tushki7 0:60d829a0353a 215 /* Memory Region definition */
tushki7 0:60d829a0353a 216 typedef struct RegionStruct {
tushki7 0:60d829a0353a 217 mmu_region_size_Type rg_t;
tushki7 0:60d829a0353a 218 mmu_memory_Type mem_t;
tushki7 0:60d829a0353a 219 uint8_t domain;
tushki7 0:60d829a0353a 220 mmu_cacheability_Type inner_norm_t;
tushki7 0:60d829a0353a 221 mmu_cacheability_Type outer_norm_t;
tushki7 0:60d829a0353a 222 mmu_ecc_check_Type e_t;
tushki7 0:60d829a0353a 223 mmu_execute_Type xn_t;
tushki7 0:60d829a0353a 224 mmu_global_Type g_t;
tushki7 0:60d829a0353a 225 mmu_secure_Type sec_t;
tushki7 0:60d829a0353a 226 mmu_access_Type priv_t;
tushki7 0:60d829a0353a 227 mmu_access_Type user_t;
tushki7 0:60d829a0353a 228 mmu_shared_Type sh_t;
tushki7 0:60d829a0353a 229
tushki7 0:60d829a0353a 230 } mmu_region_attributes_Type;
tushki7 0:60d829a0353a 231
tushki7 0:60d829a0353a 232 /** \brief Set section execution-never attribute
tushki7 0:60d829a0353a 233
tushki7 0:60d829a0353a 234 The function sets section execution-never attribute
tushki7 0:60d829a0353a 235
tushki7 0:60d829a0353a 236 \param [out] descriptor_l1 L1 descriptor.
tushki7 0:60d829a0353a 237 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
tushki7 0:60d829a0353a 238
tushki7 0:60d829a0353a 239 \return 0
tushki7 0:60d829a0353a 240 */
tushki7 0:60d829a0353a 241 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
tushki7 0:60d829a0353a 242 {
tushki7 0:60d829a0353a 243 *descriptor_l1 &= SECTION_XN_MASK;
tushki7 0:60d829a0353a 244 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
tushki7 0:60d829a0353a 245 return 0;
tushki7 0:60d829a0353a 246 }
tushki7 0:60d829a0353a 247
tushki7 0:60d829a0353a 248 /** \brief Set section domain
tushki7 0:60d829a0353a 249
tushki7 0:60d829a0353a 250 The function sets section domain
tushki7 0:60d829a0353a 251
tushki7 0:60d829a0353a 252 \param [out] descriptor_l1 L1 descriptor.
tushki7 0:60d829a0353a 253 \param [in] domain Section domain
tushki7 0:60d829a0353a 254
tushki7 0:60d829a0353a 255 \return 0
tushki7 0:60d829a0353a 256 */
tushki7 0:60d829a0353a 257 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
tushki7 0:60d829a0353a 258 {
tushki7 0:60d829a0353a 259 *descriptor_l1 &= SECTION_DOMAIN_MASK;
tushki7 0:60d829a0353a 260 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
tushki7 0:60d829a0353a 261 return 0;
tushki7 0:60d829a0353a 262 }
tushki7 0:60d829a0353a 263
tushki7 0:60d829a0353a 264 /** \brief Set section parity check
tushki7 0:60d829a0353a 265
tushki7 0:60d829a0353a 266 The function sets section parity check
tushki7 0:60d829a0353a 267
tushki7 0:60d829a0353a 268 \param [out] descriptor_l1 L1 descriptor.
tushki7 0:60d829a0353a 269 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
tushki7 0:60d829a0353a 270
tushki7 0:60d829a0353a 271 \return 0
tushki7 0:60d829a0353a 272 */
tushki7 0:60d829a0353a 273 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
tushki7 0:60d829a0353a 274 {
tushki7 0:60d829a0353a 275 *descriptor_l1 &= SECTION_P_MASK;
tushki7 0:60d829a0353a 276 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
tushki7 0:60d829a0353a 277 return 0;
tushki7 0:60d829a0353a 278 }
tushki7 0:60d829a0353a 279
tushki7 0:60d829a0353a 280 /** \brief Set section access privileges
tushki7 0:60d829a0353a 281
tushki7 0:60d829a0353a 282 The function sets section access privileges
tushki7 0:60d829a0353a 283
tushki7 0:60d829a0353a 284 \param [out] descriptor_l1 L1 descriptor.
tushki7 0:60d829a0353a 285 \param [in] user User Level Access: NO_ACCESS, RW, READ
tushki7 0:60d829a0353a 286 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
tushki7 0:60d829a0353a 287 \param [in] afe Access flag enable
tushki7 0:60d829a0353a 288
tushki7 0:60d829a0353a 289 \return 0
tushki7 0:60d829a0353a 290 */
tushki7 0:60d829a0353a 291 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
tushki7 0:60d829a0353a 292 {
tushki7 0:60d829a0353a 293 uint32_t ap = 0;
tushki7 0:60d829a0353a 294
tushki7 0:60d829a0353a 295 if (afe == 0) { //full access
tushki7 0:60d829a0353a 296 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
tushki7 0:60d829a0353a 297 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
tushki7 0:60d829a0353a 298 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
tushki7 0:60d829a0353a 299 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
tushki7 0:60d829a0353a 300 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
tushki7 0:60d829a0353a 301 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
tushki7 0:60d829a0353a 302 }
tushki7 0:60d829a0353a 303
tushki7 0:60d829a0353a 304 else { //Simplified access
tushki7 0:60d829a0353a 305 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
tushki7 0:60d829a0353a 306 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
tushki7 0:60d829a0353a 307 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
tushki7 0:60d829a0353a 308 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
tushki7 0:60d829a0353a 309 }
tushki7 0:60d829a0353a 310
tushki7 0:60d829a0353a 311 *descriptor_l1 &= SECTION_AP_MASK;
tushki7 0:60d829a0353a 312 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
tushki7 0:60d829a0353a 313 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
tushki7 0:60d829a0353a 314
tushki7 0:60d829a0353a 315 return 0;
tushki7 0:60d829a0353a 316 }
tushki7 0:60d829a0353a 317
tushki7 0:60d829a0353a 318 /** \brief Set section shareability
tushki7 0:60d829a0353a 319
tushki7 0:60d829a0353a 320 The function sets section shareability
tushki7 0:60d829a0353a 321
tushki7 0:60d829a0353a 322 \param [out] descriptor_l1 L1 descriptor.
tushki7 0:60d829a0353a 323 \param [in] s_bit Section shareability: NON_SHARED, SHARED
tushki7 0:60d829a0353a 324
tushki7 0:60d829a0353a 325 \return 0
tushki7 0:60d829a0353a 326 */
tushki7 0:60d829a0353a 327 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
tushki7 0:60d829a0353a 328 {
tushki7 0:60d829a0353a 329 *descriptor_l1 &= SECTION_S_MASK;
tushki7 0:60d829a0353a 330 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
tushki7 0:60d829a0353a 331 return 0;
tushki7 0:60d829a0353a 332 }
tushki7 0:60d829a0353a 333
tushki7 0:60d829a0353a 334 /** \brief Set section Global attribute
tushki7 0:60d829a0353a 335
tushki7 0:60d829a0353a 336 The function sets section Global attribute
tushki7 0:60d829a0353a 337
tushki7 0:60d829a0353a 338 \param [out] descriptor_l1 L1 descriptor.
tushki7 0:60d829a0353a 339 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
tushki7 0:60d829a0353a 340
tushki7 0:60d829a0353a 341 \return 0
tushki7 0:60d829a0353a 342 */
tushki7 0:60d829a0353a 343 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
tushki7 0:60d829a0353a 344 {
tushki7 0:60d829a0353a 345 *descriptor_l1 &= SECTION_NG_MASK;
tushki7 0:60d829a0353a 346 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
tushki7 0:60d829a0353a 347 return 0;
tushki7 0:60d829a0353a 348 }
tushki7 0:60d829a0353a 349
tushki7 0:60d829a0353a 350 /** \brief Set section Security attribute
tushki7 0:60d829a0353a 351
tushki7 0:60d829a0353a 352 The function sets section Global attribute
tushki7 0:60d829a0353a 353
tushki7 0:60d829a0353a 354 \param [out] descriptor_l1 L1 descriptor.
tushki7 0:60d829a0353a 355 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
tushki7 0:60d829a0353a 356
tushki7 0:60d829a0353a 357 \return 0
tushki7 0:60d829a0353a 358 */
tushki7 0:60d829a0353a 359 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
tushki7 0:60d829a0353a 360 {
tushki7 0:60d829a0353a 361 *descriptor_l1 &= SECTION_NS_MASK;
tushki7 0:60d829a0353a 362 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
tushki7 0:60d829a0353a 363 return 0;
tushki7 0:60d829a0353a 364 }
tushki7 0:60d829a0353a 365
tushki7 0:60d829a0353a 366 /* Page 4k or 64k */
tushki7 0:60d829a0353a 367 /** \brief Set 4k/64k page execution-never attribute
tushki7 0:60d829a0353a 368
tushki7 0:60d829a0353a 369 The function sets 4k/64k page execution-never attribute
tushki7 0:60d829a0353a 370
tushki7 0:60d829a0353a 371 \param [out] descriptor_l2 L2 descriptor.
tushki7 0:60d829a0353a 372 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
tushki7 0:60d829a0353a 373 \param [in] page Page size: PAGE_4k, PAGE_64k,
tushki7 0:60d829a0353a 374
tushki7 0:60d829a0353a 375 \return 0
tushki7 0:60d829a0353a 376 */
tushki7 0:60d829a0353a 377 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
tushki7 0:60d829a0353a 378 {
tushki7 0:60d829a0353a 379 if (page == PAGE_4k)
tushki7 0:60d829a0353a 380 {
tushki7 0:60d829a0353a 381 *descriptor_l2 &= PAGE_XN_4K_MASK;
tushki7 0:60d829a0353a 382 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
tushki7 0:60d829a0353a 383 }
tushki7 0:60d829a0353a 384 else
tushki7 0:60d829a0353a 385 {
tushki7 0:60d829a0353a 386 *descriptor_l2 &= PAGE_XN_64K_MASK;
tushki7 0:60d829a0353a 387 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
tushki7 0:60d829a0353a 388 }
tushki7 0:60d829a0353a 389 return 0;
tushki7 0:60d829a0353a 390 }
tushki7 0:60d829a0353a 391
tushki7 0:60d829a0353a 392 /** \brief Set 4k/64k page domain
tushki7 0:60d829a0353a 393
tushki7 0:60d829a0353a 394 The function sets 4k/64k page domain
tushki7 0:60d829a0353a 395
tushki7 0:60d829a0353a 396 \param [out] descriptor_l1 L1 descriptor.
tushki7 0:60d829a0353a 397 \param [in] domain Page domain
tushki7 0:60d829a0353a 398
tushki7 0:60d829a0353a 399 \return 0
tushki7 0:60d829a0353a 400 */
tushki7 0:60d829a0353a 401 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
tushki7 0:60d829a0353a 402 {
tushki7 0:60d829a0353a 403 *descriptor_l1 &= PAGE_DOMAIN_MASK;
tushki7 0:60d829a0353a 404 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
tushki7 0:60d829a0353a 405 return 0;
tushki7 0:60d829a0353a 406 }
tushki7 0:60d829a0353a 407
tushki7 0:60d829a0353a 408 /** \brief Set 4k/64k page parity check
tushki7 0:60d829a0353a 409
tushki7 0:60d829a0353a 410 The function sets 4k/64k page parity check
tushki7 0:60d829a0353a 411
tushki7 0:60d829a0353a 412 \param [out] descriptor_l1 L1 descriptor.
tushki7 0:60d829a0353a 413 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
tushki7 0:60d829a0353a 414
tushki7 0:60d829a0353a 415 \return 0
tushki7 0:60d829a0353a 416 */
tushki7 0:60d829a0353a 417 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
tushki7 0:60d829a0353a 418 {
tushki7 0:60d829a0353a 419 *descriptor_l1 &= SECTION_P_MASK;
tushki7 0:60d829a0353a 420 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
tushki7 0:60d829a0353a 421 return 0;
tushki7 0:60d829a0353a 422 }
tushki7 0:60d829a0353a 423
tushki7 0:60d829a0353a 424 /** \brief Set 4k/64k page access privileges
tushki7 0:60d829a0353a 425
tushki7 0:60d829a0353a 426 The function sets 4k/64k page access privileges
tushki7 0:60d829a0353a 427
tushki7 0:60d829a0353a 428 \param [out] descriptor_l2 L2 descriptor.
tushki7 0:60d829a0353a 429 \param [in] user User Level Access: NO_ACCESS, RW, READ
tushki7 0:60d829a0353a 430 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
tushki7 0:60d829a0353a 431 \param [in] afe Access flag enable
tushki7 0:60d829a0353a 432
tushki7 0:60d829a0353a 433 \return 0
tushki7 0:60d829a0353a 434 */
tushki7 0:60d829a0353a 435 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
tushki7 0:60d829a0353a 436 {
tushki7 0:60d829a0353a 437 uint32_t ap = 0;
tushki7 0:60d829a0353a 438
tushki7 0:60d829a0353a 439 if (afe == 0) { //full access
tushki7 0:60d829a0353a 440 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
tushki7 0:60d829a0353a 441 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
tushki7 0:60d829a0353a 442 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
tushki7 0:60d829a0353a 443 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
tushki7 0:60d829a0353a 444 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
tushki7 0:60d829a0353a 445 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
tushki7 0:60d829a0353a 446 }
tushki7 0:60d829a0353a 447
tushki7 0:60d829a0353a 448 else { //Simplified access
tushki7 0:60d829a0353a 449 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
tushki7 0:60d829a0353a 450 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
tushki7 0:60d829a0353a 451 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
tushki7 0:60d829a0353a 452 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
tushki7 0:60d829a0353a 453 }
tushki7 0:60d829a0353a 454
tushki7 0:60d829a0353a 455 *descriptor_l2 &= PAGE_AP_MASK;
tushki7 0:60d829a0353a 456 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
tushki7 0:60d829a0353a 457 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
tushki7 0:60d829a0353a 458
tushki7 0:60d829a0353a 459 return 0;
tushki7 0:60d829a0353a 460 }
tushki7 0:60d829a0353a 461
tushki7 0:60d829a0353a 462 /** \brief Set 4k/64k page shareability
tushki7 0:60d829a0353a 463
tushki7 0:60d829a0353a 464 The function sets 4k/64k page shareability
tushki7 0:60d829a0353a 465
tushki7 0:60d829a0353a 466 \param [out] descriptor_l2 L2 descriptor.
tushki7 0:60d829a0353a 467 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
tushki7 0:60d829a0353a 468
tushki7 0:60d829a0353a 469 \return 0
tushki7 0:60d829a0353a 470 */
tushki7 0:60d829a0353a 471 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
tushki7 0:60d829a0353a 472 {
tushki7 0:60d829a0353a 473 *descriptor_l2 &= PAGE_S_MASK;
tushki7 0:60d829a0353a 474 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
tushki7 0:60d829a0353a 475 return 0;
tushki7 0:60d829a0353a 476 }
tushki7 0:60d829a0353a 477
tushki7 0:60d829a0353a 478 /** \brief Set 4k/64k page Global attribute
tushki7 0:60d829a0353a 479
tushki7 0:60d829a0353a 480 The function sets 4k/64k page Global attribute
tushki7 0:60d829a0353a 481
tushki7 0:60d829a0353a 482 \param [out] descriptor_l2 L2 descriptor.
tushki7 0:60d829a0353a 483 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
tushki7 0:60d829a0353a 484
tushki7 0:60d829a0353a 485 \return 0
tushki7 0:60d829a0353a 486 */
tushki7 0:60d829a0353a 487 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
tushki7 0:60d829a0353a 488 {
tushki7 0:60d829a0353a 489 *descriptor_l2 &= PAGE_NG_MASK;
tushki7 0:60d829a0353a 490 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
tushki7 0:60d829a0353a 491 return 0;
tushki7 0:60d829a0353a 492 }
tushki7 0:60d829a0353a 493
tushki7 0:60d829a0353a 494 /** \brief Set 4k/64k page Security attribute
tushki7 0:60d829a0353a 495
tushki7 0:60d829a0353a 496 The function sets 4k/64k page Global attribute
tushki7 0:60d829a0353a 497
tushki7 0:60d829a0353a 498 \param [out] descriptor_l1 L1 descriptor.
tushki7 0:60d829a0353a 499 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
tushki7 0:60d829a0353a 500
tushki7 0:60d829a0353a 501 \return 0
tushki7 0:60d829a0353a 502 */
tushki7 0:60d829a0353a 503 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
tushki7 0:60d829a0353a 504 {
tushki7 0:60d829a0353a 505 *descriptor_l1 &= PAGE_NS_MASK;
tushki7 0:60d829a0353a 506 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
tushki7 0:60d829a0353a 507 return 0;
tushki7 0:60d829a0353a 508 }
tushki7 0:60d829a0353a 509
tushki7 0:60d829a0353a 510
tushki7 0:60d829a0353a 511 /** \brief Set Section memory attributes
tushki7 0:60d829a0353a 512
tushki7 0:60d829a0353a 513 The function sets section memory attributes
tushki7 0:60d829a0353a 514
tushki7 0:60d829a0353a 515 \param [out] descriptor_l1 L1 descriptor.
tushki7 0:60d829a0353a 516 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
tushki7 0:60d829a0353a 517 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
tushki7 0:60d829a0353a 518 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
tushki7 0:60d829a0353a 519
tushki7 0:60d829a0353a 520 \return 0
tushki7 0:60d829a0353a 521 */
tushki7 0:60d829a0353a 522 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
tushki7 0:60d829a0353a 523 {
tushki7 0:60d829a0353a 524 *descriptor_l1 &= SECTION_TEXCB_MASK;
tushki7 0:60d829a0353a 525
tushki7 0:60d829a0353a 526 if (STRONGLY_ORDERED == mem)
tushki7 0:60d829a0353a 527 {
tushki7 0:60d829a0353a 528 return 0;
tushki7 0:60d829a0353a 529 }
tushki7 0:60d829a0353a 530 else if (SHARED_DEVICE == mem)
tushki7 0:60d829a0353a 531 {
tushki7 0:60d829a0353a 532 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
tushki7 0:60d829a0353a 533 }
tushki7 0:60d829a0353a 534 else if (NON_SHARED_DEVICE == mem)
tushki7 0:60d829a0353a 535 {
tushki7 0:60d829a0353a 536 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
tushki7 0:60d829a0353a 537 }
tushki7 0:60d829a0353a 538 else if (NORMAL == mem)
tushki7 0:60d829a0353a 539 {
tushki7 0:60d829a0353a 540 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
tushki7 0:60d829a0353a 541 switch(inner)
tushki7 0:60d829a0353a 542 {
tushki7 0:60d829a0353a 543 case NON_CACHEABLE:
tushki7 0:60d829a0353a 544 break;
tushki7 0:60d829a0353a 545 case WB_WA:
tushki7 0:60d829a0353a 546 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
tushki7 0:60d829a0353a 547 break;
tushki7 0:60d829a0353a 548 case WT:
tushki7 0:60d829a0353a 549 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
tushki7 0:60d829a0353a 550 break;
tushki7 0:60d829a0353a 551 case WB_NO_WA:
tushki7 0:60d829a0353a 552 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
tushki7 0:60d829a0353a 553 break;
tushki7 0:60d829a0353a 554 }
tushki7 0:60d829a0353a 555 switch(outer)
tushki7 0:60d829a0353a 556 {
tushki7 0:60d829a0353a 557 case NON_CACHEABLE:
tushki7 0:60d829a0353a 558 break;
tushki7 0:60d829a0353a 559 case WB_WA:
tushki7 0:60d829a0353a 560 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
tushki7 0:60d829a0353a 561 break;
tushki7 0:60d829a0353a 562 case WT:
tushki7 0:60d829a0353a 563 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
tushki7 0:60d829a0353a 564 break;
tushki7 0:60d829a0353a 565 case WB_NO_WA:
tushki7 0:60d829a0353a 566 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
tushki7 0:60d829a0353a 567 break;
tushki7 0:60d829a0353a 568 }
tushki7 0:60d829a0353a 569 }
tushki7 0:60d829a0353a 570
tushki7 0:60d829a0353a 571 return 0;
tushki7 0:60d829a0353a 572 }
tushki7 0:60d829a0353a 573
tushki7 0:60d829a0353a 574 /** \brief Set 4k/64k page memory attributes
tushki7 0:60d829a0353a 575
tushki7 0:60d829a0353a 576 The function sets 4k/64k page memory attributes
tushki7 0:60d829a0353a 577
tushki7 0:60d829a0353a 578 \param [out] descriptor_l2 L2 descriptor.
tushki7 0:60d829a0353a 579 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
tushki7 0:60d829a0353a 580 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
tushki7 0:60d829a0353a 581 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
tushki7 0:60d829a0353a 582
tushki7 0:60d829a0353a 583 \return 0
tushki7 0:60d829a0353a 584 */
tushki7 0:60d829a0353a 585 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
tushki7 0:60d829a0353a 586 {
tushki7 0:60d829a0353a 587 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
tushki7 0:60d829a0353a 588
tushki7 0:60d829a0353a 589 if (page == PAGE_64k)
tushki7 0:60d829a0353a 590 {
tushki7 0:60d829a0353a 591 //same as section
tushki7 0:60d829a0353a 592 __memory_section(descriptor_l2, mem, outer, inner);
tushki7 0:60d829a0353a 593 }
tushki7 0:60d829a0353a 594 else
tushki7 0:60d829a0353a 595 {
tushki7 0:60d829a0353a 596 if (STRONGLY_ORDERED == mem)
tushki7 0:60d829a0353a 597 {
tushki7 0:60d829a0353a 598 return 0;
tushki7 0:60d829a0353a 599 }
tushki7 0:60d829a0353a 600 else if (SHARED_DEVICE == mem)
tushki7 0:60d829a0353a 601 {
tushki7 0:60d829a0353a 602 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
tushki7 0:60d829a0353a 603 }
tushki7 0:60d829a0353a 604 else if (NON_SHARED_DEVICE == mem)
tushki7 0:60d829a0353a 605 {
tushki7 0:60d829a0353a 606 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
tushki7 0:60d829a0353a 607 }
tushki7 0:60d829a0353a 608 else if (NORMAL == mem)
tushki7 0:60d829a0353a 609 {
tushki7 0:60d829a0353a 610 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
tushki7 0:60d829a0353a 611 switch(inner)
tushki7 0:60d829a0353a 612 {
tushki7 0:60d829a0353a 613 case NON_CACHEABLE:
tushki7 0:60d829a0353a 614 break;
tushki7 0:60d829a0353a 615 case WB_WA:
tushki7 0:60d829a0353a 616 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
tushki7 0:60d829a0353a 617 break;
tushki7 0:60d829a0353a 618 case WT:
tushki7 0:60d829a0353a 619 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
tushki7 0:60d829a0353a 620 break;
tushki7 0:60d829a0353a 621 case WB_NO_WA:
tushki7 0:60d829a0353a 622 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
tushki7 0:60d829a0353a 623 break;
tushki7 0:60d829a0353a 624 }
tushki7 0:60d829a0353a 625 switch(outer)
tushki7 0:60d829a0353a 626 {
tushki7 0:60d829a0353a 627 case NON_CACHEABLE:
tushki7 0:60d829a0353a 628 break;
tushki7 0:60d829a0353a 629 case WB_WA:
tushki7 0:60d829a0353a 630 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
tushki7 0:60d829a0353a 631 break;
tushki7 0:60d829a0353a 632 case WT:
tushki7 0:60d829a0353a 633 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
tushki7 0:60d829a0353a 634 break;
tushki7 0:60d829a0353a 635 case WB_NO_WA:
tushki7 0:60d829a0353a 636 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
tushki7 0:60d829a0353a 637 break;
tushki7 0:60d829a0353a 638 }
tushki7 0:60d829a0353a 639 }
tushki7 0:60d829a0353a 640 }
tushki7 0:60d829a0353a 641
tushki7 0:60d829a0353a 642 return 0;
tushki7 0:60d829a0353a 643 }
tushki7 0:60d829a0353a 644
tushki7 0:60d829a0353a 645 /** \brief Create a L1 section descriptor
tushki7 0:60d829a0353a 646
tushki7 0:60d829a0353a 647 The function creates a section descriptor.
tushki7 0:60d829a0353a 648
tushki7 0:60d829a0353a 649 Assumptions:
tushki7 0:60d829a0353a 650 - 16MB super sections not suported
tushki7 0:60d829a0353a 651 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
tushki7 0:60d829a0353a 652 - Functions always return 0
tushki7 0:60d829a0353a 653
tushki7 0:60d829a0353a 654 \param [out] descriptor L1 descriptor
tushki7 0:60d829a0353a 655 \param [out] descriptor2 L2 descriptor
tushki7 0:60d829a0353a 656 \param [in] reg Section attributes
tushki7 0:60d829a0353a 657
tushki7 0:60d829a0353a 658 \return 0
tushki7 0:60d829a0353a 659 */
tushki7 0:60d829a0353a 660 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
tushki7 0:60d829a0353a 661 {
tushki7 0:60d829a0353a 662 *descriptor = 0;
tushki7 0:60d829a0353a 663
tushki7 0:60d829a0353a 664 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
tushki7 0:60d829a0353a 665 __xn_section(descriptor,reg.xn_t);
tushki7 0:60d829a0353a 666 __domain_section(descriptor, reg.domain);
tushki7 0:60d829a0353a 667 __p_section(descriptor, reg.e_t);
tushki7 0:60d829a0353a 668 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
tushki7 0:60d829a0353a 669 __shared_section(descriptor,reg.sh_t);
tushki7 0:60d829a0353a 670 __global_section(descriptor,reg.g_t);
tushki7 0:60d829a0353a 671 __secure_section(descriptor,reg.sec_t);
tushki7 0:60d829a0353a 672 *descriptor &= SECTION_MASK;
tushki7 0:60d829a0353a 673 *descriptor |= SECTION_DESCRIPTOR;
tushki7 0:60d829a0353a 674
tushki7 0:60d829a0353a 675 return 0;
tushki7 0:60d829a0353a 676
tushki7 0:60d829a0353a 677 }
tushki7 0:60d829a0353a 678
tushki7 0:60d829a0353a 679
tushki7 0:60d829a0353a 680 /** \brief Create a L1 and L2 4k/64k page descriptor
tushki7 0:60d829a0353a 681
tushki7 0:60d829a0353a 682 The function creates a 4k/64k page descriptor.
tushki7 0:60d829a0353a 683 Assumptions:
tushki7 0:60d829a0353a 684 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
tushki7 0:60d829a0353a 685 - Functions always return 0
tushki7 0:60d829a0353a 686
tushki7 0:60d829a0353a 687 \param [out] descriptor L1 descriptor
tushki7 0:60d829a0353a 688 \param [out] descriptor2 L2 descriptor
tushki7 0:60d829a0353a 689 \param [in] reg 4k/64k page attributes
tushki7 0:60d829a0353a 690
tushki7 0:60d829a0353a 691 \return 0
tushki7 0:60d829a0353a 692 */
tushki7 0:60d829a0353a 693 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
tushki7 0:60d829a0353a 694 {
tushki7 0:60d829a0353a 695 *descriptor = 0;
tushki7 0:60d829a0353a 696 *descriptor2 = 0;
tushki7 0:60d829a0353a 697
tushki7 0:60d829a0353a 698 switch (reg.rg_t)
tushki7 0:60d829a0353a 699 {
tushki7 0:60d829a0353a 700 case PAGE_4k:
tushki7 0:60d829a0353a 701 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
tushki7 0:60d829a0353a 702 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
tushki7 0:60d829a0353a 703 __domain_page(descriptor, reg.domain);
tushki7 0:60d829a0353a 704 __p_page(descriptor, reg.e_t);
tushki7 0:60d829a0353a 705 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
tushki7 0:60d829a0353a 706 __shared_page(descriptor2,reg.sh_t);
tushki7 0:60d829a0353a 707 __global_page(descriptor2,reg.g_t);
tushki7 0:60d829a0353a 708 __secure_page(descriptor,reg.sec_t);
tushki7 0:60d829a0353a 709 *descriptor &= PAGE_L1_MASK;
tushki7 0:60d829a0353a 710 *descriptor |= PAGE_L1_DESCRIPTOR;
tushki7 0:60d829a0353a 711 *descriptor2 &= PAGE_L2_4K_MASK;
tushki7 0:60d829a0353a 712 *descriptor2 |= PAGE_L2_4K_DESC;
tushki7 0:60d829a0353a 713 break;
tushki7 0:60d829a0353a 714
tushki7 0:60d829a0353a 715 case PAGE_64k:
tushki7 0:60d829a0353a 716 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
tushki7 0:60d829a0353a 717 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
tushki7 0:60d829a0353a 718 __domain_page(descriptor, reg.domain);
tushki7 0:60d829a0353a 719 __p_page(descriptor, reg.e_t);
tushki7 0:60d829a0353a 720 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
tushki7 0:60d829a0353a 721 __shared_page(descriptor2,reg.sh_t);
tushki7 0:60d829a0353a 722 __global_page(descriptor2,reg.g_t);
tushki7 0:60d829a0353a 723 __secure_page(descriptor,reg.sec_t);
tushki7 0:60d829a0353a 724 *descriptor &= PAGE_L1_MASK;
tushki7 0:60d829a0353a 725 *descriptor |= PAGE_L1_DESCRIPTOR;
tushki7 0:60d829a0353a 726 *descriptor2 &= PAGE_L2_64K_MASK;
tushki7 0:60d829a0353a 727 *descriptor2 |= PAGE_L2_64K_DESC;
tushki7 0:60d829a0353a 728 break;
tushki7 0:60d829a0353a 729
tushki7 0:60d829a0353a 730 case SECTION:
tushki7 0:60d829a0353a 731 //error
tushki7 0:60d829a0353a 732 break;
tushki7 0:60d829a0353a 733
tushki7 0:60d829a0353a 734 }
tushki7 0:60d829a0353a 735
tushki7 0:60d829a0353a 736 return 0;
tushki7 0:60d829a0353a 737
tushki7 0:60d829a0353a 738 }
tushki7 0:60d829a0353a 739
tushki7 0:60d829a0353a 740 /** \brief Create a 1MB Section
tushki7 0:60d829a0353a 741
tushki7 0:60d829a0353a 742 \param [in] ttb Translation table base address
tushki7 0:60d829a0353a 743 \param [in] base_address Section base address
tushki7 0:60d829a0353a 744 \param [in] count Number of sections to create
tushki7 0:60d829a0353a 745 \param [in] descriptor_l1 L1 descriptor (region attributes)
tushki7 0:60d829a0353a 746
tushki7 0:60d829a0353a 747 */
tushki7 0:60d829a0353a 748 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
tushki7 0:60d829a0353a 749 {
tushki7 0:60d829a0353a 750 uint32_t offset;
tushki7 0:60d829a0353a 751 uint32_t entry;
tushki7 0:60d829a0353a 752 uint32_t i;
tushki7 0:60d829a0353a 753
tushki7 0:60d829a0353a 754 offset = base_address >> 20;
tushki7 0:60d829a0353a 755 entry = (base_address & 0xFFF00000) | descriptor_l1;
tushki7 0:60d829a0353a 756
tushki7 0:60d829a0353a 757 //4 bytes aligned
tushki7 0:60d829a0353a 758 ttb = ttb + offset;
tushki7 0:60d829a0353a 759
tushki7 0:60d829a0353a 760 for (i = 0; i < count; i++ )
tushki7 0:60d829a0353a 761 {
tushki7 0:60d829a0353a 762 //4 bytes aligned
tushki7 0:60d829a0353a 763 *ttb++ = entry;
tushki7 0:60d829a0353a 764 entry += OFFSET_1M;
tushki7 0:60d829a0353a 765 }
tushki7 0:60d829a0353a 766 }
tushki7 0:60d829a0353a 767
tushki7 0:60d829a0353a 768 /** \brief Create a 4k page entry
tushki7 0:60d829a0353a 769
tushki7 0:60d829a0353a 770 \param [in] ttb L1 table base address
tushki7 0:60d829a0353a 771 \param [in] base_address 4k base address
tushki7 0:60d829a0353a 772 \param [in] count Number of 4k pages to create
tushki7 0:60d829a0353a 773 \param [in] descriptor_l1 L1 descriptor (region attributes)
tushki7 0:60d829a0353a 774 \param [in] ttb_l2 L2 table base address
tushki7 0:60d829a0353a 775 \param [in] descriptor_l2 L2 descriptor (region attributes)
tushki7 0:60d829a0353a 776
tushki7 0:60d829a0353a 777 */
tushki7 0:60d829a0353a 778 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
tushki7 0:60d829a0353a 779 {
tushki7 0:60d829a0353a 780
tushki7 0:60d829a0353a 781 uint32_t offset, offset2;
tushki7 0:60d829a0353a 782 uint32_t entry, entry2;
tushki7 0:60d829a0353a 783 uint32_t i;
tushki7 0:60d829a0353a 784
tushki7 0:60d829a0353a 785
tushki7 0:60d829a0353a 786 offset = base_address >> 20;
tushki7 0:60d829a0353a 787 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
tushki7 0:60d829a0353a 788
tushki7 0:60d829a0353a 789 //4 bytes aligned
tushki7 0:60d829a0353a 790 ttb += offset;
tushki7 0:60d829a0353a 791 //create l1_entry
tushki7 0:60d829a0353a 792 *ttb = entry;
tushki7 0:60d829a0353a 793
tushki7 0:60d829a0353a 794 offset2 = (base_address & 0xff000) >> 12;
tushki7 0:60d829a0353a 795 ttb_l2 += offset2;
tushki7 0:60d829a0353a 796 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
tushki7 0:60d829a0353a 797 for (i = 0; i < count; i++ )
tushki7 0:60d829a0353a 798 {
tushki7 0:60d829a0353a 799 //4 bytes aligned
tushki7 0:60d829a0353a 800 *ttb_l2++ = entry2;
tushki7 0:60d829a0353a 801 entry2 += OFFSET_4K;
tushki7 0:60d829a0353a 802 }
tushki7 0:60d829a0353a 803 }
tushki7 0:60d829a0353a 804
tushki7 0:60d829a0353a 805 /** \brief Create a 64k page entry
tushki7 0:60d829a0353a 806
tushki7 0:60d829a0353a 807 \param [in] ttb L1 table base address
tushki7 0:60d829a0353a 808 \param [in] base_address 64k base address
tushki7 0:60d829a0353a 809 \param [in] count Number of 64k pages to create
tushki7 0:60d829a0353a 810 \param [in] descriptor_l1 L1 descriptor (region attributes)
tushki7 0:60d829a0353a 811 \param [in] ttb_l2 L2 table base address
tushki7 0:60d829a0353a 812 \param [in] descriptor_l2 L2 descriptor (region attributes)
tushki7 0:60d829a0353a 813
tushki7 0:60d829a0353a 814 */
tushki7 0:60d829a0353a 815 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
tushki7 0:60d829a0353a 816 {
tushki7 0:60d829a0353a 817 uint32_t offset, offset2;
tushki7 0:60d829a0353a 818 uint32_t entry, entry2;
tushki7 0:60d829a0353a 819 uint32_t i,j;
tushki7 0:60d829a0353a 820
tushki7 0:60d829a0353a 821
tushki7 0:60d829a0353a 822 offset = base_address >> 20;
tushki7 0:60d829a0353a 823 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
tushki7 0:60d829a0353a 824
tushki7 0:60d829a0353a 825 //4 bytes aligned
tushki7 0:60d829a0353a 826 ttb += offset;
tushki7 0:60d829a0353a 827 //create l1_entry
tushki7 0:60d829a0353a 828 *ttb = entry;
tushki7 0:60d829a0353a 829
tushki7 0:60d829a0353a 830 offset2 = (base_address & 0xff000) >> 12;
tushki7 0:60d829a0353a 831 ttb_l2 += offset2;
tushki7 0:60d829a0353a 832 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
tushki7 0:60d829a0353a 833 for (i = 0; i < count; i++ )
tushki7 0:60d829a0353a 834 {
tushki7 0:60d829a0353a 835 //create 16 entries
tushki7 0:60d829a0353a 836 for (j = 0; j < 16; j++)
tushki7 0:60d829a0353a 837 //4 bytes aligned
tushki7 0:60d829a0353a 838 *ttb_l2++ = entry2;
tushki7 0:60d829a0353a 839 entry2 += OFFSET_64K;
tushki7 0:60d829a0353a 840 }
tushki7 0:60d829a0353a 841 }
tushki7 0:60d829a0353a 842
tushki7 0:60d829a0353a 843 /*@} end of MMU_Functions */
tushki7 0:60d829a0353a 844 #endif
tushki7 0:60d829a0353a 845
tushki7 0:60d829a0353a 846 #ifdef __cplusplus
tushki7 0:60d829a0353a 847 }
tushki7 0:60d829a0353a 848 #endif