Tushar Sachdeva / FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies:   C12832

mbed/TARGET_ARCH_GPRS/core_caFunc.h@1:eb68c94a8ee5, 2015-04-12 (annotated)

Committer:
tushki7
Date:
Sun Apr 12 15:45:52 2015 +0000
Revision:
1:eb68c94a8ee5
Parent:
0:60d829a0353a 
A simple 128x32 LCD program with ARM mbed IoT Starter Kit;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tushki7 0:60d829a0353a 1 /**************************************************************************//**
tushki7 0:60d829a0353a 2 * @file core_caFunc.h
tushki7 0:60d829a0353a 3 * @brief CMSIS Cortex-A Core Function Access Header File
tushki7 0:60d829a0353a 4 * @version V3.10
tushki7 0:60d829a0353a 5 * @date 9 May 2013
tushki7 0:60d829a0353a 6 *
tushki7 0:60d829a0353a 7 * @note
tushki7 0:60d829a0353a 8 *
tushki7 0:60d829a0353a 9 ******************************************************************************/
tushki7 0:60d829a0353a 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
tushki7 0:60d829a0353a 11
tushki7 0:60d829a0353a 12 All rights reserved.
tushki7 0:60d829a0353a 13 Redistribution and use in source and binary forms, with or without
tushki7 0:60d829a0353a 14 modification, are permitted provided that the following conditions are met:
tushki7 0:60d829a0353a 15 - Redistributions of source code must retain the above copyright
tushki7 0:60d829a0353a 16 notice, this list of conditions and the following disclaimer.
tushki7 0:60d829a0353a 17 - Redistributions in binary form must reproduce the above copyright
tushki7 0:60d829a0353a 18 notice, this list of conditions and the following disclaimer in the
tushki7 0:60d829a0353a 19 documentation and/or other materials provided with the distribution.
tushki7 0:60d829a0353a 20 - Neither the name of ARM nor the names of its contributors may be used
tushki7 0:60d829a0353a 21 to endorse or promote products derived from this software without
tushki7 0:60d829a0353a 22 specific prior written permission.
tushki7 0:60d829a0353a 23 *
tushki7 0:60d829a0353a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
tushki7 0:60d829a0353a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
tushki7 0:60d829a0353a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
tushki7 0:60d829a0353a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
tushki7 0:60d829a0353a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
tushki7 0:60d829a0353a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
tushki7 0:60d829a0353a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
tushki7 0:60d829a0353a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
tushki7 0:60d829a0353a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
tushki7 0:60d829a0353a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
tushki7 0:60d829a0353a 34 POSSIBILITY OF SUCH DAMAGE.
tushki7 0:60d829a0353a 35 ---------------------------------------------------------------------------*/
tushki7 0:60d829a0353a 36
tushki7 0:60d829a0353a 37
tushki7 0:60d829a0353a 38 #ifndef __CORE_CAFUNC_H__
tushki7 0:60d829a0353a 39 #define __CORE_CAFUNC_H__
tushki7 0:60d829a0353a 40
tushki7 0:60d829a0353a 41
tushki7 0:60d829a0353a 42 /* ########################### Core Function Access ########################### */
tushki7 0:60d829a0353a 43 /** \ingroup CMSIS_Core_FunctionInterface
tushki7 0:60d829a0353a 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
tushki7 0:60d829a0353a 45 @{
tushki7 0:60d829a0353a 46 */
tushki7 0:60d829a0353a 47
tushki7 0:60d829a0353a 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
tushki7 0:60d829a0353a 49 /* ARM armcc specific functions */
tushki7 0:60d829a0353a 50
tushki7 0:60d829a0353a 51 #if (__ARMCC_VERSION < 400677)
tushki7 0:60d829a0353a 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
tushki7 0:60d829a0353a 53 #endif
tushki7 0:60d829a0353a 54
tushki7 0:60d829a0353a 55 #define MODE_USR 0x10
tushki7 0:60d829a0353a 56 #define MODE_FIQ 0x11
tushki7 0:60d829a0353a 57 #define MODE_IRQ 0x12
tushki7 0:60d829a0353a 58 #define MODE_SVC 0x13
tushki7 0:60d829a0353a 59 #define MODE_MON 0x16
tushki7 0:60d829a0353a 60 #define MODE_ABT 0x17
tushki7 0:60d829a0353a 61 #define MODE_HYP 0x1A
tushki7 0:60d829a0353a 62 #define MODE_UND 0x1B
tushki7 0:60d829a0353a 63 #define MODE_SYS 0x1F
tushki7 0:60d829a0353a 64
tushki7 0:60d829a0353a 65 /** \brief Get APSR Register
tushki7 0:60d829a0353a 66
tushki7 0:60d829a0353a 67 This function returns the content of the APSR Register.
tushki7 0:60d829a0353a 68
tushki7 0:60d829a0353a 69 \return APSR Register value
tushki7 0:60d829a0353a 70 */
tushki7 0:60d829a0353a 71 __STATIC_INLINE uint32_t __get_APSR(void)
tushki7 0:60d829a0353a 72 {
tushki7 0:60d829a0353a 73 register uint32_t __regAPSR __ASM("apsr");
tushki7 0:60d829a0353a 74 return(__regAPSR);
tushki7 0:60d829a0353a 75 }
tushki7 0:60d829a0353a 76
tushki7 0:60d829a0353a 77
tushki7 0:60d829a0353a 78 /** \brief Get CPSR Register
tushki7 0:60d829a0353a 79
tushki7 0:60d829a0353a 80 This function returns the content of the CPSR Register.
tushki7 0:60d829a0353a 81
tushki7 0:60d829a0353a 82 \return CPSR Register value
tushki7 0:60d829a0353a 83 */
tushki7 0:60d829a0353a 84 __STATIC_INLINE uint32_t __get_CPSR(void)
tushki7 0:60d829a0353a 85 {
tushki7 0:60d829a0353a 86 register uint32_t __regCPSR __ASM("cpsr");
tushki7 0:60d829a0353a 87 return(__regCPSR);
tushki7 0:60d829a0353a 88 }
tushki7 0:60d829a0353a 89
tushki7 0:60d829a0353a 90 /** \brief Set Stack Pointer
tushki7 0:60d829a0353a 91
tushki7 0:60d829a0353a 92 This function assigns the given value to the current stack pointer.
tushki7 0:60d829a0353a 93
tushki7 0:60d829a0353a 94 \param [in] topOfStack Stack Pointer value to set
tushki7 0:60d829a0353a 95 */
tushki7 0:60d829a0353a 96 register uint32_t __regSP __ASM("sp");
tushki7 0:60d829a0353a 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
tushki7 0:60d829a0353a 98 {
tushki7 0:60d829a0353a 99 __regSP = topOfStack;
tushki7 0:60d829a0353a 100 }
tushki7 0:60d829a0353a 101
tushki7 0:60d829a0353a 102
tushki7 0:60d829a0353a 103 /** \brief Get link register
tushki7 0:60d829a0353a 104
tushki7 0:60d829a0353a 105 This function returns the value of the link register
tushki7 0:60d829a0353a 106
tushki7 0:60d829a0353a 107 \return Value of link register
tushki7 0:60d829a0353a 108 */
tushki7 0:60d829a0353a 109 register uint32_t __reglr __ASM("lr");
tushki7 0:60d829a0353a 110 __STATIC_INLINE uint32_t __get_LR(void)
tushki7 0:60d829a0353a 111 {
tushki7 0:60d829a0353a 112 return(__reglr);
tushki7 0:60d829a0353a 113 }
tushki7 0:60d829a0353a 114
tushki7 0:60d829a0353a 115 /** \brief Set link register
tushki7 0:60d829a0353a 116
tushki7 0:60d829a0353a 117 This function sets the value of the link register
tushki7 0:60d829a0353a 118
tushki7 0:60d829a0353a 119 \param [in] lr LR value to set
tushki7 0:60d829a0353a 120 */
tushki7 0:60d829a0353a 121 __STATIC_INLINE void __set_LR(uint32_t lr)
tushki7 0:60d829a0353a 122 {
tushki7 0:60d829a0353a 123 __reglr = lr;
tushki7 0:60d829a0353a 124 }
tushki7 0:60d829a0353a 125
tushki7 0:60d829a0353a 126 /** \brief Set Process Stack Pointer
tushki7 0:60d829a0353a 127
tushki7 0:60d829a0353a 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
tushki7 0:60d829a0353a 129
tushki7 0:60d829a0353a 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
tushki7 0:60d829a0353a 131 */
tushki7 0:60d829a0353a 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
tushki7 0:60d829a0353a 133 {
tushki7 0:60d829a0353a 134 ARM
tushki7 0:60d829a0353a 135 PRESERVE8
tushki7 0:60d829a0353a 136
tushki7 0:60d829a0353a 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
tushki7 0:60d829a0353a 138 MRS R1, CPSR
tushki7 0:60d829a0353a 139 CPS #MODE_SYS ;no effect in USR mode
tushki7 0:60d829a0353a 140 MOV SP, R0
tushki7 0:60d829a0353a 141 MSR CPSR_c, R1 ;no effect in USR mode
tushki7 0:60d829a0353a 142 ISB
tushki7 0:60d829a0353a 143 BX LR
tushki7 0:60d829a0353a 144
tushki7 0:60d829a0353a 145 }
tushki7 0:60d829a0353a 146
tushki7 0:60d829a0353a 147 /** \brief Set User Mode
tushki7 0:60d829a0353a 148
tushki7 0:60d829a0353a 149 This function changes the processor state to User Mode
tushki7 0:60d829a0353a 150
tushki7 0:60d829a0353a 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
tushki7 0:60d829a0353a 152 */
tushki7 0:60d829a0353a 153 __STATIC_ASM void __set_CPS_USR(void)
tushki7 0:60d829a0353a 154 {
tushki7 0:60d829a0353a 155 ARM
tushki7 0:60d829a0353a 156
tushki7 0:60d829a0353a 157 CPS #MODE_USR
tushki7 0:60d829a0353a 158 BX LR
tushki7 0:60d829a0353a 159 }
tushki7 0:60d829a0353a 160
tushki7 0:60d829a0353a 161
tushki7 0:60d829a0353a 162 /** \brief Enable FIQ
tushki7 0:60d829a0353a 163
tushki7 0:60d829a0353a 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
tushki7 0:60d829a0353a 165 Can only be executed in Privileged modes.
tushki7 0:60d829a0353a 166 */
tushki7 0:60d829a0353a 167 #define __enable_fault_irq __enable_fiq
tushki7 0:60d829a0353a 168
tushki7 0:60d829a0353a 169
tushki7 0:60d829a0353a 170 /** \brief Disable FIQ
tushki7 0:60d829a0353a 171
tushki7 0:60d829a0353a 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
tushki7 0:60d829a0353a 173 Can only be executed in Privileged modes.
tushki7 0:60d829a0353a 174 */
tushki7 0:60d829a0353a 175 #define __disable_fault_irq __disable_fiq
tushki7 0:60d829a0353a 176
tushki7 0:60d829a0353a 177
tushki7 0:60d829a0353a 178 /** \brief Get FPSCR
tushki7 0:60d829a0353a 179
tushki7 0:60d829a0353a 180 This function returns the current value of the Floating Point Status/Control register.
tushki7 0:60d829a0353a 181
tushki7 0:60d829a0353a 182 \return Floating Point Status/Control register value
tushki7 0:60d829a0353a 183 */
tushki7 0:60d829a0353a 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
tushki7 0:60d829a0353a 185 {
tushki7 0:60d829a0353a 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
tushki7 0:60d829a0353a 187 register uint32_t __regfpscr __ASM("fpscr");
tushki7 0:60d829a0353a 188 return(__regfpscr);
tushki7 0:60d829a0353a 189 #else
tushki7 0:60d829a0353a 190 return(0);
tushki7 0:60d829a0353a 191 #endif
tushki7 0:60d829a0353a 192 }
tushki7 0:60d829a0353a 193
tushki7 0:60d829a0353a 194
tushki7 0:60d829a0353a 195 /** \brief Set FPSCR
tushki7 0:60d829a0353a 196
tushki7 0:60d829a0353a 197 This function assigns the given value to the Floating Point Status/Control register.
tushki7 0:60d829a0353a 198
tushki7 0:60d829a0353a 199 \param [in] fpscr Floating Point Status/Control value to set
tushki7 0:60d829a0353a 200 */
tushki7 0:60d829a0353a 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
tushki7 0:60d829a0353a 202 {
tushki7 0:60d829a0353a 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
tushki7 0:60d829a0353a 204 register uint32_t __regfpscr __ASM("fpscr");
tushki7 0:60d829a0353a 205 __regfpscr = (fpscr);
tushki7 0:60d829a0353a 206 #endif
tushki7 0:60d829a0353a 207 }
tushki7 0:60d829a0353a 208
tushki7 0:60d829a0353a 209 /** \brief Get FPEXC
tushki7 0:60d829a0353a 210
tushki7 0:60d829a0353a 211 This function returns the current value of the Floating Point Exception Control register.
tushki7 0:60d829a0353a 212
tushki7 0:60d829a0353a 213 \return Floating Point Exception Control register value
tushki7 0:60d829a0353a 214 */
tushki7 0:60d829a0353a 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
tushki7 0:60d829a0353a 216 {
tushki7 0:60d829a0353a 217 #if (__FPU_PRESENT == 1)
tushki7 0:60d829a0353a 218 register uint32_t __regfpexc __ASM("fpexc");
tushki7 0:60d829a0353a 219 return(__regfpexc);
tushki7 0:60d829a0353a 220 #else
tushki7 0:60d829a0353a 221 return(0);
tushki7 0:60d829a0353a 222 #endif
tushki7 0:60d829a0353a 223 }
tushki7 0:60d829a0353a 224
tushki7 0:60d829a0353a 225
tushki7 0:60d829a0353a 226 /** \brief Set FPEXC
tushki7 0:60d829a0353a 227
tushki7 0:60d829a0353a 228 This function assigns the given value to the Floating Point Exception Control register.
tushki7 0:60d829a0353a 229
tushki7 0:60d829a0353a 230 \param [in] fpscr Floating Point Exception Control value to set
tushki7 0:60d829a0353a 231 */
tushki7 0:60d829a0353a 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
tushki7 0:60d829a0353a 233 {
tushki7 0:60d829a0353a 234 #if (__FPU_PRESENT == 1)
tushki7 0:60d829a0353a 235 register uint32_t __regfpexc __ASM("fpexc");
tushki7 0:60d829a0353a 236 __regfpexc = (fpexc);
tushki7 0:60d829a0353a 237 #endif
tushki7 0:60d829a0353a 238 }
tushki7 0:60d829a0353a 239
tushki7 0:60d829a0353a 240 /** \brief Get CPACR
tushki7 0:60d829a0353a 241
tushki7 0:60d829a0353a 242 This function returns the current value of the Coprocessor Access Control register.
tushki7 0:60d829a0353a 243
tushki7 0:60d829a0353a 244 \return Coprocessor Access Control register value
tushki7 0:60d829a0353a 245 */
tushki7 0:60d829a0353a 246 __STATIC_INLINE uint32_t __get_CPACR(void)
tushki7 0:60d829a0353a 247 {
tushki7 0:60d829a0353a 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
tushki7 0:60d829a0353a 249 return __regCPACR;
tushki7 0:60d829a0353a 250 }
tushki7 0:60d829a0353a 251
tushki7 0:60d829a0353a 252 /** \brief Set CPACR
tushki7 0:60d829a0353a 253
tushki7 0:60d829a0353a 254 This function assigns the given value to the Coprocessor Access Control register.
tushki7 0:60d829a0353a 255
tushki7 0:60d829a0353a 256 \param [in] cpacr Coporcessor Acccess Control value to set
tushki7 0:60d829a0353a 257 */
tushki7 0:60d829a0353a 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
tushki7 0:60d829a0353a 259 {
tushki7 0:60d829a0353a 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
tushki7 0:60d829a0353a 261 __regCPACR = cpacr;
tushki7 0:60d829a0353a 262 __ISB();
tushki7 0:60d829a0353a 263 }
tushki7 0:60d829a0353a 264
tushki7 0:60d829a0353a 265 /** \brief Get CBAR
tushki7 0:60d829a0353a 266
tushki7 0:60d829a0353a 267 This function returns the value of the Configuration Base Address register.
tushki7 0:60d829a0353a 268
tushki7 0:60d829a0353a 269 \return Configuration Base Address register value
tushki7 0:60d829a0353a 270 */
tushki7 0:60d829a0353a 271 __STATIC_INLINE uint32_t __get_CBAR() {
tushki7 0:60d829a0353a 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
tushki7 0:60d829a0353a 273 return(__regCBAR);
tushki7 0:60d829a0353a 274 }
tushki7 0:60d829a0353a 275
tushki7 0:60d829a0353a 276 /** \brief Get TTBR0
tushki7 0:60d829a0353a 277
tushki7 0:60d829a0353a 278 This function returns the value of the Configuration Base Address register.
tushki7 0:60d829a0353a 279
tushki7 0:60d829a0353a 280 \return Translation Table Base Register 0 value
tushki7 0:60d829a0353a 281 */
tushki7 0:60d829a0353a 282 __STATIC_INLINE uint32_t __get_TTBR0() {
tushki7 0:60d829a0353a 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
tushki7 0:60d829a0353a 284 return(__regTTBR0);
tushki7 0:60d829a0353a 285 }
tushki7 0:60d829a0353a 286
tushki7 0:60d829a0353a 287 /** \brief Set TTBR0
tushki7 0:60d829a0353a 288
tushki7 0:60d829a0353a 289 This function assigns the given value to the Coprocessor Access Control register.
tushki7 0:60d829a0353a 290
tushki7 0:60d829a0353a 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
tushki7 0:60d829a0353a 292 */
tushki7 0:60d829a0353a 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
tushki7 0:60d829a0353a 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
tushki7 0:60d829a0353a 295 __regTTBR0 = ttbr0;
tushki7 0:60d829a0353a 296 __ISB();
tushki7 0:60d829a0353a 297 }
tushki7 0:60d829a0353a 298
tushki7 0:60d829a0353a 299 /** \brief Get DACR
tushki7 0:60d829a0353a 300
tushki7 0:60d829a0353a 301 This function returns the value of the Domain Access Control Register.
tushki7 0:60d829a0353a 302
tushki7 0:60d829a0353a 303 \return Domain Access Control Register value
tushki7 0:60d829a0353a 304 */
tushki7 0:60d829a0353a 305 __STATIC_INLINE uint32_t __get_DACR() {
tushki7 0:60d829a0353a 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
tushki7 0:60d829a0353a 307 return(__regDACR);
tushki7 0:60d829a0353a 308 }
tushki7 0:60d829a0353a 309
tushki7 0:60d829a0353a 310 /** \brief Set DACR
tushki7 0:60d829a0353a 311
tushki7 0:60d829a0353a 312 This function assigns the given value to the Coprocessor Access Control register.
tushki7 0:60d829a0353a 313
tushki7 0:60d829a0353a 314 \param [in] dacr Domain Access Control Register value to set
tushki7 0:60d829a0353a 315 */
tushki7 0:60d829a0353a 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
tushki7 0:60d829a0353a 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
tushki7 0:60d829a0353a 318 __regDACR = dacr;
tushki7 0:60d829a0353a 319 __ISB();
tushki7 0:60d829a0353a 320 }
tushki7 0:60d829a0353a 321
tushki7 0:60d829a0353a 322 /******************************** Cache and BTAC enable ****************************************************/
tushki7 0:60d829a0353a 323
tushki7 0:60d829a0353a 324 /** \brief Set SCTLR
tushki7 0:60d829a0353a 325
tushki7 0:60d829a0353a 326 This function assigns the given value to the System Control Register.
tushki7 0:60d829a0353a 327
tushki7 0:60d829a0353a 328 \param [in] sctlr System Control Register, value to set
tushki7 0:60d829a0353a 329 */
tushki7 0:60d829a0353a 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
tushki7 0:60d829a0353a 331 {
tushki7 0:60d829a0353a 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
tushki7 0:60d829a0353a 333 __regSCTLR = sctlr;
tushki7 0:60d829a0353a 334 }
tushki7 0:60d829a0353a 335
tushki7 0:60d829a0353a 336 /** \brief Get SCTLR
tushki7 0:60d829a0353a 337
tushki7 0:60d829a0353a 338 This function returns the value of the System Control Register.
tushki7 0:60d829a0353a 339
tushki7 0:60d829a0353a 340 \return System Control Register value
tushki7 0:60d829a0353a 341 */
tushki7 0:60d829a0353a 342 __STATIC_INLINE uint32_t __get_SCTLR() {
tushki7 0:60d829a0353a 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
tushki7 0:60d829a0353a 344 return(__regSCTLR);
tushki7 0:60d829a0353a 345 }
tushki7 0:60d829a0353a 346
tushki7 0:60d829a0353a 347 /** \brief Enable Caches
tushki7 0:60d829a0353a 348
tushki7 0:60d829a0353a 349 Enable Caches
tushki7 0:60d829a0353a 350 */
tushki7 0:60d829a0353a 351 __STATIC_INLINE void __enable_caches(void) {
tushki7 0:60d829a0353a 352 // Set I bit 12 to enable I Cache
tushki7 0:60d829a0353a 353 // Set C bit 2 to enable D Cache
tushki7 0:60d829a0353a 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
tushki7 0:60d829a0353a 355 }
tushki7 0:60d829a0353a 356
tushki7 0:60d829a0353a 357 /** \brief Disable Caches
tushki7 0:60d829a0353a 358
tushki7 0:60d829a0353a 359 Disable Caches
tushki7 0:60d829a0353a 360 */
tushki7 0:60d829a0353a 361 __STATIC_INLINE void __disable_caches(void) {
tushki7 0:60d829a0353a 362 // Clear I bit 12 to disable I Cache
tushki7 0:60d829a0353a 363 // Clear C bit 2 to disable D Cache
tushki7 0:60d829a0353a 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
tushki7 0:60d829a0353a 365 __ISB();
tushki7 0:60d829a0353a 366 }
tushki7 0:60d829a0353a 367
tushki7 0:60d829a0353a 368 /** \brief Enable BTAC
tushki7 0:60d829a0353a 369
tushki7 0:60d829a0353a 370 Enable BTAC
tushki7 0:60d829a0353a 371 */
tushki7 0:60d829a0353a 372 __STATIC_INLINE void __enable_btac(void) {
tushki7 0:60d829a0353a 373 // Set Z bit 11 to enable branch prediction
tushki7 0:60d829a0353a 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
tushki7 0:60d829a0353a 375 __ISB();
tushki7 0:60d829a0353a 376 }
tushki7 0:60d829a0353a 377
tushki7 0:60d829a0353a 378 /** \brief Disable BTAC
tushki7 0:60d829a0353a 379
tushki7 0:60d829a0353a 380 Disable BTAC
tushki7 0:60d829a0353a 381 */
tushki7 0:60d829a0353a 382 __STATIC_INLINE void __disable_btac(void) {
tushki7 0:60d829a0353a 383 // Clear Z bit 11 to disable branch prediction
tushki7 0:60d829a0353a 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
tushki7 0:60d829a0353a 385 }
tushki7 0:60d829a0353a 386
tushki7 0:60d829a0353a 387
tushki7 0:60d829a0353a 388 /** \brief Enable MMU
tushki7 0:60d829a0353a 389
tushki7 0:60d829a0353a 390 Enable MMU
tushki7 0:60d829a0353a 391 */
tushki7 0:60d829a0353a 392 __STATIC_INLINE void __enable_mmu(void) {
tushki7 0:60d829a0353a 393 // Set M bit 0 to enable the MMU
tushki7 0:60d829a0353a 394 // Set AFE bit to enable simplified access permissions model
tushki7 0:60d829a0353a 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
tushki7 0:60d829a0353a 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
tushki7 0:60d829a0353a 397 __ISB();
tushki7 0:60d829a0353a 398 }
tushki7 0:60d829a0353a 399
tushki7 0:60d829a0353a 400 /** \brief Enable MMU
tushki7 0:60d829a0353a 401
tushki7 0:60d829a0353a 402 Enable MMU
tushki7 0:60d829a0353a 403 */
tushki7 0:60d829a0353a 404 __STATIC_INLINE void __disable_mmu(void) {
tushki7 0:60d829a0353a 405 // Clear M bit 0 to disable the MMU
tushki7 0:60d829a0353a 406 __set_SCTLR( __get_SCTLR() & ~1);
tushki7 0:60d829a0353a 407 __ISB();
tushki7 0:60d829a0353a 408 }
tushki7 0:60d829a0353a 409
tushki7 0:60d829a0353a 410 /******************************** TLB maintenance operations ************************************************/
tushki7 0:60d829a0353a 411 /** \brief Invalidate the whole tlb
tushki7 0:60d829a0353a 412
tushki7 0:60d829a0353a 413 TLBIALL. Invalidate the whole tlb
tushki7 0:60d829a0353a 414 */
tushki7 0:60d829a0353a 415
tushki7 0:60d829a0353a 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
tushki7 0:60d829a0353a 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
tushki7 0:60d829a0353a 418 __TLBIALL = 0;
tushki7 0:60d829a0353a 419 __DSB();
tushki7 0:60d829a0353a 420 __ISB();
tushki7 0:60d829a0353a 421 }
tushki7 0:60d829a0353a 422
tushki7 0:60d829a0353a 423 /******************************** BTB maintenance operations ************************************************/
tushki7 0:60d829a0353a 424 /** \brief Invalidate entire branch predictor array
tushki7 0:60d829a0353a 425
tushki7 0:60d829a0353a 426 BPIALL. Branch Predictor Invalidate All.
tushki7 0:60d829a0353a 427 */
tushki7 0:60d829a0353a 428
tushki7 0:60d829a0353a 429 __STATIC_INLINE void __v7_inv_btac(void) {
tushki7 0:60d829a0353a 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
tushki7 0:60d829a0353a 431 __BPIALL = 0;
tushki7 0:60d829a0353a 432 __DSB(); //ensure completion of the invalidation
tushki7 0:60d829a0353a 433 __ISB(); //ensure instruction fetch path sees new state
tushki7 0:60d829a0353a 434 }
tushki7 0:60d829a0353a 435
tushki7 0:60d829a0353a 436
tushki7 0:60d829a0353a 437 /******************************** L1 cache operations ******************************************************/
tushki7 0:60d829a0353a 438
tushki7 0:60d829a0353a 439 /** \brief Invalidate the whole I$
tushki7 0:60d829a0353a 440
tushki7 0:60d829a0353a 441 ICIALLU. Instruction Cache Invalidate All to PoU
tushki7 0:60d829a0353a 442 */
tushki7 0:60d829a0353a 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
tushki7 0:60d829a0353a 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
tushki7 0:60d829a0353a 445 __ICIALLU = 0;
tushki7 0:60d829a0353a 446 __DSB(); //ensure completion of the invalidation
tushki7 0:60d829a0353a 447 __ISB(); //ensure instruction fetch path sees new I cache state
tushki7 0:60d829a0353a 448 }
tushki7 0:60d829a0353a 449
tushki7 0:60d829a0353a 450 /** \brief Clean D$ by MVA
tushki7 0:60d829a0353a 451
tushki7 0:60d829a0353a 452 DCCMVAC. Data cache clean by MVA to PoC
tushki7 0:60d829a0353a 453 */
tushki7 0:60d829a0353a 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
tushki7 0:60d829a0353a 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
tushki7 0:60d829a0353a 456 __DCCMVAC = (uint32_t)va;
tushki7 0:60d829a0353a 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
tushki7 0:60d829a0353a 458 }
tushki7 0:60d829a0353a 459
tushki7 0:60d829a0353a 460 /** \brief Invalidate D$ by MVA
tushki7 0:60d829a0353a 461
tushki7 0:60d829a0353a 462 DCIMVAC. Data cache invalidate by MVA to PoC
tushki7 0:60d829a0353a 463 */
tushki7 0:60d829a0353a 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
tushki7 0:60d829a0353a 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
tushki7 0:60d829a0353a 466 __DCIMVAC = (uint32_t)va;
tushki7 0:60d829a0353a 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
tushki7 0:60d829a0353a 468 }
tushki7 0:60d829a0353a 469
tushki7 0:60d829a0353a 470 /** \brief Clean and Invalidate D$ by MVA
tushki7 0:60d829a0353a 471
tushki7 0:60d829a0353a 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
tushki7 0:60d829a0353a 473 */
tushki7 0:60d829a0353a 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
tushki7 0:60d829a0353a 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
tushki7 0:60d829a0353a 476 __DCCIMVAC = (uint32_t)va;
tushki7 0:60d829a0353a 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
tushki7 0:60d829a0353a 478 }
tushki7 0:60d829a0353a 479
tushki7 0:60d829a0353a 480 /** \brief
tushki7 0:60d829a0353a 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
tushki7 0:60d829a0353a 482 */
tushki7 0:60d829a0353a 483 #pragma push
tushki7 0:60d829a0353a 484 #pragma arm
tushki7 0:60d829a0353a 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
tushki7 0:60d829a0353a 486 ARM
tushki7 0:60d829a0353a 487
tushki7 0:60d829a0353a 488 PUSH {R4-R11}
tushki7 0:60d829a0353a 489
tushki7 0:60d829a0353a 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
tushki7 0:60d829a0353a 491 ANDS R3, R6, #0x07000000 // Extract coherency level
tushki7 0:60d829a0353a 492 MOV R3, R3, LSR #23 // Total cache levels << 1
tushki7 0:60d829a0353a 493 BEQ Finished // If 0, no need to clean
tushki7 0:60d829a0353a 494
tushki7 0:60d829a0353a 495 MOV R10, #0 // R10 holds current cache level << 1
tushki7 0:60d829a0353a 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
tushki7 0:60d829a0353a 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
tushki7 0:60d829a0353a 498 AND R1, R1, #7 // Isolate those lower 3 bits
tushki7 0:60d829a0353a 499 CMP R1, #2
tushki7 0:60d829a0353a 500 BLT Skip // No cache or only instruction cache at this level
tushki7 0:60d829a0353a 501
tushki7 0:60d829a0353a 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
tushki7 0:60d829a0353a 503 ISB // ISB to sync the change to the CacheSizeID reg
tushki7 0:60d829a0353a 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
tushki7 0:60d829a0353a 505 AND R2, R1, #7 // Extract the line length field
tushki7 0:60d829a0353a 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
tushki7 0:60d829a0353a 507 LDR R4, =0x3FF
tushki7 0:60d829a0353a 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
tushki7 0:60d829a0353a 509 CLZ R5, R4 // R5 is the bit position of the way size increment
tushki7 0:60d829a0353a 510 LDR R7, =0x7FFF
tushki7 0:60d829a0353a 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
tushki7 0:60d829a0353a 512
tushki7 0:60d829a0353a 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
tushki7 0:60d829a0353a 514
tushki7 0:60d829a0353a 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
tushki7 0:60d829a0353a 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
tushki7 0:60d829a0353a 517 CMP R0, #0
tushki7 0:60d829a0353a 518 BNE Dccsw
tushki7 0:60d829a0353a 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
tushki7 0:60d829a0353a 520 B cont
tushki7 0:60d829a0353a 521 Dccsw CMP R0, #1
tushki7 0:60d829a0353a 522 BNE Dccisw
tushki7 0:60d829a0353a 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
tushki7 0:60d829a0353a 524 B cont
tushki7 0:60d829a0353a 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
tushki7 0:60d829a0353a 526 cont SUBS R9, R9, #1 // Decrement the Way number
tushki7 0:60d829a0353a 527 BGE Loop3
tushki7 0:60d829a0353a 528 SUBS R7, R7, #1 // Decrement the Set number
tushki7 0:60d829a0353a 529 BGE Loop2
tushki7 0:60d829a0353a 530 Skip ADD R10, R10, #2 // increment the cache number
tushki7 0:60d829a0353a 531 CMP R3, R10
tushki7 0:60d829a0353a 532 BGT Loop1
tushki7 0:60d829a0353a 533
tushki7 0:60d829a0353a 534 Finished
tushki7 0:60d829a0353a 535 DSB
tushki7 0:60d829a0353a 536 POP {R4-R11}
tushki7 0:60d829a0353a 537 BX lr
tushki7 0:60d829a0353a 538
tushki7 0:60d829a0353a 539 }
tushki7 0:60d829a0353a 540 #pragma pop
tushki7 0:60d829a0353a 541
tushki7 0:60d829a0353a 542 /** \brief __v7_all_cache - helper function
tushki7 0:60d829a0353a 543
tushki7 0:60d829a0353a 544 */
tushki7 0:60d829a0353a 545
tushki7 0:60d829a0353a 546 /** \brief Invalidate the whole D$
tushki7 0:60d829a0353a 547
tushki7 0:60d829a0353a 548 DCISW. Invalidate by Set/Way
tushki7 0:60d829a0353a 549 */
tushki7 0:60d829a0353a 550
tushki7 0:60d829a0353a 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
tushki7 0:60d829a0353a 552 __v7_all_cache(0);
tushki7 0:60d829a0353a 553 }
tushki7 0:60d829a0353a 554
tushki7 0:60d829a0353a 555 /** \brief Clean the whole D$
tushki7 0:60d829a0353a 556
tushki7 0:60d829a0353a 557 DCCSW. Clean by Set/Way
tushki7 0:60d829a0353a 558 */
tushki7 0:60d829a0353a 559
tushki7 0:60d829a0353a 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
tushki7 0:60d829a0353a 561 __v7_all_cache(1);
tushki7 0:60d829a0353a 562 }
tushki7 0:60d829a0353a 563
tushki7 0:60d829a0353a 564 /** \brief Clean and invalidate the whole D$
tushki7 0:60d829a0353a 565
tushki7 0:60d829a0353a 566 DCCISW. Clean and Invalidate by Set/Way
tushki7 0:60d829a0353a 567 */
tushki7 0:60d829a0353a 568
tushki7 0:60d829a0353a 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
tushki7 0:60d829a0353a 570 __v7_all_cache(2);
tushki7 0:60d829a0353a 571 }
tushki7 0:60d829a0353a 572
tushki7 0:60d829a0353a 573 #include "core_ca_mmu.h"
tushki7 0:60d829a0353a 574
tushki7 0:60d829a0353a 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
tushki7 0:60d829a0353a 576
tushki7 0:60d829a0353a 577 #error IAR Compiler support not implemented for Cortex-A
tushki7 0:60d829a0353a 578
tushki7 0:60d829a0353a 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
tushki7 0:60d829a0353a 580
tushki7 0:60d829a0353a 581 /* GNU gcc specific functions */
tushki7 0:60d829a0353a 582
tushki7 0:60d829a0353a 583 #define MODE_USR 0x10
tushki7 0:60d829a0353a 584 #define MODE_FIQ 0x11
tushki7 0:60d829a0353a 585 #define MODE_IRQ 0x12
tushki7 0:60d829a0353a 586 #define MODE_SVC 0x13
tushki7 0:60d829a0353a 587 #define MODE_MON 0x16
tushki7 0:60d829a0353a 588 #define MODE_ABT 0x17
tushki7 0:60d829a0353a 589 #define MODE_HYP 0x1A
tushki7 0:60d829a0353a 590 #define MODE_UND 0x1B
tushki7 0:60d829a0353a 591 #define MODE_SYS 0x1F
tushki7 0:60d829a0353a 592
tushki7 0:60d829a0353a 593
tushki7 0:60d829a0353a 594 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
tushki7 0:60d829a0353a 595 {
tushki7 0:60d829a0353a 596 __ASM volatile ("cpsie i");
tushki7 0:60d829a0353a 597 }
tushki7 0:60d829a0353a 598
tushki7 0:60d829a0353a 599 /** \brief Disable IRQ Interrupts
tushki7 0:60d829a0353a 600
tushki7 0:60d829a0353a 601 This function disables IRQ interrupts by setting the I-bit in the CPSR.
tushki7 0:60d829a0353a 602 Can only be executed in Privileged modes.
tushki7 0:60d829a0353a 603 */
tushki7 0:60d829a0353a 604 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
tushki7 0:60d829a0353a 605 {
tushki7 0:60d829a0353a 606 uint32_t result;
tushki7 0:60d829a0353a 607
tushki7 0:60d829a0353a 608 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
tushki7 0:60d829a0353a 609 __ASM volatile ("cpsid i");
tushki7 0:60d829a0353a 610 return(result & 0x80);
tushki7 0:60d829a0353a 611 }
tushki7 0:60d829a0353a 612
tushki7 0:60d829a0353a 613
tushki7 0:60d829a0353a 614 /** \brief Get APSR Register
tushki7 0:60d829a0353a 615
tushki7 0:60d829a0353a 616 This function returns the content of the APSR Register.
tushki7 0:60d829a0353a 617
tushki7 0:60d829a0353a 618 \return APSR Register value
tushki7 0:60d829a0353a 619 */
tushki7 0:60d829a0353a 620 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
tushki7 0:60d829a0353a 621 {
tushki7 0:60d829a0353a 622 #if 1
tushki7 0:60d829a0353a 623 uint32_t result;
tushki7 0:60d829a0353a 624
tushki7 0:60d829a0353a 625 __ASM volatile ("mrs %0, apsr" : "=r" (result) );
tushki7 0:60d829a0353a 626 return (result);
tushki7 0:60d829a0353a 627 #else
tushki7 0:60d829a0353a 628 register uint32_t __regAPSR __ASM("apsr");
tushki7 0:60d829a0353a 629 return(__regAPSR);
tushki7 0:60d829a0353a 630 #endif
tushki7 0:60d829a0353a 631 }
tushki7 0:60d829a0353a 632
tushki7 0:60d829a0353a 633
tushki7 0:60d829a0353a 634 /** \brief Get CPSR Register
tushki7 0:60d829a0353a 635
tushki7 0:60d829a0353a 636 This function returns the content of the CPSR Register.
tushki7 0:60d829a0353a 637
tushki7 0:60d829a0353a 638 \return CPSR Register value
tushki7 0:60d829a0353a 639 */
tushki7 0:60d829a0353a 640 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
tushki7 0:60d829a0353a 641 {
tushki7 0:60d829a0353a 642 #if 1
tushki7 0:60d829a0353a 643 register uint32_t __regCPSR;
tushki7 0:60d829a0353a 644 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
tushki7 0:60d829a0353a 645 #else
tushki7 0:60d829a0353a 646 register uint32_t __regCPSR __ASM("cpsr");
tushki7 0:60d829a0353a 647 #endif
tushki7 0:60d829a0353a 648 return(__regCPSR);
tushki7 0:60d829a0353a 649 }
tushki7 0:60d829a0353a 650
tushki7 0:60d829a0353a 651 #if 0
tushki7 0:60d829a0353a 652 /** \brief Set Stack Pointer
tushki7 0:60d829a0353a 653
tushki7 0:60d829a0353a 654 This function assigns the given value to the current stack pointer.
tushki7 0:60d829a0353a 655
tushki7 0:60d829a0353a 656 \param [in] topOfStack Stack Pointer value to set
tushki7 0:60d829a0353a 657 */
tushki7 0:60d829a0353a 658 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
tushki7 0:60d829a0353a 659 {
tushki7 0:60d829a0353a 660 register uint32_t __regSP __ASM("sp");
tushki7 0:60d829a0353a 661 __regSP = topOfStack;
tushki7 0:60d829a0353a 662 }
tushki7 0:60d829a0353a 663 #endif
tushki7 0:60d829a0353a 664
tushki7 0:60d829a0353a 665 /** \brief Get link register
tushki7 0:60d829a0353a 666
tushki7 0:60d829a0353a 667 This function returns the value of the link register
tushki7 0:60d829a0353a 668
tushki7 0:60d829a0353a 669 \return Value of link register
tushki7 0:60d829a0353a 670 */
tushki7 0:60d829a0353a 671 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
tushki7 0:60d829a0353a 672 {
tushki7 0:60d829a0353a 673 register uint32_t __reglr __ASM("lr");
tushki7 0:60d829a0353a 674 return(__reglr);
tushki7 0:60d829a0353a 675 }
tushki7 0:60d829a0353a 676
tushki7 0:60d829a0353a 677 #if 0
tushki7 0:60d829a0353a 678 /** \brief Set link register
tushki7 0:60d829a0353a 679
tushki7 0:60d829a0353a 680 This function sets the value of the link register
tushki7 0:60d829a0353a 681
tushki7 0:60d829a0353a 682 \param [in] lr LR value to set
tushki7 0:60d829a0353a 683 */
tushki7 0:60d829a0353a 684 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
tushki7 0:60d829a0353a 685 {
tushki7 0:60d829a0353a 686 register uint32_t __reglr __ASM("lr");
tushki7 0:60d829a0353a 687 __reglr = lr;
tushki7 0:60d829a0353a 688 }
tushki7 0:60d829a0353a 689 #endif
tushki7 0:60d829a0353a 690
tushki7 0:60d829a0353a 691 /** \brief Set Process Stack Pointer
tushki7 0:60d829a0353a 692
tushki7 0:60d829a0353a 693 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
tushki7 0:60d829a0353a 694
tushki7 0:60d829a0353a 695 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
tushki7 0:60d829a0353a 696 */
tushki7 0:60d829a0353a 697 extern void __set_PSP(uint32_t topOfProcStack);
tushki7 0:60d829a0353a 698
tushki7 0:60d829a0353a 699 /** \brief Set User Mode
tushki7 0:60d829a0353a 700
tushki7 0:60d829a0353a 701 This function changes the processor state to User Mode
tushki7 0:60d829a0353a 702
tushki7 0:60d829a0353a 703 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
tushki7 0:60d829a0353a 704 */
tushki7 0:60d829a0353a 705 extern void __set_CPS_USR(void);
tushki7 0:60d829a0353a 706
tushki7 0:60d829a0353a 707 /** \brief Enable FIQ
tushki7 0:60d829a0353a 708
tushki7 0:60d829a0353a 709 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
tushki7 0:60d829a0353a 710 Can only be executed in Privileged modes.
tushki7 0:60d829a0353a 711 */
tushki7 0:60d829a0353a 712 #define __enable_fault_irq __enable_fiq
tushki7 0:60d829a0353a 713
tushki7 0:60d829a0353a 714
tushki7 0:60d829a0353a 715 /** \brief Disable FIQ
tushki7 0:60d829a0353a 716
tushki7 0:60d829a0353a 717 This function disables FIQ interrupts by setting the F-bit in the CPSR.
tushki7 0:60d829a0353a 718 Can only be executed in Privileged modes.
tushki7 0:60d829a0353a 719 */
tushki7 0:60d829a0353a 720 #define __disable_fault_irq __disable_fiq
tushki7 0:60d829a0353a 721
tushki7 0:60d829a0353a 722
tushki7 0:60d829a0353a 723 /** \brief Get FPSCR
tushki7 0:60d829a0353a 724
tushki7 0:60d829a0353a 725 This function returns the current value of the Floating Point Status/Control register.
tushki7 0:60d829a0353a 726
tushki7 0:60d829a0353a 727 \return Floating Point Status/Control register value
tushki7 0:60d829a0353a 728 */
tushki7 0:60d829a0353a 729 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
tushki7 0:60d829a0353a 730 {
tushki7 0:60d829a0353a 731 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
tushki7 0:60d829a0353a 732 #if 1
tushki7 0:60d829a0353a 733 uint32_t result;
tushki7 0:60d829a0353a 734
tushki7 0:60d829a0353a 735 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
tushki7 0:60d829a0353a 736 return (result);
tushki7 0:60d829a0353a 737 #else
tushki7 0:60d829a0353a 738 register uint32_t __regfpscr __ASM("fpscr");
tushki7 0:60d829a0353a 739 return(__regfpscr);
tushki7 0:60d829a0353a 740 #endif
tushki7 0:60d829a0353a 741 #else
tushki7 0:60d829a0353a 742 return(0);
tushki7 0:60d829a0353a 743 #endif
tushki7 0:60d829a0353a 744 }
tushki7 0:60d829a0353a 745
tushki7 0:60d829a0353a 746
tushki7 0:60d829a0353a 747 /** \brief Set FPSCR
tushki7 0:60d829a0353a 748
tushki7 0:60d829a0353a 749 This function assigns the given value to the Floating Point Status/Control register.
tushki7 0:60d829a0353a 750
tushki7 0:60d829a0353a 751 \param [in] fpscr Floating Point Status/Control value to set
tushki7 0:60d829a0353a 752 */
tushki7 0:60d829a0353a 753 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
tushki7 0:60d829a0353a 754 {
tushki7 0:60d829a0353a 755 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
tushki7 0:60d829a0353a 756 #if 1
tushki7 0:60d829a0353a 757 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
tushki7 0:60d829a0353a 758 #else
tushki7 0:60d829a0353a 759 register uint32_t __regfpscr __ASM("fpscr");
tushki7 0:60d829a0353a 760 __regfpscr = (fpscr);
tushki7 0:60d829a0353a 761 #endif
tushki7 0:60d829a0353a 762 #endif
tushki7 0:60d829a0353a 763 }
tushki7 0:60d829a0353a 764
tushki7 0:60d829a0353a 765 /** \brief Get FPEXC
tushki7 0:60d829a0353a 766
tushki7 0:60d829a0353a 767 This function returns the current value of the Floating Point Exception Control register.
tushki7 0:60d829a0353a 768
tushki7 0:60d829a0353a 769 \return Floating Point Exception Control register value
tushki7 0:60d829a0353a 770 */
tushki7 0:60d829a0353a 771 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
tushki7 0:60d829a0353a 772 {
tushki7 0:60d829a0353a 773 #if (__FPU_PRESENT == 1)
tushki7 0:60d829a0353a 774 #if 1
tushki7 0:60d829a0353a 775 uint32_t result;
tushki7 0:60d829a0353a 776
tushki7 0:60d829a0353a 777 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
tushki7 0:60d829a0353a 778 return (result);
tushki7 0:60d829a0353a 779 #else
tushki7 0:60d829a0353a 780 register uint32_t __regfpexc __ASM("fpexc");
tushki7 0:60d829a0353a 781 return(__regfpexc);
tushki7 0:60d829a0353a 782 #endif
tushki7 0:60d829a0353a 783 #else
tushki7 0:60d829a0353a 784 return(0);
tushki7 0:60d829a0353a 785 #endif
tushki7 0:60d829a0353a 786 }
tushki7 0:60d829a0353a 787
tushki7 0:60d829a0353a 788
tushki7 0:60d829a0353a 789 /** \brief Set FPEXC
tushki7 0:60d829a0353a 790
tushki7 0:60d829a0353a 791 This function assigns the given value to the Floating Point Exception Control register.
tushki7 0:60d829a0353a 792
tushki7 0:60d829a0353a 793 \param [in] fpscr Floating Point Exception Control value to set
tushki7 0:60d829a0353a 794 */
tushki7 0:60d829a0353a 795 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
tushki7 0:60d829a0353a 796 {
tushki7 0:60d829a0353a 797 #if (__FPU_PRESENT == 1)
tushki7 0:60d829a0353a 798 #if 1
tushki7 0:60d829a0353a 799 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
tushki7 0:60d829a0353a 800 #else
tushki7 0:60d829a0353a 801 register uint32_t __regfpexc __ASM("fpexc");
tushki7 0:60d829a0353a 802 __regfpexc = (fpexc);
tushki7 0:60d829a0353a 803 #endif
tushki7 0:60d829a0353a 804 #endif
tushki7 0:60d829a0353a 805 }
tushki7 0:60d829a0353a 806
tushki7 0:60d829a0353a 807 /** \brief Get CPACR
tushki7 0:60d829a0353a 808
tushki7 0:60d829a0353a 809 This function returns the current value of the Coprocessor Access Control register.
tushki7 0:60d829a0353a 810
tushki7 0:60d829a0353a 811 \return Coprocessor Access Control register value
tushki7 0:60d829a0353a 812 */
tushki7 0:60d829a0353a 813 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
tushki7 0:60d829a0353a 814 {
tushki7 0:60d829a0353a 815 #if 1
tushki7 0:60d829a0353a 816 register uint32_t __regCPACR;
tushki7 0:60d829a0353a 817 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
tushki7 0:60d829a0353a 818 #else
tushki7 0:60d829a0353a 819 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
tushki7 0:60d829a0353a 820 #endif
tushki7 0:60d829a0353a 821 return __regCPACR;
tushki7 0:60d829a0353a 822 }
tushki7 0:60d829a0353a 823
tushki7 0:60d829a0353a 824 /** \brief Set CPACR
tushki7 0:60d829a0353a 825
tushki7 0:60d829a0353a 826 This function assigns the given value to the Coprocessor Access Control register.
tushki7 0:60d829a0353a 827
tushki7 0:60d829a0353a 828 \param [in] cpacr Coporcessor Acccess Control value to set
tushki7 0:60d829a0353a 829 */
tushki7 0:60d829a0353a 830 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
tushki7 0:60d829a0353a 831 {
tushki7 0:60d829a0353a 832 #if 1
tushki7 0:60d829a0353a 833 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
tushki7 0:60d829a0353a 834 #else
tushki7 0:60d829a0353a 835 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
tushki7 0:60d829a0353a 836 __regCPACR = cpacr;
tushki7 0:60d829a0353a 837 #endif
tushki7 0:60d829a0353a 838 __ISB();
tushki7 0:60d829a0353a 839 }
tushki7 0:60d829a0353a 840
tushki7 0:60d829a0353a 841 /** \brief Get CBAR
tushki7 0:60d829a0353a 842
tushki7 0:60d829a0353a 843 This function returns the value of the Configuration Base Address register.
tushki7 0:60d829a0353a 844
tushki7 0:60d829a0353a 845 \return Configuration Base Address register value
tushki7 0:60d829a0353a 846 */
tushki7 0:60d829a0353a 847 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
tushki7 0:60d829a0353a 848 #if 1
tushki7 0:60d829a0353a 849 register uint32_t __regCBAR;
tushki7 0:60d829a0353a 850 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
tushki7 0:60d829a0353a 851 #else
tushki7 0:60d829a0353a 852 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
tushki7 0:60d829a0353a 853 #endif
tushki7 0:60d829a0353a 854 return(__regCBAR);
tushki7 0:60d829a0353a 855 }
tushki7 0:60d829a0353a 856
tushki7 0:60d829a0353a 857 /** \brief Get TTBR0
tushki7 0:60d829a0353a 858
tushki7 0:60d829a0353a 859 This function returns the value of the Configuration Base Address register.
tushki7 0:60d829a0353a 860
tushki7 0:60d829a0353a 861 \return Translation Table Base Register 0 value
tushki7 0:60d829a0353a 862 */
tushki7 0:60d829a0353a 863 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
tushki7 0:60d829a0353a 864 #if 1
tushki7 0:60d829a0353a 865 register uint32_t __regTTBR0;
tushki7 0:60d829a0353a 866 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
tushki7 0:60d829a0353a 867 #else
tushki7 0:60d829a0353a 868 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
tushki7 0:60d829a0353a 869 #endif
tushki7 0:60d829a0353a 870 return(__regTTBR0);
tushki7 0:60d829a0353a 871 }
tushki7 0:60d829a0353a 872
tushki7 0:60d829a0353a 873 /** \brief Set TTBR0
tushki7 0:60d829a0353a 874
tushki7 0:60d829a0353a 875 This function assigns the given value to the Coprocessor Access Control register.
tushki7 0:60d829a0353a 876
tushki7 0:60d829a0353a 877 \param [in] ttbr0 Translation Table Base Register 0 value to set
tushki7 0:60d829a0353a 878 */
tushki7 0:60d829a0353a 879 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
tushki7 0:60d829a0353a 880 #if 1
tushki7 0:60d829a0353a 881 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
tushki7 0:60d829a0353a 882 #else
tushki7 0:60d829a0353a 883 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
tushki7 0:60d829a0353a 884 __regTTBR0 = ttbr0;
tushki7 0:60d829a0353a 885 #endif
tushki7 0:60d829a0353a 886 __ISB();
tushki7 0:60d829a0353a 887 }
tushki7 0:60d829a0353a 888
tushki7 0:60d829a0353a 889 /** \brief Get DACR
tushki7 0:60d829a0353a 890
tushki7 0:60d829a0353a 891 This function returns the value of the Domain Access Control Register.
tushki7 0:60d829a0353a 892
tushki7 0:60d829a0353a 893 \return Domain Access Control Register value
tushki7 0:60d829a0353a 894 */
tushki7 0:60d829a0353a 895 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
tushki7 0:60d829a0353a 896 #if 1
tushki7 0:60d829a0353a 897 register uint32_t __regDACR;
tushki7 0:60d829a0353a 898 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
tushki7 0:60d829a0353a 899 #else
tushki7 0:60d829a0353a 900 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
tushki7 0:60d829a0353a 901 #endif
tushki7 0:60d829a0353a 902 return(__regDACR);
tushki7 0:60d829a0353a 903 }
tushki7 0:60d829a0353a 904
tushki7 0:60d829a0353a 905 /** \brief Set DACR
tushki7 0:60d829a0353a 906
tushki7 0:60d829a0353a 907 This function assigns the given value to the Coprocessor Access Control register.
tushki7 0:60d829a0353a 908
tushki7 0:60d829a0353a 909 \param [in] dacr Domain Access Control Register value to set
tushki7 0:60d829a0353a 910 */
tushki7 0:60d829a0353a 911 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
tushki7 0:60d829a0353a 912 #if 1
tushki7 0:60d829a0353a 913 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
tushki7 0:60d829a0353a 914 #else
tushki7 0:60d829a0353a 915 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
tushki7 0:60d829a0353a 916 __regDACR = dacr;
tushki7 0:60d829a0353a 917 #endif
tushki7 0:60d829a0353a 918 __ISB();
tushki7 0:60d829a0353a 919 }
tushki7 0:60d829a0353a 920
tushki7 0:60d829a0353a 921 /******************************** Cache and BTAC enable ****************************************************/
tushki7 0:60d829a0353a 922
tushki7 0:60d829a0353a 923 /** \brief Set SCTLR
tushki7 0:60d829a0353a 924
tushki7 0:60d829a0353a 925 This function assigns the given value to the System Control Register.
tushki7 0:60d829a0353a 926
tushki7 0:60d829a0353a 927 \param [in] sctlr System Control Register, value to set
tushki7 0:60d829a0353a 928 */
tushki7 0:60d829a0353a 929 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
tushki7 0:60d829a0353a 930 {
tushki7 0:60d829a0353a 931 #if 1
tushki7 0:60d829a0353a 932 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
tushki7 0:60d829a0353a 933 #else
tushki7 0:60d829a0353a 934 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
tushki7 0:60d829a0353a 935 __regSCTLR = sctlr;
tushki7 0:60d829a0353a 936 #endif
tushki7 0:60d829a0353a 937 }
tushki7 0:60d829a0353a 938
tushki7 0:60d829a0353a 939 /** \brief Get SCTLR
tushki7 0:60d829a0353a 940
tushki7 0:60d829a0353a 941 This function returns the value of the System Control Register.
tushki7 0:60d829a0353a 942
tushki7 0:60d829a0353a 943 \return System Control Register value
tushki7 0:60d829a0353a 944 */
tushki7 0:60d829a0353a 945 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
tushki7 0:60d829a0353a 946 #if 1
tushki7 0:60d829a0353a 947 register uint32_t __regSCTLR;
tushki7 0:60d829a0353a 948 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
tushki7 0:60d829a0353a 949 #else
tushki7 0:60d829a0353a 950 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
tushki7 0:60d829a0353a 951 #endif
tushki7 0:60d829a0353a 952 return(__regSCTLR);
tushki7 0:60d829a0353a 953 }
tushki7 0:60d829a0353a 954
tushki7 0:60d829a0353a 955 /** \brief Enable Caches
tushki7 0:60d829a0353a 956
tushki7 0:60d829a0353a 957 Enable Caches
tushki7 0:60d829a0353a 958 */
tushki7 0:60d829a0353a 959 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
tushki7 0:60d829a0353a 960 // Set I bit 12 to enable I Cache
tushki7 0:60d829a0353a 961 // Set C bit 2 to enable D Cache
tushki7 0:60d829a0353a 962 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
tushki7 0:60d829a0353a 963 }
tushki7 0:60d829a0353a 964
tushki7 0:60d829a0353a 965 /** \brief Disable Caches
tushki7 0:60d829a0353a 966
tushki7 0:60d829a0353a 967 Disable Caches
tushki7 0:60d829a0353a 968 */
tushki7 0:60d829a0353a 969 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
tushki7 0:60d829a0353a 970 // Clear I bit 12 to disable I Cache
tushki7 0:60d829a0353a 971 // Clear C bit 2 to disable D Cache
tushki7 0:60d829a0353a 972 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
tushki7 0:60d829a0353a 973 __ISB();
tushki7 0:60d829a0353a 974 }
tushki7 0:60d829a0353a 975
tushki7 0:60d829a0353a 976 /** \brief Enable BTAC
tushki7 0:60d829a0353a 977
tushki7 0:60d829a0353a 978 Enable BTAC
tushki7 0:60d829a0353a 979 */
tushki7 0:60d829a0353a 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
tushki7 0:60d829a0353a 981 // Set Z bit 11 to enable branch prediction
tushki7 0:60d829a0353a 982 __set_SCTLR( __get_SCTLR() | (1 << 11));
tushki7 0:60d829a0353a 983 __ISB();
tushki7 0:60d829a0353a 984 }
tushki7 0:60d829a0353a 985
tushki7 0:60d829a0353a 986 /** \brief Disable BTAC
tushki7 0:60d829a0353a 987
tushki7 0:60d829a0353a 988 Disable BTAC
tushki7 0:60d829a0353a 989 */
tushki7 0:60d829a0353a 990 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
tushki7 0:60d829a0353a 991 // Clear Z bit 11 to disable branch prediction
tushki7 0:60d829a0353a 992 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
tushki7 0:60d829a0353a 993 }
tushki7 0:60d829a0353a 994
tushki7 0:60d829a0353a 995
tushki7 0:60d829a0353a 996 /** \brief Enable MMU
tushki7 0:60d829a0353a 997
tushki7 0:60d829a0353a 998 Enable MMU
tushki7 0:60d829a0353a 999 */
tushki7 0:60d829a0353a 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
tushki7 0:60d829a0353a 1001 // Set M bit 0 to enable the MMU
tushki7 0:60d829a0353a 1002 // Set AFE bit to enable simplified access permissions model
tushki7 0:60d829a0353a 1003 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
tushki7 0:60d829a0353a 1004 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
tushki7 0:60d829a0353a 1005 __ISB();
tushki7 0:60d829a0353a 1006 }
tushki7 0:60d829a0353a 1007
tushki7 0:60d829a0353a 1008 /** \brief Enable MMU
tushki7 0:60d829a0353a 1009
tushki7 0:60d829a0353a 1010 Enable MMU
tushki7 0:60d829a0353a 1011 */
tushki7 0:60d829a0353a 1012 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
tushki7 0:60d829a0353a 1013 // Clear M bit 0 to disable the MMU
tushki7 0:60d829a0353a 1014 __set_SCTLR( __get_SCTLR() & ~1);
tushki7 0:60d829a0353a 1015 __ISB();
tushki7 0:60d829a0353a 1016 }
tushki7 0:60d829a0353a 1017
tushki7 0:60d829a0353a 1018 /******************************** TLB maintenance operations ************************************************/
tushki7 0:60d829a0353a 1019 /** \brief Invalidate the whole tlb
tushki7 0:60d829a0353a 1020
tushki7 0:60d829a0353a 1021 TLBIALL. Invalidate the whole tlb
tushki7 0:60d829a0353a 1022 */
tushki7 0:60d829a0353a 1023
tushki7 0:60d829a0353a 1024 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
tushki7 0:60d829a0353a 1025 #if 1
tushki7 0:60d829a0353a 1026 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
tushki7 0:60d829a0353a 1027 #else
tushki7 0:60d829a0353a 1028 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
tushki7 0:60d829a0353a 1029 __TLBIALL = 0;
tushki7 0:60d829a0353a 1030 #endif
tushki7 0:60d829a0353a 1031 __DSB();
tushki7 0:60d829a0353a 1032 __ISB();
tushki7 0:60d829a0353a 1033 }
tushki7 0:60d829a0353a 1034
tushki7 0:60d829a0353a 1035 /******************************** BTB maintenance operations ************************************************/
tushki7 0:60d829a0353a 1036 /** \brief Invalidate entire branch predictor array
tushki7 0:60d829a0353a 1037
tushki7 0:60d829a0353a 1038 BPIALL. Branch Predictor Invalidate All.
tushki7 0:60d829a0353a 1039 */
tushki7 0:60d829a0353a 1040
tushki7 0:60d829a0353a 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
tushki7 0:60d829a0353a 1042 #if 1
tushki7 0:60d829a0353a 1043 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
tushki7 0:60d829a0353a 1044 #else
tushki7 0:60d829a0353a 1045 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
tushki7 0:60d829a0353a 1046 __BPIALL = 0;
tushki7 0:60d829a0353a 1047 #endif
tushki7 0:60d829a0353a 1048 __DSB(); //ensure completion of the invalidation
tushki7 0:60d829a0353a 1049 __ISB(); //ensure instruction fetch path sees new state
tushki7 0:60d829a0353a 1050 }
tushki7 0:60d829a0353a 1051
tushki7 0:60d829a0353a 1052
tushki7 0:60d829a0353a 1053 /******************************** L1 cache operations ******************************************************/
tushki7 0:60d829a0353a 1054
tushki7 0:60d829a0353a 1055 /** \brief Invalidate the whole I$
tushki7 0:60d829a0353a 1056
tushki7 0:60d829a0353a 1057 ICIALLU. Instruction Cache Invalidate All to PoU
tushki7 0:60d829a0353a 1058 */
tushki7 0:60d829a0353a 1059 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
tushki7 0:60d829a0353a 1060 #if 1
tushki7 0:60d829a0353a 1061 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
tushki7 0:60d829a0353a 1062 #else
tushki7 0:60d829a0353a 1063 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
tushki7 0:60d829a0353a 1064 __ICIALLU = 0;
tushki7 0:60d829a0353a 1065 #endif
tushki7 0:60d829a0353a 1066 __DSB(); //ensure completion of the invalidation
tushki7 0:60d829a0353a 1067 __ISB(); //ensure instruction fetch path sees new I cache state
tushki7 0:60d829a0353a 1068 }
tushki7 0:60d829a0353a 1069
tushki7 0:60d829a0353a 1070 /** \brief Clean D$ by MVA
tushki7 0:60d829a0353a 1071
tushki7 0:60d829a0353a 1072 DCCMVAC. Data cache clean by MVA to PoC
tushki7 0:60d829a0353a 1073 */
tushki7 0:60d829a0353a 1074 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
tushki7 0:60d829a0353a 1075 #if 1
tushki7 0:60d829a0353a 1076 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
tushki7 0:60d829a0353a 1077 #else
tushki7 0:60d829a0353a 1078 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
tushki7 0:60d829a0353a 1079 __DCCMVAC = (uint32_t)va;
tushki7 0:60d829a0353a 1080 #endif
tushki7 0:60d829a0353a 1081 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
tushki7 0:60d829a0353a 1082 }
tushki7 0:60d829a0353a 1083
tushki7 0:60d829a0353a 1084 /** \brief Invalidate D$ by MVA
tushki7 0:60d829a0353a 1085
tushki7 0:60d829a0353a 1086 DCIMVAC. Data cache invalidate by MVA to PoC
tushki7 0:60d829a0353a 1087 */
tushki7 0:60d829a0353a 1088 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
tushki7 0:60d829a0353a 1089 #if 1
tushki7 0:60d829a0353a 1090 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
tushki7 0:60d829a0353a 1091 #else
tushki7 0:60d829a0353a 1092 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
tushki7 0:60d829a0353a 1093 __DCIMVAC = (uint32_t)va;
tushki7 0:60d829a0353a 1094 #endif
tushki7 0:60d829a0353a 1095 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
tushki7 0:60d829a0353a 1096 }
tushki7 0:60d829a0353a 1097
tushki7 0:60d829a0353a 1098 /** \brief Clean and Invalidate D$ by MVA
tushki7 0:60d829a0353a 1099
tushki7 0:60d829a0353a 1100 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
tushki7 0:60d829a0353a 1101 */
tushki7 0:60d829a0353a 1102 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
tushki7 0:60d829a0353a 1103 #if 1
tushki7 0:60d829a0353a 1104 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
tushki7 0:60d829a0353a 1105 #else
tushki7 0:60d829a0353a 1106 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
tushki7 0:60d829a0353a 1107 __DCCIMVAC = (uint32_t)va;
tushki7 0:60d829a0353a 1108 #endif
tushki7 0:60d829a0353a 1109 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
tushki7 0:60d829a0353a 1110 }
tushki7 0:60d829a0353a 1111
tushki7 0:60d829a0353a 1112 /** \brief
tushki7 0:60d829a0353a 1113 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
tushki7 0:60d829a0353a 1114 */
tushki7 0:60d829a0353a 1115
tushki7 0:60d829a0353a 1116 /** \brief __v7_all_cache - helper function
tushki7 0:60d829a0353a 1117
tushki7 0:60d829a0353a 1118 */
tushki7 0:60d829a0353a 1119
tushki7 0:60d829a0353a 1120 extern void __v7_all_cache(uint32_t op);
tushki7 0:60d829a0353a 1121
tushki7 0:60d829a0353a 1122
tushki7 0:60d829a0353a 1123 /** \brief Invalidate the whole D$
tushki7 0:60d829a0353a 1124
tushki7 0:60d829a0353a 1125 DCISW. Invalidate by Set/Way
tushki7 0:60d829a0353a 1126 */
tushki7 0:60d829a0353a 1127
tushki7 0:60d829a0353a 1128 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
tushki7 0:60d829a0353a 1129 __v7_all_cache(0);
tushki7 0:60d829a0353a 1130 }
tushki7 0:60d829a0353a 1131
tushki7 0:60d829a0353a 1132 /** \brief Clean the whole D$
tushki7 0:60d829a0353a 1133
tushki7 0:60d829a0353a 1134 DCCSW. Clean by Set/Way
tushki7 0:60d829a0353a 1135 */
tushki7 0:60d829a0353a 1136
tushki7 0:60d829a0353a 1137 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
tushki7 0:60d829a0353a 1138 __v7_all_cache(1);
tushki7 0:60d829a0353a 1139 }
tushki7 0:60d829a0353a 1140
tushki7 0:60d829a0353a 1141 /** \brief Clean and invalidate the whole D$
tushki7 0:60d829a0353a 1142
tushki7 0:60d829a0353a 1143 DCCISW. Clean and Invalidate by Set/Way
tushki7 0:60d829a0353a 1144 */
tushki7 0:60d829a0353a 1145
tushki7 0:60d829a0353a 1146 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
tushki7 0:60d829a0353a 1147 __v7_all_cache(2);
tushki7 0:60d829a0353a 1148 }
tushki7 0:60d829a0353a 1149
tushki7 0:60d829a0353a 1150 #include "core_ca_mmu.h"
tushki7 0:60d829a0353a 1151
tushki7 0:60d829a0353a 1152 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
tushki7 0:60d829a0353a 1153
tushki7 0:60d829a0353a 1154 #error TASKING Compiler support not implemented for Cortex-A
tushki7 0:60d829a0353a 1155
tushki7 0:60d829a0353a 1156 #endif
tushki7 0:60d829a0353a 1157
tushki7 0:60d829a0353a 1158 /*@} end of CMSIS_Core_RegAccFunctions */
tushki7 0:60d829a0353a 1159
tushki7 0:60d829a0353a 1160
tushki7 0:60d829a0353a 1161 #endif /* __CORE_CAFUNC_H__ */