FRDM_K64F_LCD - A simple 128x32 graphical LCD program to quicksta…

Users » tushki7 » Code » FRDM_K64F_LCD

A simple 128x32 graphical LCD program to quickstart with LCD on ARM mbed IoT Starter Kit. This requires mbed Applciation Shield with FRDM-K64F platform.

Dependencies: C12832

mbed/TARGET_SSCI824/LPC82x.h@0:60d829a0353a, 2015-04-11 (annotated)

Committer:: tushki7
Date:: Sat Apr 11 04:08:13 2015 +0000
Revision:: 0:60d829a0353a

A simple 128x32 LCD program to quickstart with LCD on ARM mbed IoT Starter kit. Mbed Application Shield is required if using FRDM-K64F platform.

Who changed what in which revision?

User	Revision	Line number	New contents of line
tushki7	0:60d829a0353a	1
tushki7	0:60d829a0353a	2	/**************************************************************************************************//
tushki7	0:60d829a0353a	3	* @file LPC82x.h
tushki7	0:60d829a0353a	4	*
tushki7	0:60d829a0353a	5	* @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
tushki7	0:60d829a0353a	6	* LPC82x from .
tushki7	0:60d829a0353a	7	*
tushki7	0:60d829a0353a	8	* @version V0.4
tushki7	0:60d829a0353a	9	* @date 17. June 2014
tushki7	0:60d829a0353a	10	*
tushki7	0:60d829a0353a	11	* @note Generated with SVDConv V2.80
tushki7	0:60d829a0353a	12	* from CMSIS SVD File 'LPC82x.svd' Version 0.4,
tushki7	0:60d829a0353a	13	*******************************************************************************************************/
tushki7	0:60d829a0353a	14
tushki7	0:60d829a0353a	15
tushki7	0:60d829a0353a	16
tushki7	0:60d829a0353a	17	/** @addtogroup (null)
tushki7	0:60d829a0353a	18	* @{
tushki7	0:60d829a0353a	19	*/
tushki7	0:60d829a0353a	20
tushki7	0:60d829a0353a	21	/** @addtogroup LPC82x
tushki7	0:60d829a0353a	22	* @{
tushki7	0:60d829a0353a	23	*/
tushki7	0:60d829a0353a	24
tushki7	0:60d829a0353a	25	#ifndef LPC82X_H
tushki7	0:60d829a0353a	26	#define LPC82X_H
tushki7	0:60d829a0353a	27
tushki7	0:60d829a0353a	28	#ifdef __cplusplus
tushki7	0:60d829a0353a	29	extern "C" {
tushki7	0:60d829a0353a	30	#endif
tushki7	0:60d829a0353a	31
tushki7	0:60d829a0353a	32
tushki7	0:60d829a0353a	33	/* ------------------------- Interrupt Number Definition ------------------------ */
tushki7	0:60d829a0353a	34
tushki7	0:60d829a0353a	35	typedef enum {
tushki7	0:60d829a0353a	36	/* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
tushki7	0:60d829a0353a	37	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
tushki7	0:60d829a0353a	38	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
tushki7	0:60d829a0353a	39	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
tushki7	0:60d829a0353a	40	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
tushki7	0:60d829a0353a	41	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
tushki7	0:60d829a0353a	42	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
tushki7	0:60d829a0353a	43	SysTick_IRQn = -1, /!< 15 System Tick Timer /
tushki7	0:60d829a0353a	44	/* ---------------------- LPC82x Specific Interrupt Numbers --------------------- */
tushki7	0:60d829a0353a	45	SPI0_IRQn = 0, /!< 0 SPI0 /
tushki7	0:60d829a0353a	46	SPI1_IRQn = 1, /!< 1 SPI1 /
tushki7	0:60d829a0353a	47	UART0_IRQn = 3, /!< 3 UART0 /
tushki7	0:60d829a0353a	48	UART1_IRQn = 4, /!< 4 UART1 /
tushki7	0:60d829a0353a	49	UART2_IRQn = 5, /!< 5 UART2 /
tushki7	0:60d829a0353a	50	I2C1_IRQn = 7, /!< 7 I2C1 /
tushki7	0:60d829a0353a	51	I2C0_IRQn = 8, /!< 8 I2C0 /
tushki7	0:60d829a0353a	52	SCT_IRQn = 9, /!< 9 SCT /
tushki7	0:60d829a0353a	53	MRT_IRQn = 10, /!< 10 MRT /
tushki7	0:60d829a0353a	54	CMP_IRQn = 11, /!< 11 CMP /
tushki7	0:60d829a0353a	55	WDT_IRQn = 12, /!< 12 WDT /
tushki7	0:60d829a0353a	56	BOD_IRQn = 13, /!< 13 BOD /
tushki7	0:60d829a0353a	57	FLASH_IRQn = 14, /!< 14 FLASH /
tushki7	0:60d829a0353a	58	WKT_IRQn = 15, /!< 15 WKT /
tushki7	0:60d829a0353a	59	ADC_SEQA_IRQn = 16, /!< 16 ADC_SEQA /
tushki7	0:60d829a0353a	60	ADC_SEQB_IRQn = 17, /!< 17 ADC_SEQB /
tushki7	0:60d829a0353a	61	ADC_THCMP_IRQn = 18, /!< 18 ADC_THCMP /
tushki7	0:60d829a0353a	62	ADC_OVR_IRQn = 19, /!< 19 ADC_OVR /
tushki7	0:60d829a0353a	63	DMA_IRQn = 20, /!< 20 DMA /
tushki7	0:60d829a0353a	64	I2C2_IRQn = 21, /!< 21 I2C2 /
tushki7	0:60d829a0353a	65	I2C3_IRQn = 22, /!< 22 I2C3 /
tushki7	0:60d829a0353a	66	PIN_INT0_IRQn = 24, /!< 24 PIN_INT0 /
tushki7	0:60d829a0353a	67	PIN_INT1_IRQn = 25, /!< 25 PIN_INT1 /
tushki7	0:60d829a0353a	68	PIN_INT2_IRQn = 26, /!< 26 PIN_INT2 /
tushki7	0:60d829a0353a	69	PIN_INT3_IRQn = 27, /!< 27 PIN_INT3 /
tushki7	0:60d829a0353a	70	PIN_INT4_IRQn = 28, /!< 28 PIN_INT4 /
tushki7	0:60d829a0353a	71	PIN_INT5_IRQn = 29, /!< 29 PIN_INT5 /
tushki7	0:60d829a0353a	72	PIN_INT6_IRQn = 30, /!< 30 PIN_INT6 /
tushki7	0:60d829a0353a	73	PIN_INT7_IRQn = 31 /!< 31 PIN_INT7 /
tushki7	0:60d829a0353a	74	} IRQn_Type;
tushki7	0:60d829a0353a	75
tushki7	0:60d829a0353a	76
tushki7	0:60d829a0353a	77	/** @addtogroup Configuration_of_CMSIS
tushki7	0:60d829a0353a	78	* @{
tushki7	0:60d829a0353a	79	*/
tushki7	0:60d829a0353a	80
tushki7	0:60d829a0353a	81
tushki7	0:60d829a0353a	82	/* ================================================================================ */
tushki7	0:60d829a0353a	83	/* ================ Processor and Core Peripheral Section ================ */
tushki7	0:60d829a0353a	84	/* ================================================================================ */
tushki7	0:60d829a0353a	85
tushki7	0:60d829a0353a	86	/* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
tushki7	0:60d829a0353a	87	#define __CM0PLUS_REV 0x0001 /!< Cortex-M0PLUS Core Revision /
tushki7	0:60d829a0353a	88	#define __MPU_PRESENT 0 /!< MPU present or not /
tushki7	0:60d829a0353a	89	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
tushki7	0:60d829a0353a	90	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
tushki7	0:60d829a0353a	91	#define __VTOR_PRESENT 1 /!< Set to 1 if CPU supports Vector Table Offset Register /
tushki7	0:60d829a0353a	92	/** @} / / End of group Configuration_of_CMSIS */
tushki7	0:60d829a0353a	93
tushki7	0:60d829a0353a	94	#include "core_cm0plus.h" /!< Cortex-M0PLUS processor and core peripherals /
tushki7	0:60d829a0353a	95	#include "system_LPC82x.h" /!< LPC82x System /
tushki7	0:60d829a0353a	96
tushki7	0:60d829a0353a	97
tushki7	0:60d829a0353a	98	/* ================================================================================ */
tushki7	0:60d829a0353a	99	/* ================ Device Specific Peripheral Section ================ */
tushki7	0:60d829a0353a	100	/* ================================================================================ */
tushki7	0:60d829a0353a	101
tushki7	0:60d829a0353a	102
tushki7	0:60d829a0353a	103	/** @addtogroup Device_Peripheral_Registers
tushki7	0:60d829a0353a	104	* @{
tushki7	0:60d829a0353a	105	*/
tushki7	0:60d829a0353a	106
tushki7	0:60d829a0353a	107
tushki7	0:60d829a0353a	108	/* ------------------- Start of section using anonymous unions ------------------ */
tushki7	0:60d829a0353a	109	#if defined(__CC_ARM)
tushki7	0:60d829a0353a	110	#pragma push
tushki7	0:60d829a0353a	111	#pragma anon_unions
tushki7	0:60d829a0353a	112	#elif defined(__ICCARM__)
tushki7	0:60d829a0353a	113	#pragma language=extended
tushki7	0:60d829a0353a	114	#elif defined(__GNUC__)
tushki7	0:60d829a0353a	115	/* anonymous unions are enabled by default */
tushki7	0:60d829a0353a	116	#elif defined(__TMS470__)
tushki7	0:60d829a0353a	117	/* anonymous unions are enabled by default */
tushki7	0:60d829a0353a	118	#elif defined(__TASKING__)
tushki7	0:60d829a0353a	119	#pragma warning 586
tushki7	0:60d829a0353a	120	#else
tushki7	0:60d829a0353a	121	#warning Not supported compiler type
tushki7	0:60d829a0353a	122	#endif
tushki7	0:60d829a0353a	123
tushki7	0:60d829a0353a	124
tushki7	0:60d829a0353a	125
tushki7	0:60d829a0353a	126	/* ================================================================================ */
tushki7	0:60d829a0353a	127	/* ================ WWDT ================ */
tushki7	0:60d829a0353a	128	/* ================================================================================ */
tushki7	0:60d829a0353a	129
tushki7	0:60d829a0353a	130
tushki7	0:60d829a0353a	131	/**
tushki7	0:60d829a0353a	132	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
tushki7	0:60d829a0353a	133	*/
tushki7	0:60d829a0353a	134
tushki7	0:60d829a0353a	135	typedef struct { /!< (@ 0x40000000) WWDT Structure /
tushki7	0:60d829a0353a	136	__IO uint32_t MOD; /*!< (@ 0x40000000) Watchdog mode register. This register contains
tushki7	0:60d829a0353a	137	the basic mode and status of the Watchdog Timer. */
tushki7	0:60d829a0353a	138	__IO uint32_t TC; /*!< (@ 0x40000004) Watchdog timer constant register. This 24-bit
tushki7	0:60d829a0353a	139	register determines the time-out value. */
tushki7	0:60d829a0353a	140	__O uint32_t FEED; /*!< (@ 0x40000008) Watchdog feed sequence register. Writing 0xAA
tushki7	0:60d829a0353a	141	followed by 0x55 to this register reloads the Watchdog timer
tushki7	0:60d829a0353a	142	with the value contained in WDTC. */
tushki7	0:60d829a0353a	143	__I uint32_t TV; /*!< (@ 0x4000000C) Watchdog timer value register. This 24-bit register
tushki7	0:60d829a0353a	144	reads out the current value of the Watchdog timer. */
tushki7	0:60d829a0353a	145	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	146	__IO uint32_t WARNINT; /!< (@ 0x40000014) Watchdog Warning Interrupt compare value. /
tushki7	0:60d829a0353a	147	__IO uint32_t WINDOW; /!< (@ 0x40000018) Watchdog Window compare value. /
tushki7	0:60d829a0353a	148	} LPC_WWDT_Type;
tushki7	0:60d829a0353a	149
tushki7	0:60d829a0353a	150
tushki7	0:60d829a0353a	151	/* ================================================================================ */
tushki7	0:60d829a0353a	152	/* ================ MRT ================ */
tushki7	0:60d829a0353a	153	/* ================================================================================ */
tushki7	0:60d829a0353a	154
tushki7	0:60d829a0353a	155
tushki7	0:60d829a0353a	156	/**
tushki7	0:60d829a0353a	157	* @brief Multi-Rate Timer (MRT) (MRT)
tushki7	0:60d829a0353a	158	*/
tushki7	0:60d829a0353a	159
tushki7	0:60d829a0353a	160	typedef struct { /!< (@ 0x40004000) MRT Structure /
tushki7	0:60d829a0353a	161	__IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
tushki7	0:60d829a0353a	162	is loaded into the TIMER0 register. */
tushki7	0:60d829a0353a	163	__I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
tushki7	0:60d829a0353a	164	value of the down-counter. */
tushki7	0:60d829a0353a	165	__IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
tushki7	0:60d829a0353a	166	the MRT0 modes. */
tushki7	0:60d829a0353a	167	__IO uint32_t STAT0; /!< (@ 0x4000400C) MRT0 Status register. /
tushki7	0:60d829a0353a	168	__IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
tushki7	0:60d829a0353a	169	is loaded into the TIMER0 register. */
tushki7	0:60d829a0353a	170	__I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
tushki7	0:60d829a0353a	171	value of the down-counter. */
tushki7	0:60d829a0353a	172	__IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
tushki7	0:60d829a0353a	173	the MRT0 modes. */
tushki7	0:60d829a0353a	174	__IO uint32_t STAT1; /!< (@ 0x4000401C) MRT0 Status register. /
tushki7	0:60d829a0353a	175	__IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
tushki7	0:60d829a0353a	176	is loaded into the TIMER0 register. */
tushki7	0:60d829a0353a	177	__I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
tushki7	0:60d829a0353a	178	value of the down-counter. */
tushki7	0:60d829a0353a	179	__IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
tushki7	0:60d829a0353a	180	the MRT0 modes. */
tushki7	0:60d829a0353a	181	__IO uint32_t STAT2; /!< (@ 0x4000402C) MRT0 Status register. /
tushki7	0:60d829a0353a	182	__IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
tushki7	0:60d829a0353a	183	is loaded into the TIMER0 register. */
tushki7	0:60d829a0353a	184	__I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
tushki7	0:60d829a0353a	185	value of the down-counter. */
tushki7	0:60d829a0353a	186	__IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
tushki7	0:60d829a0353a	187	the MRT0 modes. */
tushki7	0:60d829a0353a	188	__IO uint32_t STAT3; /!< (@ 0x4000403C) MRT0 Status register. /
tushki7	0:60d829a0353a	189	__I uint32_t RESERVED0[45];
tushki7	0:60d829a0353a	190	__I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
tushki7	0:60d829a0353a	191	the number of the first idle channel. */
tushki7	0:60d829a0353a	192	__IO uint32_t IRQ_FLAG; /!< (@ 0x400040F8) Global interrupt flag register /
tushki7	0:60d829a0353a	193	} LPC_MRT_Type;
tushki7	0:60d829a0353a	194
tushki7	0:60d829a0353a	195
tushki7	0:60d829a0353a	196	/* ================================================================================ */
tushki7	0:60d829a0353a	197	/* ================ WKT ================ */
tushki7	0:60d829a0353a	198	/* ================================================================================ */
tushki7	0:60d829a0353a	199
tushki7	0:60d829a0353a	200
tushki7	0:60d829a0353a	201	/**
tushki7	0:60d829a0353a	202	* @brief Self wake-up timer (WKT) (WKT)
tushki7	0:60d829a0353a	203	*/
tushki7	0:60d829a0353a	204
tushki7	0:60d829a0353a	205	typedef struct { /!< (@ 0x40008000) WKT Structure /
tushki7	0:60d829a0353a	206	__IO uint32_t CTRL; /!< (@ 0x40008000) Self wake-up timer control register. /
tushki7	0:60d829a0353a	207	__I uint32_t RESERVED0[2];
tushki7	0:60d829a0353a	208	__IO uint32_t COUNT; /!< (@ 0x4000800C) Counter register. /
tushki7	0:60d829a0353a	209	} LPC_WKT_Type;
tushki7	0:60d829a0353a	210
tushki7	0:60d829a0353a	211
tushki7	0:60d829a0353a	212	/* ================================================================================ */
tushki7	0:60d829a0353a	213	/* ================ SWM ================ */
tushki7	0:60d829a0353a	214	/* ================================================================================ */
tushki7	0:60d829a0353a	215
tushki7	0:60d829a0353a	216
tushki7	0:60d829a0353a	217	/**
tushki7	0:60d829a0353a	218	* @brief Switch matrix (SWM) (SWM)
tushki7	0:60d829a0353a	219	*/
tushki7	0:60d829a0353a	220
tushki7	0:60d829a0353a	221	typedef struct { /!< (@ 0x4000C000) SWM Structure /
tushki7	0:60d829a0353a	222	union {
tushki7	0:60d829a0353a	223	__IO uint32_t PINASSIGN[12];
tushki7	0:60d829a0353a	224	struct {
tushki7	0:60d829a0353a	225	__IO uint32_t PINASSIGN0; /*!< (@ 0x4000C000) Pin assign register 0. Assign movable functions
tushki7	0:60d829a0353a	226	U0_TXD, U0_RXD, U0_RTS, U0_CTS. */
tushki7	0:60d829a0353a	227	__IO uint32_t PINASSIGN1; /*!< (@ 0x4000C004) Pin assign register 1. Assign movable functions
tushki7	0:60d829a0353a	228	U0_SCLK, U1_TXD, U1_RXD, U1_RTS. */
tushki7	0:60d829a0353a	229	__IO uint32_t PINASSIGN2; /*!< (@ 0x4000C008) Pin assign register 2. Assign movable functions
tushki7	0:60d829a0353a	230	U1_CTS, U1_SCLK, U2_TXD, U2_RXD. */
tushki7	0:60d829a0353a	231	__IO uint32_t PINASSIGN3; /*!< (@ 0x4000C00C) Pin assign register 3. Assign movable function
tushki7	0:60d829a0353a	232	U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. */
tushki7	0:60d829a0353a	233	__IO uint32_t PINASSIGN4; /*!< (@ 0x4000C010) Pin assign register 4. Assign movable functions
tushki7	0:60d829a0353a	234	SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1. */
tushki7	0:60d829a0353a	235	__IO uint32_t PINASSIGN5; /*!< (@ 0x4000C014) Pin assign register 5. Assign movable functions
tushki7	0:60d829a0353a	236	SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI */
tushki7	0:60d829a0353a	237	__IO uint32_t PINASSIGN6; /*!< (@ 0x4000C018) Pin assign register 6. Assign movable functions
tushki7	0:60d829a0353a	238	SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0. */
tushki7	0:60d829a0353a	239	__IO uint32_t PINASSIGN7; /*!< (@ 0x4000C01C) Pin assign register 7. Assign movable functions
tushki7	0:60d829a0353a	240	SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0. */
tushki7	0:60d829a0353a	241	__IO uint32_t PINASSIGN8; /*!< (@ 0x4000C020) Pin assign register 8. Assign movable functions
tushki7	0:60d829a0353a	242	SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4. */
tushki7	0:60d829a0353a	243	__IO uint32_t PINASSIGN9; /*!< (@ 0x4000C024) Pin assign register 9. Assign movable functions
tushki7	0:60d829a0353a	244	SCT_OUT5, I2C1_SDA, I2C1_SCL, I2C2_SDA. */
tushki7	0:60d829a0353a	245	__IO uint32_t PINASSIGN10; /*!< (@ 0x4000C028) Pin assign register 10. Assign movable functions
tushki7	0:60d829a0353a	246	I2C2_SCL, I2C3_SDA, I2C3_SCL, ADC_PINTRIG0. */
tushki7	0:60d829a0353a	247	__IO uint32_t PINASSIGN11; /*!< (@ 0x4000C02C) Pin assign register 11. Assign movable functions
tushki7	0:60d829a0353a	248	ADC_PINTRIG1, ACMP_O, CLKOUT, GPIO_INT_BMAT */
tushki7	0:60d829a0353a	249	};
tushki7	0:60d829a0353a	250	};
tushki7	0:60d829a0353a	251	__I uint32_t RESERVED0[100];
tushki7	0:60d829a0353a	252	__IO uint32_t PINENABLE0; /*!< (@ 0x4000C1C0) Pin enable register 0. Enables fixed-pin functions
tushki7	0:60d829a0353a	253	ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN,
tushki7	0:60d829a0353a	254	VDDCMP. */
tushki7	0:60d829a0353a	255	} LPC_SWM_Type;
tushki7	0:60d829a0353a	256
tushki7	0:60d829a0353a	257
tushki7	0:60d829a0353a	258	/* ================================================================================ */
tushki7	0:60d829a0353a	259	/* ================ ADC ================ */
tushki7	0:60d829a0353a	260	/* ================================================================================ */
tushki7	0:60d829a0353a	261
tushki7	0:60d829a0353a	262
tushki7	0:60d829a0353a	263	/**
tushki7	0:60d829a0353a	264	* @brief 12-bit Analog-to-Digital Converter (ADC) (ADC)
tushki7	0:60d829a0353a	265	*/
tushki7	0:60d829a0353a	266
tushki7	0:60d829a0353a	267	typedef struct { /!< (@ 0x4001C000) ADC Structure /
tushki7	0:60d829a0353a	268	__IO uint32_t CTRL; /*!< (@ 0x4001C000) A/D Control Register. Contains the clock divide
tushki7	0:60d829a0353a	269	value, enable bits for each sequence and the A/D power-down
tushki7	0:60d829a0353a	270	bit. */
tushki7	0:60d829a0353a	271	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	272	__IO uint32_t SEQA_CTRL; /*!< (@ 0x4001C008) A/D Conversion Sequence-A control Register: Controls
tushki7	0:60d829a0353a	273	triggering and channel selection for conversion sequence-A.
tushki7	0:60d829a0353a	274	Also specifies interrupt mode for sequence-A. */
tushki7	0:60d829a0353a	275	__IO uint32_t SEQB_CTRL; /*!< (@ 0x4001C00C) A/D Conversion Sequence-B Control Register: Controls
tushki7	0:60d829a0353a	276	triggering and channel selection for conversion sequence-B.
tushki7	0:60d829a0353a	277	Also specifies interrupt mode for sequence-B. */
tushki7	0:60d829a0353a	278	__IO uint32_t SEQA_GDAT; /*!< (@ 0x4001C010) A/D Sequence-A Global Data Register. This register
tushki7	0:60d829a0353a	279	contains the result of the most recent A/D conversion performed
tushki7	0:60d829a0353a	280	under sequence-A */
tushki7	0:60d829a0353a	281	__IO uint32_t SEQB_GDAT; /*!< (@ 0x4001C014) A/D Sequence-B Global Data Register. This register
tushki7	0:60d829a0353a	282	contains the result of the most recent A/D conversion performed
tushki7	0:60d829a0353a	283	under sequence-B */
tushki7	0:60d829a0353a	284	__I uint32_t RESERVED1[2];
tushki7	0:60d829a0353a	285	__I uint32_t DAT0; /*!< (@ 0x4001C020) A/D Channel 0 Data Register. This register contains
tushki7	0:60d829a0353a	286	the result of the most recent conversion completed on channel
tushki7	0:60d829a0353a	287	0. */
tushki7	0:60d829a0353a	288	__I uint32_t DAT1; /*!< (@ 0x4001C024) A/D Channel 0 Data Register. This register contains
tushki7	0:60d829a0353a	289	the result of the most recent conversion completed on channel
tushki7	0:60d829a0353a	290	0. */
tushki7	0:60d829a0353a	291	__I uint32_t DAT2; /*!< (@ 0x4001C028) A/D Channel 0 Data Register. This register contains
tushki7	0:60d829a0353a	292	the result of the most recent conversion completed on channel
tushki7	0:60d829a0353a	293	0. */
tushki7	0:60d829a0353a	294	__I uint32_t DAT3; /*!< (@ 0x4001C02C) A/D Channel 0 Data Register. This register contains
tushki7	0:60d829a0353a	295	the result of the most recent conversion completed on channel
tushki7	0:60d829a0353a	296	0. */
tushki7	0:60d829a0353a	297	__I uint32_t DAT4; /*!< (@ 0x4001C030) A/D Channel 0 Data Register. This register contains
tushki7	0:60d829a0353a	298	the result of the most recent conversion completed on channel
tushki7	0:60d829a0353a	299	0. */
tushki7	0:60d829a0353a	300	__I uint32_t DAT5; /*!< (@ 0x4001C034) A/D Channel 0 Data Register. This register contains
tushki7	0:60d829a0353a	301	the result of the most recent conversion completed on channel
tushki7	0:60d829a0353a	302	0. */
tushki7	0:60d829a0353a	303	__I uint32_t DAT6; /*!< (@ 0x4001C038) A/D Channel 0 Data Register. This register contains
tushki7	0:60d829a0353a	304	the result of the most recent conversion completed on channel
tushki7	0:60d829a0353a	305	0. */
tushki7	0:60d829a0353a	306	__I uint32_t DAT7; /*!< (@ 0x4001C03C) A/D Channel 0 Data Register. This register contains
tushki7	0:60d829a0353a	307	the result of the most recent conversion completed on channel
tushki7	0:60d829a0353a	308	0. */
tushki7	0:60d829a0353a	309	__I uint32_t DAT8; /*!< (@ 0x4001C040) A/D Channel 0 Data Register. This register contains
tushki7	0:60d829a0353a	310	the result of the most recent conversion completed on channel
tushki7	0:60d829a0353a	311	0. */
tushki7	0:60d829a0353a	312	__I uint32_t DAT9; /*!< (@ 0x4001C044) A/D Channel 0 Data Register. This register contains
tushki7	0:60d829a0353a	313	the result of the most recent conversion completed on channel
tushki7	0:60d829a0353a	314	0. */
tushki7	0:60d829a0353a	315	__I uint32_t DAT10; /*!< (@ 0x4001C048) A/D Channel 0 Data Register. This register contains
tushki7	0:60d829a0353a	316	the result of the most recent conversion completed on channel
tushki7	0:60d829a0353a	317	0. */
tushki7	0:60d829a0353a	318	__I uint32_t DAT11; /*!< (@ 0x4001C04C) A/D Channel 0 Data Register. This register contains
tushki7	0:60d829a0353a	319	the result of the most recent conversion completed on channel
tushki7	0:60d829a0353a	320	0. */
tushki7	0:60d829a0353a	321	__IO uint32_t THR0_LOW; /*!< (@ 0x4001C050) A/D Low Compare Threshold Register 0 : Contains
tushki7	0:60d829a0353a	322	the lower threshold level for automatic threshold comparison
tushki7	0:60d829a0353a	323	for any channels linked to threshold pair 0. */
tushki7	0:60d829a0353a	324	__IO uint32_t THR1_LOW; /*!< (@ 0x4001C054) A/D Low Compare Threshold Register 1: Contains
tushki7	0:60d829a0353a	325	the lower threshold level for automatic threshold comparison
tushki7	0:60d829a0353a	326	for any channels linked to threshold pair 1. */
tushki7	0:60d829a0353a	327	__IO uint32_t THR0_HIGH; /*!< (@ 0x4001C058) A/D High Compare Threshold Register 0: Contains
tushki7	0:60d829a0353a	328	the upper threshold level for automatic threshold comparison
tushki7	0:60d829a0353a	329	for any channels linked to threshold pair 0. */
tushki7	0:60d829a0353a	330	__IO uint32_t THR1_HIGH; /*!< (@ 0x4001C05C) A/D High Compare Threshold Register 1: Contains
tushki7	0:60d829a0353a	331	the upper threshold level for automatic threshold comparison
tushki7	0:60d829a0353a	332	for any channels linked to threshold pair 1. */
tushki7	0:60d829a0353a	333	__IO uint32_t CHAN_THRSEL; /*!< (@ 0x4001C060) A/D Channel-Threshold Select Register. Specifies
tushki7	0:60d829a0353a	334	which set of threshold compare registers are to be used for
tushki7	0:60d829a0353a	335	each channel */
tushki7	0:60d829a0353a	336	__IO uint32_t INTEN; /*!< (@ 0x4001C064) A/D Interrupt Enable Register. This register
tushki7	0:60d829a0353a	337	contains enable bits that enable the sequence-A, sequence-B,
tushki7	0:60d829a0353a	338	threshold compare and data overrun interrupts to be generated. */
tushki7	0:60d829a0353a	339	__IO uint32_t FLAGS; /*!< (@ 0x4001C068) A/D Flags Register. Contains the four interrupt
tushki7	0:60d829a0353a	340	request flags and the individual component overrun and threshold-compare
tushki7	0:60d829a0353a	341	flags. (The overrun bits replicate information stored in the
tushki7	0:60d829a0353a	342	result registers). */
tushki7	0:60d829a0353a	343	__IO uint32_t TRM; /!< (@ 0x4001C06C) ADC trim register. /
tushki7	0:60d829a0353a	344	} LPC_ADC_Type;
tushki7	0:60d829a0353a	345
tushki7	0:60d829a0353a	346
tushki7	0:60d829a0353a	347	/* ================================================================================ */
tushki7	0:60d829a0353a	348	/* ================ PMU ================ */
tushki7	0:60d829a0353a	349	/* ================================================================================ */
tushki7	0:60d829a0353a	350
tushki7	0:60d829a0353a	351
tushki7	0:60d829a0353a	352	/**
tushki7	0:60d829a0353a	353	* @brief Power Management Unit (PMU) (PMU)
tushki7	0:60d829a0353a	354	*/
tushki7	0:60d829a0353a	355
tushki7	0:60d829a0353a	356	typedef struct { /!< (@ 0x40020000) PMU Structure /
tushki7	0:60d829a0353a	357	__IO uint32_t PCON; /!< (@ 0x40020000) Power control register /
tushki7	0:60d829a0353a	358	__IO uint32_t GPREG0; /!< (@ 0x40020004) General purpose register 0 /
tushki7	0:60d829a0353a	359	__IO uint32_t GPREG1; /!< (@ 0x40020008) General purpose register 0 /
tushki7	0:60d829a0353a	360	__IO uint32_t GPREG2; /!< (@ 0x4002000C) General purpose register 0 /
tushki7	0:60d829a0353a	361	__IO uint32_t GPREG3; /!< (@ 0x40020010) General purpose register 0 /
tushki7	0:60d829a0353a	362	__IO uint32_t DPDCTRL; /*!< (@ 0x40020014) Deep power-down control register. Also includes
tushki7	0:60d829a0353a	363	bits for general purpose storage. */
tushki7	0:60d829a0353a	364	} LPC_PMU_Type;
tushki7	0:60d829a0353a	365
tushki7	0:60d829a0353a	366
tushki7	0:60d829a0353a	367	/* ================================================================================ */
tushki7	0:60d829a0353a	368	/* ================ CMP ================ */
tushki7	0:60d829a0353a	369	/* ================================================================================ */
tushki7	0:60d829a0353a	370
tushki7	0:60d829a0353a	371
tushki7	0:60d829a0353a	372	/**
tushki7	0:60d829a0353a	373	* @brief Analog comparator (CMP)
tushki7	0:60d829a0353a	374	*/
tushki7	0:60d829a0353a	375
tushki7	0:60d829a0353a	376	typedef struct { /!< (@ 0x40024000) CMP Structure /
tushki7	0:60d829a0353a	377	__IO uint32_t CTRL; /!< (@ 0x40024000) Comparator control register /
tushki7	0:60d829a0353a	378	__IO uint32_t LAD; /!< (@ 0x40024004) Voltage ladder register /
tushki7	0:60d829a0353a	379	} LPC_CMP_Type;
tushki7	0:60d829a0353a	380
tushki7	0:60d829a0353a	381
tushki7	0:60d829a0353a	382	/* ================================================================================ */
tushki7	0:60d829a0353a	383	/* ================ DMATRIGMUX ================ */
tushki7	0:60d829a0353a	384	/* ================================================================================ */
tushki7	0:60d829a0353a	385
tushki7	0:60d829a0353a	386
tushki7	0:60d829a0353a	387	/**
tushki7	0:60d829a0353a	388	* @brief DMA trigger mux (DMATRIGMUX)
tushki7	0:60d829a0353a	389	*/
tushki7	0:60d829a0353a	390
tushki7	0:60d829a0353a	391	typedef struct { /!< (@ 0x40028000) DMATRIGMUX Structure /
tushki7	0:60d829a0353a	392	__IO uint32_t DMA_ITRIG_INMUX0; /*!< (@ 0x40028000) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	393	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	394	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	395	__IO uint32_t DMA_ITRIG_INMUX1; /*!< (@ 0x40028004) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	396	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	397	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	398	__IO uint32_t DMA_ITRIG_INMUX2; /*!< (@ 0x40028008) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	399	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	400	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	401	__IO uint32_t DMA_ITRIG_INMUX3; /*!< (@ 0x4002800C) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	402	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	403	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	404	__IO uint32_t DMA_ITRIG_INMUX4; /*!< (@ 0x40028010) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	405	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	406	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	407	__IO uint32_t DMA_ITRIG_INMUX5; /*!< (@ 0x40028014) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	408	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	409	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	410	__IO uint32_t DMA_ITRIG_INMUX6; /*!< (@ 0x40028018) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	411	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	412	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	413	__IO uint32_t DMA_ITRIG_INMUX7; /*!< (@ 0x4002801C) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	414	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	415	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	416	__IO uint32_t DMA_ITRIG_INMUX8; /*!< (@ 0x40028020) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	417	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	418	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	419	__IO uint32_t DMA_ITRIG_INMUX9; /*!< (@ 0x40028024) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	420	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	421	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	422	__IO uint32_t DMA_ITRIG_INMUX10; /*!< (@ 0x40028028) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	423	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	424	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	425	__IO uint32_t DMA_ITRIG_INMUX11; /*!< (@ 0x4002802C) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	426	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	427	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	428	__IO uint32_t DMA_ITRIG_INMUX12; /*!< (@ 0x40028030) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	429	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	430	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	431	__IO uint32_t DMA_ITRIG_INMUX13; /*!< (@ 0x40028034) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	432	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	433	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	434	__IO uint32_t DMA_ITRIG_INMUX14; /*!< (@ 0x40028038) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	435	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	436	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	437	__IO uint32_t DMA_ITRIG_INMUX15; /*!< (@ 0x4002803C) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	438	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	439	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	440	__IO uint32_t DMA_ITRIG_INMUX16; /*!< (@ 0x40028040) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	441	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	442	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	443	__IO uint32_t DMA_ITRIG_INMUX17; /*!< (@ 0x40028044) Input mux register for trigger inputs 0 to 23
tushki7	0:60d829a0353a	444	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
tushki7	0:60d829a0353a	445	interrupts, and DMA requests. */
tushki7	0:60d829a0353a	446	} LPC_DMATRIGMUX_Type;
tushki7	0:60d829a0353a	447
tushki7	0:60d829a0353a	448
tushki7	0:60d829a0353a	449	/* ================================================================================ */
tushki7	0:60d829a0353a	450	/* ================ INPUTMUX ================ */
tushki7	0:60d829a0353a	451	/* ================================================================================ */
tushki7	0:60d829a0353a	452
tushki7	0:60d829a0353a	453
tushki7	0:60d829a0353a	454	/**
tushki7	0:60d829a0353a	455	* @brief Input multiplexing (INPUTMUX)
tushki7	0:60d829a0353a	456	*/
tushki7	0:60d829a0353a	457
tushki7	0:60d829a0353a	458	typedef struct { /!< (@ 0x4002C000) INPUTMUX Structure /
tushki7	0:60d829a0353a	459	__IO uint32_t DMA_INMUX_INMUX0; /*!< (@ 0x4002C000) Input mux register for DMA trigger input 20.
tushki7	0:60d829a0353a	460	Selects from 18 DMA trigger outputs. */
tushki7	0:60d829a0353a	461	__IO uint32_t DMA_INMUX_INMUX1; /*!< (@ 0x4002C004) Input mux register for DMA trigger input 20.
tushki7	0:60d829a0353a	462	Selects from 18 DMA trigger outputs. */
tushki7	0:60d829a0353a	463	__I uint32_t RESERVED0[6];
tushki7	0:60d829a0353a	464	__IO uint32_t SCT0_INMUX0; /!< (@ 0x4002C020) Input mux register for SCT input 0 /
tushki7	0:60d829a0353a	465	__IO uint32_t SCT0_INMUX1; /!< (@ 0x4002C024) Input mux register for SCT input 0 /
tushki7	0:60d829a0353a	466	__IO uint32_t SCT0_INMUX2; /!< (@ 0x4002C028) Input mux register for SCT input 0 /
tushki7	0:60d829a0353a	467	__IO uint32_t SCT0_INMUX3; /!< (@ 0x4002C02C) Input mux register for SCT input 0 /
tushki7	0:60d829a0353a	468	} LPC_INPUTMUX_Type;
tushki7	0:60d829a0353a	469
tushki7	0:60d829a0353a	470
tushki7	0:60d829a0353a	471	/* ================================================================================ */
tushki7	0:60d829a0353a	472	/* ================ FLASHCTRL ================ */
tushki7	0:60d829a0353a	473	/* ================================================================================ */
tushki7	0:60d829a0353a	474
tushki7	0:60d829a0353a	475
tushki7	0:60d829a0353a	476	/**
tushki7	0:60d829a0353a	477	* @brief Flash controller (FLASHCTRL)
tushki7	0:60d829a0353a	478	*/
tushki7	0:60d829a0353a	479
tushki7	0:60d829a0353a	480	typedef struct { /!< (@ 0x40040000) FLASHCTRL Structure /
tushki7	0:60d829a0353a	481	__I uint32_t RESERVED0[4];
tushki7	0:60d829a0353a	482	__IO uint32_t FLASHCFG; /!< (@ 0x40040010) Flash configuration register /
tushki7	0:60d829a0353a	483	__I uint32_t RESERVED1[3];
tushki7	0:60d829a0353a	484	__IO uint32_t FMSSTART; /!< (@ 0x40040020) Signature start address register /
tushki7	0:60d829a0353a	485	__IO uint32_t FMSSTOP; /!< (@ 0x40040024) Signature stop-address register /
tushki7	0:60d829a0353a	486	__I uint32_t RESERVED2;
tushki7	0:60d829a0353a	487	__I uint32_t FMSW0; /!< (@ 0x4004002C) Signature Word /
tushki7	0:60d829a0353a	488	} LPC_FLASHCTRL_Type;
tushki7	0:60d829a0353a	489
tushki7	0:60d829a0353a	490
tushki7	0:60d829a0353a	491	/* ================================================================================ */
tushki7	0:60d829a0353a	492	/* ================ IOCON ================ */
tushki7	0:60d829a0353a	493	/* ================================================================================ */
tushki7	0:60d829a0353a	494
tushki7	0:60d829a0353a	495
tushki7	0:60d829a0353a	496	/**
tushki7	0:60d829a0353a	497	* @brief I/O configuration (IOCON) (IOCON)
tushki7	0:60d829a0353a	498	*/
tushki7	0:60d829a0353a	499
tushki7	0:60d829a0353a	500	typedef struct { /!< (@ 0x40044000) IOCON Structure /
tushki7	0:60d829a0353a	501	__IO uint32_t PIO0_17; /!< (@ 0x40044000) I/O configuration for pin PIO0_17 /
tushki7	0:60d829a0353a	502	__IO uint32_t PIO0_13; /!< (@ 0x40044004) I/O configuration for pin PIO0_13 /
tushki7	0:60d829a0353a	503	__IO uint32_t PIO0_12; /!< (@ 0x40044008) I/O configuration for pin PIO0_12 /
tushki7	0:60d829a0353a	504	__IO uint32_t PIO0_5; /!< (@ 0x4004400C) I/O configuration for pin PIO0_5/RESET /
tushki7	0:60d829a0353a	505	__IO uint32_t PIO0_4; /!< (@ 0x40044010) I/O configuration for pin PIO0_4 /
tushki7	0:60d829a0353a	506	__IO uint32_t PIO0_3; /!< (@ 0x40044014) I/O configuration for pin PIO0_3/SWCLK /
tushki7	0:60d829a0353a	507	__IO uint32_t PIO0_2; /!< (@ 0x40044018) I/O configuration for pin PIO0_2/SWDIO /
tushki7	0:60d829a0353a	508	__IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11. This is the
tushki7	0:60d829a0353a	509	pin configuration for the true open-drain pin. */
tushki7	0:60d829a0353a	510	__IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10. This is the
tushki7	0:60d829a0353a	511	pin configuration for the true open-drain pin. */
tushki7	0:60d829a0353a	512	__IO uint32_t PIO0_16; /!< (@ 0x40044024) I/O configuration for pin PIO0_16 /
tushki7	0:60d829a0353a	513	__IO uint32_t PIO0_15; /!< (@ 0x40044028) I/O configuration for pin PIO0_15 /
tushki7	0:60d829a0353a	514	__IO uint32_t PIO0_1; /!< (@ 0x4004402C) I/O configuration for pin PIO0_17 /
tushki7	0:60d829a0353a	515	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	516	__IO uint32_t PIO0_9; /!< (@ 0x40044034) I/O configuration for pin PIO0_9/XTALOUT /
tushki7	0:60d829a0353a	517	__IO uint32_t PIO0_8; /!< (@ 0x40044038) I/O configuration for pin PIO0_8/XTALIN /
tushki7	0:60d829a0353a	518	__IO uint32_t PIO0_7; /!< (@ 0x4004403C) I/O configuration for pin PIO0_7 /
tushki7	0:60d829a0353a	519	__IO uint32_t PIO0_6; /!< (@ 0x40044040) I/O configuration for pin PIO0_6/VDDCMP /
tushki7	0:60d829a0353a	520	__IO uint32_t PIO0_0; /!< (@ 0x40044044) I/O configuration for pin PIO0_0/ACMP_I0 /
tushki7	0:60d829a0353a	521	__IO uint32_t PIO0_14; /!< (@ 0x40044048) I/O configuration for pin PIO0_14 /
tushki7	0:60d829a0353a	522	__I uint32_t RESERVED1;
tushki7	0:60d829a0353a	523	__IO uint32_t PIO0_28; /!< (@ 0x40044050) I/O configuration for pin PIO0_28 /
tushki7	0:60d829a0353a	524	__IO uint32_t PIO0_27; /!< (@ 0x40044054) I/O configuration for pin PIO0_27 /
tushki7	0:60d829a0353a	525	__IO uint32_t PIO0_26; /!< (@ 0x40044058) I/O configuration for pin PIO0_26 /
tushki7	0:60d829a0353a	526	__IO uint32_t PIO0_25; /!< (@ 0x4004405C) I/O configuration for pin PIO0_25 /
tushki7	0:60d829a0353a	527	__IO uint32_t PIO0_24; /!< (@ 0x40044060) I/O configuration for pin PIO0_24 /
tushki7	0:60d829a0353a	528	__IO uint32_t PIO0_23; /!< (@ 0x40044064) I/O configuration for pin PIO0_23/ADC_3 /
tushki7	0:60d829a0353a	529	__IO uint32_t PIO0_22; /!< (@ 0x40044068) I/O configuration for pin PIO0_22/ADC_4 /
tushki7	0:60d829a0353a	530	__IO uint32_t PIO0_21; /!< (@ 0x4004406C) I/O configuration for pin PIO0_21/ACMP_I4/ADC_5 /
tushki7	0:60d829a0353a	531	__IO uint32_t PIO0_20; /!< (@ 0x40044070) I/O configuration for pin PIO0_20/ADC_6 /
tushki7	0:60d829a0353a	532	__IO uint32_t PIO0_19; /!< (@ 0x40044074) I/O configuration for pin PIO0_19/ADC_7 /
tushki7	0:60d829a0353a	533	__IO uint32_t PIO0_18; /!< (@ 0x40044078) I/O configuration for pin PIO0_18/ADC_8 /
tushki7	0:60d829a0353a	534	} LPC_IOCON_Type;
tushki7	0:60d829a0353a	535
tushki7	0:60d829a0353a	536
tushki7	0:60d829a0353a	537	/* ================================================================================ */
tushki7	0:60d829a0353a	538	/* ================ SYSCON ================ */
tushki7	0:60d829a0353a	539	/* ================================================================================ */
tushki7	0:60d829a0353a	540
tushki7	0:60d829a0353a	541
tushki7	0:60d829a0353a	542	/**
tushki7	0:60d829a0353a	543	* @brief System configuration (SYSCON) (SYSCON)
tushki7	0:60d829a0353a	544	*/
tushki7	0:60d829a0353a	545
tushki7	0:60d829a0353a	546	typedef struct { /!< (@ 0x40048000) SYSCON Structure /
tushki7	0:60d829a0353a	547	__IO uint32_t SYSMEMREMAP; /!< (@ 0x40048000) System memory remap /
tushki7	0:60d829a0353a	548	__IO uint32_t PRESETCTRL; /!< (@ 0x40048004) Peripheral reset control /
tushki7	0:60d829a0353a	549	__IO uint32_t SYSPLLCTRL; /!< (@ 0x40048008) System PLL control /
tushki7	0:60d829a0353a	550	__I uint32_t SYSPLLSTAT; /!< (@ 0x4004800C) System PLL status /
tushki7	0:60d829a0353a	551	__I uint32_t RESERVED0[4];
tushki7	0:60d829a0353a	552	__IO uint32_t SYSOSCCTRL; /!< (@ 0x40048020) System oscillator control /
tushki7	0:60d829a0353a	553	__IO uint32_t WDTOSCCTRL; /!< (@ 0x40048024) Watchdog oscillator control /
tushki7	0:60d829a0353a	554	__IO uint32_t IRCCTRL; /!< (@ 0x40048028) IRC control /
tushki7	0:60d829a0353a	555	__I uint32_t RESERVED1;
tushki7	0:60d829a0353a	556	__IO uint32_t SYSRSTSTAT; /!< (@ 0x40048030) System reset status register /
tushki7	0:60d829a0353a	557	__I uint32_t RESERVED2[3];
tushki7	0:60d829a0353a	558	__IO uint32_t SYSPLLCLKSEL; /!< (@ 0x40048040) System PLL clock source select /
tushki7	0:60d829a0353a	559	__IO uint32_t SYSPLLCLKUEN; /!< (@ 0x40048044) System PLL clock source update enable /
tushki7	0:60d829a0353a	560	__I uint32_t RESERVED3[10];
tushki7	0:60d829a0353a	561	__IO uint32_t MAINCLKSEL; /!< (@ 0x40048070) Main clock source select /
tushki7	0:60d829a0353a	562	__IO uint32_t MAINCLKUEN; /!< (@ 0x40048074) Main clock source update enable /
tushki7	0:60d829a0353a	563	__IO uint32_t SYSAHBCLKDIV; /!< (@ 0x40048078) System clock divider /
tushki7	0:60d829a0353a	564	__I uint32_t RESERVED4;
tushki7	0:60d829a0353a	565	__IO uint32_t SYSAHBCLKCTRL; /!< (@ 0x40048080) System clock control /
tushki7	0:60d829a0353a	566	__I uint32_t RESERVED5[4];
tushki7	0:60d829a0353a	567	__IO uint32_t UARTCLKDIV; /!< (@ 0x40048094) USART clock divider /
tushki7	0:60d829a0353a	568	__I uint32_t RESERVED6[18];
tushki7	0:60d829a0353a	569	__IO uint32_t CLKOUTSEL; /!< (@ 0x400480E0) CLKOUT clock source select /
tushki7	0:60d829a0353a	570	__IO uint32_t CLKOUTUEN; /!< (@ 0x400480E4) CLKOUT clock source update enable /
tushki7	0:60d829a0353a	571	__IO uint32_t CLKOUTDIV; /!< (@ 0x400480E8) CLKOUT clock divider /
tushki7	0:60d829a0353a	572	__I uint32_t RESERVED7;
tushki7	0:60d829a0353a	573	__IO uint32_t UARTFRGDIV; /*!< (@ 0x400480F0) USART1 to USART4 common fractional generator
tushki7	0:60d829a0353a	574	divider value */
tushki7	0:60d829a0353a	575	__IO uint32_t UARTFRGMULT; /*!< (@ 0x400480F4) USART1 to USART4 common fractional generator
tushki7	0:60d829a0353a	576	multiplier value */
tushki7	0:60d829a0353a	577	__I uint32_t RESERVED8;
tushki7	0:60d829a0353a	578	__IO uint32_t EXTTRACECMD; /!< (@ 0x400480FC) External trace buffer command register /
tushki7	0:60d829a0353a	579	__I uint32_t PIOPORCAP0; /!< (@ 0x40048100) POR captured PIO status 0 /
tushki7	0:60d829a0353a	580	__I uint32_t RESERVED9[12];
tushki7	0:60d829a0353a	581	__IO uint32_t IOCONCLKDIV6; /*!< (@ 0x40048134) Peripheral clock 6 to the IOCON block for programmable
tushki7	0:60d829a0353a	582	glitch filter */
tushki7	0:60d829a0353a	583	__I uint32_t RESERVED10[6];
tushki7	0:60d829a0353a	584	__IO uint32_t BODCTRL; /!< (@ 0x40048150) Brown-Out Detect /
tushki7	0:60d829a0353a	585	__IO uint32_t SYSTCKCAL; /!< (@ 0x40048154) System tick counter calibration /
tushki7	0:60d829a0353a	586	__I uint32_t RESERVED11[6];
tushki7	0:60d829a0353a	587	__IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt
tushki7	0:60d829a0353a	588	latency and determinism. */
tushki7	0:60d829a0353a	589	__IO uint32_t NMISRC; /!< (@ 0x40048174) NMI Source Control /
tushki7	0:60d829a0353a	590	union {
tushki7	0:60d829a0353a	591	__IO uint32_t PINTSEL[8];
tushki7	0:60d829a0353a	592	struct {
tushki7	0:60d829a0353a	593	__IO uint32_t PINTSEL0; /!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 /
tushki7	0:60d829a0353a	594	__IO uint32_t PINTSEL1; /!< (@ 0x4004817C) GPIO Pin Interrupt Select register 0 /
tushki7	0:60d829a0353a	595	__IO uint32_t PINTSEL2; /!< (@ 0x40048180) GPIO Pin Interrupt Select register 0 /
tushki7	0:60d829a0353a	596	__IO uint32_t PINTSEL3; /!< (@ 0x40048184) GPIO Pin Interrupt Select register 0 /
tushki7	0:60d829a0353a	597	__IO uint32_t PINTSEL4; /!< (@ 0x40048188) GPIO Pin Interrupt Select register 0 /
tushki7	0:60d829a0353a	598	__IO uint32_t PINTSEL5; /!< (@ 0x4004818C) GPIO Pin Interrupt Select register 0 /
tushki7	0:60d829a0353a	599	__IO uint32_t PINTSEL6; /!< (@ 0x40048190) GPIO Pin Interrupt Select register 0 /
tushki7	0:60d829a0353a	600	__IO uint32_t PINTSEL7; /!< (@ 0x40048194) GPIO Pin Interrupt Select register 0 /
tushki7	0:60d829a0353a	601	};
tushki7	0:60d829a0353a	602	};
tushki7	0:60d829a0353a	603	__I uint32_t RESERVED12[27];
tushki7	0:60d829a0353a	604	__IO uint32_t STARTERP0; /!< (@ 0x40048204) Start logic 0 pin wake-up enable register /
tushki7	0:60d829a0353a	605	__I uint32_t RESERVED13[3];
tushki7	0:60d829a0353a	606	__IO uint32_t STARTERP1; /!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register /
tushki7	0:60d829a0353a	607	__I uint32_t RESERVED14[6];
tushki7	0:60d829a0353a	608	__IO uint32_t PDSLEEPCFG; /!< (@ 0x40048230) Power-down states in deep-sleep mode /
tushki7	0:60d829a0353a	609	__IO uint32_t PDAWAKECFG; /!< (@ 0x40048234) Power-down states for wake-up from deep-sleep /
tushki7	0:60d829a0353a	610	__IO uint32_t PDRUNCFG; /!< (@ 0x40048238) Power configuration register /
tushki7	0:60d829a0353a	611	__I uint32_t RESERVED15[111];
tushki7	0:60d829a0353a	612	__I uint32_t DEVICE_ID; /!< (@ 0x400483F8) Device ID /
tushki7	0:60d829a0353a	613	} LPC_SYSCON_Type;
tushki7	0:60d829a0353a	614
tushki7	0:60d829a0353a	615
tushki7	0:60d829a0353a	616	/* ================================================================================ */
tushki7	0:60d829a0353a	617	/* ================ I2C0 ================ */
tushki7	0:60d829a0353a	618	/* ================================================================================ */
tushki7	0:60d829a0353a	619
tushki7	0:60d829a0353a	620
tushki7	0:60d829a0353a	621	/**
tushki7	0:60d829a0353a	622	* @brief I2C0-bus interface (I2C0)
tushki7	0:60d829a0353a	623	*/
tushki7	0:60d829a0353a	624
tushki7	0:60d829a0353a	625	typedef struct { /!< (@ 0x40050000) I2C0 Structure /
tushki7	0:60d829a0353a	626	__IO uint32_t CFG; /!< (@ 0x40050000) Configuration for shared functions. /
tushki7	0:60d829a0353a	627	__IO uint32_t STAT; /*!< (@ 0x40050004) Status register for Master, Slave, and Monitor
tushki7	0:60d829a0353a	628	functions. */
tushki7	0:60d829a0353a	629	__IO uint32_t INTENSET; /!< (@ 0x40050008) Interrupt Enable Set and read register. /
tushki7	0:60d829a0353a	630	__O uint32_t INTENCLR; /!< (@ 0x4005000C) Interrupt Enable Clear register. /
tushki7	0:60d829a0353a	631	__IO uint32_t TIMEOUT; /!< (@ 0x40050010) Time-out value register. /
tushki7	0:60d829a0353a	632	__IO uint32_t CLKDIV; /*!< (@ 0x40050014) Clock pre-divider for the entire I2C block. This
tushki7	0:60d829a0353a	633	determines what time increments are used for the MSTTIME and
tushki7	0:60d829a0353a	634	SLVTIME registers. */
tushki7	0:60d829a0353a	635	__I uint32_t INTSTAT; /*!< (@ 0x40050018) Interrupt Status register for Master, Slave,
tushki7	0:60d829a0353a	636	and Monitor functions. */
tushki7	0:60d829a0353a	637	__I uint32_t RESERVED0;
tushki7	0:60d829a0353a	638	__IO uint32_t MSTCTL; /!< (@ 0x40050020) Master control register. /
tushki7	0:60d829a0353a	639	__IO uint32_t MSTTIME; /!< (@ 0x40050024) Master timing configuration. /
tushki7	0:60d829a0353a	640	__IO uint32_t MSTDAT; /*!< (@ 0x40050028) Combined Master receiver and transmitter data
tushki7	0:60d829a0353a	641	register. */
tushki7	0:60d829a0353a	642	__I uint32_t RESERVED1[5];
tushki7	0:60d829a0353a	643	__IO uint32_t SLVCTL; /!< (@ 0x40050040) Slave control register. /
tushki7	0:60d829a0353a	644	__IO uint32_t SLVDAT; /*!< (@ 0x40050044) Combined Slave receiver and transmitter data
tushki7	0:60d829a0353a	645	register. */
tushki7	0:60d829a0353a	646	union {
tushki7	0:60d829a0353a	647	__IO uint32_t SLVADR[4];
tushki7	0:60d829a0353a	648	struct {
tushki7	0:60d829a0353a	649	__IO uint32_t SLVADR0; /!< (@ 0x40050048) Slave address 0. /
tushki7	0:60d829a0353a	650	__IO uint32_t SLVADR1; /!< (@ 0x4005004C) Slave address 0. /
tushki7	0:60d829a0353a	651	__IO uint32_t SLVADR2; /!< (@ 0x40050050) Slave address 0. /
tushki7	0:60d829a0353a	652	__IO uint32_t SLVADR3; /!< (@ 0x40050054) Slave address 0. /
tushki7	0:60d829a0353a	653	};
tushki7	0:60d829a0353a	654	};
tushki7	0:60d829a0353a	655	__IO uint32_t SLVQUAL0; /!< (@ 0x40050058) Slave Qualification for address 0. /
tushki7	0:60d829a0353a	656	__I uint32_t RESERVED2[9];
tushki7	0:60d829a0353a	657	__I uint32_t MONRXDAT; /!< (@ 0x40050080) Monitor receiver data register. /
tushki7	0:60d829a0353a	658	} LPC_I2C0_Type;
tushki7	0:60d829a0353a	659
tushki7	0:60d829a0353a	660
tushki7	0:60d829a0353a	661	/* ================================================================================ */
tushki7	0:60d829a0353a	662	/* ================ SPI0 ================ */
tushki7	0:60d829a0353a	663	/* ================================================================================ */
tushki7	0:60d829a0353a	664
tushki7	0:60d829a0353a	665
tushki7	0:60d829a0353a	666	/**
tushki7	0:60d829a0353a	667	* @brief SPI0 (SPI0)
tushki7	0:60d829a0353a	668	*/
tushki7	0:60d829a0353a	669
tushki7	0:60d829a0353a	670	typedef struct { /!< (@ 0x40058000) SPI0 Structure /
tushki7	0:60d829a0353a	671	__IO uint32_t CFG; /!< (@ 0x40058000) SPI Configuration register /
tushki7	0:60d829a0353a	672	__IO uint32_t DLY; /!< (@ 0x40058004) SPI Delay register /
tushki7	0:60d829a0353a	673	__IO uint32_t STAT; /*!< (@ 0x40058008) SPI Status. Some status flags can be cleared
tushki7	0:60d829a0353a	674	by writing a 1 to that bit position */
tushki7	0:60d829a0353a	675	__IO uint32_t INTENSET; /*!< (@ 0x4005800C) SPI Interrupt Enable read and Set. A complete
tushki7	0:60d829a0353a	676	value may be read from this register. Writing a 1 to any implemented
tushki7	0:60d829a0353a	677	bit position causes that bit to be set. */
tushki7	0:60d829a0353a	678	__O uint32_t INTENCLR; /*!< (@ 0x40058010) SPI Interrupt Enable Clear. Writing a 1 to any
tushki7	0:60d829a0353a	679	implemented bit position causes the corresponding bit in INTENSET
tushki7	0:60d829a0353a	680	to be cleared. */
tushki7	0:60d829a0353a	681	__I uint32_t RXDAT; /!< (@ 0x40058014) SPI Receive Data /
tushki7	0:60d829a0353a	682	__IO uint32_t TXDATCTL; /!< (@ 0x40058018) SPI Transmit Data with Control /
tushki7	0:60d829a0353a	683	__IO uint32_t TXDAT; /!< (@ 0x4005801C) SPI Transmit Data /
tushki7	0:60d829a0353a	684	__IO uint32_t TXCTL; /!< (@ 0x40058020) SPI Transmit Control /
tushki7	0:60d829a0353a	685	__IO uint32_t DIV; /!< (@ 0x40058024) SPI clock Divider /
tushki7	0:60d829a0353a	686	__I uint32_t INTSTAT; /!< (@ 0x40058028) SPI Interrupt Status /
tushki7	0:60d829a0353a	687	} LPC_SPI0_Type;
tushki7	0:60d829a0353a	688
tushki7	0:60d829a0353a	689
tushki7	0:60d829a0353a	690	/* ================================================================================ */
tushki7	0:60d829a0353a	691	/* ================ USART0 ================ */
tushki7	0:60d829a0353a	692	/* ================================================================================ */
tushki7	0:60d829a0353a	693
tushki7	0:60d829a0353a	694
tushki7	0:60d829a0353a	695	/**
tushki7	0:60d829a0353a	696	* @brief USART0 (USART0)
tushki7	0:60d829a0353a	697	*/
tushki7	0:60d829a0353a	698
tushki7	0:60d829a0353a	699	typedef struct { /!< (@ 0x40064000) USART0 Structure /
tushki7	0:60d829a0353a	700	__IO uint32_t CFG; /*!< (@ 0x40064000) USART Configuration register. Basic USART configuration
tushki7	0:60d829a0353a	701	settings that typically are not changed during operation. */
tushki7	0:60d829a0353a	702	__IO uint32_t CTL; /*!< (@ 0x40064004) USART Control register. USART control settings
tushki7	0:60d829a0353a	703	that are more likely to change during operation. */
tushki7	0:60d829a0353a	704	__IO uint32_t STAT; /*!< (@ 0x40064008) USART Status register. The complete status value
tushki7	0:60d829a0353a	705	can be read here. Writing ones clears some bits in the register.
tushki7	0:60d829a0353a	706	Some bits can be cleared by writing a 1 to them. */
tushki7	0:60d829a0353a	707	__IO uint32_t INTENSET; /*!< (@ 0x4006400C) Interrupt Enable read and Set register. Contains
tushki7	0:60d829a0353a	708	an individual interrupt enable bit for each potential USART
tushki7	0:60d829a0353a	709	interrupt. A complete value may be read from this register.
tushki7	0:60d829a0353a	710	Writing a 1 to any implemented bit position causes that bit
tushki7	0:60d829a0353a	711	to be set. */
tushki7	0:60d829a0353a	712	__O uint32_t INTENCLR; /*!< (@ 0x40064010) Interrupt Enable Clear register. Allows clearing
tushki7	0:60d829a0353a	713	any combination of bits in the INTENSET register. Writing a
tushki7	0:60d829a0353a	714	1 to any implemented bit position causes the corresponding bit
tushki7	0:60d829a0353a	715	to be cleared. */
tushki7	0:60d829a0353a	716	__I uint32_t RXDAT; /*!< (@ 0x40064014) Receiver Data register. Contains the last character
tushki7	0:60d829a0353a	717	received. */
tushki7	0:60d829a0353a	718	__I uint32_t RXDATSTAT; /*!< (@ 0x40064018) Receiver Data with Status register. Combines
tushki7	0:60d829a0353a	719	the last character received with the current USART receive status.
tushki7	0:60d829a0353a	720	Allows DMA or software to recover incoming data and status together. */
tushki7	0:60d829a0353a	721	__IO uint32_t TXDAT; /*!< (@ 0x4006401C) Transmit Data register. Data to be transmitted
tushki7	0:60d829a0353a	722	is written here. */
tushki7	0:60d829a0353a	723	__IO uint32_t BRG; /*!< (@ 0x40064020) Baud Rate Generator register. 16-bit integer
tushki7	0:60d829a0353a	724	baud rate divisor value. */
tushki7	0:60d829a0353a	725	__I uint32_t INTSTAT; /*!< (@ 0x40064024) Interrupt status register. Reflects interrupts
tushki7	0:60d829a0353a	726	that are currently enabled. */
tushki7	0:60d829a0353a	727	__IO uint32_t OSR; /*!< (@ 0x40064028) Oversample selection register for asynchronous
tushki7	0:60d829a0353a	728	communication. */
tushki7	0:60d829a0353a	729	__IO uint32_t ADDR; /!< (@ 0x4006402C) Address register for automatic address matching. /
tushki7	0:60d829a0353a	730	} LPC_USART0_Type;
tushki7	0:60d829a0353a	731
tushki7	0:60d829a0353a	732
tushki7	0:60d829a0353a	733	/* ================================================================================ */
tushki7	0:60d829a0353a	734	/* ================ CRC ================ */
tushki7	0:60d829a0353a	735	/* ================================================================================ */
tushki7	0:60d829a0353a	736
tushki7	0:60d829a0353a	737
tushki7	0:60d829a0353a	738	/**
tushki7	0:60d829a0353a	739	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
tushki7	0:60d829a0353a	740	*/
tushki7	0:60d829a0353a	741
tushki7	0:60d829a0353a	742	typedef struct { /!< (@ 0x50000000) CRC Structure /
tushki7	0:60d829a0353a	743	__IO uint32_t MODE; /!< (@ 0x50000000) CRC mode register /
tushki7	0:60d829a0353a	744	__IO uint32_t SEED; /!< (@ 0x50000004) CRC seed register /
tushki7	0:60d829a0353a	745
tushki7	0:60d829a0353a	746	union {
tushki7	0:60d829a0353a	747	__O uint32_t WR_DATA; /!< (@ 0x50000008) CRC data register /
tushki7	0:60d829a0353a	748	__I uint32_t SUM; /!< (@ 0x50000008) CRC checksum register /
tushki7	0:60d829a0353a	749	};
tushki7	0:60d829a0353a	750	} LPC_CRC_Type;
tushki7	0:60d829a0353a	751
tushki7	0:60d829a0353a	752
tushki7	0:60d829a0353a	753	/* ================================================================================ */
tushki7	0:60d829a0353a	754	/* ================ SCT ================ */
tushki7	0:60d829a0353a	755	/* ================================================================================ */
tushki7	0:60d829a0353a	756
tushki7	0:60d829a0353a	757
tushki7	0:60d829a0353a	758	/**
tushki7	0:60d829a0353a	759	* @brief State Configurable Timer (SCT) (SCT)
tushki7	0:60d829a0353a	760	*/
tushki7	0:60d829a0353a	761
tushki7	0:60d829a0353a	762	typedef struct { /!< (@ 0x50004000) SCT Structure /
tushki7	0:60d829a0353a	763	__IO uint32_t CONFIG; /!< (@ 0x50004000) SCT configuration register /
tushki7	0:60d829a0353a	764	__IO uint32_t CTRL; /!< (@ 0x50004004) SCT control register /
tushki7	0:60d829a0353a	765	__IO uint32_t LIMIT; /!< (@ 0x50004008) SCT limit register /
tushki7	0:60d829a0353a	766	__IO uint32_t HALT; /!< (@ 0x5000400C) SCT halt condition register /
tushki7	0:60d829a0353a	767	__IO uint32_t STOP; /!< (@ 0x50004010) SCT stop condition register /
tushki7	0:60d829a0353a	768	__IO uint32_t START; /!< (@ 0x50004014) SCT start condition register /
tushki7	0:60d829a0353a	769	__I uint32_t RESERVED0[10];
tushki7	0:60d829a0353a	770	__IO uint32_t COUNT; /!< (@ 0x50004040) SCT counter register /
tushki7	0:60d829a0353a	771	__IO uint32_t STATE; /!< (@ 0x50004044) SCT state register /
tushki7	0:60d829a0353a	772	__I uint32_t INPUT; /!< (@ 0x50004048) SCT input register /
tushki7	0:60d829a0353a	773	__IO uint32_t REGMODE; /!< (@ 0x5000404C) SCT match/capture registers mode register /
tushki7	0:60d829a0353a	774	__IO uint32_t OUTPUT; /!< (@ 0x50004050) SCT output register /
tushki7	0:60d829a0353a	775	__IO uint32_t OUTPUTDIRCTRL; /!< (@ 0x50004054) SCT output counter direction control register /
tushki7	0:60d829a0353a	776	__IO uint32_t RES; /!< (@ 0x50004058) SCT conflict resolution register /
tushki7	0:60d829a0353a	777	__IO uint32_t DMAREQ0; /!< (@ 0x5000405C) SCT DMA request 0 register /
tushki7	0:60d829a0353a	778	__IO uint32_t DMAREQ1; /!< (@ 0x50004060) SCT DMA request 1 register /
tushki7	0:60d829a0353a	779	__I uint32_t RESERVED1[35];
tushki7	0:60d829a0353a	780	__IO uint32_t EVEN; /!< (@ 0x500040F0) SCT event enable register /
tushki7	0:60d829a0353a	781	__IO uint32_t EVFLAG; /!< (@ 0x500040F4) SCT event flag register /
tushki7	0:60d829a0353a	782	__IO uint32_t CONEN; /!< (@ 0x500040F8) SCT conflict enable register /
tushki7	0:60d829a0353a	783	__IO uint32_t CONFLAG; /!< (@ 0x500040FC) SCT conflict flag register /
tushki7	0:60d829a0353a	784
tushki7	0:60d829a0353a	785	union {
tushki7	0:60d829a0353a	786	union {
tushki7	0:60d829a0353a	787	__IO uint32_t CAP0; /*!< (@ 0x50004100) SCT capture register of capture channel 0 to
tushki7	0:60d829a0353a	788	7; REGMOD0 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	789	__IO uint32_t MATCH0; /*!< (@ 0x50004100) SCT match value register of match channels 0
tushki7	0:60d829a0353a	790	to 7; REGMOD0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	791	};
tushki7	0:60d829a0353a	792
tushki7	0:60d829a0353a	793	union {
tushki7	0:60d829a0353a	794	__IO uint32_t CAP1; /*!< (@ 0x50004104) SCT capture register of capture channel 0 to
tushki7	0:60d829a0353a	795	7; REGMOD0 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	796	__IO uint32_t MATCH1; /*!< (@ 0x50004104) SCT match value register of match channels 0
tushki7	0:60d829a0353a	797	to 7; REGMOD0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	798	};
tushki7	0:60d829a0353a	799
tushki7	0:60d829a0353a	800	union {
tushki7	0:60d829a0353a	801	__IO uint32_t CAP2; /*!< (@ 0x50004108) SCT capture register of capture channel 0 to
tushki7	0:60d829a0353a	802	7; REGMOD0 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	803	__IO uint32_t MATCH2; /*!< (@ 0x50004108) SCT match value register of match channels 0
tushki7	0:60d829a0353a	804	to 7; REGMOD0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	805	};
tushki7	0:60d829a0353a	806
tushki7	0:60d829a0353a	807	union {
tushki7	0:60d829a0353a	808	__IO uint32_t MATCH3; /*!< (@ 0x5000410C) SCT match value register of match channels 0
tushki7	0:60d829a0353a	809	to 7; REGMOD0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	810	__IO uint32_t CAP3; /*!< (@ 0x5000410C) SCT capture register of capture channel 0 to
tushki7	0:60d829a0353a	811	7; REGMOD0 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	812	};
tushki7	0:60d829a0353a	813
tushki7	0:60d829a0353a	814	union {
tushki7	0:60d829a0353a	815	__IO uint32_t CAP4; /*!< (@ 0x50004110) SCT capture register of capture channel 0 to
tushki7	0:60d829a0353a	816	7; REGMOD0 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	817	__IO uint32_t MATCH4; /*!< (@ 0x50004110) SCT match value register of match channels 0
tushki7	0:60d829a0353a	818	to 7; REGMOD0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	819	};
tushki7	0:60d829a0353a	820
tushki7	0:60d829a0353a	821	union {
tushki7	0:60d829a0353a	822	__IO uint32_t MATCH5; /*!< (@ 0x50004114) SCT match value register of match channels 0
tushki7	0:60d829a0353a	823	to 7; REGMOD0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	824	__IO uint32_t CAP5; /*!< (@ 0x50004114) SCT capture register of capture channel 0 to
tushki7	0:60d829a0353a	825	7; REGMOD0 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	826	};
tushki7	0:60d829a0353a	827
tushki7	0:60d829a0353a	828	union {
tushki7	0:60d829a0353a	829	__IO uint32_t CAP6; /*!< (@ 0x50004118) SCT capture register of capture channel 0 to
tushki7	0:60d829a0353a	830	7; REGMOD0 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	831	__IO uint32_t MATCH6; /*!< (@ 0x50004118) SCT match value register of match channels 0
tushki7	0:60d829a0353a	832	to 7; REGMOD0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	833	};
tushki7	0:60d829a0353a	834
tushki7	0:60d829a0353a	835	union {
tushki7	0:60d829a0353a	836	__IO uint32_t CAP7; /*!< (@ 0x5000411C) SCT capture register of capture channel 0 to
tushki7	0:60d829a0353a	837	7; REGMOD0 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	838	__IO uint32_t MATCH7; /*!< (@ 0x5000411C) SCT match value register of match channels 0
tushki7	0:60d829a0353a	839	to 7; REGMOD0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	840	};
tushki7	0:60d829a0353a	841	__IO uint32_t CAP[8];
tushki7	0:60d829a0353a	842	__IO uint32_t MATCH[8];
tushki7	0:60d829a0353a	843	};
tushki7	0:60d829a0353a	844	__I uint32_t RESERVED2[56];
tushki7	0:60d829a0353a	845
tushki7	0:60d829a0353a	846	union {
tushki7	0:60d829a0353a	847	struct {
tushki7	0:60d829a0353a	848	union {
tushki7	0:60d829a0353a	849	__IO uint32_t CAPCTRL0; /*!< (@ 0x50004200) SCT capture control register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	850	= 1 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	851	__IO uint32_t MATCHREL0; /*!< (@ 0x50004200) SCT match reload value register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	852	= 0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	853	};
tushki7	0:60d829a0353a	854
tushki7	0:60d829a0353a	855	union {
tushki7	0:60d829a0353a	856	__IO uint32_t CAPCTRL1; /*!< (@ 0x50004204) SCT capture control register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	857	= 1 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	858	__IO uint32_t MATCHREL1; /*!< (@ 0x50004204) SCT match reload value register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	859	= 0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	860	};
tushki7	0:60d829a0353a	861
tushki7	0:60d829a0353a	862	union {
tushki7	0:60d829a0353a	863	__IO uint32_t CAPCTRL2; /*!< (@ 0x50004208) SCT capture control register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	864	= 1 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	865	__IO uint32_t MATCHREL2; /*!< (@ 0x50004208) SCT match reload value register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	866	= 0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	867	};
tushki7	0:60d829a0353a	868
tushki7	0:60d829a0353a	869	union {
tushki7	0:60d829a0353a	870	__IO uint32_t MATCHREL3; /*!< (@ 0x5000420C) SCT match reload value register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	871	= 0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	872	__IO uint32_t CAPCTRL3; /*!< (@ 0x5000420C) SCT capture control register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	873	= 1 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	874	};
tushki7	0:60d829a0353a	875
tushki7	0:60d829a0353a	876	union {
tushki7	0:60d829a0353a	877	__IO uint32_t CAPCTRL4; /*!< (@ 0x50004210) SCT capture control register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	878	= 1 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	879	__IO uint32_t MATCHREL4; /*!< (@ 0x50004210) SCT match reload value register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	880	= 0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	881	};
tushki7	0:60d829a0353a	882
tushki7	0:60d829a0353a	883	union {
tushki7	0:60d829a0353a	884	__IO uint32_t CAPCTRL5; /*!< (@ 0x50004214) SCT capture control register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	885	= 1 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	886	__IO uint32_t MATCHREL5; /*!< (@ 0x50004214) SCT match reload value register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	887	= 0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	888	};
tushki7	0:60d829a0353a	889
tushki7	0:60d829a0353a	890	union {
tushki7	0:60d829a0353a	891	__IO uint32_t CAPCTRL6; /*!< (@ 0x50004218) SCT capture control register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	892	= 1 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	893	__IO uint32_t MATCHREL6; /*!< (@ 0x50004218) SCT match reload value register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	894	= 0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	895	};
tushki7	0:60d829a0353a	896
tushki7	0:60d829a0353a	897	union {
tushki7	0:60d829a0353a	898	__IO uint32_t CAPCTRL7; /*!< (@ 0x5000421C) SCT capture control register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	899	= 1 to REGMODE7 = 1 */
tushki7	0:60d829a0353a	900	__IO uint32_t MATCHREL7; /*!< (@ 0x5000421C) SCT match reload value register 0 to 7; REGMOD0
tushki7	0:60d829a0353a	901	= 0 to REGMODE7 = 0 */
tushki7	0:60d829a0353a	902	};
tushki7	0:60d829a0353a	903	};
tushki7	0:60d829a0353a	904	__IO uint32_t MATCHREL[8];
tushki7	0:60d829a0353a	905	};
tushki7	0:60d829a0353a	906	__I uint32_t RESERVED3[56];
tushki7	0:60d829a0353a	907
tushki7	0:60d829a0353a	908	union {
tushki7	0:60d829a0353a	909	struct {
tushki7	0:60d829a0353a	910	__IO uint32_t EV0_STATE; /!< (@ 0x50004300) SCT event state register 0 /
tushki7	0:60d829a0353a	911	__IO uint32_t EV0_CTRL; /!< (@ 0x50004304) SCT event control register 0 /
tushki7	0:60d829a0353a	912	__IO uint32_t EV1_STATE; /!< (@ 0x50004308) SCT event state register 0 /
tushki7	0:60d829a0353a	913	__IO uint32_t EV1_CTRL; /!< (@ 0x5000430C) SCT event control register 0 /
tushki7	0:60d829a0353a	914	__IO uint32_t EV2_STATE; /!< (@ 0x50004310) SCT event state register 0 /
tushki7	0:60d829a0353a	915	__IO uint32_t EV2_CTRL; /!< (@ 0x50004314) SCT event control register 0 /
tushki7	0:60d829a0353a	916	__IO uint32_t EV3_STATE; /!< (@ 0x50004318) SCT event state register 0 /
tushki7	0:60d829a0353a	917	__IO uint32_t EV3_CTRL; /!< (@ 0x5000431C) SCT event control register 0 /
tushki7	0:60d829a0353a	918	__IO uint32_t EV4_STATE; /!< (@ 0x50004320) SCT event state register 0 /
tushki7	0:60d829a0353a	919	__IO uint32_t EV4_CTRL; /!< (@ 0x50004324) SCT event control register 0 /
tushki7	0:60d829a0353a	920	__IO uint32_t EV5_STATE; /!< (@ 0x50004328) SCT event state register 0 /
tushki7	0:60d829a0353a	921	__IO uint32_t EV5_CTRL; /!< (@ 0x5000432C) SCT event control register 0 /
tushki7	0:60d829a0353a	922	__IO uint32_t EV6_STATE; /!< (@ 0x50004330) SCT event state register 0 /
tushki7	0:60d829a0353a	923	__IO uint32_t EV6_CTRL; /!< (@ 0x50004334) SCT event control register 0 /
tushki7	0:60d829a0353a	924	__IO uint32_t EV7_STATE; /!< (@ 0x50004338) SCT event state register 0 /
tushki7	0:60d829a0353a	925	__IO uint32_t EV7_CTRL; /!< (@ 0x5000433C) SCT event control register 0 /
tushki7	0:60d829a0353a	926	};
tushki7	0:60d829a0353a	927	__IO struct {
tushki7	0:60d829a0353a	928	uint32_t STATE;
tushki7	0:60d829a0353a	929	uint32_t CTRL;
tushki7	0:60d829a0353a	930	} EVENT[8];
tushki7	0:60d829a0353a	931	};
tushki7	0:60d829a0353a	932
tushki7	0:60d829a0353a	933	__I uint32_t RESERVED4[112];
tushki7	0:60d829a0353a	934
tushki7	0:60d829a0353a	935	union {
tushki7	0:60d829a0353a	936	struct {
tushki7	0:60d829a0353a	937	__IO uint32_t OUT0_SET; /!< (@ 0x50004500) SCT output 0 set register /
tushki7	0:60d829a0353a	938	__IO uint32_t OUT0_CLR; /!< (@ 0x50004504) SCT output 0 clear register /
tushki7	0:60d829a0353a	939	__IO uint32_t OUT1_SET; /!< (@ 0x50004508) SCT output 0 set register /
tushki7	0:60d829a0353a	940	__IO uint32_t OUT1_CLR; /!< (@ 0x5000450C) SCT output 0 clear register /
tushki7	0:60d829a0353a	941	__IO uint32_t OUT2_SET; /!< (@ 0x50004510) SCT output 0 set register /
tushki7	0:60d829a0353a	942	__IO uint32_t OUT2_CLR; /!< (@ 0x50004514) SCT output 0 clear register /
tushki7	0:60d829a0353a	943	__IO uint32_t OUT3_SET; /!< (@ 0x50004518) SCT output 0 set register /
tushki7	0:60d829a0353a	944	__IO uint32_t OUT3_CLR; /!< (@ 0x5000451C) SCT output 0 clear register /
tushki7	0:60d829a0353a	945	__IO uint32_t OUT4_SET; /!< (@ 0x50004520) SCT output 0 set register /
tushki7	0:60d829a0353a	946	__IO uint32_t OUT4_CLR; /!< (@ 0x50004524) SCT output 0 clear register /
tushki7	0:60d829a0353a	947	__IO uint32_t OUT5_SET; /!< (@ 0x50004528) SCT output 0 set register /
tushki7	0:60d829a0353a	948	__IO uint32_t OUT5_CLR; /!< (@ 0x5000452C) SCT output 0 clear register /
tushki7	0:60d829a0353a	949	};
tushki7	0:60d829a0353a	950	__IO struct {
tushki7	0:60d829a0353a	951	uint32_t SET;
tushki7	0:60d829a0353a	952	uint32_t CLR;
tushki7	0:60d829a0353a	953	} OUT[6];
tushki7	0:60d829a0353a	954	};
tushki7	0:60d829a0353a	955
tushki7	0:60d829a0353a	956	} LPC_SCT_Type;
tushki7	0:60d829a0353a	957
tushki7	0:60d829a0353a	958
tushki7	0:60d829a0353a	959	/* ================================================================================ */
tushki7	0:60d829a0353a	960	/* ================ DMA ================ */
tushki7	0:60d829a0353a	961	/* ================================================================================ */
tushki7	0:60d829a0353a	962
tushki7	0:60d829a0353a	963
tushki7	0:60d829a0353a	964	/**
tushki7	0:60d829a0353a	965	* @brief DMA controller (DMA)
tushki7	0:60d829a0353a	966	*/
tushki7	0:60d829a0353a	967
tushki7	0:60d829a0353a	968	typedef struct { /!< (@ 0x50008000) DMA Structure /
tushki7	0:60d829a0353a	969	__IO uint32_t CTRL; /!< (@ 0x50008000) DMA control. /
tushki7	0:60d829a0353a	970	__I uint32_t INTSTAT; /!< (@ 0x50008004) Interrupt status. /
tushki7	0:60d829a0353a	971	__IO uint32_t SRAMBASE; /!< (@ 0x50008008) SRAM address of the channel configuration table. /
tushki7	0:60d829a0353a	972	__I uint32_t RESERVED0[5];
tushki7	0:60d829a0353a	973	__IO uint32_t ENABLESET0; /!< (@ 0x50008020) Channel Enable read and Set for all DMA channels. /
tushki7	0:60d829a0353a	974	__I uint32_t RESERVED1;
tushki7	0:60d829a0353a	975	__O uint32_t ENABLECLR0; /!< (@ 0x50008028) Channel Enable Clear for all DMA channels. /
tushki7	0:60d829a0353a	976	__I uint32_t RESERVED2;
tushki7	0:60d829a0353a	977	__I uint32_t ACTIVE0; /!< (@ 0x50008030) Channel Active status for all DMA channels. /
tushki7	0:60d829a0353a	978	__I uint32_t RESERVED3;
tushki7	0:60d829a0353a	979	__I uint32_t BUSY0; /!< (@ 0x50008038) Channel Busy status for all DMA channels. /
tushki7	0:60d829a0353a	980	__I uint32_t RESERVED4;
tushki7	0:60d829a0353a	981	__IO uint32_t ERRINT0; /!< (@ 0x50008040) Error Interrupt status for all DMA channels. /
tushki7	0:60d829a0353a	982	__I uint32_t RESERVED5;
tushki7	0:60d829a0353a	983	__IO uint32_t INTENSET0; /!< (@ 0x50008048) Interrupt Enable read and Set for all DMA channels. /
tushki7	0:60d829a0353a	984	__I uint32_t RESERVED6;
tushki7	0:60d829a0353a	985	__O uint32_t INTENCLR0; /!< (@ 0x50008050) Interrupt Enable Clear for all DMA channels. /
tushki7	0:60d829a0353a	986	__I uint32_t RESERVED7;
tushki7	0:60d829a0353a	987	__IO uint32_t INTA0; /!< (@ 0x50008058) Interrupt A status for all DMA channels. /
tushki7	0:60d829a0353a	988	__I uint32_t RESERVED8;
tushki7	0:60d829a0353a	989	__IO uint32_t INTB0; /!< (@ 0x50008060) Interrupt B status for all DMA channels. /
tushki7	0:60d829a0353a	990	__I uint32_t RESERVED9;
tushki7	0:60d829a0353a	991	__O uint32_t SETVALID0; /!< (@ 0x50008068) Set ValidPending control bits for all DMA channels. /
tushki7	0:60d829a0353a	992	__I uint32_t RESERVED10;
tushki7	0:60d829a0353a	993	__O uint32_t SETTRIG0; /!< (@ 0x50008070) Set Trigger control bits for all DMA channels. /
tushki7	0:60d829a0353a	994	__I uint32_t RESERVED11;
tushki7	0:60d829a0353a	995	__O uint32_t ABORT0; /!< (@ 0x50008078) Channel Abort control for all DMA channels. /
tushki7	0:60d829a0353a	996	__I uint32_t RESERVED12[225];
tushki7	0:60d829a0353a	997	__IO uint32_t CFG0; /!< (@ 0x50008400) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	998	__I uint32_t CTLSTAT0; /!< (@ 0x50008404) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	999	__IO uint32_t XFERCFG0; /*!< (@ 0x50008408) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1000	0. */
tushki7	0:60d829a0353a	1001	__I uint32_t RESERVED13;
tushki7	0:60d829a0353a	1002	__IO uint32_t CFG1; /!< (@ 0x50008410) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1003	__I uint32_t CTLSTAT1; /!< (@ 0x50008414) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1004	__IO uint32_t XFERCFG1; /*!< (@ 0x50008418) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1005	0. */
tushki7	0:60d829a0353a	1006	__I uint32_t RESERVED14;
tushki7	0:60d829a0353a	1007	__IO uint32_t CFG2; /!< (@ 0x50008420) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1008	__I uint32_t CTLSTAT2; /!< (@ 0x50008424) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1009	__IO uint32_t XFERCFG2; /*!< (@ 0x50008428) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1010	0. */
tushki7	0:60d829a0353a	1011	__I uint32_t RESERVED15;
tushki7	0:60d829a0353a	1012	__IO uint32_t CFG3; /!< (@ 0x50008430) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1013	__I uint32_t CTLSTAT3; /!< (@ 0x50008434) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1014	__IO uint32_t XFERCFG3; /*!< (@ 0x50008438) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1015	0. */
tushki7	0:60d829a0353a	1016	__I uint32_t RESERVED16;
tushki7	0:60d829a0353a	1017	__IO uint32_t CFG4; /!< (@ 0x50008440) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1018	__I uint32_t CTLSTAT4; /!< (@ 0x50008444) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1019	__IO uint32_t XFERCFG4; /*!< (@ 0x50008448) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1020	0. */
tushki7	0:60d829a0353a	1021	__I uint32_t RESERVED17;
tushki7	0:60d829a0353a	1022	__IO uint32_t CFG5; /!< (@ 0x50008450) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1023	__I uint32_t CTLSTAT5; /!< (@ 0x50008454) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1024	__IO uint32_t XFERCFG5; /*!< (@ 0x50008458) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1025	0. */
tushki7	0:60d829a0353a	1026	__I uint32_t RESERVED18;
tushki7	0:60d829a0353a	1027	__IO uint32_t CFG6; /!< (@ 0x50008460) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1028	__I uint32_t CTLSTAT6; /!< (@ 0x50008464) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1029	__IO uint32_t XFERCFG6; /*!< (@ 0x50008468) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1030	0. */
tushki7	0:60d829a0353a	1031	__I uint32_t RESERVED19;
tushki7	0:60d829a0353a	1032	__IO uint32_t CFG7; /!< (@ 0x50008470) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1033	__I uint32_t CTLSTAT7; /!< (@ 0x50008474) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1034	__IO uint32_t XFERCFG7; /*!< (@ 0x50008478) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1035	0. */
tushki7	0:60d829a0353a	1036	__I uint32_t RESERVED20;
tushki7	0:60d829a0353a	1037	__IO uint32_t CFG8; /!< (@ 0x50008480) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1038	__I uint32_t CTLSTAT8; /!< (@ 0x50008484) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1039	__IO uint32_t XFERCFG8; /*!< (@ 0x50008488) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1040	0. */
tushki7	0:60d829a0353a	1041	__I uint32_t RESERVED21;
tushki7	0:60d829a0353a	1042	__IO uint32_t CFG9; /!< (@ 0x50008490) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1043	__I uint32_t CTLSTAT9; /!< (@ 0x50008494) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1044	__IO uint32_t XFERCFG9; /*!< (@ 0x50008498) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1045	0. */
tushki7	0:60d829a0353a	1046	__I uint32_t RESERVED22;
tushki7	0:60d829a0353a	1047	__IO uint32_t CFG10; /!< (@ 0x500084A0) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1048	__I uint32_t CTLSTAT10; /!< (@ 0x500084A4) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1049	__IO uint32_t XFERCFG10; /*!< (@ 0x500084A8) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1050	0. */
tushki7	0:60d829a0353a	1051	__I uint32_t RESERVED23;
tushki7	0:60d829a0353a	1052	__IO uint32_t CFG11; /!< (@ 0x500084B0) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1053	__I uint32_t CTLSTAT11; /!< (@ 0x500084B4) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1054	__IO uint32_t XFERCFG11; /*!< (@ 0x500084B8) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1055	0. */
tushki7	0:60d829a0353a	1056	__I uint32_t RESERVED24;
tushki7	0:60d829a0353a	1057	__IO uint32_t CFG12; /!< (@ 0x500084C0) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1058	__I uint32_t CTLSTAT12; /!< (@ 0x500084C4) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1059	__IO uint32_t XFERCFG12; /*!< (@ 0x500084C8) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1060	0. */
tushki7	0:60d829a0353a	1061	__I uint32_t RESERVED25;
tushki7	0:60d829a0353a	1062	__IO uint32_t CFG13; /!< (@ 0x500084D0) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1063	__I uint32_t CTLSTAT13; /!< (@ 0x500084D4) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1064	__IO uint32_t XFERCFG13; /*!< (@ 0x500084D8) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1065	0. */
tushki7	0:60d829a0353a	1066	__I uint32_t RESERVED26;
tushki7	0:60d829a0353a	1067	__IO uint32_t CFG14; /!< (@ 0x500084E0) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1068	__I uint32_t CTLSTAT14; /!< (@ 0x500084E4) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1069	__IO uint32_t XFERCFG14; /*!< (@ 0x500084E8) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1070	0. */
tushki7	0:60d829a0353a	1071	__I uint32_t RESERVED27;
tushki7	0:60d829a0353a	1072	__IO uint32_t CFG15; /!< (@ 0x500084F0) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1073	__I uint32_t CTLSTAT15; /!< (@ 0x500084F4) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1074	__IO uint32_t XFERCFG15; /*!< (@ 0x500084F8) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1075	0. */
tushki7	0:60d829a0353a	1076	__I uint32_t RESERVED28;
tushki7	0:60d829a0353a	1077	__IO uint32_t CFG16; /!< (@ 0x50008500) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1078	__I uint32_t CTLSTAT16; /!< (@ 0x50008504) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1079	__IO uint32_t XFERCFG16; /*!< (@ 0x50008508) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1080	0. */
tushki7	0:60d829a0353a	1081	__I uint32_t RESERVED29;
tushki7	0:60d829a0353a	1082	__IO uint32_t CFG17; /!< (@ 0x50008510) Configuration register for DMA channel 0. /
tushki7	0:60d829a0353a	1083	__I uint32_t CTLSTAT17; /!< (@ 0x50008514) Control and status register for DMA channel 0. /
tushki7	0:60d829a0353a	1084	__IO uint32_t XFERCFG17; /*!< (@ 0x50008518) Transfer configuration register for DMA channel
tushki7	0:60d829a0353a	1085	0. */
tushki7	0:60d829a0353a	1086	} LPC_DMA_Type;
tushki7	0:60d829a0353a	1087
tushki7	0:60d829a0353a	1088
tushki7	0:60d829a0353a	1089	/* ================================================================================ */
tushki7	0:60d829a0353a	1090	/* ================ GPIO_PORT ================ */
tushki7	0:60d829a0353a	1091	/* ================================================================================ */
tushki7	0:60d829a0353a	1092
tushki7	0:60d829a0353a	1093
tushki7	0:60d829a0353a	1094	/**
tushki7	0:60d829a0353a	1095	* @brief General Purpose I/O port (GPIO) (GPIO_PORT)
tushki7	0:60d829a0353a	1096	*/
tushki7	0:60d829a0353a	1097
tushki7	0:60d829a0353a	1098	typedef struct { /!< (@ 0xA0000000) GPIO_PORT Structure /
tushki7	0:60d829a0353a	1099	__IO uint8_t B0; /!< (@ 0xA0000000) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1100	__IO uint8_t B1; /!< (@ 0xA0000001) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1101	__IO uint8_t B2; /!< (@ 0xA0000002) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1102	__IO uint8_t B3; /!< (@ 0xA0000003) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1103	__IO uint8_t B4; /!< (@ 0xA0000004) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1104	__IO uint8_t B5; /!< (@ 0xA0000005) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1105	__IO uint8_t B6; /!< (@ 0xA0000006) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1106	__IO uint8_t B7; /!< (@ 0xA0000007) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1107	__IO uint8_t B8; /!< (@ 0xA0000008) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1108	__IO uint8_t B9; /!< (@ 0xA0000009) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1109	__IO uint8_t B10; /!< (@ 0xA000000A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1110	__IO uint8_t B11; /!< (@ 0xA000000B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1111	__IO uint8_t B12; /!< (@ 0xA000000C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1112	__IO uint8_t B13; /!< (@ 0xA000000D) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1113	__IO uint8_t B14; /!< (@ 0xA000000E) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1114	__IO uint8_t B15; /!< (@ 0xA000000F) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1115	__IO uint8_t B16; /!< (@ 0xA0000010) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1116	__IO uint8_t B17; /!< (@ 0xA0000011) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1117	__IO uint8_t B18; /!< (@ 0xA0000012) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1118	__IO uint8_t B19; /!< (@ 0xA0000013) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1119	__IO uint8_t B20; /!< (@ 0xA0000014) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1120	__IO uint8_t B21; /!< (@ 0xA0000015) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1121	__IO uint8_t B22; /!< (@ 0xA0000016) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1122	__IO uint8_t B23; /!< (@ 0xA0000017) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1123	__IO uint8_t B24; /!< (@ 0xA0000018) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1124	__IO uint8_t B25; /!< (@ 0xA0000019) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1125	__IO uint8_t B26; /!< (@ 0xA000001A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1126	__IO uint8_t B27; /!< (@ 0xA000001B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1127	__IO uint8_t B28; /!< (@ 0xA000001C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
tushki7	0:60d829a0353a	1128	__I uint8_t RESERVED0[4067];
tushki7	0:60d829a0353a	1129	__IO uint32_t W0; /!< (@ 0xA0001000) Word pin registers port 0 /
tushki7	0:60d829a0353a	1130	__IO uint32_t W1; /!< (@ 0xA0001004) Word pin registers port 0 /
tushki7	0:60d829a0353a	1131	__IO uint32_t W2; /!< (@ 0xA0001008) Word pin registers port 0 /
tushki7	0:60d829a0353a	1132	__IO uint32_t W3; /!< (@ 0xA000100C) Word pin registers port 0 /
tushki7	0:60d829a0353a	1133	__IO uint32_t W4; /!< (@ 0xA0001010) Word pin registers port 0 /
tushki7	0:60d829a0353a	1134	__IO uint32_t W5; /!< (@ 0xA0001014) Word pin registers port 0 /
tushki7	0:60d829a0353a	1135	__IO uint32_t W6; /!< (@ 0xA0001018) Word pin registers port 0 /
tushki7	0:60d829a0353a	1136	__IO uint32_t W7; /!< (@ 0xA000101C) Word pin registers port 0 /
tushki7	0:60d829a0353a	1137	__IO uint32_t W8; /!< (@ 0xA0001020) Word pin registers port 0 /
tushki7	0:60d829a0353a	1138	__IO uint32_t W9; /!< (@ 0xA0001024) Word pin registers port 0 /
tushki7	0:60d829a0353a	1139	__IO uint32_t W10; /!< (@ 0xA0001028) Word pin registers port 0 /
tushki7	0:60d829a0353a	1140	__IO uint32_t W11; /!< (@ 0xA000102C) Word pin registers port 0 /
tushki7	0:60d829a0353a	1141	__IO uint32_t W12; /!< (@ 0xA0001030) Word pin registers port 0 /
tushki7	0:60d829a0353a	1142	__IO uint32_t W13; /!< (@ 0xA0001034) Word pin registers port 0 /
tushki7	0:60d829a0353a	1143	__IO uint32_t W14; /!< (@ 0xA0001038) Word pin registers port 0 /
tushki7	0:60d829a0353a	1144	__IO uint32_t W15; /!< (@ 0xA000103C) Word pin registers port 0 /
tushki7	0:60d829a0353a	1145	__IO uint32_t W16; /!< (@ 0xA0001040) Word pin registers port 0 /
tushki7	0:60d829a0353a	1146	__IO uint32_t W17; /!< (@ 0xA0001044) Word pin registers port 0 /
tushki7	0:60d829a0353a	1147	__IO uint32_t W18; /!< (@ 0xA0001048) Word pin registers port 0 /
tushki7	0:60d829a0353a	1148	__IO uint32_t W19; /!< (@ 0xA000104C) Word pin registers port 0 /
tushki7	0:60d829a0353a	1149	__IO uint32_t W20; /!< (@ 0xA0001050) Word pin registers port 0 /
tushki7	0:60d829a0353a	1150	__IO uint32_t W21; /!< (@ 0xA0001054) Word pin registers port 0 /
tushki7	0:60d829a0353a	1151	__IO uint32_t W22; /!< (@ 0xA0001058) Word pin registers port 0 /
tushki7	0:60d829a0353a	1152	__IO uint32_t W23; /!< (@ 0xA000105C) Word pin registers port 0 /
tushki7	0:60d829a0353a	1153	__IO uint32_t W24; /!< (@ 0xA0001060) Word pin registers port 0 /
tushki7	0:60d829a0353a	1154	__IO uint32_t W25; /!< (@ 0xA0001064) Word pin registers port 0 /
tushki7	0:60d829a0353a	1155	__IO uint32_t W26; /!< (@ 0xA0001068) Word pin registers port 0 /
tushki7	0:60d829a0353a	1156	__IO uint32_t W27; /!< (@ 0xA000106C) Word pin registers port 0 /
tushki7	0:60d829a0353a	1157	__IO uint32_t W28; /!< (@ 0xA0001070) Word pin registers port 0 /
tushki7	0:60d829a0353a	1158	__I uint32_t RESERVED1[995];
tushki7	0:60d829a0353a	1159	__IO uint32_t DIR0; /!< (@ 0xA0002000) Direction registers port 0 /
tushki7	0:60d829a0353a	1160	__I uint32_t RESERVED2[31];
tushki7	0:60d829a0353a	1161	__IO uint32_t MASK0; /!< (@ 0xA0002080) Mask register port 0 /
tushki7	0:60d829a0353a	1162	__I uint32_t RESERVED3[31];
tushki7	0:60d829a0353a	1163	__IO uint32_t PIN0; /!< (@ 0xA0002100) Port pin register port 0 /
tushki7	0:60d829a0353a	1164	__I uint32_t RESERVED4[31];
tushki7	0:60d829a0353a	1165	__IO uint32_t MPIN0; /!< (@ 0xA0002180) Masked port register port 0 /
tushki7	0:60d829a0353a	1166	__I uint32_t RESERVED5[31];
tushki7	0:60d829a0353a	1167	__IO uint32_t SET0; /*!< (@ 0xA0002200) Write: Set register for port 0 Read: output bits
tushki7	0:60d829a0353a	1168	for port 0 */
tushki7	0:60d829a0353a	1169	__I uint32_t RESERVED6[31];
tushki7	0:60d829a0353a	1170	__O uint32_t CLR0; /!< (@ 0xA0002280) Clear port 0 /
tushki7	0:60d829a0353a	1171	__I uint32_t RESERVED7[31];
tushki7	0:60d829a0353a	1172	__O uint32_t NOT0; /!< (@ 0xA0002300) Toggle port 0 /
tushki7	0:60d829a0353a	1173	__I uint32_t RESERVED8[31];
tushki7	0:60d829a0353a	1174	__O uint32_t DIRSET0; /!< (@ 0xA0002380) Set pin direction bits for port 0. /
tushki7	0:60d829a0353a	1175	__I uint32_t RESERVED9[31];
tushki7	0:60d829a0353a	1176	__O uint32_t DIRCLR0; /!< (@ 0xA0002400) Clear pin direction bits for port 0. /
tushki7	0:60d829a0353a	1177	__I uint32_t RESERVED10[31];
tushki7	0:60d829a0353a	1178	__O uint32_t DIRNOT0; /!< (@ 0xA0002480) Toggle pin direction bits for port 0. /
tushki7	0:60d829a0353a	1179	} LPC_GPIO_PORT_Type;
tushki7	0:60d829a0353a	1180
tushki7	0:60d829a0353a	1181
tushki7	0:60d829a0353a	1182	/* ================================================================================ */
tushki7	0:60d829a0353a	1183	/* ================ PIN_INT ================ */
tushki7	0:60d829a0353a	1184	/* ================================================================================ */
tushki7	0:60d829a0353a	1185
tushki7	0:60d829a0353a	1186
tushki7	0:60d829a0353a	1187	/**
tushki7	0:60d829a0353a	1188	* @brief Pin interrupt and pattern match engine (PIN_INT)
tushki7	0:60d829a0353a	1189	*/
tushki7	0:60d829a0353a	1190
tushki7	0:60d829a0353a	1191	typedef struct { /!< (@ 0xA0004000) PIN_INT Structure /
tushki7	0:60d829a0353a	1192	__IO uint32_t ISEL; /!< (@ 0xA0004000) Pin Interrupt Mode register /
tushki7	0:60d829a0353a	1193	__IO uint32_t IENR; /*!< (@ 0xA0004004) Pin interrupt level or rising edge interrupt
tushki7	0:60d829a0353a	1194	enable register */
tushki7	0:60d829a0353a	1195	__O uint32_t SIENR; /*!< (@ 0xA0004008) Pin interrupt level (rising edge) interrupt set
tushki7	0:60d829a0353a	1196	register */
tushki7	0:60d829a0353a	1197	__O uint32_t CIENR; /*!< (@ 0xA000400C) Pin interrupt level or rising edge interrupt
tushki7	0:60d829a0353a	1198	clear register */
tushki7	0:60d829a0353a	1199	__IO uint32_t IENF; /*!< (@ 0xA0004010) Pin interrupt active level or falling edge interrupt
tushki7	0:60d829a0353a	1200	enable register */
tushki7	0:60d829a0353a	1201	__O uint32_t SIENF; /*!< (@ 0xA0004014) Pin interrupt active level or falling edge interrupt
tushki7	0:60d829a0353a	1202	set register */
tushki7	0:60d829a0353a	1203	__O uint32_t CIENF; /*!< (@ 0xA0004018) Pin interrupt active level (falling edge) interrupt
tushki7	0:60d829a0353a	1204	clear register */
tushki7	0:60d829a0353a	1205	__IO uint32_t RISE; /!< (@ 0xA000401C) Pin interrupt rising edge register /
tushki7	0:60d829a0353a	1206	__IO uint32_t FALL; /!< (@ 0xA0004020) Pin interrupt falling edge register /
tushki7	0:60d829a0353a	1207	__IO uint32_t IST; /!< (@ 0xA0004024) Pin interrupt status register /
tushki7	0:60d829a0353a	1208	__IO uint32_t PMCTRL; /!< (@ 0xA0004028) GPIO pattern match interrupt control register /
tushki7	0:60d829a0353a	1209	__IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source
tushki7	0:60d829a0353a	1210	register */
tushki7	0:60d829a0353a	1211	__IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration
tushki7	0:60d829a0353a	1212	register */
tushki7	0:60d829a0353a	1213	} LPC_PIN_INT_Type;
tushki7	0:60d829a0353a	1214
tushki7	0:60d829a0353a	1215
tushki7	0:60d829a0353a	1216	/* -------------------- End of section using anonymous unions ------------------- */
tushki7	0:60d829a0353a	1217	#if defined(__CC_ARM)
tushki7	0:60d829a0353a	1218	#pragma pop
tushki7	0:60d829a0353a	1219	#elif defined(__ICCARM__)
tushki7	0:60d829a0353a	1220	/* leave anonymous unions enabled */
tushki7	0:60d829a0353a	1221	#elif defined(__GNUC__)
tushki7	0:60d829a0353a	1222	/* anonymous unions are enabled by default */
tushki7	0:60d829a0353a	1223	#elif defined(__TMS470__)
tushki7	0:60d829a0353a	1224	/* anonymous unions are enabled by default */
tushki7	0:60d829a0353a	1225	#elif defined(__TASKING__)
tushki7	0:60d829a0353a	1226	#pragma warning restore
tushki7	0:60d829a0353a	1227	#else
tushki7	0:60d829a0353a	1228	#warning Not supported compiler type
tushki7	0:60d829a0353a	1229	#endif
tushki7	0:60d829a0353a	1230
tushki7	0:60d829a0353a	1231
tushki7	0:60d829a0353a	1232
tushki7	0:60d829a0353a	1233
tushki7	0:60d829a0353a	1234	/* ================================================================================ */
tushki7	0:60d829a0353a	1235	/* ================ Peripheral memory map ================ */
tushki7	0:60d829a0353a	1236	/* ================================================================================ */
tushki7	0:60d829a0353a	1237
tushki7	0:60d829a0353a	1238	#define LPC_WWDT_BASE 0x40000000UL
tushki7	0:60d829a0353a	1239	#define LPC_MRT_BASE 0x40004000UL
tushki7	0:60d829a0353a	1240	#define LPC_WKT_BASE 0x40008000UL
tushki7	0:60d829a0353a	1241	#define LPC_SWM_BASE 0x4000C000UL
tushki7	0:60d829a0353a	1242	#define LPC_ADC_BASE 0x4001C000UL
tushki7	0:60d829a0353a	1243	#define LPC_PMU_BASE 0x40020000UL
tushki7	0:60d829a0353a	1244	#define LPC_CMP_BASE 0x40024000UL
tushki7	0:60d829a0353a	1245	#define LPC_DMATRIGMUX_BASE 0x40028000UL
tushki7	0:60d829a0353a	1246	#define LPC_INPUTMUX_BASE 0x4002C000UL
tushki7	0:60d829a0353a	1247	#define LPC_FLASHCTRL_BASE 0x40040000UL
tushki7	0:60d829a0353a	1248	#define LPC_IOCON_BASE 0x40044000UL
tushki7	0:60d829a0353a	1249	#define LPC_SYSCON_BASE 0x40048000UL
tushki7	0:60d829a0353a	1250	#define LPC_I2C0_BASE 0x40050000UL
tushki7	0:60d829a0353a	1251	#define LPC_I2C1_BASE 0x40054000UL
tushki7	0:60d829a0353a	1252	#define LPC_SPI0_BASE 0x40058000UL
tushki7	0:60d829a0353a	1253	#define LPC_SPI1_BASE 0x4005C000UL
tushki7	0:60d829a0353a	1254	#define LPC_USART0_BASE 0x40064000UL
tushki7	0:60d829a0353a	1255	#define LPC_USART1_BASE 0x40068000UL
tushki7	0:60d829a0353a	1256	#define LPC_USART2_BASE 0x4006C000UL
tushki7	0:60d829a0353a	1257	#define LPC_I2C2_BASE 0x40070000UL
tushki7	0:60d829a0353a	1258	#define LPC_I2C3_BASE 0x40074000UL
tushki7	0:60d829a0353a	1259	#define LPC_CRC_BASE 0x50000000UL
tushki7	0:60d829a0353a	1260	#define LPC_SCT_BASE 0x50004000UL
tushki7	0:60d829a0353a	1261	#define LPC_DMA_BASE 0x50008000UL
tushki7	0:60d829a0353a	1262	#define LPC_GPIO_PORT_BASE 0xA0000000UL
tushki7	0:60d829a0353a	1263	#define LPC_PIN_INT_BASE 0xA0004000UL
tushki7	0:60d829a0353a	1264
tushki7	0:60d829a0353a	1265
tushki7	0:60d829a0353a	1266	/* ================================================================================ */
tushki7	0:60d829a0353a	1267	/* ================ Peripheral declaration ================ */
tushki7	0:60d829a0353a	1268	/* ================================================================================ */
tushki7	0:60d829a0353a	1269
tushki7	0:60d829a0353a	1270	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
tushki7	0:60d829a0353a	1271	#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
tushki7	0:60d829a0353a	1272	#define LPC_WKT ((LPC_WKT_Type *) LPC_WKT_BASE)
tushki7	0:60d829a0353a	1273	#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
tushki7	0:60d829a0353a	1274	#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
tushki7	0:60d829a0353a	1275	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
tushki7	0:60d829a0353a	1276	#define LPC_CMP ((LPC_CMP_Type *) LPC_CMP_BASE)
tushki7	0:60d829a0353a	1277	#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
tushki7	0:60d829a0353a	1278	#define LPC_INPUTMUX ((LPC_INPUTMUX_Type *) LPC_INPUTMUX_BASE)
tushki7	0:60d829a0353a	1279	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
tushki7	0:60d829a0353a	1280	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
tushki7	0:60d829a0353a	1281	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
tushki7	0:60d829a0353a	1282	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
tushki7	0:60d829a0353a	1283	#define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
tushki7	0:60d829a0353a	1284	#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
tushki7	0:60d829a0353a	1285	#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
tushki7	0:60d829a0353a	1286	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
tushki7	0:60d829a0353a	1287	#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
tushki7	0:60d829a0353a	1288	#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
tushki7	0:60d829a0353a	1289	#define LPC_I2C2 ((LPC_I2C0_Type *) LPC_I2C2_BASE)
tushki7	0:60d829a0353a	1290	#define LPC_I2C3 ((LPC_I2C0_Type *) LPC_I2C3_BASE)
tushki7	0:60d829a0353a	1291	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
tushki7	0:60d829a0353a	1292	#define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE)
tushki7	0:60d829a0353a	1293	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
tushki7	0:60d829a0353a	1294	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
tushki7	0:60d829a0353a	1295	#define LPC_PIN_INT ((LPC_PIN_INT_Type *) LPC_PIN_INT_BASE)
tushki7	0:60d829a0353a	1296
tushki7	0:60d829a0353a	1297
tushki7	0:60d829a0353a	1298	/** @} / / End of group Device_Peripheral_Registers */
tushki7	0:60d829a0353a	1299	/** @} / / End of group LPC82x */
tushki7	0:60d829a0353a	1300	/** @} / / End of group (null) */
tushki7	0:60d829a0353a	1301
tushki7	0:60d829a0353a	1302	#ifdef __cplusplus
tushki7	0:60d829a0353a	1303	}
tushki7	0:60d829a0353a	1304	#endif
tushki7	0:60d829a0353a	1305
tushki7	0:60d829a0353a	1306
tushki7	0:60d829a0353a	1307	#endif /* LPC82x_H */
tushki7	0:60d829a0353a	1308

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Type:	Program
Created:	11 Apr 2015
Imports:	100
Forks:	0
Commits:	2
Dependents:	0
Dependencies:	1
Followers:	2

mbed/TARGET_SSCI824/LPC82x.h@0:60d829a0353a, 2015-04-11 (annotated)

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