lpc17xx_gpdma.h

00001 /***********************************************************************//**
00002  * @file        lpc17xx_gpdma.h
00003  * @brief        Contains all macro definitions and function prototypes
00004  *                 support for GPDMA firmware library on LPC17xx
00005  * @version        2.0
00006  * @date        21. May. 2010
00007  * @author        NXP MCU SW Application Team
00008  **************************************************************************
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * products. This software is supplied "AS IS" without any warranties.
00012  * NXP Semiconductors assumes no responsibility or liability for the
00013  * use of the software, conveys no license or title under any patent,
00014  * copyright, or mask work right to the product. NXP Semiconductors
00015  * reserves the right to make changes in the software without
00016  * notification. NXP Semiconductors also make no representation or
00017  * warranty that such application will be suitable for the specified
00018  * use without further testing or modification.
00019  **************************************************************************/
00020 
00021 /* Peripheral group ----------------------------------------------------------- */
00022 /** @defgroup GPDMA GPDMA
00023  * @ingroup LPC1700CMSIS_FwLib_Drivers
00024  * @{
00025  */
00026 
00027 #ifndef LPC17XX_GPDMA_H_
00028 #define LPC17XX_GPDMA_H_
00029 
00030 /* Includes ------------------------------------------------------------------- */
00031 #include "LPC17xx.h"
00032 #include "lpc_types.h"
00033 
00034 
00035 #ifdef __cplusplus
00036 extern "C"
00037 {
00038 #endif
00039 
00040 /* Public Macros -------------------------------------------------------------- */
00041 /** @defgroup GPDMA_Public_Macros GPDMA Public Macros
00042  * @{
00043  */
00044 
00045 /** Peripheral declaration   */
00046 #define DMAREQSEL                      (*(__IO uint32_t *)  ( 0x4000C1C4))
00047 
00048 /** DMA Connection number definitions */
00049 #define GPDMA_CONN_SSP0_Tx             ((0UL))         /**< SSP0 Tx */
00050 #define GPDMA_CONN_SSP0_Rx             ((1UL))         /**< SSP0 Rx */
00051 #define GPDMA_CONN_SSP1_Tx             ((2UL))         /**< SSP1 Tx */
00052 #define GPDMA_CONN_SSP1_Rx             ((3UL))         /**< SSP1 Rx */
00053 #define GPDMA_CONN_ADC                 ((4UL))         /**< ADC */
00054 #define GPDMA_CONN_I2S_Channel_0       ((5UL))         /**< I2S channel 0 */
00055 #define GPDMA_CONN_I2S_Channel_1       ((6UL))         /**< I2S channel 1 */
00056 #define GPDMA_CONN_DAC                 ((7UL))         /**< DAC */
00057 #define GPDMA_CONN_UART0_Tx            ((8UL))         /**< UART0 Tx */
00058 #define GPDMA_CONN_UART0_Rx            ((9UL))         /**< UART0 Rx */
00059 #define GPDMA_CONN_UART1_Tx            ((10UL))         /**< UART1 Tx */
00060 #define GPDMA_CONN_UART1_Rx            ((11UL))         /**< UART1 Rx */
00061 #define GPDMA_CONN_UART2_Tx            ((12UL))         /**< UART2 Tx */
00062 #define GPDMA_CONN_UART2_Rx            ((13UL))         /**< UART2 Rx */
00063 #define GPDMA_CONN_UART3_Tx            ((14UL))         /**< UART3 Tx */
00064 #define GPDMA_CONN_UART3_Rx            ((15UL))         /**< UART3 Rx */
00065 #define GPDMA_CONN_MAT0_0              ((16UL))         /**< MAT0.0 */
00066 #define GPDMA_CONN_MAT0_1              ((17UL))         /**< MAT0.1 */
00067 #define GPDMA_CONN_MAT1_0              ((18UL))         /**< MAT1.0 */
00068 #define GPDMA_CONN_MAT1_1              ((19UL))         /**< MAT1.1 */
00069 #define GPDMA_CONN_MAT2_0              ((20UL))         /**< MAT2.0 */
00070 #define GPDMA_CONN_MAT2_1              ((21UL))         /**< MAT2.1 */
00071 #define GPDMA_CONN_MAT3_0              ((22UL))         /**< MAT3.0 */
00072 #define GPDMA_CONN_MAT3_1              ((23UL))         /**< MAT3.1 */
00073 
00074 /** GPDMA Transfer type definitions */
00075 #define GPDMA_TRANSFERTYPE_M2M         ((0UL))     /**< Memory to memory - DMA control */
00076 #define GPDMA_TRANSFERTYPE_M2P         ((1UL))     /**< Memory to peripheral - DMA control */
00077 #define GPDMA_TRANSFERTYPE_P2M         ((2UL))     /**< Peripheral to memory - DMA control */
00078 #define GPDMA_TRANSFERTYPE_P2P         ((3UL))     /**< Source peripheral to destination peripheral - DMA control */
00079 
00080 /** Burst size in Source and Destination definitions */
00081 #define GPDMA_BSIZE_1      ((0UL)) /**< Burst size = 1 */
00082 #define GPDMA_BSIZE_4      ((1UL)) /**< Burst size = 4 */
00083 #define GPDMA_BSIZE_8      ((2UL)) /**< Burst size = 8 */
00084 #define GPDMA_BSIZE_16     ((3UL)) /**< Burst size = 16 */
00085 #define GPDMA_BSIZE_32     ((4UL)) /**< Burst size = 32 */
00086 #define GPDMA_BSIZE_64     ((5UL)) /**< Burst size = 64 */
00087 #define GPDMA_BSIZE_128    ((6UL)) /**< Burst size = 128 */
00088 #define GPDMA_BSIZE_256    ((7UL)) /**< Burst size = 256 */
00089 
00090 /** Width in Source transfer width and Destination transfer width definitions */
00091 #define GPDMA_WIDTH_BYTE         ((0UL)) /**< Width = 1 byte */
00092 #define GPDMA_WIDTH_HALFWORD     ((1UL)) /**< Width = 2 bytes */
00093 #define GPDMA_WIDTH_WORD         ((2UL)) /**< Width = 4 bytes */
00094 
00095 /** DMA Request Select Mode definitions */
00096 #define GPDMA_REQSEL_UART      ((0UL)) /**< UART TX/RX is selected */
00097 #define GPDMA_REQSEL_TIMER     ((1UL)) /**< Timer match is selected */
00098 
00099 /**
00100  * @}
00101  */
00102 
00103 
00104 /* Private Macros ------------------------------------------------------------- */
00105 /** @defgroup GPDMA_Private_Macros GPDMA Private Macros
00106  * @{
00107  */
00108 
00109 /* --------------------- BIT DEFINITIONS -------------------------------------- */
00110 /*********************************************************************//**
00111  * Macro defines for DMA Interrupt Status register
00112  **********************************************************************/
00113 #define GPDMA_DMACIntStat_Ch(n)            (((1UL<<n)&0xFF))
00114 #define GPDMA_DMACIntStat_BITMASK        ((0xFF))
00115 
00116 /*********************************************************************//**
00117  * Macro defines for DMA Interrupt Terminal Count Request Status register
00118  **********************************************************************/
00119 #define GPDMA_DMACIntTCStat_Ch(n)        (((1UL<<n)&0xFF))
00120 #define GPDMA_DMACIntTCStat_BITMASK        ((0xFF))
00121 
00122 /*********************************************************************//**
00123  * Macro defines for DMA Interrupt Terminal Count Request Clear register
00124  **********************************************************************/
00125 #define GPDMA_DMACIntTCClear_Ch(n)        (((1UL<<n)&0xFF))
00126 #define GPDMA_DMACIntTCClear_BITMASK    ((0xFF))
00127 
00128 /*********************************************************************//**
00129  * Macro defines for DMA Interrupt Error Status register
00130  **********************************************************************/
00131 #define GPDMA_DMACIntErrStat_Ch(n)        (((1UL<<n)&0xFF))
00132 #define GPDMA_DMACIntErrStat_BITMASK    ((0xFF))
00133 
00134 /*********************************************************************//**
00135  * Macro defines for DMA Interrupt Error Clear register
00136  **********************************************************************/
00137 #define GPDMA_DMACIntErrClr_Ch(n)        (((1UL<<n)&0xFF))
00138 #define GPDMA_DMACIntErrClr_BITMASK        ((0xFF))
00139 
00140 /*********************************************************************//**
00141  * Macro defines for DMA Raw Interrupt Terminal Count Status register
00142  **********************************************************************/
00143 #define GPDMA_DMACRawIntTCStat_Ch(n)    (((1UL<<n)&0xFF))
00144 #define GPDMA_DMACRawIntTCStat_BITMASK    ((0xFF))
00145 
00146 /*********************************************************************//**
00147  * Macro defines for DMA Raw Error Interrupt Status register
00148  **********************************************************************/
00149 #define GPDMA_DMACRawIntErrStat_Ch(n)    (((1UL<<n)&0xFF))
00150 #define GPDMA_DMACRawIntErrStat_BITMASK    ((0xFF))
00151 
00152 /*********************************************************************//**
00153  * Macro defines for DMA Enabled Channel register
00154  **********************************************************************/
00155 #define GPDMA_DMACEnbldChns_Ch(n)        (((1UL<<n)&0xFF))
00156 #define GPDMA_DMACEnbldChns_BITMASK        ((0xFF))
00157 
00158 /*********************************************************************//**
00159  * Macro defines for DMA Software Burst Request register
00160  **********************************************************************/
00161 #define    GPDMA_DMACSoftBReq_Src(n)        (((1UL<<n)&0xFFFF))
00162 #define GPDMA_DMACSoftBReq_BITMASK        ((0xFFFF))
00163 
00164 /*********************************************************************//**
00165  * Macro defines for DMA Software Single Request register
00166  **********************************************************************/
00167 #define GPDMA_DMACSoftSReq_Src(n)         (((1UL<<n)&0xFFFF))
00168 #define GPDMA_DMACSoftSReq_BITMASK        ((0xFFFF))
00169 
00170 /*********************************************************************//**
00171  * Macro defines for DMA Software Last Burst Request register
00172  **********************************************************************/
00173 #define GPDMA_DMACSoftLBReq_Src(n)        (((1UL<<n)&0xFFFF))
00174 #define GPDMA_DMACSoftLBReq_BITMASK        ((0xFFFF))
00175 
00176 /*********************************************************************//**
00177  * Macro defines for DMA Software Last Single Request register
00178  **********************************************************************/
00179 #define GPDMA_DMACSoftLSReq_Src(n)         (((1UL<<n)&0xFFFF))
00180 #define GPDMA_DMACSoftLSReq_BITMASK        ((0xFFFF))
00181 
00182 /*********************************************************************//**
00183  * Macro defines for DMA Configuration register
00184  **********************************************************************/
00185 #define GPDMA_DMACConfig_E                ((0x01))     /**< DMA Controller enable*/
00186 #define GPDMA_DMACConfig_M                ((0x02))     /**< AHB Master endianness configuration*/
00187 #define GPDMA_DMACConfig_BITMASK        ((0x03))
00188 
00189 /*********************************************************************//**
00190  * Macro defines for DMA Synchronization register
00191  **********************************************************************/
00192 #define GPDMA_DMACSync_Src(n)            (((1UL<<n)&0xFFFF))
00193 #define GPDMA_DMACSync_BITMASK            ((0xFFFF))
00194 
00195 /*********************************************************************//**
00196  * Macro defines for DMA Request Select register
00197  **********************************************************************/
00198 #define GPDMA_DMAReqSel_Input(n)        (((1UL<<(n-8))&0xFF))
00199 #define GPDMA_DMAReqSel_BITMASK            ((0xFF))
00200 
00201 /*********************************************************************//**
00202  * Macro defines for DMA Channel Linked List Item registers
00203  **********************************************************************/
00204 /** DMA Channel Linked List Item registers bit mask*/
00205 #define GPDMA_DMACCxLLI_BITMASK         ((0xFFFFFFFC))
00206 
00207 /*********************************************************************//**
00208  * Macro defines for DMA channel control registers
00209  **********************************************************************/
00210 #define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0))     /**< Transfer size*/
00211 #define GPDMA_DMACCxControl_SBSize(n)        (((n&0x07)<<12))     /**< Source burst size*/
00212 #define GPDMA_DMACCxControl_DBSize(n)        (((n&0x07)<<15))     /**< Destination burst size*/
00213 #define GPDMA_DMACCxControl_SWidth(n)        (((n&0x07)<<18))     /**< Source transfer width*/
00214 #define GPDMA_DMACCxControl_DWidth(n)        (((n&0x07)<<21))     /**< Destination transfer width*/
00215 #define GPDMA_DMACCxControl_SI                ((1UL<<26))         /**< Source increment*/
00216 #define GPDMA_DMACCxControl_DI                ((1UL<<27))         /**< Destination increment*/
00217 #define GPDMA_DMACCxControl_Prot1            ((1UL<<28))         /**< Indicates that the access is in user mode or privileged mode*/
00218 #define GPDMA_DMACCxControl_Prot2            ((1UL<<29))         /**< Indicates that the access is bufferable or not bufferable*/
00219 #define GPDMA_DMACCxControl_Prot3            ((1UL<<30))         /**< Indicates that the access is cacheable or not cacheable*/
00220 #define GPDMA_DMACCxControl_I                ((1UL<<31))         /**< Terminal count interrupt enable bit */
00221 /** DMA channel control registers bit mask */
00222 #define GPDMA_DMACCxControl_BITMASK            ((0xFCFFFFFF))
00223 
00224 /*********************************************************************//**
00225  * Macro defines for DMA Channel Configuration registers
00226  **********************************************************************/
00227 #define GPDMA_DMACCxConfig_E                     ((1UL<<0))            /**< DMA control enable*/
00228 #define GPDMA_DMACCxConfig_SrcPeripheral(n)     (((n&0x1F)<<1))     /**< Source peripheral*/
00229 #define GPDMA_DMACCxConfig_DestPeripheral(n)     (((n&0x1F)<<6))     /**< Destination peripheral*/
00230 #define GPDMA_DMACCxConfig_TransferType(n)         (((n&0x7)<<11))     /**< This value indicates the type of transfer*/
00231 #define GPDMA_DMACCxConfig_IE                     ((1UL<<14))            /**< Interrupt error mask*/
00232 #define GPDMA_DMACCxConfig_ITC                     ((1UL<<15))         /**< Terminal count interrupt mask*/
00233 #define GPDMA_DMACCxConfig_L                     ((1UL<<16))         /**< Lock*/
00234 #define GPDMA_DMACCxConfig_A                     ((1UL<<17))         /**< Active*/
00235 #define GPDMA_DMACCxConfig_H                     ((1UL<<18))         /**< Halt*/
00236 /** DMA Channel Configuration registers bit mask */
00237 #define GPDMA_DMACCxConfig_BITMASK                ((0x7FFFF))
00238 
00239 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
00240 /* Macros check GPDMA channel */
00241 #define PARAM_GPDMA_CHANNEL(n)    ((n>=0) && (n<=7))
00242 
00243 /* Macros check GPDMA connection type */
00244 #define PARAM_GPDMA_CONN(n)        ((n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
00245 || (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
00246 || (n==GPDMA_CONN_ADC) || (n==GPDMA_CONN_I2S_Channel_0) \
00247 || (n==GPDMA_CONN_I2S_Channel_1) || (n==GPDMA_CONN_DAC) \
00248 || (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
00249 || (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
00250 || (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
00251 || (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
00252 || (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
00253 || (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
00254 || (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
00255 || (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
00256 
00257 /* Macros check GPDMA burst size type */
00258 #define PARAM_GPDMA_BSIZE(n)    ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
00259 || (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
00260 || (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
00261 || (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
00262 
00263 /* Macros check GPDMA width type */
00264 #define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
00265 || (n==GPDMA_WIDTH_WORD))
00266 
00267 /* Macros check GPDMA status type */
00268 #define PARAM_GPDMA_STAT(n)    ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
00269 || (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
00270 || (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
00271 
00272 /* Macros check GPDMA transfer type */
00273 #define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)||(n==GPDMA_TRANSFERTYPE_M2P) \
00274 ||(n==GPDMA_TRANSFERTYPE_P2M)||(n==GPDMA_TRANSFERTYPE_P2P))
00275 
00276 /* Macros check GPDMA state clear type */
00277 #define PARAM_GPDMA_STATCLR(n)    ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
00278 
00279 /* Macros check GPDMA request select type */
00280 #define PARAM_GPDMA_REQSEL(n)    ((n==GPDMA_REQSEL_UART) || (n==GPDMA_REQSEL_TIMER))
00281 /**
00282  * @}
00283  */
00284 
00285 
00286 /* Public Types --------------------------------------------------------------- */
00287 /** @defgroup GPDMA_Public_Types GPDMA Public Types
00288  * @{
00289  */
00290 
00291 /**
00292  * @brief GPDMA Status enumeration
00293  */
00294 typedef enum {
00295     GPDMA_STAT_INT,            /**< GPDMA Interrupt Status */
00296     GPDMA_STAT_INTTC,        /**< GPDMA Interrupt Terminal Count Request Status */
00297     GPDMA_STAT_INTERR,        /**< GPDMA Interrupt Error Status */
00298     GPDMA_STAT_RAWINTTC,    /**< GPDMA Raw Interrupt Terminal Count Status */
00299     GPDMA_STAT_RAWINTERR,    /**< GPDMA Raw Error Interrupt Status */
00300     GPDMA_STAT_ENABLED_CH    /**< GPDMA Enabled Channel Status */
00301 } GPDMA_Status_Type;
00302 
00303 /**
00304  * @brief GPDMA Interrupt clear status enumeration
00305  */
00306 typedef enum{
00307     GPDMA_STATCLR_INTTC,    /**< GPDMA Interrupt Terminal Count Request Clear */
00308     GPDMA_STATCLR_INTERR    /**< GPDMA Interrupt Error Clear */
00309 }GPDMA_StateClear_Type;
00310 
00311 /**
00312  * @brief GPDMA Channel configuration structure type definition
00313  */
00314 typedef struct {
00315     uint32_t ChannelNum;     /**< DMA channel number, should be in
00316                                 range from 0 to 7.
00317                                 Note: DMA channel 0 has the highest priority
00318                                 and DMA channel 7 the lowest priority.
00319                                 */
00320     uint32_t TransferSize;    /**< Length/Size of transfer */
00321     uint32_t TransferWidth;    /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
00322     uint32_t SrcMemAddr;    /**< Physical Source Address, used in case TransferType is chosen as
00323                                  GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
00324     uint32_t DstMemAddr;    /**< Physical Destination Address, used in case TransferType is chosen as
00325                                  GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
00326     uint32_t TransferType;    /**< Transfer Type, should be one of the following:
00327                             - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
00328                             - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
00329                             - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
00330                             - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
00331                             */
00332     uint32_t SrcConn;        /**< Peripheral Source Connection type, used in case TransferType is chosen as
00333                             GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
00334                             following:
00335                              - GPDMA_CONN_SSP0_Tx: SSP0, Tx
00336                              - GPDMA_CONN_SSP0_Rx: SSP0, Rx
00337                              - GPDMA_CONN_SSP1_Tx: SSP1, Tx
00338                              - GPDMA_CONN_SSP1_Rx: SSP1, Rx
00339                              - GPDMA_CONN_ADC: ADC
00340                              - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
00341                              - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
00342                              - GPDMA_CONN_DAC: DAC
00343                              - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
00344                              - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
00345                              - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
00346                              - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
00347                              - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
00348                              - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
00349                              - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
00350                              - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
00351                              */
00352     uint32_t DstConn;        /**< Peripheral Destination Connection type, used in case TransferType is chosen as
00353                             GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
00354                             following:
00355                              - GPDMA_CONN_SSP0_Tx: SSP0, Tx
00356                              - GPDMA_CONN_SSP0_Rx: SSP0, Rx
00357                              - GPDMA_CONN_SSP1_Tx: SSP1, Tx
00358                              - GPDMA_CONN_SSP1_Rx: SSP1, Rx
00359                              - GPDMA_CONN_ADC: ADC
00360                              - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
00361                              - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
00362                              - GPDMA_CONN_DAC: DAC
00363                              - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
00364                              - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
00365                              - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
00366                              - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
00367                              - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
00368                              - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
00369                              - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
00370                              - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
00371                              */
00372     uint32_t DMALLI;        /**< Linker List Item structure data address
00373                             if there's no Linker List, set as '0'
00374                             */
00375 } GPDMA_Channel_CFG_Type;
00376 
00377 /**
00378  * @brief GPDMA Linker List Item structure type definition
00379  */
00380 typedef struct {
00381     uint32_t SrcAddr;    /**< Source Address */
00382     uint32_t DstAddr;    /**< Destination address */
00383     uint32_t NextLLI;    /**< Next LLI address, otherwise set to '0' */
00384     uint32_t Control;    /**< GPDMA Control of this LLI */
00385 } GPDMA_LLI_Type;
00386 
00387 
00388 /**
00389  * @}
00390  */
00391 
00392 /* Public Functions ----------------------------------------------------------- */
00393 /** @defgroup GPDMA_Public_Functions GPDMA Public Functions
00394  * @{
00395  */
00396 
00397 void GPDMA_Init(void);
00398 //Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs);
00399 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
00400 IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
00401 void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
00402 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
00403 //void GPDMA_IntHandler(void);
00404 
00405 /**
00406  * @}
00407  */
00408 
00409 
00410 #ifdef __cplusplus
00411 }
00412 #endif
00413 
00414 #endif /* LPC17XX_GPDMA_H_ */
00415 
00416 /**
00417  * @}
00418  */
00419 
00420 /* --------------------------------- End Of File ------------------------------ */