Ken Todotani
Memory to Memory DMA demo from CMSIS example. This demo execute 1000 times of 32 word memory to memory DMA (copy), and also measures number of dummy loop execution during DMA cylcles. Line 56 of "DMA_M2M.c" can change DMA source. where; 1)static : source is SRAM 2)const : source is Flash ROM
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lpc17xx_clkpwr.c
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00001 /***********************************************************************//** 00002 * @file lpc17xx_clkpwr.c 00003 * @brief Contains all functions support for Clock and Power Control 00004 * firmware library on LPC17xx 00005 * @version 3.0 00006 * @date 18. June. 2010 00007 * @author NXP MCU SW Application Team 00008 ************************************************************************** 00009 * Software that is described herein is for illustrative purposes only 00010 * which provides customers with programming information regarding the 00011 * products. This software is supplied "AS IS" without any warranties. 00012 * NXP Semiconductors assumes no responsibility or liability for the 00013 * use of the software, conveys no license or title under any patent, 00014 * copyright, or mask work right to the product. NXP Semiconductors 00015 * reserves the right to make changes in the software without 00016 * notification. NXP Semiconductors also make no representation or 00017 * warranty that such application will be suitable for the specified 00018 * use without further testing or modification. 00019 **********************************************************************/ 00020 00021 /* Peripheral group ----------------------------------------------------------- */ 00022 /** @addtogroup CLKPWR 00023 * @{ 00024 */ 00025 00026 /* Includes ------------------------------------------------------------------- */ 00027 #include "lpc17xx_clkpwr.h" 00028 00029 00030 /* Public Functions ----------------------------------------------------------- */ 00031 /** @addtogroup CLKPWR_Public_Functions 00032 * @{ 00033 */ 00034 00035 /*********************************************************************//** 00036 * @brief Set value of each Peripheral Clock Selection 00037 * @param[in] ClkType Peripheral Clock Selection of each type, 00038 * should be one of the following: 00039 * - CLKPWR_PCLKSEL_WDT : WDT 00040 - CLKPWR_PCLKSEL_TIMER0 : Timer 0 00041 - CLKPWR_PCLKSEL_TIMER1 : Timer 1 00042 - CLKPWR_PCLKSEL_UART0 : UART 0 00043 - CLKPWR_PCLKSEL_UART1 : UART 1 00044 - CLKPWR_PCLKSEL_PWM1 : PWM 1 00045 - CLKPWR_PCLKSEL_I2C0 : I2C 0 00046 - CLKPWR_PCLKSEL_SPI : SPI 00047 - CLKPWR_PCLKSEL_SSP1 : SSP 1 00048 - CLKPWR_PCLKSEL_DAC : DAC 00049 - CLKPWR_PCLKSEL_ADC : ADC 00050 - CLKPWR_PCLKSEL_CAN1 : CAN 1 00051 - CLKPWR_PCLKSEL_CAN2 : CAN 2 00052 - CLKPWR_PCLKSEL_ACF : ACF 00053 - CLKPWR_PCLKSEL_QEI : QEI 00054 - CLKPWR_PCLKSEL_PCB : PCB 00055 - CLKPWR_PCLKSEL_I2C1 : I2C 1 00056 - CLKPWR_PCLKSEL_SSP0 : SSP 0 00057 - CLKPWR_PCLKSEL_TIMER2 : Timer 2 00058 - CLKPWR_PCLKSEL_TIMER3 : Timer 3 00059 - CLKPWR_PCLKSEL_UART2 : UART 2 00060 - CLKPWR_PCLKSEL_UART3 : UART 3 00061 - CLKPWR_PCLKSEL_I2C2 : I2C 2 00062 - CLKPWR_PCLKSEL_I2S : I2S 00063 - CLKPWR_PCLKSEL_RIT : RIT 00064 - CLKPWR_PCLKSEL_SYSCON : SYSCON 00065 - CLKPWR_PCLKSEL_MC : MC 00066 00067 * @param[in] DivVal Value of divider, should be: 00068 * - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4 00069 * - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1 00070 * - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2 00071 * 00072 * @return none 00073 **********************************************************************/ 00074 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal) 00075 { 00076 uint32_t bitpos; 00077 00078 bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32); 00079 00080 /* PCLKSEL0 selected */ 00081 if (ClkType < 32) 00082 { 00083 /* Clear two bit at bit position */ 00084 LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos))); 00085 00086 /* Set two selected bit */ 00087 LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal)); 00088 } 00089 /* PCLKSEL1 selected */ 00090 else 00091 { 00092 /* Clear two bit at bit position */ 00093 LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos)); 00094 00095 /* Set two selected bit */ 00096 LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal)); 00097 } 00098 } 00099 00100 00101 /*********************************************************************//** 00102 * @brief Get current value of each Peripheral Clock Selection 00103 * @param[in] ClkType Peripheral Clock Selection of each type, 00104 * should be one of the following: 00105 * - CLKPWR_PCLKSEL_WDT : WDT 00106 - CLKPWR_PCLKSEL_TIMER0 : Timer 0 00107 - CLKPWR_PCLKSEL_TIMER1 : Timer 1 00108 - CLKPWR_PCLKSEL_UART0 : UART 0 00109 - CLKPWR_PCLKSEL_UART1 : UART 1 00110 - CLKPWR_PCLKSEL_PWM1 : PWM 1 00111 - CLKPWR_PCLKSEL_I2C0 : I2C 0 00112 - CLKPWR_PCLKSEL_SPI : SPI 00113 - CLKPWR_PCLKSEL_SSP1 : SSP 1 00114 - CLKPWR_PCLKSEL_DAC : DAC 00115 - CLKPWR_PCLKSEL_ADC : ADC 00116 - CLKPWR_PCLKSEL_CAN1 : CAN 1 00117 - CLKPWR_PCLKSEL_CAN2 : CAN 2 00118 - CLKPWR_PCLKSEL_ACF : ACF 00119 - CLKPWR_PCLKSEL_QEI : QEI 00120 - CLKPWR_PCLKSEL_PCB : PCB 00121 - CLKPWR_PCLKSEL_I2C1 : I2C 1 00122 - CLKPWR_PCLKSEL_SSP0 : SSP 0 00123 - CLKPWR_PCLKSEL_TIMER2 : Timer 2 00124 - CLKPWR_PCLKSEL_TIMER3 : Timer 3 00125 - CLKPWR_PCLKSEL_UART2 : UART 2 00126 - CLKPWR_PCLKSEL_UART3 : UART 3 00127 - CLKPWR_PCLKSEL_I2C2 : I2C 2 00128 - CLKPWR_PCLKSEL_I2S : I2S 00129 - CLKPWR_PCLKSEL_RIT : RIT 00130 - CLKPWR_PCLKSEL_SYSCON : SYSCON 00131 - CLKPWR_PCLKSEL_MC : MC 00132 00133 * @return Value of Selected Peripheral Clock Selection 00134 **********************************************************************/ 00135 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType) 00136 { 00137 uint32_t bitpos, retval; 00138 00139 if (ClkType < 32) 00140 { 00141 bitpos = ClkType; 00142 retval = LPC_SC->PCLKSEL0; 00143 } 00144 else 00145 { 00146 bitpos = ClkType - 32; 00147 retval = LPC_SC->PCLKSEL1; 00148 } 00149 00150 retval = CLKPWR_PCLKSEL_GET(bitpos, retval); 00151 return retval; 00152 } 00153 00154 00155 00156 /*********************************************************************//** 00157 * @brief Get current value of each Peripheral Clock 00158 * @param[in] ClkType Peripheral Clock Selection of each type, 00159 * should be one of the following: 00160 * - CLKPWR_PCLKSEL_WDT : WDT 00161 - CLKPWR_PCLKSEL_TIMER0 : Timer 0 00162 - CLKPWR_PCLKSEL_TIMER1 : Timer 1 00163 - CLKPWR_PCLKSEL_UART0 : UART 0 00164 - CLKPWR_PCLKSEL_UART1 : UART 1 00165 - CLKPWR_PCLKSEL_PWM1 : PWM 1 00166 - CLKPWR_PCLKSEL_I2C0 : I2C 0 00167 - CLKPWR_PCLKSEL_SPI : SPI 00168 - CLKPWR_PCLKSEL_SSP1 : SSP 1 00169 - CLKPWR_PCLKSEL_DAC : DAC 00170 - CLKPWR_PCLKSEL_ADC : ADC 00171 - CLKPWR_PCLKSEL_CAN1 : CAN 1 00172 - CLKPWR_PCLKSEL_CAN2 : CAN 2 00173 - CLKPWR_PCLKSEL_ACF : ACF 00174 - CLKPWR_PCLKSEL_QEI : QEI 00175 - CLKPWR_PCLKSEL_PCB : PCB 00176 - CLKPWR_PCLKSEL_I2C1 : I2C 1 00177 - CLKPWR_PCLKSEL_SSP0 : SSP 0 00178 - CLKPWR_PCLKSEL_TIMER2 : Timer 2 00179 - CLKPWR_PCLKSEL_TIMER3 : Timer 3 00180 - CLKPWR_PCLKSEL_UART2 : UART 2 00181 - CLKPWR_PCLKSEL_UART3 : UART 3 00182 - CLKPWR_PCLKSEL_I2C2 : I2C 2 00183 - CLKPWR_PCLKSEL_I2S : I2S 00184 - CLKPWR_PCLKSEL_RIT : RIT 00185 - CLKPWR_PCLKSEL_SYSCON : SYSCON 00186 - CLKPWR_PCLKSEL_MC : MC 00187 00188 * @return Value of Selected Peripheral Clock 00189 **********************************************************************/ 00190 uint32_t CLKPWR_GetPCLK (uint32_t ClkType) 00191 { 00192 uint32_t retval, div; 00193 00194 retval = SystemCoreClock; 00195 div = CLKPWR_GetPCLKSEL(ClkType); 00196 00197 switch (div) 00198 { 00199 case 0: 00200 div = 4; 00201 break; 00202 00203 case 1: 00204 div = 1; 00205 break; 00206 00207 case 2: 00208 div = 2; 00209 break; 00210 00211 case 3: 00212 div = 8; 00213 break; 00214 } 00215 retval /= div; 00216 00217 return retval; 00218 } 00219 00220 00221 00222 /*********************************************************************//** 00223 * @brief Configure power supply for each peripheral according to NewState 00224 * @param[in] PPType Type of peripheral used to enable power, 00225 * should be one of the following: 00226 * - CLKPWR_PCONP_PCTIM0 : Timer 0 00227 - CLKPWR_PCONP_PCTIM1 : Timer 1 00228 - CLKPWR_PCONP_PCUART0 : UART 0 00229 - CLKPWR_PCONP_PCUART1 : UART 1 00230 - CLKPWR_PCONP_PCPWM1 : PWM 1 00231 - CLKPWR_PCONP_PCI2C0 : I2C 0 00232 - CLKPWR_PCONP_PCSPI : SPI 00233 - CLKPWR_PCONP_PCRTC : RTC 00234 - CLKPWR_PCONP_PCSSP1 : SSP 1 00235 - CLKPWR_PCONP_PCAD : ADC 00236 - CLKPWR_PCONP_PCAN1 : CAN 1 00237 - CLKPWR_PCONP_PCAN2 : CAN 2 00238 - CLKPWR_PCONP_PCGPIO : GPIO 00239 - CLKPWR_PCONP_PCRIT : RIT 00240 - CLKPWR_PCONP_PCMC : MC 00241 - CLKPWR_PCONP_PCQEI : QEI 00242 - CLKPWR_PCONP_PCI2C1 : I2C 1 00243 - CLKPWR_PCONP_PCSSP0 : SSP 0 00244 - CLKPWR_PCONP_PCTIM2 : Timer 2 00245 - CLKPWR_PCONP_PCTIM3 : Timer 3 00246 - CLKPWR_PCONP_PCUART2 : UART 2 00247 - CLKPWR_PCONP_PCUART3 : UART 3 00248 - CLKPWR_PCONP_PCI2C2 : I2C 2 00249 - CLKPWR_PCONP_PCI2S : I2S 00250 - CLKPWR_PCONP_PCGPDMA : GPDMA 00251 - CLKPWR_PCONP_PCENET : Ethernet 00252 - CLKPWR_PCONP_PCUSB : USB 00253 * 00254 * @param[in] NewState New state of Peripheral Power, should be: 00255 * - ENABLE : Enable power for this peripheral 00256 * - DISABLE : Disable power for this peripheral 00257 * 00258 * @return none 00259 **********************************************************************/ 00260 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState) 00261 { 00262 if (NewState == ENABLE) 00263 { 00264 LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK; 00265 } 00266 else if (NewState == DISABLE) 00267 { 00268 LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK; 00269 } 00270 } 00271 00272 00273 /*********************************************************************//** 00274 * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3. 00275 * @param[in] None 00276 * @return None 00277 **********************************************************************/ 00278 void CLKPWR_Sleep(void) 00279 { 00280 LPC_SC->PCON = 0x00; 00281 /* Sleep Mode*/ 00282 __WFI(); 00283 } 00284 00285 00286 /*********************************************************************//** 00287 * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3. 00288 * @param[in] None 00289 * @return None 00290 **********************************************************************/ 00291 void CLKPWR_DeepSleep(void) 00292 { 00293 /* Deep-Sleep Mode, set SLEEPDEEP bit */ 00294 SCB->SCR = 0x4; 00295 LPC_SC->PCON = 0x8; 00296 /* Deep Sleep Mode*/ 00297 __WFI(); 00298 } 00299 00300 00301 /*********************************************************************//** 00302 * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3. 00303 * @param[in] None 00304 * @return None 00305 **********************************************************************/ 00306 void CLKPWR_PowerDown(void) 00307 { 00308 /* Deep-Sleep Mode, set SLEEPDEEP bit */ 00309 SCB->SCR = 0x4; 00310 LPC_SC->PCON = 0x09; 00311 /* Power Down Mode*/ 00312 __WFI(); 00313 } 00314 00315 00316 /*********************************************************************//** 00317 * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3. 00318 * @param[in] None 00319 * @return None 00320 **********************************************************************/ 00321 void CLKPWR_DeepPowerDown(void) 00322 { 00323 /* Deep-Sleep Mode, set SLEEPDEEP bit */ 00324 SCB->SCR = 0x4; 00325 LPC_SC->PCON = 0x03; 00326 /* Deep Power Down Mode*/ 00327 __WFI(); 00328 } 00329 00330 /** 00331 * @} 00332 */ 00333 00334 /** 00335 * @} 00336 */ 00337 00338 /* --------------------------------- End Of File ------------------------------ */
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