Ken Todotani / Mbed 2 deprecated DMA_M2M

Memory to Memory DMA demo from CMSIS example. This demo execute 1000 times of 32 word memory to memory DMA (copy), and also measures number of dummy loop execution during DMA cylcles. Line 56 of "DMA_M2M.c" can change DMA source. where; 1)static : source is SRAM 2)const : source is Flash ROM

Dependencies:   mbed

CMSIS_Lib/lpc17xx_gpdma.h@0:692bf16d1455, 2010-11-14 (annotated)

Committer:
todotani
Date:
Sun Nov 14 03:26:04 2010 +0000
Revision:
0:692bf16d1455
2010/11/14

Who changed what in which revision?

UserRevisionLine numberNew contents of line
todotani 0:692bf16d1455 1 /***********************************************************************//**
todotani 0:692bf16d1455 2 * @file lpc17xx_gpdma.h
todotani 0:692bf16d1455 3 * @brief Contains all macro definitions and function prototypes
todotani 0:692bf16d1455 4 * support for GPDMA firmware library on LPC17xx
todotani 0:692bf16d1455 5 * @version 2.0
todotani 0:692bf16d1455 6 * @date 21. May. 2010
todotani 0:692bf16d1455 7 * @author NXP MCU SW Application Team
todotani 0:692bf16d1455 8 **************************************************************************
todotani 0:692bf16d1455 9 * Software that is described herein is for illustrative purposes only
todotani 0:692bf16d1455 10 * which provides customers with programming information regarding the
todotani 0:692bf16d1455 11 * products. This software is supplied "AS IS" without any warranties.
todotani 0:692bf16d1455 12 * NXP Semiconductors assumes no responsibility or liability for the
todotani 0:692bf16d1455 13 * use of the software, conveys no license or title under any patent,
todotani 0:692bf16d1455 14 * copyright, or mask work right to the product. NXP Semiconductors
todotani 0:692bf16d1455 15 * reserves the right to make changes in the software without
todotani 0:692bf16d1455 16 * notification. NXP Semiconductors also make no representation or
todotani 0:692bf16d1455 17 * warranty that such application will be suitable for the specified
todotani 0:692bf16d1455 18 * use without further testing or modification.
todotani 0:692bf16d1455 19 **************************************************************************/
todotani 0:692bf16d1455 20
todotani 0:692bf16d1455 21 /* Peripheral group ----------------------------------------------------------- */
todotani 0:692bf16d1455 22 /** @defgroup GPDMA GPDMA
todotani 0:692bf16d1455 23 * @ingroup LPC1700CMSIS_FwLib_Drivers
todotani 0:692bf16d1455 24 * @{
todotani 0:692bf16d1455 25 */
todotani 0:692bf16d1455 26
todotani 0:692bf16d1455 27 #ifndef LPC17XX_GPDMA_H_
todotani 0:692bf16d1455 28 #define LPC17XX_GPDMA_H_
todotani 0:692bf16d1455 29
todotani 0:692bf16d1455 30 /* Includes ------------------------------------------------------------------- */
todotani 0:692bf16d1455 31 #include "LPC17xx.h"
todotani 0:692bf16d1455 32 #include "lpc_types.h"
todotani 0:692bf16d1455 33
todotani 0:692bf16d1455 34
todotani 0:692bf16d1455 35 #ifdef __cplusplus
todotani 0:692bf16d1455 36 extern "C"
todotani 0:692bf16d1455 37 {
todotani 0:692bf16d1455 38 #endif
todotani 0:692bf16d1455 39
todotani 0:692bf16d1455 40 /* Public Macros -------------------------------------------------------------- */
todotani 0:692bf16d1455 41 /** @defgroup GPDMA_Public_Macros GPDMA Public Macros
todotani 0:692bf16d1455 42 * @{
todotani 0:692bf16d1455 43 */
todotani 0:692bf16d1455 44
todotani 0:692bf16d1455 45 /** Peripheral declaration */
todotani 0:692bf16d1455 46 #define DMAREQSEL (*(__IO uint32_t *) ( 0x4000C1C4))
todotani 0:692bf16d1455 47
todotani 0:692bf16d1455 48 /** DMA Connection number definitions */
todotani 0:692bf16d1455 49 #define GPDMA_CONN_SSP0_Tx ((0UL)) /**< SSP0 Tx */
todotani 0:692bf16d1455 50 #define GPDMA_CONN_SSP0_Rx ((1UL)) /**< SSP0 Rx */
todotani 0:692bf16d1455 51 #define GPDMA_CONN_SSP1_Tx ((2UL)) /**< SSP1 Tx */
todotani 0:692bf16d1455 52 #define GPDMA_CONN_SSP1_Rx ((3UL)) /**< SSP1 Rx */
todotani 0:692bf16d1455 53 #define GPDMA_CONN_ADC ((4UL)) /**< ADC */
todotani 0:692bf16d1455 54 #define GPDMA_CONN_I2S_Channel_0 ((5UL)) /**< I2S channel 0 */
todotani 0:692bf16d1455 55 #define GPDMA_CONN_I2S_Channel_1 ((6UL)) /**< I2S channel 1 */
todotani 0:692bf16d1455 56 #define GPDMA_CONN_DAC ((7UL)) /**< DAC */
todotani 0:692bf16d1455 57 #define GPDMA_CONN_UART0_Tx ((8UL)) /**< UART0 Tx */
todotani 0:692bf16d1455 58 #define GPDMA_CONN_UART0_Rx ((9UL)) /**< UART0 Rx */
todotani 0:692bf16d1455 59 #define GPDMA_CONN_UART1_Tx ((10UL)) /**< UART1 Tx */
todotani 0:692bf16d1455 60 #define GPDMA_CONN_UART1_Rx ((11UL)) /**< UART1 Rx */
todotani 0:692bf16d1455 61 #define GPDMA_CONN_UART2_Tx ((12UL)) /**< UART2 Tx */
todotani 0:692bf16d1455 62 #define GPDMA_CONN_UART2_Rx ((13UL)) /**< UART2 Rx */
todotani 0:692bf16d1455 63 #define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
todotani 0:692bf16d1455 64 #define GPDMA_CONN_UART3_Rx ((15UL)) /**< UART3 Rx */
todotani 0:692bf16d1455 65 #define GPDMA_CONN_MAT0_0 ((16UL)) /**< MAT0.0 */
todotani 0:692bf16d1455 66 #define GPDMA_CONN_MAT0_1 ((17UL)) /**< MAT0.1 */
todotani 0:692bf16d1455 67 #define GPDMA_CONN_MAT1_0 ((18UL)) /**< MAT1.0 */
todotani 0:692bf16d1455 68 #define GPDMA_CONN_MAT1_1 ((19UL)) /**< MAT1.1 */
todotani 0:692bf16d1455 69 #define GPDMA_CONN_MAT2_0 ((20UL)) /**< MAT2.0 */
todotani 0:692bf16d1455 70 #define GPDMA_CONN_MAT2_1 ((21UL)) /**< MAT2.1 */
todotani 0:692bf16d1455 71 #define GPDMA_CONN_MAT3_0 ((22UL)) /**< MAT3.0 */
todotani 0:692bf16d1455 72 #define GPDMA_CONN_MAT3_1 ((23UL)) /**< MAT3.1 */
todotani 0:692bf16d1455 73
todotani 0:692bf16d1455 74 /** GPDMA Transfer type definitions */
todotani 0:692bf16d1455 75 #define GPDMA_TRANSFERTYPE_M2M ((0UL)) /**< Memory to memory - DMA control */
todotani 0:692bf16d1455 76 #define GPDMA_TRANSFERTYPE_M2P ((1UL)) /**< Memory to peripheral - DMA control */
todotani 0:692bf16d1455 77 #define GPDMA_TRANSFERTYPE_P2M ((2UL)) /**< Peripheral to memory - DMA control */
todotani 0:692bf16d1455 78 #define GPDMA_TRANSFERTYPE_P2P ((3UL)) /**< Source peripheral to destination peripheral - DMA control */
todotani 0:692bf16d1455 79
todotani 0:692bf16d1455 80 /** Burst size in Source and Destination definitions */
todotani 0:692bf16d1455 81 #define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
todotani 0:692bf16d1455 82 #define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
todotani 0:692bf16d1455 83 #define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
todotani 0:692bf16d1455 84 #define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
todotani 0:692bf16d1455 85 #define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
todotani 0:692bf16d1455 86 #define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
todotani 0:692bf16d1455 87 #define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
todotani 0:692bf16d1455 88 #define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
todotani 0:692bf16d1455 89
todotani 0:692bf16d1455 90 /** Width in Source transfer width and Destination transfer width definitions */
todotani 0:692bf16d1455 91 #define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
todotani 0:692bf16d1455 92 #define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
todotani 0:692bf16d1455 93 #define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
todotani 0:692bf16d1455 94
todotani 0:692bf16d1455 95 /** DMA Request Select Mode definitions */
todotani 0:692bf16d1455 96 #define GPDMA_REQSEL_UART ((0UL)) /**< UART TX/RX is selected */
todotani 0:692bf16d1455 97 #define GPDMA_REQSEL_TIMER ((1UL)) /**< Timer match is selected */
todotani 0:692bf16d1455 98
todotani 0:692bf16d1455 99 /**
todotani 0:692bf16d1455 100 * @}
todotani 0:692bf16d1455 101 */
todotani 0:692bf16d1455 102
todotani 0:692bf16d1455 103
todotani 0:692bf16d1455 104 /* Private Macros ------------------------------------------------------------- */
todotani 0:692bf16d1455 105 /** @defgroup GPDMA_Private_Macros GPDMA Private Macros
todotani 0:692bf16d1455 106 * @{
todotani 0:692bf16d1455 107 */
todotani 0:692bf16d1455 108
todotani 0:692bf16d1455 109 /* --------------------- BIT DEFINITIONS -------------------------------------- */
todotani 0:692bf16d1455 110 /*********************************************************************//**
todotani 0:692bf16d1455 111 * Macro defines for DMA Interrupt Status register
todotani 0:692bf16d1455 112 **********************************************************************/
todotani 0:692bf16d1455 113 #define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
todotani 0:692bf16d1455 114 #define GPDMA_DMACIntStat_BITMASK ((0xFF))
todotani 0:692bf16d1455 115
todotani 0:692bf16d1455 116 /*********************************************************************//**
todotani 0:692bf16d1455 117 * Macro defines for DMA Interrupt Terminal Count Request Status register
todotani 0:692bf16d1455 118 **********************************************************************/
todotani 0:692bf16d1455 119 #define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
todotani 0:692bf16d1455 120 #define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
todotani 0:692bf16d1455 121
todotani 0:692bf16d1455 122 /*********************************************************************//**
todotani 0:692bf16d1455 123 * Macro defines for DMA Interrupt Terminal Count Request Clear register
todotani 0:692bf16d1455 124 **********************************************************************/
todotani 0:692bf16d1455 125 #define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
todotani 0:692bf16d1455 126 #define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
todotani 0:692bf16d1455 127
todotani 0:692bf16d1455 128 /*********************************************************************//**
todotani 0:692bf16d1455 129 * Macro defines for DMA Interrupt Error Status register
todotani 0:692bf16d1455 130 **********************************************************************/
todotani 0:692bf16d1455 131 #define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
todotani 0:692bf16d1455 132 #define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
todotani 0:692bf16d1455 133
todotani 0:692bf16d1455 134 /*********************************************************************//**
todotani 0:692bf16d1455 135 * Macro defines for DMA Interrupt Error Clear register
todotani 0:692bf16d1455 136 **********************************************************************/
todotani 0:692bf16d1455 137 #define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
todotani 0:692bf16d1455 138 #define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
todotani 0:692bf16d1455 139
todotani 0:692bf16d1455 140 /*********************************************************************//**
todotani 0:692bf16d1455 141 * Macro defines for DMA Raw Interrupt Terminal Count Status register
todotani 0:692bf16d1455 142 **********************************************************************/
todotani 0:692bf16d1455 143 #define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
todotani 0:692bf16d1455 144 #define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
todotani 0:692bf16d1455 145
todotani 0:692bf16d1455 146 /*********************************************************************//**
todotani 0:692bf16d1455 147 * Macro defines for DMA Raw Error Interrupt Status register
todotani 0:692bf16d1455 148 **********************************************************************/
todotani 0:692bf16d1455 149 #define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
todotani 0:692bf16d1455 150 #define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
todotani 0:692bf16d1455 151
todotani 0:692bf16d1455 152 /*********************************************************************//**
todotani 0:692bf16d1455 153 * Macro defines for DMA Enabled Channel register
todotani 0:692bf16d1455 154 **********************************************************************/
todotani 0:692bf16d1455 155 #define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
todotani 0:692bf16d1455 156 #define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
todotani 0:692bf16d1455 157
todotani 0:692bf16d1455 158 /*********************************************************************//**
todotani 0:692bf16d1455 159 * Macro defines for DMA Software Burst Request register
todotani 0:692bf16d1455 160 **********************************************************************/
todotani 0:692bf16d1455 161 #define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
todotani 0:692bf16d1455 162 #define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
todotani 0:692bf16d1455 163
todotani 0:692bf16d1455 164 /*********************************************************************//**
todotani 0:692bf16d1455 165 * Macro defines for DMA Software Single Request register
todotani 0:692bf16d1455 166 **********************************************************************/
todotani 0:692bf16d1455 167 #define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
todotani 0:692bf16d1455 168 #define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
todotani 0:692bf16d1455 169
todotani 0:692bf16d1455 170 /*********************************************************************//**
todotani 0:692bf16d1455 171 * Macro defines for DMA Software Last Burst Request register
todotani 0:692bf16d1455 172 **********************************************************************/
todotani 0:692bf16d1455 173 #define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
todotani 0:692bf16d1455 174 #define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
todotani 0:692bf16d1455 175
todotani 0:692bf16d1455 176 /*********************************************************************//**
todotani 0:692bf16d1455 177 * Macro defines for DMA Software Last Single Request register
todotani 0:692bf16d1455 178 **********************************************************************/
todotani 0:692bf16d1455 179 #define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
todotani 0:692bf16d1455 180 #define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
todotani 0:692bf16d1455 181
todotani 0:692bf16d1455 182 /*********************************************************************//**
todotani 0:692bf16d1455 183 * Macro defines for DMA Configuration register
todotani 0:692bf16d1455 184 **********************************************************************/
todotani 0:692bf16d1455 185 #define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/
todotani 0:692bf16d1455 186 #define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/
todotani 0:692bf16d1455 187 #define GPDMA_DMACConfig_BITMASK ((0x03))
todotani 0:692bf16d1455 188
todotani 0:692bf16d1455 189 /*********************************************************************//**
todotani 0:692bf16d1455 190 * Macro defines for DMA Synchronization register
todotani 0:692bf16d1455 191 **********************************************************************/
todotani 0:692bf16d1455 192 #define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
todotani 0:692bf16d1455 193 #define GPDMA_DMACSync_BITMASK ((0xFFFF))
todotani 0:692bf16d1455 194
todotani 0:692bf16d1455 195 /*********************************************************************//**
todotani 0:692bf16d1455 196 * Macro defines for DMA Request Select register
todotani 0:692bf16d1455 197 **********************************************************************/
todotani 0:692bf16d1455 198 #define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
todotani 0:692bf16d1455 199 #define GPDMA_DMAReqSel_BITMASK ((0xFF))
todotani 0:692bf16d1455 200
todotani 0:692bf16d1455 201 /*********************************************************************//**
todotani 0:692bf16d1455 202 * Macro defines for DMA Channel Linked List Item registers
todotani 0:692bf16d1455 203 **********************************************************************/
todotani 0:692bf16d1455 204 /** DMA Channel Linked List Item registers bit mask*/
todotani 0:692bf16d1455 205 #define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
todotani 0:692bf16d1455 206
todotani 0:692bf16d1455 207 /*********************************************************************//**
todotani 0:692bf16d1455 208 * Macro defines for DMA channel control registers
todotani 0:692bf16d1455 209 **********************************************************************/
todotani 0:692bf16d1455 210 #define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/
todotani 0:692bf16d1455 211 #define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/
todotani 0:692bf16d1455 212 #define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/
todotani 0:692bf16d1455 213 #define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/
todotani 0:692bf16d1455 214 #define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/
todotani 0:692bf16d1455 215 #define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/
todotani 0:692bf16d1455 216 #define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/
todotani 0:692bf16d1455 217 #define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/
todotani 0:692bf16d1455 218 #define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/
todotani 0:692bf16d1455 219 #define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/
todotani 0:692bf16d1455 220 #define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */
todotani 0:692bf16d1455 221 /** DMA channel control registers bit mask */
todotani 0:692bf16d1455 222 #define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
todotani 0:692bf16d1455 223
todotani 0:692bf16d1455 224 /*********************************************************************//**
todotani 0:692bf16d1455 225 * Macro defines for DMA Channel Configuration registers
todotani 0:692bf16d1455 226 **********************************************************************/
todotani 0:692bf16d1455 227 #define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/
todotani 0:692bf16d1455 228 #define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/
todotani 0:692bf16d1455 229 #define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/
todotani 0:692bf16d1455 230 #define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/
todotani 0:692bf16d1455 231 #define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/
todotani 0:692bf16d1455 232 #define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/
todotani 0:692bf16d1455 233 #define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/
todotani 0:692bf16d1455 234 #define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/
todotani 0:692bf16d1455 235 #define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/
todotani 0:692bf16d1455 236 /** DMA Channel Configuration registers bit mask */
todotani 0:692bf16d1455 237 #define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
todotani 0:692bf16d1455 238
todotani 0:692bf16d1455 239 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
todotani 0:692bf16d1455 240 /* Macros check GPDMA channel */
todotani 0:692bf16d1455 241 #define PARAM_GPDMA_CHANNEL(n) ((n>=0) && (n<=7))
todotani 0:692bf16d1455 242
todotani 0:692bf16d1455 243 /* Macros check GPDMA connection type */
todotani 0:692bf16d1455 244 #define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
todotani 0:692bf16d1455 245 || (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
todotani 0:692bf16d1455 246 || (n==GPDMA_CONN_ADC) || (n==GPDMA_CONN_I2S_Channel_0) \
todotani 0:692bf16d1455 247 || (n==GPDMA_CONN_I2S_Channel_1) || (n==GPDMA_CONN_DAC) \
todotani 0:692bf16d1455 248 || (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
todotani 0:692bf16d1455 249 || (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
todotani 0:692bf16d1455 250 || (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
todotani 0:692bf16d1455 251 || (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
todotani 0:692bf16d1455 252 || (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
todotani 0:692bf16d1455 253 || (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
todotani 0:692bf16d1455 254 || (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
todotani 0:692bf16d1455 255 || (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
todotani 0:692bf16d1455 256
todotani 0:692bf16d1455 257 /* Macros check GPDMA burst size type */
todotani 0:692bf16d1455 258 #define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
todotani 0:692bf16d1455 259 || (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
todotani 0:692bf16d1455 260 || (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
todotani 0:692bf16d1455 261 || (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
todotani 0:692bf16d1455 262
todotani 0:692bf16d1455 263 /* Macros check GPDMA width type */
todotani 0:692bf16d1455 264 #define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
todotani 0:692bf16d1455 265 || (n==GPDMA_WIDTH_WORD))
todotani 0:692bf16d1455 266
todotani 0:692bf16d1455 267 /* Macros check GPDMA status type */
todotani 0:692bf16d1455 268 #define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
todotani 0:692bf16d1455 269 || (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
todotani 0:692bf16d1455 270 || (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
todotani 0:692bf16d1455 271
todotani 0:692bf16d1455 272 /* Macros check GPDMA transfer type */
todotani 0:692bf16d1455 273 #define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)||(n==GPDMA_TRANSFERTYPE_M2P) \
todotani 0:692bf16d1455 274 ||(n==GPDMA_TRANSFERTYPE_P2M)||(n==GPDMA_TRANSFERTYPE_P2P))
todotani 0:692bf16d1455 275
todotani 0:692bf16d1455 276 /* Macros check GPDMA state clear type */
todotani 0:692bf16d1455 277 #define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
todotani 0:692bf16d1455 278
todotani 0:692bf16d1455 279 /* Macros check GPDMA request select type */
todotani 0:692bf16d1455 280 #define PARAM_GPDMA_REQSEL(n) ((n==GPDMA_REQSEL_UART) || (n==GPDMA_REQSEL_TIMER))
todotani 0:692bf16d1455 281 /**
todotani 0:692bf16d1455 282 * @}
todotani 0:692bf16d1455 283 */
todotani 0:692bf16d1455 284
todotani 0:692bf16d1455 285
todotani 0:692bf16d1455 286 /* Public Types --------------------------------------------------------------- */
todotani 0:692bf16d1455 287 /** @defgroup GPDMA_Public_Types GPDMA Public Types
todotani 0:692bf16d1455 288 * @{
todotani 0:692bf16d1455 289 */
todotani 0:692bf16d1455 290
todotani 0:692bf16d1455 291 /**
todotani 0:692bf16d1455 292 * @brief GPDMA Status enumeration
todotani 0:692bf16d1455 293 */
todotani 0:692bf16d1455 294 typedef enum {
todotani 0:692bf16d1455 295 GPDMA_STAT_INT, /**< GPDMA Interrupt Status */
todotani 0:692bf16d1455 296 GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */
todotani 0:692bf16d1455 297 GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */
todotani 0:692bf16d1455 298 GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */
todotani 0:692bf16d1455 299 GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */
todotani 0:692bf16d1455 300 GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */
todotani 0:692bf16d1455 301 } GPDMA_Status_Type;
todotani 0:692bf16d1455 302
todotani 0:692bf16d1455 303 /**
todotani 0:692bf16d1455 304 * @brief GPDMA Interrupt clear status enumeration
todotani 0:692bf16d1455 305 */
todotani 0:692bf16d1455 306 typedef enum{
todotani 0:692bf16d1455 307 GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
todotani 0:692bf16d1455 308 GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
todotani 0:692bf16d1455 309 }GPDMA_StateClear_Type;
todotani 0:692bf16d1455 310
todotani 0:692bf16d1455 311 /**
todotani 0:692bf16d1455 312 * @brief GPDMA Channel configuration structure type definition
todotani 0:692bf16d1455 313 */
todotani 0:692bf16d1455 314 typedef struct {
todotani 0:692bf16d1455 315 uint32_t ChannelNum; /**< DMA channel number, should be in
todotani 0:692bf16d1455 316 range from 0 to 7.
todotani 0:692bf16d1455 317 Note: DMA channel 0 has the highest priority
todotani 0:692bf16d1455 318 and DMA channel 7 the lowest priority.
todotani 0:692bf16d1455 319 */
todotani 0:692bf16d1455 320 uint32_t TransferSize; /**< Length/Size of transfer */
todotani 0:692bf16d1455 321 uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
todotani 0:692bf16d1455 322 uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
todotani 0:692bf16d1455 323 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
todotani 0:692bf16d1455 324 uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
todotani 0:692bf16d1455 325 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
todotani 0:692bf16d1455 326 uint32_t TransferType; /**< Transfer Type, should be one of the following:
todotani 0:692bf16d1455 327 - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
todotani 0:692bf16d1455 328 - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
todotani 0:692bf16d1455 329 - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
todotani 0:692bf16d1455 330 - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
todotani 0:692bf16d1455 331 */
todotani 0:692bf16d1455 332 uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
todotani 0:692bf16d1455 333 GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
todotani 0:692bf16d1455 334 following:
todotani 0:692bf16d1455 335 - GPDMA_CONN_SSP0_Tx: SSP0, Tx
todotani 0:692bf16d1455 336 - GPDMA_CONN_SSP0_Rx: SSP0, Rx
todotani 0:692bf16d1455 337 - GPDMA_CONN_SSP1_Tx: SSP1, Tx
todotani 0:692bf16d1455 338 - GPDMA_CONN_SSP1_Rx: SSP1, Rx
todotani 0:692bf16d1455 339 - GPDMA_CONN_ADC: ADC
todotani 0:692bf16d1455 340 - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
todotani 0:692bf16d1455 341 - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
todotani 0:692bf16d1455 342 - GPDMA_CONN_DAC: DAC
todotani 0:692bf16d1455 343 - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
todotani 0:692bf16d1455 344 - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
todotani 0:692bf16d1455 345 - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
todotani 0:692bf16d1455 346 - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
todotani 0:692bf16d1455 347 - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
todotani 0:692bf16d1455 348 - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
todotani 0:692bf16d1455 349 - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
todotani 0:692bf16d1455 350 - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
todotani 0:692bf16d1455 351 */
todotani 0:692bf16d1455 352 uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
todotani 0:692bf16d1455 353 GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
todotani 0:692bf16d1455 354 following:
todotani 0:692bf16d1455 355 - GPDMA_CONN_SSP0_Tx: SSP0, Tx
todotani 0:692bf16d1455 356 - GPDMA_CONN_SSP0_Rx: SSP0, Rx
todotani 0:692bf16d1455 357 - GPDMA_CONN_SSP1_Tx: SSP1, Tx
todotani 0:692bf16d1455 358 - GPDMA_CONN_SSP1_Rx: SSP1, Rx
todotani 0:692bf16d1455 359 - GPDMA_CONN_ADC: ADC
todotani 0:692bf16d1455 360 - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
todotani 0:692bf16d1455 361 - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
todotani 0:692bf16d1455 362 - GPDMA_CONN_DAC: DAC
todotani 0:692bf16d1455 363 - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
todotani 0:692bf16d1455 364 - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
todotani 0:692bf16d1455 365 - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
todotani 0:692bf16d1455 366 - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
todotani 0:692bf16d1455 367 - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
todotani 0:692bf16d1455 368 - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
todotani 0:692bf16d1455 369 - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
todotani 0:692bf16d1455 370 - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
todotani 0:692bf16d1455 371 */
todotani 0:692bf16d1455 372 uint32_t DMALLI; /**< Linker List Item structure data address
todotani 0:692bf16d1455 373 if there's no Linker List, set as '0'
todotani 0:692bf16d1455 374 */
todotani 0:692bf16d1455 375 } GPDMA_Channel_CFG_Type;
todotani 0:692bf16d1455 376
todotani 0:692bf16d1455 377 /**
todotani 0:692bf16d1455 378 * @brief GPDMA Linker List Item structure type definition
todotani 0:692bf16d1455 379 */
todotani 0:692bf16d1455 380 typedef struct {
todotani 0:692bf16d1455 381 uint32_t SrcAddr; /**< Source Address */
todotani 0:692bf16d1455 382 uint32_t DstAddr; /**< Destination address */
todotani 0:692bf16d1455 383 uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */
todotani 0:692bf16d1455 384 uint32_t Control; /**< GPDMA Control of this LLI */
todotani 0:692bf16d1455 385 } GPDMA_LLI_Type;
todotani 0:692bf16d1455 386
todotani 0:692bf16d1455 387
todotani 0:692bf16d1455 388 /**
todotani 0:692bf16d1455 389 * @}
todotani 0:692bf16d1455 390 */
todotani 0:692bf16d1455 391
todotani 0:692bf16d1455 392 /* Public Functions ----------------------------------------------------------- */
todotani 0:692bf16d1455 393 /** @defgroup GPDMA_Public_Functions GPDMA Public Functions
todotani 0:692bf16d1455 394 * @{
todotani 0:692bf16d1455 395 */
todotani 0:692bf16d1455 396
todotani 0:692bf16d1455 397 void GPDMA_Init(void);
todotani 0:692bf16d1455 398 //Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs);
todotani 0:692bf16d1455 399 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
todotani 0:692bf16d1455 400 IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
todotani 0:692bf16d1455 401 void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
todotani 0:692bf16d1455 402 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
todotani 0:692bf16d1455 403 //void GPDMA_IntHandler(void);
todotani 0:692bf16d1455 404
todotani 0:692bf16d1455 405 /**
todotani 0:692bf16d1455 406 * @}
todotani 0:692bf16d1455 407 */
todotani 0:692bf16d1455 408
todotani 0:692bf16d1455 409
todotani 0:692bf16d1455 410 #ifdef __cplusplus
todotani 0:692bf16d1455 411 }
todotani 0:692bf16d1455 412 #endif
todotani 0:692bf16d1455 413
todotani 0:692bf16d1455 414 #endif /* LPC17XX_GPDMA_H_ */
todotani 0:692bf16d1455 415
todotani 0:692bf16d1455 416 /**
todotani 0:692bf16d1455 417 * @}
todotani 0:692bf16d1455 418 */
todotani 0:692bf16d1455 419
todotani 0:692bf16d1455 420 /* --------------------------------- End Of File ------------------------------ */