hello world
Fork of lmic_MOTE_L152RC by
hal.cpp@11:671d85a0f15b, 2016-02-09 (annotated)
- Committer:
- tmulrooney
- Date:
- Tue Feb 09 00:28:59 2016 +0000
- Revision:
- 11:671d85a0f15b
- Parent:
- TARGET_MOTE_L152RC/hal.cpp@6:dfc048cda33f
hello world
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
dudmuck | 0:f2716e543d97 | 1 | /* HAL for MOTE_L152RC */ |
dudmuck | 0:f2716e543d97 | 2 | |
dudmuck | 0:f2716e543d97 | 3 | #include "mbed.h" |
dudmuck | 0:f2716e543d97 | 4 | #include "oslmic.h" |
dudmuck | 0:f2716e543d97 | 5 | #include "debug.h" |
dudmuck | 0:f2716e543d97 | 6 | |
tmulrooney | 11:671d85a0f15b | 7 | #define RADIO_MOSI PTD6 |
tmulrooney | 11:671d85a0f15b | 8 | #define RADIO_MISO PTD7 |
tmulrooney | 11:671d85a0f15b | 9 | #define RADIO_SCLK PTD5 |
tmulrooney | 11:671d85a0f15b | 10 | #define RADIO_NSS PTD4 |
tmulrooney | 11:671d85a0f15b | 11 | //#define RESET_PIN PTC1 /* *** TODO *** */ |
dudmuck | 0:f2716e543d97 | 12 | |
tmulrooney | 11:671d85a0f15b | 13 | //#define RFSW1 PTC1 //NorAm_Mote RFSwitch_CNTR_1 *** TODO *** |
tmulrooney | 11:671d85a0f15b | 14 | //#define RFSW2 PTC1 //NorAm_Mote RFSwitch_CNTR_2 *** TODO *** |
dudmuck | 0:f2716e543d97 | 15 | |
tmulrooney | 11:671d85a0f15b | 16 | static DigitalOut nss(PTD4); |
dudmuck | 0:f2716e543d97 | 17 | static SPI spi(RADIO_MOSI, RADIO_MISO, RADIO_SCLK); // (mosi, miso, sclk) |
dudmuck | 0:f2716e543d97 | 18 | |
tmulrooney | 11:671d85a0f15b | 19 | //static DigitalInOut rst(RESET_PIN); |
dudmuck | 0:f2716e543d97 | 20 | |
tmulrooney | 11:671d85a0f15b | 21 | //DigitalOut rfsw1(RFSW1); |
tmulrooney | 11:671d85a0f15b | 22 | //DigitalOut rfsw2(RFSW2); |
tmulrooney | 11:671d85a0f15b | 23 | |
tmulrooney | 11:671d85a0f15b | 24 | //DigitalOut hdr_fem_csd(PTC1); /* *** TODO *** */ |
dudmuck | 0:f2716e543d97 | 25 | |
tmulrooney | 11:671d85a0f15b | 26 | static InterruptIn dio0(PTC2); |
tmulrooney | 11:671d85a0f15b | 27 | static InterruptIn dio1(PTC4); /* *** TODO *** */ |
tmulrooney | 11:671d85a0f15b | 28 | static InterruptIn dio2(PTC3); |
dudmuck | 0:f2716e543d97 | 29 | |
tmulrooney | 11:671d85a0f15b | 30 | //extern RTC_HandleTypeDef RtcHandle; |
tmulrooney | 11:671d85a0f15b | 31 | u4_t sleepTimeout; |
dudmuck | 0:f2716e543d97 | 32 | |
dudmuck | 0:f2716e543d97 | 33 | // HAL state |
dudmuck | 0:f2716e543d97 | 34 | static struct { |
dudmuck | 0:f2716e543d97 | 35 | int irqlevel; |
dudmuck | 0:f2716e543d97 | 36 | } HAL; |
dudmuck | 0:f2716e543d97 | 37 | |
dudmuck | 0:f2716e543d97 | 38 | void radio_irq_handler (u1_t dio); |
dudmuck | 0:f2716e543d97 | 39 | |
dudmuck | 0:f2716e543d97 | 40 | static void dio0Irq( void ){ |
dudmuck | 0:f2716e543d97 | 41 | radio_irq_handler( 0 ); |
dudmuck | 0:f2716e543d97 | 42 | } |
dudmuck | 0:f2716e543d97 | 43 | static void dio1Irq( void ){ |
dudmuck | 0:f2716e543d97 | 44 | radio_irq_handler( 1 ); |
dudmuck | 0:f2716e543d97 | 45 | } |
dudmuck | 0:f2716e543d97 | 46 | static void dio2Irq( void ){ |
dudmuck | 0:f2716e543d97 | 47 | radio_irq_handler( 2 ); |
dudmuck | 0:f2716e543d97 | 48 | } |
dudmuck | 0:f2716e543d97 | 49 | |
dudmuck | 0:f2716e543d97 | 50 | void hal_disableIRQs() |
dudmuck | 0:f2716e543d97 | 51 | { |
dudmuck | 0:f2716e543d97 | 52 | __disable_irq(); |
dudmuck | 0:f2716e543d97 | 53 | HAL.irqlevel++; |
dudmuck | 0:f2716e543d97 | 54 | } |
dudmuck | 0:f2716e543d97 | 55 | |
dudmuck | 0:f2716e543d97 | 56 | void hal_enableIRQs() |
dudmuck | 0:f2716e543d97 | 57 | { |
dudmuck | 0:f2716e543d97 | 58 | if (--HAL.irqlevel == 0) { |
dudmuck | 0:f2716e543d97 | 59 | __enable_irq(); |
dudmuck | 0:f2716e543d97 | 60 | } |
dudmuck | 0:f2716e543d97 | 61 | } |
dudmuck | 0:f2716e543d97 | 62 | |
dudmuck | 0:f2716e543d97 | 63 | void hal_failed () |
dudmuck | 0:f2716e543d97 | 64 | { |
dudmuck | 0:f2716e543d97 | 65 | while (1) |
dudmuck | 0:f2716e543d97 | 66 | asm("nop"); |
dudmuck | 0:f2716e543d97 | 67 | } |
dudmuck | 0:f2716e543d97 | 68 | |
tmulrooney | 11:671d85a0f15b | 69 | //static void rtc_wkup_irq(void) |
tmulrooney | 11:671d85a0f15b | 70 | //{ |
tmulrooney | 11:671d85a0f15b | 71 | // HAL_RTCEx_WakeUpTimerIRQHandler(&RtcHandle); |
tmulrooney | 11:671d85a0f15b | 72 | //} |
dudmuck | 0:f2716e543d97 | 73 | |
tmulrooney | 11:671d85a0f15b | 74 | //void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) |
tmulrooney | 11:671d85a0f15b | 75 | //{ |
tmulrooney | 11:671d85a0f15b | 76 | // /* Clear Wake Up Flag */ |
tmulrooney | 11:671d85a0f15b | 77 | // __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); |
tmulrooney | 11:671d85a0f15b | 78 | //} |
dudmuck | 0:f2716e543d97 | 79 | |
dudmuck | 0:f2716e543d97 | 80 | /*void HAL_RCC_CCSCallback() |
dudmuck | 0:f2716e543d97 | 81 | { |
dudmuck | 0:f2716e543d97 | 82 | for (;;) asm("nop"); |
dudmuck | 0:f2716e543d97 | 83 | }*/ |
dudmuck | 0:f2716e543d97 | 84 | |
dudmuck | 0:f2716e543d97 | 85 | |
dudmuck | 0:f2716e543d97 | 86 | volatile uint32_t /*rcc_cr_a, rcc_cr_b,*/ rcc_cr_c; |
dudmuck | 0:f2716e543d97 | 87 | void hal_init (void) |
dudmuck | 0:f2716e543d97 | 88 | { |
tmulrooney | 11:671d85a0f15b | 89 | debugSW("hal_init enter\r\n"); |
dudmuck | 0:f2716e543d97 | 90 | memset(&HAL, 0x00, sizeof(HAL)); |
dudmuck | 0:f2716e543d97 | 91 | hal_disableIRQs(); |
dudmuck | 0:f2716e543d97 | 92 | |
dudmuck | 0:f2716e543d97 | 93 | #if USE_SMTC_RADIO_DRIVER |
dudmuck | 0:f2716e543d97 | 94 | |
dudmuck | 0:f2716e543d97 | 95 | #else |
dudmuck | 0:f2716e543d97 | 96 | // configure input lines |
dudmuck | 0:f2716e543d97 | 97 | dio0.mode(PullDown); |
dudmuck | 0:f2716e543d97 | 98 | dio0.rise(dio0Irq); |
dudmuck | 0:f2716e543d97 | 99 | dio0.enable_irq(); |
dudmuck | 0:f2716e543d97 | 100 | dio1.mode(PullDown); |
dudmuck | 0:f2716e543d97 | 101 | dio1.rise(dio1Irq); |
dudmuck | 0:f2716e543d97 | 102 | dio1.enable_irq(); |
dudmuck | 0:f2716e543d97 | 103 | dio2.mode(PullDown); |
dudmuck | 0:f2716e543d97 | 104 | dio2.rise(dio2Irq); |
dudmuck | 0:f2716e543d97 | 105 | dio2.enable_irq(); |
dudmuck | 0:f2716e543d97 | 106 | // configure reset line |
tmulrooney | 11:671d85a0f15b | 107 | // rst.input(); |
dudmuck | 0:f2716e543d97 | 108 | // configure spi |
tmulrooney | 11:671d85a0f15b | 109 | // spi.frequency(8000000); |
tmulrooney | 11:671d85a0f15b | 110 | spi.frequency(1000000); |
dudmuck | 0:f2716e543d97 | 111 | spi.format(8, 0); |
dudmuck | 0:f2716e543d97 | 112 | nss = 1; |
dudmuck | 0:f2716e543d97 | 113 | //RFSwitch_CNTR_2 = 1; |
dudmuck | 0:f2716e543d97 | 114 | #endif |
dudmuck | 0:f2716e543d97 | 115 | |
dudmuck | 0:f2716e543d97 | 116 | set_time(0); // initialize RTC |
dudmuck | 0:f2716e543d97 | 117 | |
dudmuck | 0:f2716e543d97 | 118 | /* Enable Ultra low power mode */ |
tmulrooney | 11:671d85a0f15b | 119 | // HAL_PWREx_EnableUltraLowPower(); |
dudmuck | 0:f2716e543d97 | 120 | |
dudmuck | 0:f2716e543d97 | 121 | /* Enable the fast wake up from Ultra low power mode */ |
tmulrooney | 11:671d85a0f15b | 122 | // HAL_PWREx_EnableFastWakeUp(); |
dudmuck | 0:f2716e543d97 | 123 | |
tmulrooney | 11:671d85a0f15b | 124 | // __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&RtcHandle, RTC_FLAG_WUTF); |
dudmuck | 0:f2716e543d97 | 125 | |
tmulrooney | 11:671d85a0f15b | 126 | // NVIC_SetVector(RTC_WKUP_IRQn, (uint32_t)rtc_wkup_irq); |
tmulrooney | 11:671d85a0f15b | 127 | // NVIC_EnableIRQ(RTC_WKUP_IRQn); |
dudmuck | 0:f2716e543d97 | 128 | |
tmulrooney | 11:671d85a0f15b | 129 | // hdr_fem_csd = 0; |
dudmuck | 0:f2716e543d97 | 130 | |
dudmuck | 0:f2716e543d97 | 131 | hal_enableIRQs(); |
dudmuck | 0:f2716e543d97 | 132 | |
tmulrooney | 11:671d85a0f15b | 133 | // GPIOA->MODER |= 0x01415500; // unused pins as outputs: PA4, PA5, PA6, PA7, PA8, (PA11,PA12 USB) |
tmulrooney | 11:671d85a0f15b | 134 | // GPIOB->MODER |= 0x00000401; // unused pins as outputs: PB0(HDR_DIO1), PB5 (PB10 pulled hi by LED), PB3-T_SWO |
tmulrooney | 11:671d85a0f15b | 135 | // GPIOC->MODER |= 0x00000041; // unused pins as outputs: PC0(HDR_FEM_CSD), PC3(SPI3_enable) |
tmulrooney | 11:671d85a0f15b | 136 | |
tmulrooney | 11:671d85a0f15b | 137 | debugSW("hal_init exit\r\n"); |
dudmuck | 0:f2716e543d97 | 138 | |
dudmuck | 0:f2716e543d97 | 139 | } |
dudmuck | 0:f2716e543d97 | 140 | |
tmulrooney | 11:671d85a0f15b | 141 | time_t lastSeconds = 0xFFFFF; |
dudmuck | 0:f2716e543d97 | 142 | u4_t hal_ticks () |
dudmuck | 0:f2716e543d97 | 143 | { |
tmulrooney | 11:671d85a0f15b | 144 | time_t seconds = time(NULL); |
tmulrooney | 11:671d85a0f15b | 145 | if(seconds != lastSeconds) |
tmulrooney | 11:671d85a0f15b | 146 | { |
tmulrooney | 11:671d85a0f15b | 147 | lastSeconds = seconds; |
tmulrooney | 11:671d85a0f15b | 148 | debugSW("hal_ticks enter %d\r\n",seconds << 14); |
tmulrooney | 11:671d85a0f15b | 149 | } |
tmulrooney | 11:671d85a0f15b | 150 | // RTC_DateTypeDef dateStruct; |
tmulrooney | 11:671d85a0f15b | 151 | // RTC_TimeTypeDef timeStruct; |
tmulrooney | 11:671d85a0f15b | 152 | // struct tm timeinfo; |
tmulrooney | 11:671d85a0f15b | 153 | // uint16_t sub_seconds; |
dudmuck | 0:f2716e543d97 | 154 | |
tmulrooney | 11:671d85a0f15b | 155 | // RtcHandle.Instance = RTC; |
dudmuck | 0:f2716e543d97 | 156 | |
dudmuck | 0:f2716e543d97 | 157 | // Read actual date and time |
dudmuck | 0:f2716e543d97 | 158 | // Warning: the time must be read first! |
tmulrooney | 11:671d85a0f15b | 159 | // HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN); |
tmulrooney | 11:671d85a0f15b | 160 | // HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN); |
tmulrooney | 11:671d85a0f15b | 161 | // sub_seconds = 16384 - timeStruct.SubSeconds; // RTC_SSR counts down |
dudmuck | 0:f2716e543d97 | 162 | |
dudmuck | 0:f2716e543d97 | 163 | // Setup a tm structure based on the RTC |
tmulrooney | 11:671d85a0f15b | 164 | // timeinfo.tm_wday = dateStruct.WeekDay; |
tmulrooney | 11:671d85a0f15b | 165 | // timeinfo.tm_mon = dateStruct.Month - 1; |
tmulrooney | 11:671d85a0f15b | 166 | // timeinfo.tm_mday = dateStruct.Date; |
tmulrooney | 11:671d85a0f15b | 167 | // timeinfo.tm_year = dateStruct.Year + 100; |
tmulrooney | 11:671d85a0f15b | 168 | // timeinfo.tm_hour = timeStruct.Hours; |
tmulrooney | 11:671d85a0f15b | 169 | // timeinfo.tm_min = timeStruct.Minutes; |
tmulrooney | 11:671d85a0f15b | 170 | // timeinfo.tm_sec = timeStruct.Seconds; |
dudmuck | 0:f2716e543d97 | 171 | |
dudmuck | 0:f2716e543d97 | 172 | // Convert to timestamp |
tmulrooney | 11:671d85a0f15b | 173 | // time_t t = mktime(&timeinfo); |
dudmuck | 0:f2716e543d97 | 174 | |
dudmuck | 0:f2716e543d97 | 175 | // 14: SSR is driven at 16384Hz |
tmulrooney | 11:671d85a0f15b | 176 | // t <<= 14; |
tmulrooney | 11:671d85a0f15b | 177 | // return t | sub_seconds; |
tmulrooney | 11:671d85a0f15b | 178 | return seconds << 14; |
dudmuck | 0:f2716e543d97 | 179 | } |
dudmuck | 0:f2716e543d97 | 180 | |
dudmuck | 0:f2716e543d97 | 181 | void hal_waitUntil (u4_t time) |
dudmuck | 0:f2716e543d97 | 182 | { |
tmulrooney | 11:671d85a0f15b | 183 | debugSW("hal_waitUntil %d\r\n", time); |
dudmuck | 0:f2716e543d97 | 184 | while (hal_ticks() < time) |
dudmuck | 0:f2716e543d97 | 185 | asm("nop"); |
tmulrooney | 11:671d85a0f15b | 186 | debugSW("hal_waitUntil exit\r\n"); |
dudmuck | 0:f2716e543d97 | 187 | } |
dudmuck | 0:f2716e543d97 | 188 | |
dudmuck | 0:f2716e543d97 | 189 | |
dudmuck | 0:f2716e543d97 | 190 | volatile char deep_sleep; |
dudmuck | 0:f2716e543d97 | 191 | /* return 1 if target time is soon, return 0 if timer was programmed */ |
dudmuck | 0:f2716e543d97 | 192 | u1_t hal_checkTimer (u4_t time) |
dudmuck | 0:f2716e543d97 | 193 | { |
dudmuck | 0:f2716e543d97 | 194 | int d = time - hal_ticks(); |
tmulrooney | 11:671d85a0f15b | 195 | if(d == 0) |
tmulrooney | 11:671d85a0f15b | 196 | return 1; |
tmulrooney | 11:671d85a0f15b | 197 | sleepTimeout = time; |
tmulrooney | 11:671d85a0f15b | 198 | debugSW("hal_checkTimer %d %d %d\r\n",time,d,sleepTimeout); |
dudmuck | 0:f2716e543d97 | 199 | |
tmulrooney | 11:671d85a0f15b | 200 | // HAL_RTCEx_DeactivateWakeUpTimer(&RtcHandle); |
tmulrooney | 11:671d85a0f15b | 201 | // __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&RtcHandle, RTC_FLAG_WUTF); |
dudmuck | 0:f2716e543d97 | 202 | |
tmulrooney | 11:671d85a0f15b | 203 | // if (d < 0x10000) { // less than 4s |
tmulrooney | 11:671d85a0f15b | 204 | // deep_sleep = 0; |
tmulrooney | 11:671d85a0f15b | 205 | // if (d < 4) |
tmulrooney | 11:671d85a0f15b | 206 | // return 1; // very soon |
tmulrooney | 11:671d85a0f15b | 207 | // if (d > ms2osticks(100)) { |
tmulrooney | 11:671d85a0f15b | 208 | // d -= 13; // HSE_PLL startup time |
tmulrooney | 11:671d85a0f15b | 209 | // deep_sleep = 1; |
tmulrooney | 11:671d85a0f15b | 210 | // } |
dudmuck | 0:f2716e543d97 | 211 | // 61.035us steps |
tmulrooney | 11:671d85a0f15b | 212 | // HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, d, RTC_WAKEUPCLOCK_RTCCLK_DIV2); |
tmulrooney | 11:671d85a0f15b | 213 | // } else if (d < 0x20000) { // less than 8s |
tmulrooney | 11:671d85a0f15b | 214 | // d -= 6; // HSE_PLL startup time |
tmulrooney | 11:671d85a0f15b | 215 | // deep_sleep = 1; |
dudmuck | 0:f2716e543d97 | 216 | // 122us steps |
tmulrooney | 11:671d85a0f15b | 217 | // HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, d >> 1, RTC_WAKEUPCLOCK_RTCCLK_DIV4); |
tmulrooney | 11:671d85a0f15b | 218 | // } else if (d < 0x40000) { // less than 16s |
tmulrooney | 11:671d85a0f15b | 219 | // deep_sleep = 1; |
dudmuck | 0:f2716e543d97 | 220 | // 244us steps |
tmulrooney | 11:671d85a0f15b | 221 | // HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, d >> 2, RTC_WAKEUPCLOCK_RTCCLK_DIV8); |
tmulrooney | 11:671d85a0f15b | 222 | // } else if (d < 0x80000) { // less than 32s |
tmulrooney | 11:671d85a0f15b | 223 | // deep_sleep = 1; |
dudmuck | 0:f2716e543d97 | 224 | // 488us steps |
tmulrooney | 11:671d85a0f15b | 225 | // HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, d >> 3, RTC_WAKEUPCLOCK_RTCCLK_DIV16); |
tmulrooney | 11:671d85a0f15b | 226 | // } else { |
tmulrooney | 11:671d85a0f15b | 227 | // deep_sleep = 1; |
dudmuck | 0:f2716e543d97 | 228 | // 1s steps to 18hours |
tmulrooney | 11:671d85a0f15b | 229 | // HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, d >> 14, RTC_WAKEUPCLOCK_CK_SPRE_16BITS); |
dudmuck | 0:f2716e543d97 | 230 | /* RTC_WAKEUPCLOCK_CK_SPRE_17BITS: 18h to 36h */ |
dudmuck | 0:f2716e543d97 | 231 | /*for (;;) |
dudmuck | 0:f2716e543d97 | 232 | asm("nop");*/ |
tmulrooney | 11:671d85a0f15b | 233 | // } |
tmulrooney | 11:671d85a0f15b | 234 | debugSW("hal_checkTimer exit\r\n"); |
tmulrooney | 11:671d85a0f15b | 235 | |
dudmuck | 0:f2716e543d97 | 236 | return 0; |
dudmuck | 0:f2716e543d97 | 237 | } |
dudmuck | 0:f2716e543d97 | 238 | |
tmulrooney | 11:671d85a0f15b | 239 | #define SLEEP_DEBUG 1 |
dudmuck | 0:f2716e543d97 | 240 | |
dudmuck | 0:f2716e543d97 | 241 | void hal_sleep () |
dudmuck | 0:f2716e543d97 | 242 | { |
tmulrooney | 11:671d85a0f15b | 243 | debugSW("hal_sleep enter\r\n"); |
tmulrooney | 11:671d85a0f15b | 244 | hal_waitUntil(sleepTimeout); |
tmulrooney | 11:671d85a0f15b | 245 | // #ifdef SLEEP_DEBUG |
tmulrooney | 11:671d85a0f15b | 246 | // u4_t start_tick, end_tick; |
tmulrooney | 11:671d85a0f15b | 247 | // volatile uint32_t time_asleep; |
tmulrooney | 11:671d85a0f15b | 248 | //#endif /* SLEEP_DEBUG */ |
dudmuck | 0:f2716e543d97 | 249 | |
tmulrooney | 11:671d85a0f15b | 250 | //#ifdef USE_DEBUGGER |
tmulrooney | 11:671d85a0f15b | 251 | // HAL_EnableDBGStopMode(); |
tmulrooney | 11:671d85a0f15b | 252 | // if (!DBGMCU->CR & DBGMCU_CR_DBG_STOP) |
tmulrooney | 11:671d85a0f15b | 253 | // for (;;) asm("nop"); |
tmulrooney | 11:671d85a0f15b | 254 | //#endif /* USE_DEBUGGER */ |
dudmuck | 0:f2716e543d97 | 255 | |
dudmuck | 1:04fd63382b03 | 256 | //printf("%x cr:%06x isr:%04x %d\r\n", RtcHandle.Instance->WUTR, RtcHandle.Instance->CR, RtcHandle.Instance->ISR, deep_sleep); |
dudmuck | 1:04fd63382b03 | 257 | //debug_done(); |
dudmuck | 1:04fd63382b03 | 258 | |
tmulrooney | 11:671d85a0f15b | 259 | // if (deep_sleep) |
tmulrooney | 11:671d85a0f15b | 260 | // debug_done(); // wait here if debug still printing |
dudmuck | 0:f2716e543d97 | 261 | |
tmulrooney | 11:671d85a0f15b | 262 | // if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(&RtcHandle, RTC_FLAG_WUTF) == 0) { |
dudmuck | 0:f2716e543d97 | 263 | // set gpio for sleep |
tmulrooney | 11:671d85a0f15b | 264 | //#ifdef SLEEP_DEBUG |
tmulrooney | 11:671d85a0f15b | 265 | // start_tick = hal_ticks(); |
tmulrooney | 11:671d85a0f15b | 266 | //#endif /* SLEEP_DEBUG */ |
dudmuck | 6:dfc048cda33f | 267 | |
dudmuck | 0:f2716e543d97 | 268 | |
tmulrooney | 11:671d85a0f15b | 269 | // if (deep_sleep) { |
tmulrooney | 11:671d85a0f15b | 270 | //#ifndef USE_DEBUGGER |
dudmuck | 0:f2716e543d97 | 271 | /* PA13 to undriven JTMS/SWDIO pin (from AF0 to GPIO), and PA2 */ |
tmulrooney | 11:671d85a0f15b | 272 | // GPIOA->MODER &= 0xf7ffffdf; |
tmulrooney | 11:671d85a0f15b | 273 | // GPIOB->MODER &= 0xffffdfff; // PB6 UART_TX to input |
tmulrooney | 11:671d85a0f15b | 274 | //#endif |
tmulrooney | 11:671d85a0f15b | 275 | // deepsleep(); // blocks until waking |
tmulrooney | 11:671d85a0f15b | 276 | //#ifndef USE_DEBUGGER |
tmulrooney | 11:671d85a0f15b | 277 | // /* PA13 back to JTMS/SWDIO pin (from GPIO to AF0), and PA2 */ |
tmulrooney | 11:671d85a0f15b | 278 | // GPIOA->MODER |= 0x08000020; |
tmulrooney | 11:671d85a0f15b | 279 | // GPIOB->MODER |= 0x00002000; // PB6 input to UART_TX |
tmulrooney | 11:671d85a0f15b | 280 | //#endif |
tmulrooney | 11:671d85a0f15b | 281 | // } else |
tmulrooney | 11:671d85a0f15b | 282 | // sleep(); // blocks until waking |
dudmuck | 0:f2716e543d97 | 283 | |
tmulrooney | 11:671d85a0f15b | 284 | //#ifdef SLEEP_DEBUG |
tmulrooney | 11:671d85a0f15b | 285 | // end_tick = hal_ticks(); |
tmulrooney | 11:671d85a0f15b | 286 | // time_asleep = end_tick - start_tick; |
tmulrooney | 11:671d85a0f15b | 287 | // printf("%u = %u - %u\r\n", time_asleep, end_tick, start_tick); |
tmulrooney | 11:671d85a0f15b | 288 | //#endif /* SLEEP_DEBUG */ |
dudmuck | 0:f2716e543d97 | 289 | // restore gpio from sleep |
tmulrooney | 11:671d85a0f15b | 290 | // } |
tmulrooney | 11:671d85a0f15b | 291 | debugSW("hal_sleep exit\r\n"); |
dudmuck | 0:f2716e543d97 | 292 | } |
dudmuck | 0:f2716e543d97 | 293 | |
dudmuck | 0:f2716e543d97 | 294 | void hal_pin_nss (u1_t val) |
dudmuck | 0:f2716e543d97 | 295 | { |
dudmuck | 0:f2716e543d97 | 296 | nss = val; |
dudmuck | 0:f2716e543d97 | 297 | } |
dudmuck | 0:f2716e543d97 | 298 | |
dudmuck | 0:f2716e543d97 | 299 | u1_t hal_spi (u1_t out) |
dudmuck | 0:f2716e543d97 | 300 | { |
tmulrooney | 11:671d85a0f15b | 301 | // return spi.write(out); |
tmulrooney | 11:671d85a0f15b | 302 | u1_t res = spi.write(out); |
tmulrooney | 11:671d85a0f15b | 303 | debugSW("hal_spi %02X %02X\r\n",out, res); |
tmulrooney | 11:671d85a0f15b | 304 | return(res); |
dudmuck | 0:f2716e543d97 | 305 | } |
dudmuck | 0:f2716e543d97 | 306 | |
dudmuck | 0:f2716e543d97 | 307 | // 0=RX 1=TX |
dudmuck | 0:f2716e543d97 | 308 | /*void hal_pin_rxtx (u1_t val) |
dudmuck | 0:f2716e543d97 | 309 | { |
dudmuck | 0:f2716e543d97 | 310 | rxtx = !val; |
dudmuck | 0:f2716e543d97 | 311 | }*/ |
dudmuck | 0:f2716e543d97 | 312 | #define OPMODE_LORA 0x80 |
dudmuck | 0:f2716e543d97 | 313 | #define OPMODE_MASK 0x07 |
dudmuck | 0:f2716e543d97 | 314 | #define OPMODE_SLEEP 0x00 |
dudmuck | 0:f2716e543d97 | 315 | #define OPMODE_STANDBY 0x01 |
dudmuck | 0:f2716e543d97 | 316 | #define OPMODE_FSTX 0x02 |
dudmuck | 0:f2716e543d97 | 317 | #define OPMODE_TX 0x03 |
dudmuck | 0:f2716e543d97 | 318 | #define OPMODE_FSRX 0x04 |
dudmuck | 0:f2716e543d97 | 319 | #define OPMODE_RX 0x05 |
dudmuck | 0:f2716e543d97 | 320 | #define OPMODE_RX_SINGLE 0x06 |
dudmuck | 0:f2716e543d97 | 321 | #define OPMODE_CAD 0x07 |
dudmuck | 0:f2716e543d97 | 322 | void hal_opmode(u1_t mode, u1_t pa_boost) |
dudmuck | 0:f2716e543d97 | 323 | { |
tmulrooney | 11:671d85a0f15b | 324 | debugSW("hal_opmode %02X %02X\r\n",mode, pa_boost); |
tmulrooney | 11:671d85a0f15b | 325 | // if (mode == OPMODE_TX) { // start of transmission |
tmulrooney | 11:671d85a0f15b | 326 | // if (pa_boost) { |
tmulrooney | 11:671d85a0f15b | 327 | // rfsw2 = 0; |
tmulrooney | 11:671d85a0f15b | 328 | // rfsw1 = 1; |
tmulrooney | 11:671d85a0f15b | 329 | // } else { |
tmulrooney | 11:671d85a0f15b | 330 | // rfsw2 = 1; |
tmulrooney | 11:671d85a0f15b | 331 | // rfsw1 = 0; |
tmulrooney | 11:671d85a0f15b | 332 | // } |
tmulrooney | 11:671d85a0f15b | 333 | // hdr_fem_csd = 0; // debug |
tmulrooney | 11:671d85a0f15b | 334 | // } else if (mode == OPMODE_RX || mode == OPMODE_RX_SINGLE || mode == OPMODE_CAD) { // start of reception |
tmulrooney | 11:671d85a0f15b | 335 | // rfsw2 = 1; |
tmulrooney | 11:671d85a0f15b | 336 | // rfsw1 = 1; |
tmulrooney | 11:671d85a0f15b | 337 | // hdr_fem_csd = 1; // debug |
tmulrooney | 11:671d85a0f15b | 338 | // } else { // RF switch shutdown |
tmulrooney | 11:671d85a0f15b | 339 | // rfsw2 = 0; |
tmulrooney | 11:671d85a0f15b | 340 | // rfsw1 = 0; |
tmulrooney | 11:671d85a0f15b | 341 | // hdr_fem_csd = 0; // debug |
tmulrooney | 11:671d85a0f15b | 342 | // } |
tmulrooney | 11:671d85a0f15b | 343 | debugSW("hal_opmode exit\r\n"); |
dudmuck | 0:f2716e543d97 | 344 | } |
dudmuck | 0:f2716e543d97 | 345 | |
dudmuck | 0:f2716e543d97 | 346 | void hal_pin_rst (u1_t val) |
dudmuck | 0:f2716e543d97 | 347 | { |
tmulrooney | 11:671d85a0f15b | 348 | debugSW("hal_pin_rst %02X\r\n",val); |
tmulrooney | 11:671d85a0f15b | 349 | // if (val == 0 || val == 1) { // drive pin |
tmulrooney | 11:671d85a0f15b | 350 | // rst.output(); |
tmulrooney | 11:671d85a0f15b | 351 | // rst = val; |
tmulrooney | 11:671d85a0f15b | 352 | // } else { // keep pin floating |
tmulrooney | 11:671d85a0f15b | 353 | // rst.input(); |
tmulrooney | 11:671d85a0f15b | 354 | // } |
tmulrooney | 11:671d85a0f15b | 355 | debugSW("hal_pin_rst exit\r\n"); |
dudmuck | 0:f2716e543d97 | 356 | } |