Timothy Mulrooney
/
SX1272Libx
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Dependents: LoRaWAN-lmic-app_tjm
registers/sx1272Regs-Fsk.h@25:856779ac8921, 2016-02-25 (annotated)
- Committer:
- tmulrooney
- Date:
- Thu Feb 25 21:28:39 2016 +0000
- Revision:
- 25:856779ac8921
- Parent:
- 23:952530fa968d
first successful join
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| tmulrooney | 23:952530fa968d | 1 | /* |
| tmulrooney | 23:952530fa968d | 2 | / _____) _ | | |
| tmulrooney | 23:952530fa968d | 3 | ( (____ _____ ____ _| |_ _____ ____| |__ |
| tmulrooney | 23:952530fa968d | 4 | \____ \| ___ | (_ _) ___ |/ ___) _ \ |
| tmulrooney | 23:952530fa968d | 5 | _____) ) ____| | | || |_| ____( (___| | | | |
| tmulrooney | 23:952530fa968d | 6 | (______/|_____)_|_|_| \__)_____)\____)_| |_| |
| tmulrooney | 23:952530fa968d | 7 | (C) 2014 Semtech |
| tmulrooney | 23:952530fa968d | 8 | |
| tmulrooney | 23:952530fa968d | 9 | Description: SX1272 FSK modem registers and bits definitions |
| tmulrooney | 23:952530fa968d | 10 | |
| tmulrooney | 23:952530fa968d | 11 | License: Revised BSD License, see LICENSE.TXT file include in the project |
| tmulrooney | 23:952530fa968d | 12 | |
| tmulrooney | 23:952530fa968d | 13 | Maintainer: Miguel Luis and Gregory Cristian |
| tmulrooney | 23:952530fa968d | 14 | */ |
| tmulrooney | 23:952530fa968d | 15 | #ifndef __SX1272_REGS_FSK_H__ |
| tmulrooney | 23:952530fa968d | 16 | #define __SX1272_REGS_FSK_H__ |
| tmulrooney | 23:952530fa968d | 17 | |
| tmulrooney | 23:952530fa968d | 18 | /*! |
| tmulrooney | 23:952530fa968d | 19 | * ============================================================================ |
| tmulrooney | 23:952530fa968d | 20 | * SX1272 Internal registers Address |
| tmulrooney | 23:952530fa968d | 21 | * ============================================================================ |
| tmulrooney | 23:952530fa968d | 22 | */ |
| tmulrooney | 23:952530fa968d | 23 | #define REG_FIFO 0x00 |
| tmulrooney | 23:952530fa968d | 24 | // Common settings |
| tmulrooney | 23:952530fa968d | 25 | #define REG_OPMODE 0x01 |
| tmulrooney | 23:952530fa968d | 26 | #define REG_BITRATEMSB 0x02 |
| tmulrooney | 23:952530fa968d | 27 | #define REG_BITRATELSB 0x03 |
| tmulrooney | 23:952530fa968d | 28 | #define REG_FDEVMSB 0x04 |
| tmulrooney | 23:952530fa968d | 29 | #define REG_FDEVLSB 0x05 |
| tmulrooney | 23:952530fa968d | 30 | #define REG_FRFMSB 0x06 |
| tmulrooney | 23:952530fa968d | 31 | #define REG_FRFMID 0x07 |
| tmulrooney | 23:952530fa968d | 32 | #define REG_FRFLSB 0x08 |
| tmulrooney | 23:952530fa968d | 33 | // Tx settings |
| tmulrooney | 23:952530fa968d | 34 | #define REG_PACONFIG 0x09 |
| tmulrooney | 23:952530fa968d | 35 | #define REG_PARAMP 0x0A |
| tmulrooney | 23:952530fa968d | 36 | #define REG_OCP 0x0B |
| tmulrooney | 23:952530fa968d | 37 | // Rx settings |
| tmulrooney | 23:952530fa968d | 38 | #define REG_LNA 0x0C |
| tmulrooney | 23:952530fa968d | 39 | #define REG_RXCONFIG 0x0D |
| tmulrooney | 23:952530fa968d | 40 | #define REG_RSSICONFIG 0x0E |
| tmulrooney | 23:952530fa968d | 41 | #define REG_RSSICOLLISION 0x0F |
| tmulrooney | 23:952530fa968d | 42 | #define REG_RSSITHRESH 0x10 |
| tmulrooney | 23:952530fa968d | 43 | #define REG_RSSIVALUE 0x11 |
| tmulrooney | 23:952530fa968d | 44 | #define REG_RXBW 0x12 |
| tmulrooney | 23:952530fa968d | 45 | #define REG_AFCBW 0x13 |
| tmulrooney | 23:952530fa968d | 46 | #define REG_OOKPEAK 0x14 |
| tmulrooney | 23:952530fa968d | 47 | #define REG_OOKFIX 0x15 |
| tmulrooney | 23:952530fa968d | 48 | #define REG_OOKAVG 0x16 |
| tmulrooney | 23:952530fa968d | 49 | #define REG_RES17 0x17 |
| tmulrooney | 23:952530fa968d | 50 | #define REG_RES18 0x18 |
| tmulrooney | 23:952530fa968d | 51 | #define REG_RES19 0x19 |
| tmulrooney | 23:952530fa968d | 52 | #define REG_AFCFEI 0x1A |
| tmulrooney | 23:952530fa968d | 53 | #define REG_AFCMSB 0x1B |
| tmulrooney | 23:952530fa968d | 54 | #define REG_AFCLSB 0x1C |
| tmulrooney | 23:952530fa968d | 55 | #define REG_FEIMSB 0x1D |
| tmulrooney | 23:952530fa968d | 56 | #define REG_FEILSB 0x1E |
| tmulrooney | 23:952530fa968d | 57 | #define REG_PREAMBLEDETECT 0x1F |
| tmulrooney | 23:952530fa968d | 58 | #define REG_RXTIMEOUT1 0x20 |
| tmulrooney | 23:952530fa968d | 59 | #define REG_RXTIMEOUT2 0x21 |
| tmulrooney | 23:952530fa968d | 60 | #define REG_RXTIMEOUT3 0x22 |
| tmulrooney | 23:952530fa968d | 61 | #define REG_RXDELAY 0x23 |
| tmulrooney | 23:952530fa968d | 62 | // Oscillator settings |
| tmulrooney | 23:952530fa968d | 63 | #define REG_OSC 0x24 |
| tmulrooney | 23:952530fa968d | 64 | // Packet handler settings |
| tmulrooney | 23:952530fa968d | 65 | #define REG_PREAMBLEMSB 0x25 |
| tmulrooney | 23:952530fa968d | 66 | #define REG_PREAMBLELSB 0x26 |
| tmulrooney | 23:952530fa968d | 67 | #define REG_SYNCCONFIG 0x27 |
| tmulrooney | 23:952530fa968d | 68 | #define REG_SYNCVALUE1 0x28 |
| tmulrooney | 23:952530fa968d | 69 | #define REG_SYNCVALUE2 0x29 |
| tmulrooney | 23:952530fa968d | 70 | #define REG_SYNCVALUE3 0x2A |
| tmulrooney | 23:952530fa968d | 71 | #define REG_SYNCVALUE4 0x2B |
| tmulrooney | 23:952530fa968d | 72 | #define REG_SYNCVALUE5 0x2C |
| tmulrooney | 23:952530fa968d | 73 | #define REG_SYNCVALUE6 0x2D |
| tmulrooney | 23:952530fa968d | 74 | #define REG_SYNCVALUE7 0x2E |
| tmulrooney | 23:952530fa968d | 75 | #define REG_SYNCVALUE8 0x2F |
| tmulrooney | 23:952530fa968d | 76 | #define REG_PACKETCONFIG1 0x30 |
| tmulrooney | 23:952530fa968d | 77 | #define REG_PACKETCONFIG2 0x31 |
| tmulrooney | 23:952530fa968d | 78 | #define REG_PAYLOADLENGTH 0x32 |
| tmulrooney | 23:952530fa968d | 79 | #define REG_NODEADRS 0x33 |
| tmulrooney | 23:952530fa968d | 80 | #define REG_BROADCASTADRS 0x34 |
| tmulrooney | 23:952530fa968d | 81 | #define REG_FIFOTHRESH 0x35 |
| tmulrooney | 23:952530fa968d | 82 | // SM settings |
| tmulrooney | 23:952530fa968d | 83 | #define REG_SEQCONFIG1 0x36 |
| tmulrooney | 23:952530fa968d | 84 | #define REG_SEQCONFIG2 0x37 |
| tmulrooney | 23:952530fa968d | 85 | #define REG_TIMERRESOL 0x38 |
| tmulrooney | 23:952530fa968d | 86 | #define REG_TIMER1COEF 0x39 |
| tmulrooney | 23:952530fa968d | 87 | #define REG_TIMER2COEF 0x3A |
| tmulrooney | 23:952530fa968d | 88 | // Service settings |
| tmulrooney | 23:952530fa968d | 89 | #define REG_IMAGECAL 0x3B |
| tmulrooney | 23:952530fa968d | 90 | #define REG_TEMP 0x3C |
| tmulrooney | 23:952530fa968d | 91 | #define REG_LOWBAT 0x3D |
| tmulrooney | 23:952530fa968d | 92 | // Status |
| tmulrooney | 23:952530fa968d | 93 | #define REG_IRQFLAGS1 0x3E |
| tmulrooney | 23:952530fa968d | 94 | #define REG_IRQFLAGS2 0x3F |
| tmulrooney | 23:952530fa968d | 95 | // I/O settings |
| tmulrooney | 23:952530fa968d | 96 | #define REG_DIOMAPPING1 0x40 |
| tmulrooney | 23:952530fa968d | 97 | #define REG_DIOMAPPING2 0x41 |
| tmulrooney | 23:952530fa968d | 98 | // Version |
| tmulrooney | 23:952530fa968d | 99 | #define REG_VERSION 0x42 |
| tmulrooney | 23:952530fa968d | 100 | // Additional settings |
| tmulrooney | 23:952530fa968d | 101 | #define REG_PLLHOP 0x44 |
| tmulrooney | 23:952530fa968d | 102 | #define REG_TCXO 0x4B |
| tmulrooney | 23:952530fa968d | 103 | #define REG_PADAC 0x4D |
| tmulrooney | 23:952530fa968d | 104 | #define REG_FORMERTEMP 0x5B |
| tmulrooney | 23:952530fa968d | 105 | #define REG_BITRATEFRAC 0x5D |
| tmulrooney | 23:952530fa968d | 106 | #define REG_AGCREF 0x61 |
| tmulrooney | 23:952530fa968d | 107 | #define REG_AGCTHRESH1 0x62 |
| tmulrooney | 23:952530fa968d | 108 | #define REG_AGCTHRESH2 0x63 |
| tmulrooney | 23:952530fa968d | 109 | #define REG_AGCTHRESH3 0x64 |
| tmulrooney | 23:952530fa968d | 110 | #define REG_PLL 0x70 |
| tmulrooney | 23:952530fa968d | 111 | |
| tmulrooney | 23:952530fa968d | 112 | /*! |
| tmulrooney | 23:952530fa968d | 113 | * ============================================================================ |
| tmulrooney | 23:952530fa968d | 114 | * SX1272 FSK bits control definition |
| tmulrooney | 23:952530fa968d | 115 | * ============================================================================ |
| tmulrooney | 23:952530fa968d | 116 | */ |
| tmulrooney | 23:952530fa968d | 117 | |
| tmulrooney | 23:952530fa968d | 118 | /*! |
| tmulrooney | 23:952530fa968d | 119 | * RegFifo |
| tmulrooney | 23:952530fa968d | 120 | */ |
| tmulrooney | 23:952530fa968d | 121 | |
| tmulrooney | 23:952530fa968d | 122 | /*! |
| tmulrooney | 23:952530fa968d | 123 | * RegOpMode |
| tmulrooney | 23:952530fa968d | 124 | */ |
| tmulrooney | 23:952530fa968d | 125 | #define RF_OPMODE_LONGRANGEMODE_MASK 0x7F |
| tmulrooney | 23:952530fa968d | 126 | #define RF_OPMODE_LONGRANGEMODE_OFF 0x00 |
| tmulrooney | 23:952530fa968d | 127 | #define RF_OPMODE_LONGRANGEMODE_ON 0x80 |
| tmulrooney | 23:952530fa968d | 128 | |
| tmulrooney | 23:952530fa968d | 129 | #define RF_OPMODE_MODULATIONTYPE_MASK 0x9F |
| tmulrooney | 23:952530fa968d | 130 | #define RF_OPMODE_MODULATIONTYPE_FSK 0x00 // Default |
| tmulrooney | 23:952530fa968d | 131 | #define RF_OPMODE_MODULATIONTYPE_OOK 0x20 |
| tmulrooney | 23:952530fa968d | 132 | |
| tmulrooney | 23:952530fa968d | 133 | #define RF_OPMODE_MODULATIONSHAPING_MASK 0xE7 |
| tmulrooney | 23:952530fa968d | 134 | #define RF_OPMODE_MODULATIONSHAPING_00 0x00 // Default |
| tmulrooney | 23:952530fa968d | 135 | #define RF_OPMODE_MODULATIONSHAPING_01 0x08 |
| tmulrooney | 23:952530fa968d | 136 | #define RF_OPMODE_MODULATIONSHAPING_10 0x10 |
| tmulrooney | 23:952530fa968d | 137 | #define RF_OPMODE_MODULATIONSHAPING_11 0x18 |
| tmulrooney | 23:952530fa968d | 138 | |
| tmulrooney | 23:952530fa968d | 139 | #define RF_OPMODE_MASK 0xF8 |
| tmulrooney | 23:952530fa968d | 140 | #define RF_OPMODE_SLEEP 0x00 |
| tmulrooney | 23:952530fa968d | 141 | #define RF_OPMODE_STANDBY 0x01 // Default |
| tmulrooney | 23:952530fa968d | 142 | #define RF_OPMODE_SYNTHESIZER_TX 0x02 |
| tmulrooney | 23:952530fa968d | 143 | #define RF_OPMODE_TRANSMITTER 0x03 |
| tmulrooney | 23:952530fa968d | 144 | #define RF_OPMODE_SYNTHESIZER_RX 0x04 |
| tmulrooney | 23:952530fa968d | 145 | #define RF_OPMODE_RECEIVER 0x05 |
| tmulrooney | 23:952530fa968d | 146 | |
| tmulrooney | 23:952530fa968d | 147 | /*! |
| tmulrooney | 23:952530fa968d | 148 | * RegBitRate (bits/sec) |
| tmulrooney | 23:952530fa968d | 149 | */ |
| tmulrooney | 23:952530fa968d | 150 | #define RF_BITRATEMSB_1200_BPS 0x68 |
| tmulrooney | 23:952530fa968d | 151 | #define RF_BITRATELSB_1200_BPS 0x2B |
| tmulrooney | 23:952530fa968d | 152 | #define RF_BITRATEMSB_2400_BPS 0x34 |
| tmulrooney | 23:952530fa968d | 153 | #define RF_BITRATELSB_2400_BPS 0x15 |
| tmulrooney | 23:952530fa968d | 154 | #define RF_BITRATEMSB_4800_BPS 0x1A // Default |
| tmulrooney | 23:952530fa968d | 155 | #define RF_BITRATELSB_4800_BPS 0x0B // Default |
| tmulrooney | 23:952530fa968d | 156 | #define RF_BITRATEMSB_9600_BPS 0x0D |
| tmulrooney | 23:952530fa968d | 157 | #define RF_BITRATELSB_9600_BPS 0x05 |
| tmulrooney | 23:952530fa968d | 158 | #define RF_BITRATEMSB_15000_BPS 0x08 |
| tmulrooney | 23:952530fa968d | 159 | #define RF_BITRATELSB_15000_BPS 0x55 |
| tmulrooney | 23:952530fa968d | 160 | #define RF_BITRATEMSB_19200_BPS 0x06 |
| tmulrooney | 23:952530fa968d | 161 | #define RF_BITRATELSB_19200_BPS 0x83 |
| tmulrooney | 23:952530fa968d | 162 | #define RF_BITRATEMSB_38400_BPS 0x03 |
| tmulrooney | 23:952530fa968d | 163 | #define RF_BITRATELSB_38400_BPS 0x41 |
| tmulrooney | 23:952530fa968d | 164 | #define RF_BITRATEMSB_76800_BPS 0x01 |
| tmulrooney | 23:952530fa968d | 165 | #define RF_BITRATELSB_76800_BPS 0xA1 |
| tmulrooney | 23:952530fa968d | 166 | #define RF_BITRATEMSB_153600_BPS 0x00 |
| tmulrooney | 23:952530fa968d | 167 | #define RF_BITRATELSB_153600_BPS 0xD0 |
| tmulrooney | 23:952530fa968d | 168 | #define RF_BITRATEMSB_57600_BPS 0x02 |
| tmulrooney | 23:952530fa968d | 169 | #define RF_BITRATELSB_57600_BPS 0x2C |
| tmulrooney | 23:952530fa968d | 170 | #define RF_BITRATEMSB_115200_BPS 0x01 |
| tmulrooney | 23:952530fa968d | 171 | #define RF_BITRATELSB_115200_BPS 0x16 |
| tmulrooney | 23:952530fa968d | 172 | #define RF_BITRATEMSB_12500_BPS 0x0A |
| tmulrooney | 23:952530fa968d | 173 | #define RF_BITRATELSB_12500_BPS 0x00 |
| tmulrooney | 23:952530fa968d | 174 | #define RF_BITRATEMSB_25000_BPS 0x05 |
| tmulrooney | 23:952530fa968d | 175 | #define RF_BITRATELSB_25000_BPS 0x00 |
| tmulrooney | 23:952530fa968d | 176 | #define RF_BITRATEMSB_50000_BPS 0x02 |
| tmulrooney | 23:952530fa968d | 177 | #define RF_BITRATELSB_50000_BPS 0x80 |
| tmulrooney | 23:952530fa968d | 178 | #define RF_BITRATEMSB_100000_BPS 0x01 |
| tmulrooney | 23:952530fa968d | 179 | #define RF_BITRATELSB_100000_BPS 0x40 |
| tmulrooney | 23:952530fa968d | 180 | #define RF_BITRATEMSB_150000_BPS 0x00 |
| tmulrooney | 23:952530fa968d | 181 | #define RF_BITRATELSB_150000_BPS 0xD5 |
| tmulrooney | 23:952530fa968d | 182 | #define RF_BITRATEMSB_200000_BPS 0x00 |
| tmulrooney | 23:952530fa968d | 183 | #define RF_BITRATELSB_200000_BPS 0xA0 |
| tmulrooney | 23:952530fa968d | 184 | #define RF_BITRATEMSB_250000_BPS 0x00 |
| tmulrooney | 23:952530fa968d | 185 | #define RF_BITRATELSB_250000_BPS 0x80 |
| tmulrooney | 23:952530fa968d | 186 | #define RF_BITRATEMSB_32768_BPS 0x03 |
| tmulrooney | 23:952530fa968d | 187 | #define RF_BITRATELSB_32768_BPS 0xD1 |
| tmulrooney | 23:952530fa968d | 188 | |
| tmulrooney | 23:952530fa968d | 189 | /*! |
| tmulrooney | 23:952530fa968d | 190 | * RegFdev (Hz) |
| tmulrooney | 23:952530fa968d | 191 | */ |
| tmulrooney | 23:952530fa968d | 192 | #define RF_FDEVMSB_2000_HZ 0x00 |
| tmulrooney | 23:952530fa968d | 193 | #define RF_FDEVLSB_2000_HZ 0x21 |
| tmulrooney | 23:952530fa968d | 194 | #define RF_FDEVMSB_5000_HZ 0x00 // Default |
| tmulrooney | 23:952530fa968d | 195 | #define RF_FDEVLSB_5000_HZ 0x52 // Default |
| tmulrooney | 23:952530fa968d | 196 | #define RF_FDEVMSB_10000_HZ 0x00 |
| tmulrooney | 23:952530fa968d | 197 | #define RF_FDEVLSB_10000_HZ 0xA4 |
| tmulrooney | 23:952530fa968d | 198 | #define RF_FDEVMSB_15000_HZ 0x00 |
| tmulrooney | 23:952530fa968d | 199 | #define RF_FDEVLSB_15000_HZ 0xF6 |
| tmulrooney | 23:952530fa968d | 200 | #define RF_FDEVMSB_20000_HZ 0x01 |
| tmulrooney | 23:952530fa968d | 201 | #define RF_FDEVLSB_20000_HZ 0x48 |
| tmulrooney | 23:952530fa968d | 202 | #define RF_FDEVMSB_25000_HZ 0x01 |
| tmulrooney | 23:952530fa968d | 203 | #define RF_FDEVLSB_25000_HZ 0x9A |
| tmulrooney | 23:952530fa968d | 204 | #define RF_FDEVMSB_30000_HZ 0x01 |
| tmulrooney | 23:952530fa968d | 205 | #define RF_FDEVLSB_30000_HZ 0xEC |
| tmulrooney | 23:952530fa968d | 206 | #define RF_FDEVMSB_35000_HZ 0x02 |
| tmulrooney | 23:952530fa968d | 207 | #define RF_FDEVLSB_35000_HZ 0x3D |
| tmulrooney | 23:952530fa968d | 208 | #define RF_FDEVMSB_40000_HZ 0x02 |
| tmulrooney | 23:952530fa968d | 209 | #define RF_FDEVLSB_40000_HZ 0x8F |
| tmulrooney | 23:952530fa968d | 210 | #define RF_FDEVMSB_45000_HZ 0x02 |
| tmulrooney | 23:952530fa968d | 211 | #define RF_FDEVLSB_45000_HZ 0xE1 |
| tmulrooney | 23:952530fa968d | 212 | #define RF_FDEVMSB_50000_HZ 0x03 |
| tmulrooney | 23:952530fa968d | 213 | #define RF_FDEVLSB_50000_HZ 0x33 |
| tmulrooney | 23:952530fa968d | 214 | #define RF_FDEVMSB_55000_HZ 0x03 |
| tmulrooney | 23:952530fa968d | 215 | #define RF_FDEVLSB_55000_HZ 0x85 |
| tmulrooney | 23:952530fa968d | 216 | #define RF_FDEVMSB_60000_HZ 0x03 |
| tmulrooney | 23:952530fa968d | 217 | #define RF_FDEVLSB_60000_HZ 0xD7 |
| tmulrooney | 23:952530fa968d | 218 | #define RF_FDEVMSB_65000_HZ 0x04 |
| tmulrooney | 23:952530fa968d | 219 | #define RF_FDEVLSB_65000_HZ 0x29 |
| tmulrooney | 23:952530fa968d | 220 | #define RF_FDEVMSB_70000_HZ 0x04 |
| tmulrooney | 23:952530fa968d | 221 | #define RF_FDEVLSB_70000_HZ 0x7B |
| tmulrooney | 23:952530fa968d | 222 | #define RF_FDEVMSB_75000_HZ 0x04 |
| tmulrooney | 23:952530fa968d | 223 | #define RF_FDEVLSB_75000_HZ 0xCD |
| tmulrooney | 23:952530fa968d | 224 | #define RF_FDEVMSB_80000_HZ 0x05 |
| tmulrooney | 23:952530fa968d | 225 | #define RF_FDEVLSB_80000_HZ 0x1F |
| tmulrooney | 23:952530fa968d | 226 | #define RF_FDEVMSB_85000_HZ 0x05 |
| tmulrooney | 23:952530fa968d | 227 | #define RF_FDEVLSB_85000_HZ 0x71 |
| tmulrooney | 23:952530fa968d | 228 | #define RF_FDEVMSB_90000_HZ 0x05 |
| tmulrooney | 23:952530fa968d | 229 | #define RF_FDEVLSB_90000_HZ 0xC3 |
| tmulrooney | 23:952530fa968d | 230 | #define RF_FDEVMSB_95000_HZ 0x06 |
| tmulrooney | 23:952530fa968d | 231 | #define RF_FDEVLSB_95000_HZ 0x14 |
| tmulrooney | 23:952530fa968d | 232 | #define RF_FDEVMSB_100000_HZ 0x06 |
| tmulrooney | 23:952530fa968d | 233 | #define RF_FDEVLSB_100000_HZ 0x66 |
| tmulrooney | 23:952530fa968d | 234 | #define RF_FDEVMSB_110000_HZ 0x07 |
| tmulrooney | 23:952530fa968d | 235 | #define RF_FDEVLSB_110000_HZ 0x0A |
| tmulrooney | 23:952530fa968d | 236 | #define RF_FDEVMSB_120000_HZ 0x07 |
| tmulrooney | 23:952530fa968d | 237 | #define RF_FDEVLSB_120000_HZ 0xAE |
| tmulrooney | 23:952530fa968d | 238 | #define RF_FDEVMSB_130000_HZ 0x08 |
| tmulrooney | 23:952530fa968d | 239 | #define RF_FDEVLSB_130000_HZ 0x52 |
| tmulrooney | 23:952530fa968d | 240 | #define RF_FDEVMSB_140000_HZ 0x08 |
| tmulrooney | 23:952530fa968d | 241 | #define RF_FDEVLSB_140000_HZ 0xF6 |
| tmulrooney | 23:952530fa968d | 242 | #define RF_FDEVMSB_150000_HZ 0x09 |
| tmulrooney | 23:952530fa968d | 243 | #define RF_FDEVLSB_150000_HZ 0x9A |
| tmulrooney | 23:952530fa968d | 244 | #define RF_FDEVMSB_160000_HZ 0x0A |
| tmulrooney | 23:952530fa968d | 245 | #define RF_FDEVLSB_160000_HZ 0x3D |
| tmulrooney | 23:952530fa968d | 246 | #define RF_FDEVMSB_170000_HZ 0x0A |
| tmulrooney | 23:952530fa968d | 247 | #define RF_FDEVLSB_170000_HZ 0xE1 |
| tmulrooney | 23:952530fa968d | 248 | #define RF_FDEVMSB_180000_HZ 0x0B |
| tmulrooney | 23:952530fa968d | 249 | #define RF_FDEVLSB_180000_HZ 0x85 |
| tmulrooney | 23:952530fa968d | 250 | #define RF_FDEVMSB_190000_HZ 0x0C |
| tmulrooney | 23:952530fa968d | 251 | #define RF_FDEVLSB_190000_HZ 0x29 |
| tmulrooney | 23:952530fa968d | 252 | #define RF_FDEVMSB_200000_HZ 0x0C |
| tmulrooney | 23:952530fa968d | 253 | #define RF_FDEVLSB_200000_HZ 0xCD |
| tmulrooney | 23:952530fa968d | 254 | |
| tmulrooney | 23:952530fa968d | 255 | /*! |
| tmulrooney | 23:952530fa968d | 256 | * RegFrf (MHz) |
| tmulrooney | 23:952530fa968d | 257 | */ |
| tmulrooney | 23:952530fa968d | 258 | #define RF_FRFMSB_863_MHZ 0xD7 |
| tmulrooney | 23:952530fa968d | 259 | #define RF_FRFMID_863_MHZ 0xC0 |
| tmulrooney | 23:952530fa968d | 260 | #define RF_FRFLSB_863_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 261 | #define RF_FRFMSB_864_MHZ 0xD8 |
| tmulrooney | 23:952530fa968d | 262 | #define RF_FRFMID_864_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 263 | #define RF_FRFLSB_864_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 264 | #define RF_FRFMSB_865_MHZ 0xD8 |
| tmulrooney | 23:952530fa968d | 265 | #define RF_FRFMID_865_MHZ 0x40 |
| tmulrooney | 23:952530fa968d | 266 | #define RF_FRFLSB_865_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 267 | #define RF_FRFMSB_866_MHZ 0xD8 |
| tmulrooney | 23:952530fa968d | 268 | #define RF_FRFMID_866_MHZ 0x80 |
| tmulrooney | 23:952530fa968d | 269 | #define RF_FRFLSB_866_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 270 | #define RF_FRFMSB_867_MHZ 0xD8 |
| tmulrooney | 23:952530fa968d | 271 | #define RF_FRFMID_867_MHZ 0xC0 |
| tmulrooney | 23:952530fa968d | 272 | #define RF_FRFLSB_867_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 273 | #define RF_FRFMSB_868_MHZ 0xD9 |
| tmulrooney | 23:952530fa968d | 274 | #define RF_FRFMID_868_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 275 | #define RF_FRFLSB_868_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 276 | #define RF_FRFMSB_869_MHZ 0xD9 |
| tmulrooney | 23:952530fa968d | 277 | #define RF_FRFMID_869_MHZ 0x40 |
| tmulrooney | 23:952530fa968d | 278 | #define RF_FRFLSB_869_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 279 | #define RF_FRFMSB_870_MHZ 0xD9 |
| tmulrooney | 23:952530fa968d | 280 | #define RF_FRFMID_870_MHZ 0x80 |
| tmulrooney | 23:952530fa968d | 281 | #define RF_FRFLSB_870_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 282 | |
| tmulrooney | 23:952530fa968d | 283 | #define RF_FRFMSB_902_MHZ 0xE1 |
| tmulrooney | 23:952530fa968d | 284 | #define RF_FRFMID_902_MHZ 0x80 |
| tmulrooney | 23:952530fa968d | 285 | #define RF_FRFLSB_902_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 286 | #define RF_FRFMSB_903_MHZ 0xE1 |
| tmulrooney | 23:952530fa968d | 287 | #define RF_FRFMID_903_MHZ 0xC0 |
| tmulrooney | 23:952530fa968d | 288 | #define RF_FRFLSB_903_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 289 | #define RF_FRFMSB_904_MHZ 0xE2 |
| tmulrooney | 23:952530fa968d | 290 | #define RF_FRFMID_904_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 291 | #define RF_FRFLSB_904_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 292 | #define RF_FRFMSB_905_MHZ 0xE2 |
| tmulrooney | 23:952530fa968d | 293 | #define RF_FRFMID_905_MHZ 0x40 |
| tmulrooney | 23:952530fa968d | 294 | #define RF_FRFLSB_905_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 295 | #define RF_FRFMSB_906_MHZ 0xE2 |
| tmulrooney | 23:952530fa968d | 296 | #define RF_FRFMID_906_MHZ 0x80 |
| tmulrooney | 23:952530fa968d | 297 | #define RF_FRFLSB_906_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 298 | #define RF_FRFMSB_907_MHZ 0xE2 |
| tmulrooney | 23:952530fa968d | 299 | #define RF_FRFMID_907_MHZ 0xC0 |
| tmulrooney | 23:952530fa968d | 300 | #define RF_FRFLSB_907_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 301 | #define RF_FRFMSB_908_MHZ 0xE3 |
| tmulrooney | 23:952530fa968d | 302 | #define RF_FRFMID_908_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 303 | #define RF_FRFLSB_908_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 304 | #define RF_FRFMSB_909_MHZ 0xE3 |
| tmulrooney | 23:952530fa968d | 305 | #define RF_FRFMID_909_MHZ 0x40 |
| tmulrooney | 23:952530fa968d | 306 | #define RF_FRFLSB_909_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 307 | #define RF_FRFMSB_910_MHZ 0xE3 |
| tmulrooney | 23:952530fa968d | 308 | #define RF_FRFMID_910_MHZ 0x80 |
| tmulrooney | 23:952530fa968d | 309 | #define RF_FRFLSB_910_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 310 | #define RF_FRFMSB_911_MHZ 0xE3 |
| tmulrooney | 23:952530fa968d | 311 | #define RF_FRFMID_911_MHZ 0xC0 |
| tmulrooney | 23:952530fa968d | 312 | #define RF_FRFLSB_911_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 313 | #define RF_FRFMSB_912_MHZ 0xE4 |
| tmulrooney | 23:952530fa968d | 314 | #define RF_FRFMID_912_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 315 | #define RF_FRFLSB_912_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 316 | #define RF_FRFMSB_913_MHZ 0xE4 |
| tmulrooney | 23:952530fa968d | 317 | #define RF_FRFMID_913_MHZ 0x40 |
| tmulrooney | 23:952530fa968d | 318 | #define RF_FRFLSB_913_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 319 | #define RF_FRFMSB_914_MHZ 0xE4 |
| tmulrooney | 23:952530fa968d | 320 | #define RF_FRFMID_914_MHZ 0x80 |
| tmulrooney | 23:952530fa968d | 321 | #define RF_FRFLSB_914_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 322 | #define RF_FRFMSB_915_MHZ 0xE4 // Default |
| tmulrooney | 23:952530fa968d | 323 | #define RF_FRFMID_915_MHZ 0xC0 // Default |
| tmulrooney | 23:952530fa968d | 324 | #define RF_FRFLSB_915_MHZ 0x00 // Default |
| tmulrooney | 23:952530fa968d | 325 | #define RF_FRFMSB_916_MHZ 0xE5 |
| tmulrooney | 23:952530fa968d | 326 | #define RF_FRFMID_916_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 327 | #define RF_FRFLSB_916_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 328 | #define RF_FRFMSB_917_MHZ 0xE5 |
| tmulrooney | 23:952530fa968d | 329 | #define RF_FRFMID_917_MHZ 0x40 |
| tmulrooney | 23:952530fa968d | 330 | #define RF_FRFLSB_917_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 331 | #define RF_FRFMSB_918_MHZ 0xE5 |
| tmulrooney | 23:952530fa968d | 332 | #define RF_FRFMID_918_MHZ 0x80 |
| tmulrooney | 23:952530fa968d | 333 | #define RF_FRFLSB_918_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 334 | #define RF_FRFMSB_919_MHZ 0xE5 |
| tmulrooney | 23:952530fa968d | 335 | #define RF_FRFMID_919_MHZ 0xC0 |
| tmulrooney | 23:952530fa968d | 336 | #define RF_FRFLSB_919_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 337 | #define RF_FRFMSB_920_MHZ 0xE6 |
| tmulrooney | 23:952530fa968d | 338 | #define RF_FRFMID_920_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 339 | #define RF_FRFLSB_920_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 340 | #define RF_FRFMSB_921_MHZ 0xE6 |
| tmulrooney | 23:952530fa968d | 341 | #define RF_FRFMID_921_MHZ 0x40 |
| tmulrooney | 23:952530fa968d | 342 | #define RF_FRFLSB_921_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 343 | #define RF_FRFMSB_922_MHZ 0xE6 |
| tmulrooney | 23:952530fa968d | 344 | #define RF_FRFMID_922_MHZ 0x80 |
| tmulrooney | 23:952530fa968d | 345 | #define RF_FRFLSB_922_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 346 | #define RF_FRFMSB_923_MHZ 0xE6 |
| tmulrooney | 23:952530fa968d | 347 | #define RF_FRFMID_923_MHZ 0xC0 |
| tmulrooney | 23:952530fa968d | 348 | #define RF_FRFLSB_923_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 349 | #define RF_FRFMSB_924_MHZ 0xE7 |
| tmulrooney | 23:952530fa968d | 350 | #define RF_FRFMID_924_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 351 | #define RF_FRFLSB_924_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 352 | #define RF_FRFMSB_925_MHZ 0xE7 |
| tmulrooney | 23:952530fa968d | 353 | #define RF_FRFMID_925_MHZ 0x40 |
| tmulrooney | 23:952530fa968d | 354 | #define RF_FRFLSB_925_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 355 | #define RF_FRFMSB_926_MHZ 0xE7 |
| tmulrooney | 23:952530fa968d | 356 | #define RF_FRFMID_926_MHZ 0x80 |
| tmulrooney | 23:952530fa968d | 357 | #define RF_FRFLSB_926_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 358 | #define RF_FRFMSB_927_MHZ 0xE7 |
| tmulrooney | 23:952530fa968d | 359 | #define RF_FRFMID_927_MHZ 0xC0 |
| tmulrooney | 23:952530fa968d | 360 | #define RF_FRFLSB_927_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 361 | #define RF_FRFMSB_928_MHZ 0xE8 |
| tmulrooney | 23:952530fa968d | 362 | #define RF_FRFMID_928_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 363 | #define RF_FRFLSB_928_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 364 | |
| tmulrooney | 23:952530fa968d | 365 | /*! |
| tmulrooney | 23:952530fa968d | 366 | * RegPaConfig |
| tmulrooney | 23:952530fa968d | 367 | */ |
| tmulrooney | 23:952530fa968d | 368 | #define RF_PACONFIG_PASELECT_MASK 0x7F |
| tmulrooney | 23:952530fa968d | 369 | #define RF_PACONFIG_PASELECT_PABOOST 0x80 |
| tmulrooney | 23:952530fa968d | 370 | #define RF_PACONFIG_PASELECT_RFO 0x00 // Default |
| tmulrooney | 23:952530fa968d | 371 | |
| tmulrooney | 23:952530fa968d | 372 | #define RF_PACONFIG_MAX_POWER_MASK 0x8F |
| tmulrooney | 23:952530fa968d | 373 | |
| tmulrooney | 23:952530fa968d | 374 | #define RF_PACONFIG_OUTPUTPOWER_MASK 0xF0 |
| tmulrooney | 23:952530fa968d | 375 | |
| tmulrooney | 23:952530fa968d | 376 | /*! |
| tmulrooney | 23:952530fa968d | 377 | * RegPaRamp |
| tmulrooney | 23:952530fa968d | 378 | */ |
| tmulrooney | 23:952530fa968d | 379 | #define RF_PARAMP_LOWPNTXPLL_MASK 0xE0 |
| tmulrooney | 23:952530fa968d | 380 | #define RF_PARAMP_LOWPNTXPLL_OFF 0x10 // Default |
| tmulrooney | 23:952530fa968d | 381 | #define RF_PARAMP_LOWPNTXPLL_ON 0x00 |
| tmulrooney | 23:952530fa968d | 382 | |
| tmulrooney | 23:952530fa968d | 383 | #define RF_PARAMP_MASK 0xF0 |
| tmulrooney | 23:952530fa968d | 384 | #define RF_PARAMP_3400_US 0x00 |
| tmulrooney | 23:952530fa968d | 385 | #define RF_PARAMP_2000_US 0x01 |
| tmulrooney | 23:952530fa968d | 386 | #define RF_PARAMP_1000_US 0x02 |
| tmulrooney | 23:952530fa968d | 387 | #define RF_PARAMP_0500_US 0x03 |
| tmulrooney | 23:952530fa968d | 388 | #define RF_PARAMP_0250_US 0x04 |
| tmulrooney | 23:952530fa968d | 389 | #define RF_PARAMP_0125_US 0x05 |
| tmulrooney | 23:952530fa968d | 390 | #define RF_PARAMP_0100_US 0x06 |
| tmulrooney | 23:952530fa968d | 391 | #define RF_PARAMP_0062_US 0x07 |
| tmulrooney | 23:952530fa968d | 392 | #define RF_PARAMP_0050_US 0x08 |
| tmulrooney | 23:952530fa968d | 393 | #define RF_PARAMP_0040_US 0x09 // Default |
| tmulrooney | 23:952530fa968d | 394 | #define RF_PARAMP_0031_US 0x0A |
| tmulrooney | 23:952530fa968d | 395 | #define RF_PARAMP_0025_US 0x0B |
| tmulrooney | 23:952530fa968d | 396 | #define RF_PARAMP_0020_US 0x0C |
| tmulrooney | 23:952530fa968d | 397 | #define RF_PARAMP_0015_US 0x0D |
| tmulrooney | 23:952530fa968d | 398 | #define RF_PARAMP_0012_US 0x0E |
| tmulrooney | 23:952530fa968d | 399 | #define RF_PARAMP_0010_US 0x0F |
| tmulrooney | 23:952530fa968d | 400 | |
| tmulrooney | 23:952530fa968d | 401 | /*! |
| tmulrooney | 23:952530fa968d | 402 | * RegOcp |
| tmulrooney | 23:952530fa968d | 403 | */ |
| tmulrooney | 23:952530fa968d | 404 | #define RF_OCP_MASK 0xDF |
| tmulrooney | 23:952530fa968d | 405 | #define RF_OCP_ON 0x20 // Default |
| tmulrooney | 23:952530fa968d | 406 | #define RF_OCP_OFF 0x00 |
| tmulrooney | 23:952530fa968d | 407 | |
| tmulrooney | 23:952530fa968d | 408 | #define RF_OCP_TRIM_MASK 0xE0 |
| tmulrooney | 23:952530fa968d | 409 | #define RF_OCP_TRIM_045_MA 0x00 |
| tmulrooney | 23:952530fa968d | 410 | #define RF_OCP_TRIM_050_MA 0x01 |
| tmulrooney | 23:952530fa968d | 411 | #define RF_OCP_TRIM_055_MA 0x02 |
| tmulrooney | 23:952530fa968d | 412 | #define RF_OCP_TRIM_060_MA 0x03 |
| tmulrooney | 23:952530fa968d | 413 | #define RF_OCP_TRIM_065_MA 0x04 |
| tmulrooney | 23:952530fa968d | 414 | #define RF_OCP_TRIM_070_MA 0x05 |
| tmulrooney | 23:952530fa968d | 415 | #define RF_OCP_TRIM_075_MA 0x06 |
| tmulrooney | 23:952530fa968d | 416 | #define RF_OCP_TRIM_080_MA 0x07 |
| tmulrooney | 23:952530fa968d | 417 | #define RF_OCP_TRIM_085_MA 0x08 |
| tmulrooney | 23:952530fa968d | 418 | #define RF_OCP_TRIM_090_MA 0x09 |
| tmulrooney | 23:952530fa968d | 419 | #define RF_OCP_TRIM_095_MA 0x0A |
| tmulrooney | 23:952530fa968d | 420 | #define RF_OCP_TRIM_100_MA 0x0B // Default |
| tmulrooney | 23:952530fa968d | 421 | #define RF_OCP_TRIM_105_MA 0x0C |
| tmulrooney | 23:952530fa968d | 422 | #define RF_OCP_TRIM_110_MA 0x0D |
| tmulrooney | 23:952530fa968d | 423 | #define RF_OCP_TRIM_115_MA 0x0E |
| tmulrooney | 23:952530fa968d | 424 | #define RF_OCP_TRIM_120_MA 0x0F |
| tmulrooney | 23:952530fa968d | 425 | #define RF_OCP_TRIM_130_MA 0x10 |
| tmulrooney | 23:952530fa968d | 426 | #define RF_OCP_TRIM_140_MA 0x11 |
| tmulrooney | 23:952530fa968d | 427 | #define RF_OCP_TRIM_150_MA 0x12 |
| tmulrooney | 23:952530fa968d | 428 | #define RF_OCP_TRIM_160_MA 0x13 |
| tmulrooney | 23:952530fa968d | 429 | #define RF_OCP_TRIM_170_MA 0x14 |
| tmulrooney | 23:952530fa968d | 430 | #define RF_OCP_TRIM_180_MA 0x15 |
| tmulrooney | 23:952530fa968d | 431 | #define RF_OCP_TRIM_190_MA 0x16 |
| tmulrooney | 23:952530fa968d | 432 | #define RF_OCP_TRIM_200_MA 0x17 |
| tmulrooney | 23:952530fa968d | 433 | #define RF_OCP_TRIM_210_MA 0x18 |
| tmulrooney | 23:952530fa968d | 434 | #define RF_OCP_TRIM_220_MA 0x19 |
| tmulrooney | 23:952530fa968d | 435 | #define RF_OCP_TRIM_230_MA 0x1A |
| tmulrooney | 23:952530fa968d | 436 | #define RF_OCP_TRIM_240_MA 0x1B |
| tmulrooney | 23:952530fa968d | 437 | |
| tmulrooney | 23:952530fa968d | 438 | /*! |
| tmulrooney | 23:952530fa968d | 439 | * RegLna |
| tmulrooney | 23:952530fa968d | 440 | */ |
| tmulrooney | 23:952530fa968d | 441 | #define RF_LNA_GAIN_MASK 0x1F |
| tmulrooney | 23:952530fa968d | 442 | #define RF_LNA_GAIN_G1 0x20 // Default |
| tmulrooney | 23:952530fa968d | 443 | #define RF_LNA_GAIN_G2 0x40 |
| tmulrooney | 23:952530fa968d | 444 | #define RF_LNA_GAIN_G3 0x60 |
| tmulrooney | 23:952530fa968d | 445 | #define RF_LNA_GAIN_G4 0x80 |
| tmulrooney | 23:952530fa968d | 446 | #define RF_LNA_GAIN_G5 0xA0 |
| tmulrooney | 23:952530fa968d | 447 | #define RF_LNA_GAIN_G6 0xC0 |
| tmulrooney | 23:952530fa968d | 448 | |
| tmulrooney | 23:952530fa968d | 449 | #define RF_LNA_BOOST_MASK 0xFC |
| tmulrooney | 23:952530fa968d | 450 | #define RF_LNA_BOOST_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 451 | #define RF_LNA_BOOST_ON 0x03 |
| tmulrooney | 23:952530fa968d | 452 | |
| tmulrooney | 23:952530fa968d | 453 | /*! |
| tmulrooney | 23:952530fa968d | 454 | * RegRxConfig |
| tmulrooney | 23:952530fa968d | 455 | */ |
| tmulrooney | 23:952530fa968d | 456 | #define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK 0x7F |
| tmulrooney | 23:952530fa968d | 457 | #define RF_RXCONFIG_RESTARTRXONCOLLISION_ON 0x80 |
| tmulrooney | 23:952530fa968d | 458 | #define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 459 | |
| tmulrooney | 23:952530fa968d | 460 | #define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK 0x40 // Write only |
| tmulrooney | 23:952530fa968d | 461 | |
| tmulrooney | 23:952530fa968d | 462 | #define RF_RXCONFIG_RESTARTRXWITHPLLLOCK 0x20 // Write only |
| tmulrooney | 23:952530fa968d | 463 | |
| tmulrooney | 23:952530fa968d | 464 | #define RF_RXCONFIG_AFCAUTO_MASK 0xEF |
| tmulrooney | 23:952530fa968d | 465 | #define RF_RXCONFIG_AFCAUTO_ON 0x10 |
| tmulrooney | 23:952530fa968d | 466 | #define RF_RXCONFIG_AFCAUTO_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 467 | |
| tmulrooney | 23:952530fa968d | 468 | #define RF_RXCONFIG_AGCAUTO_MASK 0xF7 |
| tmulrooney | 23:952530fa968d | 469 | #define RF_RXCONFIG_AGCAUTO_ON 0x08 // Default |
| tmulrooney | 23:952530fa968d | 470 | #define RF_RXCONFIG_AGCAUTO_OFF 0x00 |
| tmulrooney | 23:952530fa968d | 471 | |
| tmulrooney | 23:952530fa968d | 472 | #define RF_RXCONFIG_RXTRIGER_MASK 0xF8 |
| tmulrooney | 23:952530fa968d | 473 | #define RF_RXCONFIG_RXTRIGER_OFF 0x00 |
| tmulrooney | 23:952530fa968d | 474 | #define RF_RXCONFIG_RXTRIGER_RSSI 0x01 |
| tmulrooney | 23:952530fa968d | 475 | #define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT 0x06 // Default |
| tmulrooney | 23:952530fa968d | 476 | #define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT 0x07 |
| tmulrooney | 23:952530fa968d | 477 | |
| tmulrooney | 23:952530fa968d | 478 | /*! |
| tmulrooney | 23:952530fa968d | 479 | * RegRssiConfig |
| tmulrooney | 23:952530fa968d | 480 | */ |
| tmulrooney | 23:952530fa968d | 481 | #define RF_RSSICONFIG_OFFSET_MASK 0x07 |
| tmulrooney | 23:952530fa968d | 482 | #define RF_RSSICONFIG_OFFSET_P_00_DB 0x00 // Default |
| tmulrooney | 23:952530fa968d | 483 | #define RF_RSSICONFIG_OFFSET_P_01_DB 0x08 |
| tmulrooney | 23:952530fa968d | 484 | #define RF_RSSICONFIG_OFFSET_P_02_DB 0x10 |
| tmulrooney | 23:952530fa968d | 485 | #define RF_RSSICONFIG_OFFSET_P_03_DB 0x18 |
| tmulrooney | 23:952530fa968d | 486 | #define RF_RSSICONFIG_OFFSET_P_04_DB 0x20 |
| tmulrooney | 23:952530fa968d | 487 | #define RF_RSSICONFIG_OFFSET_P_05_DB 0x28 |
| tmulrooney | 23:952530fa968d | 488 | #define RF_RSSICONFIG_OFFSET_P_06_DB 0x30 |
| tmulrooney | 23:952530fa968d | 489 | #define RF_RSSICONFIG_OFFSET_P_07_DB 0x38 |
| tmulrooney | 23:952530fa968d | 490 | #define RF_RSSICONFIG_OFFSET_P_08_DB 0x40 |
| tmulrooney | 23:952530fa968d | 491 | #define RF_RSSICONFIG_OFFSET_P_09_DB 0x48 |
| tmulrooney | 23:952530fa968d | 492 | #define RF_RSSICONFIG_OFFSET_P_10_DB 0x50 |
| tmulrooney | 23:952530fa968d | 493 | #define RF_RSSICONFIG_OFFSET_P_11_DB 0x58 |
| tmulrooney | 23:952530fa968d | 494 | #define RF_RSSICONFIG_OFFSET_P_12_DB 0x60 |
| tmulrooney | 23:952530fa968d | 495 | #define RF_RSSICONFIG_OFFSET_P_13_DB 0x68 |
| tmulrooney | 23:952530fa968d | 496 | #define RF_RSSICONFIG_OFFSET_P_14_DB 0x70 |
| tmulrooney | 23:952530fa968d | 497 | #define RF_RSSICONFIG_OFFSET_P_15_DB 0x78 |
| tmulrooney | 23:952530fa968d | 498 | #define RF_RSSICONFIG_OFFSET_M_16_DB 0x80 |
| tmulrooney | 23:952530fa968d | 499 | #define RF_RSSICONFIG_OFFSET_M_15_DB 0x88 |
| tmulrooney | 23:952530fa968d | 500 | #define RF_RSSICONFIG_OFFSET_M_14_DB 0x90 |
| tmulrooney | 23:952530fa968d | 501 | #define RF_RSSICONFIG_OFFSET_M_13_DB 0x98 |
| tmulrooney | 23:952530fa968d | 502 | #define RF_RSSICONFIG_OFFSET_M_12_DB 0xA0 |
| tmulrooney | 23:952530fa968d | 503 | #define RF_RSSICONFIG_OFFSET_M_11_DB 0xA8 |
| tmulrooney | 23:952530fa968d | 504 | #define RF_RSSICONFIG_OFFSET_M_10_DB 0xB0 |
| tmulrooney | 23:952530fa968d | 505 | #define RF_RSSICONFIG_OFFSET_M_09_DB 0xB8 |
| tmulrooney | 23:952530fa968d | 506 | #define RF_RSSICONFIG_OFFSET_M_08_DB 0xC0 |
| tmulrooney | 23:952530fa968d | 507 | #define RF_RSSICONFIG_OFFSET_M_07_DB 0xC8 |
| tmulrooney | 23:952530fa968d | 508 | #define RF_RSSICONFIG_OFFSET_M_06_DB 0xD0 |
| tmulrooney | 23:952530fa968d | 509 | #define RF_RSSICONFIG_OFFSET_M_05_DB 0xD8 |
| tmulrooney | 23:952530fa968d | 510 | #define RF_RSSICONFIG_OFFSET_M_04_DB 0xE0 |
| tmulrooney | 23:952530fa968d | 511 | #define RF_RSSICONFIG_OFFSET_M_03_DB 0xE8 |
| tmulrooney | 23:952530fa968d | 512 | #define RF_RSSICONFIG_OFFSET_M_02_DB 0xF0 |
| tmulrooney | 23:952530fa968d | 513 | #define RF_RSSICONFIG_OFFSET_M_01_DB 0xF8 |
| tmulrooney | 23:952530fa968d | 514 | |
| tmulrooney | 23:952530fa968d | 515 | #define RF_RSSICONFIG_SMOOTHING_MASK 0xF8 |
| tmulrooney | 23:952530fa968d | 516 | #define RF_RSSICONFIG_SMOOTHING_2 0x00 |
| tmulrooney | 23:952530fa968d | 517 | #define RF_RSSICONFIG_SMOOTHING_4 0x01 |
| tmulrooney | 23:952530fa968d | 518 | #define RF_RSSICONFIG_SMOOTHING_8 0x02 // Default |
| tmulrooney | 23:952530fa968d | 519 | #define RF_RSSICONFIG_SMOOTHING_16 0x03 |
| tmulrooney | 23:952530fa968d | 520 | #define RF_RSSICONFIG_SMOOTHING_32 0x04 |
| tmulrooney | 23:952530fa968d | 521 | #define RF_RSSICONFIG_SMOOTHING_64 0x05 |
| tmulrooney | 23:952530fa968d | 522 | #define RF_RSSICONFIG_SMOOTHING_128 0x06 |
| tmulrooney | 23:952530fa968d | 523 | #define RF_RSSICONFIG_SMOOTHING_256 0x07 |
| tmulrooney | 23:952530fa968d | 524 | |
| tmulrooney | 23:952530fa968d | 525 | /*! |
| tmulrooney | 23:952530fa968d | 526 | * RegRssiCollision |
| tmulrooney | 23:952530fa968d | 527 | */ |
| tmulrooney | 23:952530fa968d | 528 | #define RF_RSSICOLISION_THRESHOLD 0x0A // Default |
| tmulrooney | 23:952530fa968d | 529 | |
| tmulrooney | 23:952530fa968d | 530 | /*! |
| tmulrooney | 23:952530fa968d | 531 | * RegRssiThresh |
| tmulrooney | 23:952530fa968d | 532 | */ |
| tmulrooney | 23:952530fa968d | 533 | #define RF_RSSITHRESH_THRESHOLD 0xFF // Default |
| tmulrooney | 23:952530fa968d | 534 | |
| tmulrooney | 23:952530fa968d | 535 | /*! |
| tmulrooney | 23:952530fa968d | 536 | * RegRssiValue (Read Only) |
| tmulrooney | 23:952530fa968d | 537 | */ |
| tmulrooney | 23:952530fa968d | 538 | |
| tmulrooney | 23:952530fa968d | 539 | /*! |
| tmulrooney | 23:952530fa968d | 540 | * RegRxBw |
| tmulrooney | 23:952530fa968d | 541 | */ |
| tmulrooney | 23:952530fa968d | 542 | #define RF_RXBW_MANT_MASK 0xE7 |
| tmulrooney | 23:952530fa968d | 543 | #define RF_RXBW_MANT_16 0x00 |
| tmulrooney | 23:952530fa968d | 544 | #define RF_RXBW_MANT_20 0x08 |
| tmulrooney | 23:952530fa968d | 545 | #define RF_RXBW_MANT_24 0x10 // Default |
| tmulrooney | 23:952530fa968d | 546 | |
| tmulrooney | 23:952530fa968d | 547 | #define RF_RXBW_EXP_MASK 0xF8 |
| tmulrooney | 23:952530fa968d | 548 | #define RF_RXBW_EXP_0 0x00 |
| tmulrooney | 23:952530fa968d | 549 | #define RF_RXBW_EXP_1 0x01 |
| tmulrooney | 23:952530fa968d | 550 | #define RF_RXBW_EXP_2 0x02 |
| tmulrooney | 23:952530fa968d | 551 | #define RF_RXBW_EXP_3 0x03 |
| tmulrooney | 23:952530fa968d | 552 | #define RF_RXBW_EXP_4 0x04 |
| tmulrooney | 23:952530fa968d | 553 | #define RF_RXBW_EXP_5 0x05 // Default |
| tmulrooney | 23:952530fa968d | 554 | #define RF_RXBW_EXP_6 0x06 |
| tmulrooney | 23:952530fa968d | 555 | #define RF_RXBW_EXP_7 0x07 |
| tmulrooney | 23:952530fa968d | 556 | |
| tmulrooney | 23:952530fa968d | 557 | /*! |
| tmulrooney | 23:952530fa968d | 558 | * RegAfcBw |
| tmulrooney | 23:952530fa968d | 559 | */ |
| tmulrooney | 23:952530fa968d | 560 | #define RF_AFCBW_MANTAFC_MASK 0xE7 |
| tmulrooney | 23:952530fa968d | 561 | #define RF_AFCBW_MANTAFC_16 0x00 |
| tmulrooney | 23:952530fa968d | 562 | #define RF_AFCBW_MANTAFC_20 0x08 // Default |
| tmulrooney | 23:952530fa968d | 563 | #define RF_AFCBW_MANTAFC_24 0x10 |
| tmulrooney | 23:952530fa968d | 564 | |
| tmulrooney | 23:952530fa968d | 565 | #define RF_AFCBW_EXPAFC_MASK 0xF8 |
| tmulrooney | 23:952530fa968d | 566 | #define RF_AFCBW_EXPAFC_0 0x00 |
| tmulrooney | 23:952530fa968d | 567 | #define RF_AFCBW_EXPAFC_1 0x01 |
| tmulrooney | 23:952530fa968d | 568 | #define RF_AFCBW_EXPAFC_2 0x02 |
| tmulrooney | 23:952530fa968d | 569 | #define RF_AFCBW_EXPAFC_3 0x03 // Default |
| tmulrooney | 23:952530fa968d | 570 | #define RF_AFCBW_EXPAFC_4 0x04 |
| tmulrooney | 23:952530fa968d | 571 | #define RF_AFCBW_EXPAFC_5 0x05 |
| tmulrooney | 23:952530fa968d | 572 | #define RF_AFCBW_EXPAFC_6 0x06 |
| tmulrooney | 23:952530fa968d | 573 | #define RF_AFCBW_EXPAFC_7 0x07 |
| tmulrooney | 23:952530fa968d | 574 | |
| tmulrooney | 23:952530fa968d | 575 | /*! |
| tmulrooney | 23:952530fa968d | 576 | * RegOokPeak |
| tmulrooney | 23:952530fa968d | 577 | */ |
| tmulrooney | 23:952530fa968d | 578 | #define RF_OOKPEAK_BITSYNC_MASK 0xDF // Default |
| tmulrooney | 23:952530fa968d | 579 | #define RF_OOKPEAK_BITSYNC_ON 0x20 // Default |
| tmulrooney | 23:952530fa968d | 580 | #define RF_OOKPEAK_BITSYNC_OFF 0x00 |
| tmulrooney | 23:952530fa968d | 581 | |
| tmulrooney | 23:952530fa968d | 582 | #define RF_OOKPEAK_OOKTHRESHTYPE_MASK 0xE7 |
| tmulrooney | 23:952530fa968d | 583 | #define RF_OOKPEAK_OOKTHRESHTYPE_FIXED 0x00 |
| tmulrooney | 23:952530fa968d | 584 | #define RF_OOKPEAK_OOKTHRESHTYPE_PEAK 0x08 // Default |
| tmulrooney | 23:952530fa968d | 585 | #define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE 0x10 |
| tmulrooney | 23:952530fa968d | 586 | |
| tmulrooney | 23:952530fa968d | 587 | #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK 0xF8 |
| tmulrooney | 23:952530fa968d | 588 | #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB 0x00 // Default |
| tmulrooney | 23:952530fa968d | 589 | #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB 0x01 |
| tmulrooney | 23:952530fa968d | 590 | #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB 0x02 |
| tmulrooney | 23:952530fa968d | 591 | #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB 0x03 |
| tmulrooney | 23:952530fa968d | 592 | #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB 0x04 |
| tmulrooney | 23:952530fa968d | 593 | #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB 0x05 |
| tmulrooney | 23:952530fa968d | 594 | #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB 0x06 |
| tmulrooney | 23:952530fa968d | 595 | #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB 0x07 |
| tmulrooney | 23:952530fa968d | 596 | |
| tmulrooney | 23:952530fa968d | 597 | /*! |
| tmulrooney | 23:952530fa968d | 598 | * RegOokFix |
| tmulrooney | 23:952530fa968d | 599 | */ |
| tmulrooney | 23:952530fa968d | 600 | #define RF_OOKFIX_OOKFIXEDTHRESHOLD 0x0C // Default |
| tmulrooney | 23:952530fa968d | 601 | |
| tmulrooney | 23:952530fa968d | 602 | /*! |
| tmulrooney | 23:952530fa968d | 603 | * RegOokAvg |
| tmulrooney | 23:952530fa968d | 604 | */ |
| tmulrooney | 23:952530fa968d | 605 | #define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK 0x1F |
| tmulrooney | 23:952530fa968d | 606 | #define RF_OOKAVG_OOKPEAKTHRESHDEC_000 0x00 // Default |
| tmulrooney | 23:952530fa968d | 607 | #define RF_OOKAVG_OOKPEAKTHRESHDEC_001 0x20 |
| tmulrooney | 23:952530fa968d | 608 | #define RF_OOKAVG_OOKPEAKTHRESHDEC_010 0x40 |
| tmulrooney | 23:952530fa968d | 609 | #define RF_OOKAVG_OOKPEAKTHRESHDEC_011 0x60 |
| tmulrooney | 23:952530fa968d | 610 | #define RF_OOKAVG_OOKPEAKTHRESHDEC_100 0x80 |
| tmulrooney | 23:952530fa968d | 611 | #define RF_OOKAVG_OOKPEAKTHRESHDEC_101 0xA0 |
| tmulrooney | 23:952530fa968d | 612 | #define RF_OOKAVG_OOKPEAKTHRESHDEC_110 0xC0 |
| tmulrooney | 23:952530fa968d | 613 | #define RF_OOKAVG_OOKPEAKTHRESHDEC_111 0xE0 |
| tmulrooney | 23:952530fa968d | 614 | |
| tmulrooney | 23:952530fa968d | 615 | #define RF_OOKAVG_AVERAGEOFFSET_MASK 0xF3 |
| tmulrooney | 23:952530fa968d | 616 | #define RF_OOKAVG_AVERAGEOFFSET_0_DB 0x00 // Default |
| tmulrooney | 23:952530fa968d | 617 | #define RF_OOKAVG_AVERAGEOFFSET_2_DB 0x04 |
| tmulrooney | 23:952530fa968d | 618 | #define RF_OOKAVG_AVERAGEOFFSET_4_DB 0x08 |
| tmulrooney | 23:952530fa968d | 619 | #define RF_OOKAVG_AVERAGEOFFSET_6_DB 0x0C |
| tmulrooney | 23:952530fa968d | 620 | |
| tmulrooney | 23:952530fa968d | 621 | #define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK 0xFC |
| tmulrooney | 23:952530fa968d | 622 | #define RF_OOKAVG_OOKAVERAGETHRESHFILT_00 0x00 |
| tmulrooney | 23:952530fa968d | 623 | #define RF_OOKAVG_OOKAVERAGETHRESHFILT_01 0x01 |
| tmulrooney | 23:952530fa968d | 624 | #define RF_OOKAVG_OOKAVERAGETHRESHFILT_10 0x02 // Default |
| tmulrooney | 23:952530fa968d | 625 | #define RF_OOKAVG_OOKAVERAGETHRESHFILT_11 0x03 |
| tmulrooney | 23:952530fa968d | 626 | |
| tmulrooney | 23:952530fa968d | 627 | /*! |
| tmulrooney | 23:952530fa968d | 628 | * RegAfcFei |
| tmulrooney | 23:952530fa968d | 629 | */ |
| tmulrooney | 23:952530fa968d | 630 | #define RF_AFCFEI_AGCSTART 0x10 |
| tmulrooney | 23:952530fa968d | 631 | |
| tmulrooney | 23:952530fa968d | 632 | #define RF_AFCFEI_AFCCLEAR 0x02 |
| tmulrooney | 23:952530fa968d | 633 | |
| tmulrooney | 23:952530fa968d | 634 | #define RF_AFCFEI_AFCAUTOCLEAR_MASK 0xFE |
| tmulrooney | 23:952530fa968d | 635 | #define RF_AFCFEI_AFCAUTOCLEAR_ON 0x01 |
| tmulrooney | 23:952530fa968d | 636 | #define RF_AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 637 | |
| tmulrooney | 23:952530fa968d | 638 | /*! |
| tmulrooney | 23:952530fa968d | 639 | * RegAfcMsb (Read Only) |
| tmulrooney | 23:952530fa968d | 640 | */ |
| tmulrooney | 23:952530fa968d | 641 | |
| tmulrooney | 23:952530fa968d | 642 | /*! |
| tmulrooney | 23:952530fa968d | 643 | * RegAfcLsb (Read Only) |
| tmulrooney | 23:952530fa968d | 644 | */ |
| tmulrooney | 23:952530fa968d | 645 | |
| tmulrooney | 23:952530fa968d | 646 | /*! |
| tmulrooney | 23:952530fa968d | 647 | * RegFeiMsb (Read Only) |
| tmulrooney | 23:952530fa968d | 648 | */ |
| tmulrooney | 23:952530fa968d | 649 | |
| tmulrooney | 23:952530fa968d | 650 | /*! |
| tmulrooney | 23:952530fa968d | 651 | * RegFeiLsb (Read Only) |
| tmulrooney | 23:952530fa968d | 652 | */ |
| tmulrooney | 23:952530fa968d | 653 | |
| tmulrooney | 23:952530fa968d | 654 | /*! |
| tmulrooney | 23:952530fa968d | 655 | * RegPreambleDetect |
| tmulrooney | 23:952530fa968d | 656 | */ |
| tmulrooney | 23:952530fa968d | 657 | #define RF_PREAMBLEDETECT_DETECTOR_MASK 0x7F |
| tmulrooney | 23:952530fa968d | 658 | #define RF_PREAMBLEDETECT_DETECTOR_ON 0x80 // Default |
| tmulrooney | 23:952530fa968d | 659 | #define RF_PREAMBLEDETECT_DETECTOR_OFF 0x00 |
| tmulrooney | 23:952530fa968d | 660 | |
| tmulrooney | 23:952530fa968d | 661 | #define RF_PREAMBLEDETECT_DETECTORSIZE_MASK 0x9F |
| tmulrooney | 23:952530fa968d | 662 | #define RF_PREAMBLEDETECT_DETECTORSIZE_1 0x00 |
| tmulrooney | 23:952530fa968d | 663 | #define RF_PREAMBLEDETECT_DETECTORSIZE_2 0x20 // Default |
| tmulrooney | 23:952530fa968d | 664 | #define RF_PREAMBLEDETECT_DETECTORSIZE_3 0x40 |
| tmulrooney | 23:952530fa968d | 665 | #define RF_PREAMBLEDETECT_DETECTORSIZE_4 0x60 |
| tmulrooney | 23:952530fa968d | 666 | |
| tmulrooney | 23:952530fa968d | 667 | #define RF_PREAMBLEDETECT_DETECTORTOL_MASK 0xE0 |
| tmulrooney | 23:952530fa968d | 668 | #define RF_PREAMBLEDETECT_DETECTORTOL_0 0x00 |
| tmulrooney | 23:952530fa968d | 669 | #define RF_PREAMBLEDETECT_DETECTORTOL_1 0x01 |
| tmulrooney | 23:952530fa968d | 670 | #define RF_PREAMBLEDETECT_DETECTORTOL_2 0x02 |
| tmulrooney | 23:952530fa968d | 671 | #define RF_PREAMBLEDETECT_DETECTORTOL_3 0x03 |
| tmulrooney | 23:952530fa968d | 672 | #define RF_PREAMBLEDETECT_DETECTORTOL_4 0x04 |
| tmulrooney | 23:952530fa968d | 673 | #define RF_PREAMBLEDETECT_DETECTORTOL_5 0x05 |
| tmulrooney | 23:952530fa968d | 674 | #define RF_PREAMBLEDETECT_DETECTORTOL_6 0x06 |
| tmulrooney | 23:952530fa968d | 675 | #define RF_PREAMBLEDETECT_DETECTORTOL_7 0x07 |
| tmulrooney | 23:952530fa968d | 676 | #define RF_PREAMBLEDETECT_DETECTORTOL_8 0x08 |
| tmulrooney | 23:952530fa968d | 677 | #define RF_PREAMBLEDETECT_DETECTORTOL_9 0x09 |
| tmulrooney | 23:952530fa968d | 678 | #define RF_PREAMBLEDETECT_DETECTORTOL_10 0x0A // Default |
| tmulrooney | 23:952530fa968d | 679 | #define RF_PREAMBLEDETECT_DETECTORTOL_11 0x0B |
| tmulrooney | 23:952530fa968d | 680 | #define RF_PREAMBLEDETECT_DETECTORTOL_12 0x0C |
| tmulrooney | 23:952530fa968d | 681 | #define RF_PREAMBLEDETECT_DETECTORTOL_13 0x0D |
| tmulrooney | 23:952530fa968d | 682 | #define RF_PREAMBLEDETECT_DETECTORTOL_14 0x0E |
| tmulrooney | 23:952530fa968d | 683 | #define RF_PREAMBLEDETECT_DETECTORTOL_15 0x0F |
| tmulrooney | 23:952530fa968d | 684 | #define RF_PREAMBLEDETECT_DETECTORTOL_16 0x10 |
| tmulrooney | 23:952530fa968d | 685 | #define RF_PREAMBLEDETECT_DETECTORTOL_17 0x11 |
| tmulrooney | 23:952530fa968d | 686 | #define RF_PREAMBLEDETECT_DETECTORTOL_18 0x12 |
| tmulrooney | 23:952530fa968d | 687 | #define RF_PREAMBLEDETECT_DETECTORTOL_19 0x13 |
| tmulrooney | 23:952530fa968d | 688 | #define RF_PREAMBLEDETECT_DETECTORTOL_20 0x14 |
| tmulrooney | 23:952530fa968d | 689 | #define RF_PREAMBLEDETECT_DETECTORTOL_21 0x15 |
| tmulrooney | 23:952530fa968d | 690 | #define RF_PREAMBLEDETECT_DETECTORTOL_22 0x16 |
| tmulrooney | 23:952530fa968d | 691 | #define RF_PREAMBLEDETECT_DETECTORTOL_23 0x17 |
| tmulrooney | 23:952530fa968d | 692 | #define RF_PREAMBLEDETECT_DETECTORTOL_24 0x18 |
| tmulrooney | 23:952530fa968d | 693 | #define RF_PREAMBLEDETECT_DETECTORTOL_25 0x19 |
| tmulrooney | 23:952530fa968d | 694 | #define RF_PREAMBLEDETECT_DETECTORTOL_26 0x1A |
| tmulrooney | 23:952530fa968d | 695 | #define RF_PREAMBLEDETECT_DETECTORTOL_27 0x1B |
| tmulrooney | 23:952530fa968d | 696 | #define RF_PREAMBLEDETECT_DETECTORTOL_28 0x1C |
| tmulrooney | 23:952530fa968d | 697 | #define RF_PREAMBLEDETECT_DETECTORTOL_29 0x1D |
| tmulrooney | 23:952530fa968d | 698 | #define RF_PREAMBLEDETECT_DETECTORTOL_30 0x1E |
| tmulrooney | 23:952530fa968d | 699 | #define RF_PREAMBLEDETECT_DETECTORTOL_31 0x1F |
| tmulrooney | 23:952530fa968d | 700 | |
| tmulrooney | 23:952530fa968d | 701 | /*! |
| tmulrooney | 23:952530fa968d | 702 | * RegRxTimeout1 |
| tmulrooney | 23:952530fa968d | 703 | */ |
| tmulrooney | 23:952530fa968d | 704 | #define RF_RXTIMEOUT1_TIMEOUTRXRSSI 0x00 // Default |
| tmulrooney | 23:952530fa968d | 705 | |
| tmulrooney | 23:952530fa968d | 706 | /*! |
| tmulrooney | 23:952530fa968d | 707 | * RegRxTimeout2 |
| tmulrooney | 23:952530fa968d | 708 | */ |
| tmulrooney | 23:952530fa968d | 709 | #define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE 0x00 // Default |
| tmulrooney | 23:952530fa968d | 710 | |
| tmulrooney | 23:952530fa968d | 711 | /*! |
| tmulrooney | 23:952530fa968d | 712 | * RegRxTimeout3 |
| tmulrooney | 23:952530fa968d | 713 | */ |
| tmulrooney | 23:952530fa968d | 714 | #define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC 0x00 // Default |
| tmulrooney | 23:952530fa968d | 715 | |
| tmulrooney | 23:952530fa968d | 716 | /*! |
| tmulrooney | 23:952530fa968d | 717 | * RegRxDelay |
| tmulrooney | 23:952530fa968d | 718 | */ |
| tmulrooney | 23:952530fa968d | 719 | #define RF_RXDELAY_INTERPACKETRXDELAY 0x00 // Default |
| tmulrooney | 23:952530fa968d | 720 | |
| tmulrooney | 23:952530fa968d | 721 | /*! |
| tmulrooney | 23:952530fa968d | 722 | * RegOsc |
| tmulrooney | 23:952530fa968d | 723 | */ |
| tmulrooney | 23:952530fa968d | 724 | #define RF_OSC_RCCALSTART 0x08 |
| tmulrooney | 23:952530fa968d | 725 | |
| tmulrooney | 23:952530fa968d | 726 | #define RF_OSC_CLKOUT_MASK 0xF8 |
| tmulrooney | 23:952530fa968d | 727 | #define RF_OSC_CLKOUT_32_MHZ 0x00 |
| tmulrooney | 23:952530fa968d | 728 | #define RF_OSC_CLKOUT_16_MHZ 0x01 |
| tmulrooney | 23:952530fa968d | 729 | #define RF_OSC_CLKOUT_8_MHZ 0x02 |
| tmulrooney | 23:952530fa968d | 730 | #define RF_OSC_CLKOUT_4_MHZ 0x03 |
| tmulrooney | 23:952530fa968d | 731 | #define RF_OSC_CLKOUT_2_MHZ 0x04 |
| tmulrooney | 23:952530fa968d | 732 | #define RF_OSC_CLKOUT_1_MHZ 0x05 // Default |
| tmulrooney | 23:952530fa968d | 733 | #define RF_OSC_CLKOUT_RC 0x06 |
| tmulrooney | 23:952530fa968d | 734 | #define RF_OSC_CLKOUT_OFF 0x07 |
| tmulrooney | 23:952530fa968d | 735 | |
| tmulrooney | 23:952530fa968d | 736 | /*! |
| tmulrooney | 23:952530fa968d | 737 | * RegPreambleMsb/RegPreambleLsb |
| tmulrooney | 23:952530fa968d | 738 | */ |
| tmulrooney | 23:952530fa968d | 739 | #define RF_PREAMBLEMSB_SIZE 0x00 // Default |
| tmulrooney | 23:952530fa968d | 740 | #define RF_PREAMBLELSB_SIZE 0x03 // Default |
| tmulrooney | 23:952530fa968d | 741 | |
| tmulrooney | 23:952530fa968d | 742 | /*! |
| tmulrooney | 23:952530fa968d | 743 | * RegSyncConfig |
| tmulrooney | 23:952530fa968d | 744 | */ |
| tmulrooney | 23:952530fa968d | 745 | #define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK 0x3F |
| tmulrooney | 23:952530fa968d | 746 | #define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON 0x80 // Default |
| tmulrooney | 23:952530fa968d | 747 | #define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40 |
| tmulrooney | 23:952530fa968d | 748 | #define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF 0x00 |
| tmulrooney | 23:952530fa968d | 749 | |
| tmulrooney | 23:952530fa968d | 750 | |
| tmulrooney | 23:952530fa968d | 751 | #define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK 0xDF |
| tmulrooney | 23:952530fa968d | 752 | #define RF_SYNCCONFIG_PREAMBLEPOLARITY_55 0x20 |
| tmulrooney | 23:952530fa968d | 753 | #define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA 0x00 // Default |
| tmulrooney | 23:952530fa968d | 754 | |
| tmulrooney | 23:952530fa968d | 755 | #define RF_SYNCCONFIG_SYNC_MASK 0xEF |
| tmulrooney | 23:952530fa968d | 756 | #define RF_SYNCCONFIG_SYNC_ON 0x10 // Default |
| tmulrooney | 23:952530fa968d | 757 | #define RF_SYNCCONFIG_SYNC_OFF 0x00 |
| tmulrooney | 23:952530fa968d | 758 | |
| tmulrooney | 23:952530fa968d | 759 | |
| tmulrooney | 23:952530fa968d | 760 | #define RF_SYNCCONFIG_SYNCSIZE_MASK 0xF8 |
| tmulrooney | 23:952530fa968d | 761 | #define RF_SYNCCONFIG_SYNCSIZE_1 0x00 |
| tmulrooney | 23:952530fa968d | 762 | #define RF_SYNCCONFIG_SYNCSIZE_2 0x01 |
| tmulrooney | 23:952530fa968d | 763 | #define RF_SYNCCONFIG_SYNCSIZE_3 0x02 |
| tmulrooney | 23:952530fa968d | 764 | #define RF_SYNCCONFIG_SYNCSIZE_4 0x03 // Default |
| tmulrooney | 23:952530fa968d | 765 | #define RF_SYNCCONFIG_SYNCSIZE_5 0x04 |
| tmulrooney | 23:952530fa968d | 766 | #define RF_SYNCCONFIG_SYNCSIZE_6 0x05 |
| tmulrooney | 23:952530fa968d | 767 | #define RF_SYNCCONFIG_SYNCSIZE_7 0x06 |
| tmulrooney | 23:952530fa968d | 768 | #define RF_SYNCCONFIG_SYNCSIZE_8 0x07 |
| tmulrooney | 23:952530fa968d | 769 | |
| tmulrooney | 23:952530fa968d | 770 | /*! |
| tmulrooney | 23:952530fa968d | 771 | * RegSyncValue1-8 |
| tmulrooney | 23:952530fa968d | 772 | */ |
| tmulrooney | 23:952530fa968d | 773 | #define RF_SYNCVALUE1_SYNCVALUE 0x01 // Default |
| tmulrooney | 23:952530fa968d | 774 | #define RF_SYNCVALUE2_SYNCVALUE 0x01 // Default |
| tmulrooney | 23:952530fa968d | 775 | #define RF_SYNCVALUE3_SYNCVALUE 0x01 // Default |
| tmulrooney | 23:952530fa968d | 776 | #define RF_SYNCVALUE4_SYNCVALUE 0x01 // Default |
| tmulrooney | 23:952530fa968d | 777 | #define RF_SYNCVALUE5_SYNCVALUE 0x01 // Default |
| tmulrooney | 23:952530fa968d | 778 | #define RF_SYNCVALUE6_SYNCVALUE 0x01 // Default |
| tmulrooney | 23:952530fa968d | 779 | #define RF_SYNCVALUE7_SYNCVALUE 0x01 // Default |
| tmulrooney | 23:952530fa968d | 780 | #define RF_SYNCVALUE8_SYNCVALUE 0x01 // Default |
| tmulrooney | 23:952530fa968d | 781 | |
| tmulrooney | 23:952530fa968d | 782 | /*! |
| tmulrooney | 23:952530fa968d | 783 | * RegPacketConfig1 |
| tmulrooney | 23:952530fa968d | 784 | */ |
| tmulrooney | 23:952530fa968d | 785 | #define RF_PACKETCONFIG1_PACKETFORMAT_MASK 0x7F |
| tmulrooney | 23:952530fa968d | 786 | #define RF_PACKETCONFIG1_PACKETFORMAT_FIXED 0x00 |
| tmulrooney | 23:952530fa968d | 787 | #define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE 0x80 // Default |
| tmulrooney | 23:952530fa968d | 788 | |
| tmulrooney | 23:952530fa968d | 789 | #define RF_PACKETCONFIG1_DCFREE_MASK 0x9F |
| tmulrooney | 23:952530fa968d | 790 | #define RF_PACKETCONFIG1_DCFREE_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 791 | #define RF_PACKETCONFIG1_DCFREE_MANCHESTER 0x20 |
| tmulrooney | 23:952530fa968d | 792 | #define RF_PACKETCONFIG1_DCFREE_WHITENING 0x40 |
| tmulrooney | 23:952530fa968d | 793 | |
| tmulrooney | 23:952530fa968d | 794 | #define RF_PACKETCONFIG1_CRC_MASK 0xEF |
| tmulrooney | 23:952530fa968d | 795 | #define RF_PACKETCONFIG1_CRC_ON 0x10 // Default |
| tmulrooney | 23:952530fa968d | 796 | #define RF_PACKETCONFIG1_CRC_OFF 0x00 |
| tmulrooney | 23:952530fa968d | 797 | |
| tmulrooney | 23:952530fa968d | 798 | #define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK 0xF7 |
| tmulrooney | 23:952530fa968d | 799 | #define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON 0x00 // Default |
| tmulrooney | 23:952530fa968d | 800 | #define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 |
| tmulrooney | 23:952530fa968d | 801 | |
| tmulrooney | 23:952530fa968d | 802 | #define RF_PACKETCONFIG1_ADDRSFILTERING_MASK 0xF9 |
| tmulrooney | 23:952530fa968d | 803 | #define RF_PACKETCONFIG1_ADDRSFILTERING_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 804 | #define RF_PACKETCONFIG1_ADDRSFILTERING_NODE 0x02 |
| tmulrooney | 23:952530fa968d | 805 | #define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04 |
| tmulrooney | 23:952530fa968d | 806 | |
| tmulrooney | 23:952530fa968d | 807 | #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK 0xFE |
| tmulrooney | 23:952530fa968d | 808 | #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT 0x00 // Default |
| tmulrooney | 23:952530fa968d | 809 | #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM 0x01 |
| tmulrooney | 23:952530fa968d | 810 | |
| tmulrooney | 23:952530fa968d | 811 | /*! |
| tmulrooney | 23:952530fa968d | 812 | * RegPacketConfig2 |
| tmulrooney | 23:952530fa968d | 813 | */ |
| tmulrooney | 23:952530fa968d | 814 | |
| tmulrooney | 23:952530fa968d | 815 | #define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE_MASK 0x7F |
| tmulrooney | 23:952530fa968d | 816 | #define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE 0x80 |
| tmulrooney | 23:952530fa968d | 817 | #define RF_PACKETCONFIG2_WMBUS_CRC_DISABLE 0x00 // Default |
| tmulrooney | 23:952530fa968d | 818 | |
| tmulrooney | 23:952530fa968d | 819 | #define RF_PACKETCONFIG2_DATAMODE_MASK 0xBF |
| tmulrooney | 23:952530fa968d | 820 | #define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS 0x00 |
| tmulrooney | 23:952530fa968d | 821 | #define RF_PACKETCONFIG2_DATAMODE_PACKET 0x40 // Default |
| tmulrooney | 23:952530fa968d | 822 | |
| tmulrooney | 23:952530fa968d | 823 | #define RF_PACKETCONFIG2_IOHOME_MASK 0xDF |
| tmulrooney | 23:952530fa968d | 824 | #define RF_PACKETCONFIG2_IOHOME_ON 0x20 |
| tmulrooney | 23:952530fa968d | 825 | #define RF_PACKETCONFIG2_IOHOME_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 826 | |
| tmulrooney | 23:952530fa968d | 827 | #define RF_PACKETCONFIG2_BEACON_MASK 0xF7 |
| tmulrooney | 23:952530fa968d | 828 | #define RF_PACKETCONFIG2_BEACON_ON 0x08 |
| tmulrooney | 23:952530fa968d | 829 | #define RF_PACKETCONFIG2_BEACON_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 830 | |
| tmulrooney | 23:952530fa968d | 831 | #define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK 0xF8 |
| tmulrooney | 23:952530fa968d | 832 | |
| tmulrooney | 23:952530fa968d | 833 | /*! |
| tmulrooney | 23:952530fa968d | 834 | * RegPayloadLength |
| tmulrooney | 23:952530fa968d | 835 | */ |
| tmulrooney | 23:952530fa968d | 836 | #define RF_PAYLOADLENGTH_LENGTH 0x40 // Default |
| tmulrooney | 23:952530fa968d | 837 | |
| tmulrooney | 23:952530fa968d | 838 | /*! |
| tmulrooney | 23:952530fa968d | 839 | * RegNodeAdrs |
| tmulrooney | 23:952530fa968d | 840 | */ |
| tmulrooney | 23:952530fa968d | 841 | #define RF_NODEADDRESS_ADDRESS 0x00 |
| tmulrooney | 23:952530fa968d | 842 | |
| tmulrooney | 23:952530fa968d | 843 | /*! |
| tmulrooney | 23:952530fa968d | 844 | * RegBroadcastAdrs |
| tmulrooney | 23:952530fa968d | 845 | */ |
| tmulrooney | 23:952530fa968d | 846 | #define RF_BROADCASTADDRESS_ADDRESS 0x00 |
| tmulrooney | 23:952530fa968d | 847 | |
| tmulrooney | 23:952530fa968d | 848 | /*! |
| tmulrooney | 23:952530fa968d | 849 | * RegFifoThresh |
| tmulrooney | 23:952530fa968d | 850 | */ |
| tmulrooney | 23:952530fa968d | 851 | #define RF_FIFOTHRESH_TXSTARTCONDITION_MASK 0x7F |
| tmulrooney | 23:952530fa968d | 852 | #define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH 0x00 // Default |
| tmulrooney | 23:952530fa968d | 853 | #define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80 |
| tmulrooney | 23:952530fa968d | 854 | |
| tmulrooney | 23:952530fa968d | 855 | #define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xC0 |
| tmulrooney | 23:952530fa968d | 856 | #define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD 0x0F // Default |
| tmulrooney | 23:952530fa968d | 857 | |
| tmulrooney | 23:952530fa968d | 858 | /*! |
| tmulrooney | 23:952530fa968d | 859 | * RegSeqConfig1 |
| tmulrooney | 23:952530fa968d | 860 | */ |
| tmulrooney | 23:952530fa968d | 861 | #define RF_SEQCONFIG1_SEQUENCER_START 0x80 |
| tmulrooney | 23:952530fa968d | 862 | |
| tmulrooney | 23:952530fa968d | 863 | #define RF_SEQCONFIG1_SEQUENCER_STOP 0x40 |
| tmulrooney | 23:952530fa968d | 864 | |
| tmulrooney | 23:952530fa968d | 865 | #define RF_SEQCONFIG1_IDLEMODE_MASK 0xDF |
| tmulrooney | 23:952530fa968d | 866 | #define RF_SEQCONFIG1_IDLEMODE_SLEEP 0x20 |
| tmulrooney | 23:952530fa968d | 867 | #define RF_SEQCONFIG1_IDLEMODE_STANDBY 0x00 // Default |
| tmulrooney | 23:952530fa968d | 868 | |
| tmulrooney | 23:952530fa968d | 869 | #define RF_SEQCONFIG1_FROMSTART_MASK 0xE7 |
| tmulrooney | 23:952530fa968d | 870 | #define RF_SEQCONFIG1_FROMSTART_TOLPS 0x00 // Default |
| tmulrooney | 23:952530fa968d | 871 | #define RF_SEQCONFIG1_FROMSTART_TORX 0x08 |
| tmulrooney | 23:952530fa968d | 872 | #define RF_SEQCONFIG1_FROMSTART_TOTX 0x10 |
| tmulrooney | 23:952530fa968d | 873 | #define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL 0x18 |
| tmulrooney | 23:952530fa968d | 874 | |
| tmulrooney | 23:952530fa968d | 875 | #define RF_SEQCONFIG1_LPS_MASK 0xFB |
| tmulrooney | 23:952530fa968d | 876 | #define RF_SEQCONFIG1_LPS_SEQUENCER_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 877 | #define RF_SEQCONFIG1_LPS_IDLE 0x04 |
| tmulrooney | 23:952530fa968d | 878 | |
| tmulrooney | 23:952530fa968d | 879 | #define RF_SEQCONFIG1_FROMIDLE_MASK 0xFD |
| tmulrooney | 23:952530fa968d | 880 | #define RF_SEQCONFIG1_FROMIDLE_TOTX 0x00 // Default |
| tmulrooney | 23:952530fa968d | 881 | #define RF_SEQCONFIG1_FROMIDLE_TORX 0x02 |
| tmulrooney | 23:952530fa968d | 882 | |
| tmulrooney | 23:952530fa968d | 883 | #define RF_SEQCONFIG1_FROMTX_MASK 0xFE |
| tmulrooney | 23:952530fa968d | 884 | #define RF_SEQCONFIG1_FROMTX_TOLPS 0x00 // Default |
| tmulrooney | 23:952530fa968d | 885 | #define RF_SEQCONFIG1_FROMTX_TORX 0x01 |
| tmulrooney | 23:952530fa968d | 886 | |
| tmulrooney | 23:952530fa968d | 887 | /*! |
| tmulrooney | 23:952530fa968d | 888 | * RegSeqConfig2 |
| tmulrooney | 23:952530fa968d | 889 | */ |
| tmulrooney | 23:952530fa968d | 890 | #define RF_SEQCONFIG2_FROMRX_MASK 0x1F |
| tmulrooney | 23:952530fa968d | 891 | #define RF_SEQCONFIG2_FROMRX_TOUNUSED_000 0x00 // Default |
| tmulrooney | 23:952530fa968d | 892 | #define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY 0x20 |
| tmulrooney | 23:952530fa968d | 893 | #define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY 0x40 |
| tmulrooney | 23:952530fa968d | 894 | #define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK 0x60 |
| tmulrooney | 23:952530fa968d | 895 | #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI 0x80 |
| tmulrooney | 23:952530fa968d | 896 | #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC 0xA0 |
| tmulrooney | 23:952530fa968d | 897 | #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0 |
| tmulrooney | 23:952530fa968d | 898 | #define RF_SEQCONFIG2_FROMRX_TOUNUSED_111 0xE0 |
| tmulrooney | 23:952530fa968d | 899 | |
| tmulrooney | 23:952530fa968d | 900 | #define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK 0xE7 |
| tmulrooney | 23:952530fa968d | 901 | #define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART 0x00 // Default |
| tmulrooney | 23:952530fa968d | 902 | #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX 0x08 |
| tmulrooney | 23:952530fa968d | 903 | #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS 0x10 |
| tmulrooney | 23:952530fa968d | 904 | #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF 0x18 |
| tmulrooney | 23:952530fa968d | 905 | |
| tmulrooney | 23:952530fa968d | 906 | #define RF_SEQCONFIG2_FROMRXPKT_MASK 0xF8 |
| tmulrooney | 23:952530fa968d | 907 | #define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 908 | #define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY 0x01 |
| tmulrooney | 23:952530fa968d | 909 | #define RF_SEQCONFIG2_FROMRXPKT_TOLPS 0x02 |
| tmulrooney | 23:952530fa968d | 910 | #define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX 0x03 |
| tmulrooney | 23:952530fa968d | 911 | #define RF_SEQCONFIG2_FROMRXPKT_TORX 0x04 |
| tmulrooney | 23:952530fa968d | 912 | |
| tmulrooney | 23:952530fa968d | 913 | /*! |
| tmulrooney | 23:952530fa968d | 914 | * RegTimerResol |
| tmulrooney | 23:952530fa968d | 915 | */ |
| tmulrooney | 23:952530fa968d | 916 | #define RF_TIMERRESOL_TIMER1RESOL_MASK 0xF3 |
| tmulrooney | 23:952530fa968d | 917 | #define RF_TIMERRESOL_TIMER1RESOL_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 918 | #define RF_TIMERRESOL_TIMER1RESOL_000064_US 0x04 |
| tmulrooney | 23:952530fa968d | 919 | #define RF_TIMERRESOL_TIMER1RESOL_004100_US 0x08 |
| tmulrooney | 23:952530fa968d | 920 | #define RF_TIMERRESOL_TIMER1RESOL_262000_US 0x0C |
| tmulrooney | 23:952530fa968d | 921 | |
| tmulrooney | 23:952530fa968d | 922 | #define RF_TIMERRESOL_TIMER2RESOL_MASK 0xFC |
| tmulrooney | 23:952530fa968d | 923 | #define RF_TIMERRESOL_TIMER2RESOL_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 924 | #define RF_TIMERRESOL_TIMER2RESOL_000064_US 0x01 |
| tmulrooney | 23:952530fa968d | 925 | #define RF_TIMERRESOL_TIMER2RESOL_004100_US 0x02 |
| tmulrooney | 23:952530fa968d | 926 | #define RF_TIMERRESOL_TIMER2RESOL_262000_US 0x03 |
| tmulrooney | 23:952530fa968d | 927 | |
| tmulrooney | 23:952530fa968d | 928 | /*! |
| tmulrooney | 23:952530fa968d | 929 | * RegTimer1Coef |
| tmulrooney | 23:952530fa968d | 930 | */ |
| tmulrooney | 23:952530fa968d | 931 | #define RF_TIMER1COEF_TIMER1COEFFICIENT 0xF5 // Default |
| tmulrooney | 23:952530fa968d | 932 | |
| tmulrooney | 23:952530fa968d | 933 | /*! |
| tmulrooney | 23:952530fa968d | 934 | * RegTimer2Coef |
| tmulrooney | 23:952530fa968d | 935 | */ |
| tmulrooney | 23:952530fa968d | 936 | #define RF_TIMER2COEF_TIMER2COEFFICIENT 0x20 // Default |
| tmulrooney | 23:952530fa968d | 937 | |
| tmulrooney | 23:952530fa968d | 938 | /*! |
| tmulrooney | 23:952530fa968d | 939 | * RegImageCal |
| tmulrooney | 23:952530fa968d | 940 | */ |
| tmulrooney | 23:952530fa968d | 941 | #define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F |
| tmulrooney | 23:952530fa968d | 942 | #define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80 |
| tmulrooney | 23:952530fa968d | 943 | #define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 944 | |
| tmulrooney | 23:952530fa968d | 945 | #define RF_IMAGECAL_IMAGECAL_MASK 0xBF |
| tmulrooney | 23:952530fa968d | 946 | #define RF_IMAGECAL_IMAGECAL_START 0x40 |
| tmulrooney | 23:952530fa968d | 947 | |
| tmulrooney | 23:952530fa968d | 948 | #define RF_IMAGECAL_IMAGECAL_RUNNING 0x20 |
| tmulrooney | 23:952530fa968d | 949 | #define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default |
| tmulrooney | 23:952530fa968d | 950 | |
| tmulrooney | 23:952530fa968d | 951 | #define RF_IMAGECAL_TEMPCHANGE_HIGHER 0x08 |
| tmulrooney | 23:952530fa968d | 952 | #define RF_IMAGECAL_TEMPCHANGE_LOWER 0x00 |
| tmulrooney | 23:952530fa968d | 953 | |
| tmulrooney | 23:952530fa968d | 954 | #define RF_IMAGECAL_TEMPTHRESHOLD_MASK 0xF9 |
| tmulrooney | 23:952530fa968d | 955 | #define RF_IMAGECAL_TEMPTHRESHOLD_05 0x00 |
| tmulrooney | 23:952530fa968d | 956 | #define RF_IMAGECAL_TEMPTHRESHOLD_10 0x02 // Default |
| tmulrooney | 23:952530fa968d | 957 | #define RF_IMAGECAL_TEMPTHRESHOLD_15 0x04 |
| tmulrooney | 23:952530fa968d | 958 | #define RF_IMAGECAL_TEMPTHRESHOLD_20 0x06 |
| tmulrooney | 23:952530fa968d | 959 | |
| tmulrooney | 23:952530fa968d | 960 | #define RF_IMAGECAL_TEMPMONITOR_MASK 0xFE |
| tmulrooney | 23:952530fa968d | 961 | #define RF_IMAGECAL_TEMPMONITOR_ON 0x00 // Default |
| tmulrooney | 23:952530fa968d | 962 | #define RF_IMAGECAL_TEMPMONITOR_OFF 0x01 |
| tmulrooney | 23:952530fa968d | 963 | |
| tmulrooney | 23:952530fa968d | 964 | /*! |
| tmulrooney | 23:952530fa968d | 965 | * RegTemp (Read Only) |
| tmulrooney | 23:952530fa968d | 966 | */ |
| tmulrooney | 23:952530fa968d | 967 | |
| tmulrooney | 23:952530fa968d | 968 | /*! |
| tmulrooney | 23:952530fa968d | 969 | * RegLowBat |
| tmulrooney | 23:952530fa968d | 970 | */ |
| tmulrooney | 23:952530fa968d | 971 | #define RF_LOWBAT_MASK 0xF7 |
| tmulrooney | 23:952530fa968d | 972 | #define RF_LOWBAT_ON 0x08 |
| tmulrooney | 23:952530fa968d | 973 | #define RF_LOWBAT_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 974 | |
| tmulrooney | 23:952530fa968d | 975 | #define RF_LOWBAT_TRIM_MASK 0xF8 |
| tmulrooney | 23:952530fa968d | 976 | #define RF_LOWBAT_TRIM_1695 0x00 |
| tmulrooney | 23:952530fa968d | 977 | #define RF_LOWBAT_TRIM_1764 0x01 |
| tmulrooney | 23:952530fa968d | 978 | #define RF_LOWBAT_TRIM_1835 0x02 // Default |
| tmulrooney | 23:952530fa968d | 979 | #define RF_LOWBAT_TRIM_1905 0x03 |
| tmulrooney | 23:952530fa968d | 980 | #define RF_LOWBAT_TRIM_1976 0x04 |
| tmulrooney | 23:952530fa968d | 981 | #define RF_LOWBAT_TRIM_2045 0x05 |
| tmulrooney | 23:952530fa968d | 982 | #define RF_LOWBAT_TRIM_2116 0x06 |
| tmulrooney | 23:952530fa968d | 983 | #define RF_LOWBAT_TRIM_2185 0x07 |
| tmulrooney | 23:952530fa968d | 984 | |
| tmulrooney | 23:952530fa968d | 985 | /*! |
| tmulrooney | 23:952530fa968d | 986 | * RegIrqFlags1 |
| tmulrooney | 23:952530fa968d | 987 | */ |
| tmulrooney | 23:952530fa968d | 988 | #define RF_IRQFLAGS1_MODEREADY 0x80 |
| tmulrooney | 23:952530fa968d | 989 | |
| tmulrooney | 23:952530fa968d | 990 | #define RF_IRQFLAGS1_RXREADY 0x40 |
| tmulrooney | 23:952530fa968d | 991 | |
| tmulrooney | 23:952530fa968d | 992 | #define RF_IRQFLAGS1_TXREADY 0x20 |
| tmulrooney | 23:952530fa968d | 993 | |
| tmulrooney | 23:952530fa968d | 994 | #define RF_IRQFLAGS1_PLLLOCK 0x10 |
| tmulrooney | 23:952530fa968d | 995 | |
| tmulrooney | 23:952530fa968d | 996 | #define RF_IRQFLAGS1_RSSI 0x08 |
| tmulrooney | 23:952530fa968d | 997 | |
| tmulrooney | 23:952530fa968d | 998 | #define RF_IRQFLAGS1_TIMEOUT 0x04 |
| tmulrooney | 23:952530fa968d | 999 | |
| tmulrooney | 23:952530fa968d | 1000 | #define RF_IRQFLAGS1_PREAMBLEDETECT 0x02 |
| tmulrooney | 23:952530fa968d | 1001 | |
| tmulrooney | 23:952530fa968d | 1002 | #define RF_IRQFLAGS1_SYNCADDRESSMATCH 0x01 |
| tmulrooney | 23:952530fa968d | 1003 | |
| tmulrooney | 23:952530fa968d | 1004 | /*! |
| tmulrooney | 23:952530fa968d | 1005 | * RegIrqFlags2 |
| tmulrooney | 23:952530fa968d | 1006 | */ |
| tmulrooney | 23:952530fa968d | 1007 | #define RF_IRQFLAGS2_FIFOFULL 0x80 |
| tmulrooney | 23:952530fa968d | 1008 | |
| tmulrooney | 23:952530fa968d | 1009 | #define RF_IRQFLAGS2_FIFOEMPTY 0x40 |
| tmulrooney | 23:952530fa968d | 1010 | |
| tmulrooney | 23:952530fa968d | 1011 | #define RF_IRQFLAGS2_FIFOLEVEL 0x20 |
| tmulrooney | 23:952530fa968d | 1012 | |
| tmulrooney | 23:952530fa968d | 1013 | #define RF_IRQFLAGS2_FIFOOVERRUN 0x10 |
| tmulrooney | 23:952530fa968d | 1014 | |
| tmulrooney | 23:952530fa968d | 1015 | #define RF_IRQFLAGS2_PACKETSENT 0x08 |
| tmulrooney | 23:952530fa968d | 1016 | |
| tmulrooney | 23:952530fa968d | 1017 | #define RF_IRQFLAGS2_PAYLOADREADY 0x04 |
| tmulrooney | 23:952530fa968d | 1018 | |
| tmulrooney | 23:952530fa968d | 1019 | #define RF_IRQFLAGS2_CRCOK 0x02 |
| tmulrooney | 23:952530fa968d | 1020 | |
| tmulrooney | 23:952530fa968d | 1021 | #define RF_IRQFLAGS2_LOWBAT 0x01 |
| tmulrooney | 23:952530fa968d | 1022 | |
| tmulrooney | 23:952530fa968d | 1023 | /*! |
| tmulrooney | 23:952530fa968d | 1024 | * RegDioMapping1 |
| tmulrooney | 23:952530fa968d | 1025 | */ |
| tmulrooney | 23:952530fa968d | 1026 | #define RF_DIOMAPPING1_DIO0_MASK 0x3F |
| tmulrooney | 23:952530fa968d | 1027 | #define RF_DIOMAPPING1_DIO0_00 0x00 // Default |
| tmulrooney | 23:952530fa968d | 1028 | #define RF_DIOMAPPING1_DIO0_01 0x40 |
| tmulrooney | 23:952530fa968d | 1029 | #define RF_DIOMAPPING1_DIO0_10 0x80 |
| tmulrooney | 23:952530fa968d | 1030 | #define RF_DIOMAPPING1_DIO0_11 0xC0 |
| tmulrooney | 23:952530fa968d | 1031 | |
| tmulrooney | 23:952530fa968d | 1032 | #define RF_DIOMAPPING1_DIO1_MASK 0xCF |
| tmulrooney | 23:952530fa968d | 1033 | #define RF_DIOMAPPING1_DIO1_00 0x00 // Default |
| tmulrooney | 23:952530fa968d | 1034 | #define RF_DIOMAPPING1_DIO1_01 0x10 |
| tmulrooney | 23:952530fa968d | 1035 | #define RF_DIOMAPPING1_DIO1_10 0x20 |
| tmulrooney | 23:952530fa968d | 1036 | #define RF_DIOMAPPING1_DIO1_11 0x30 |
| tmulrooney | 23:952530fa968d | 1037 | |
| tmulrooney | 23:952530fa968d | 1038 | #define RF_DIOMAPPING1_DIO2_MASK 0xF3 |
| tmulrooney | 23:952530fa968d | 1039 | #define RF_DIOMAPPING1_DIO2_00 0x00 // Default |
| tmulrooney | 23:952530fa968d | 1040 | #define RF_DIOMAPPING1_DIO2_01 0x04 |
| tmulrooney | 23:952530fa968d | 1041 | #define RF_DIOMAPPING1_DIO2_10 0x08 |
| tmulrooney | 23:952530fa968d | 1042 | #define RF_DIOMAPPING1_DIO2_11 0x0C |
| tmulrooney | 23:952530fa968d | 1043 | |
| tmulrooney | 23:952530fa968d | 1044 | #define RF_DIOMAPPING1_DIO3_MASK 0xFC |
| tmulrooney | 23:952530fa968d | 1045 | #define RF_DIOMAPPING1_DIO3_00 0x00 // Default |
| tmulrooney | 23:952530fa968d | 1046 | #define RF_DIOMAPPING1_DIO3_01 0x01 |
| tmulrooney | 23:952530fa968d | 1047 | #define RF_DIOMAPPING1_DIO3_10 0x02 |
| tmulrooney | 23:952530fa968d | 1048 | #define RF_DIOMAPPING1_DIO3_11 0x03 |
| tmulrooney | 23:952530fa968d | 1049 | |
| tmulrooney | 23:952530fa968d | 1050 | /*! |
| tmulrooney | 23:952530fa968d | 1051 | * RegDioMapping2 |
| tmulrooney | 23:952530fa968d | 1052 | */ |
| tmulrooney | 23:952530fa968d | 1053 | #define RF_DIOMAPPING2_DIO4_MASK 0x3F |
| tmulrooney | 23:952530fa968d | 1054 | #define RF_DIOMAPPING2_DIO4_00 0x00 // Default |
| tmulrooney | 23:952530fa968d | 1055 | #define RF_DIOMAPPING2_DIO4_01 0x40 |
| tmulrooney | 23:952530fa968d | 1056 | #define RF_DIOMAPPING2_DIO4_10 0x80 |
| tmulrooney | 23:952530fa968d | 1057 | #define RF_DIOMAPPING2_DIO4_11 0xC0 |
| tmulrooney | 23:952530fa968d | 1058 | |
| tmulrooney | 23:952530fa968d | 1059 | #define RF_DIOMAPPING2_DIO5_MASK 0xCF |
| tmulrooney | 23:952530fa968d | 1060 | #define RF_DIOMAPPING2_DIO5_00 0x00 // Default |
| tmulrooney | 23:952530fa968d | 1061 | #define RF_DIOMAPPING2_DIO5_01 0x10 |
| tmulrooney | 23:952530fa968d | 1062 | #define RF_DIOMAPPING2_DIO5_10 0x20 |
| tmulrooney | 23:952530fa968d | 1063 | #define RF_DIOMAPPING2_DIO5_11 0x30 |
| tmulrooney | 23:952530fa968d | 1064 | |
| tmulrooney | 23:952530fa968d | 1065 | #define RF_DIOMAPPING2_MAP_MASK 0xFE |
| tmulrooney | 23:952530fa968d | 1066 | #define RF_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 |
| tmulrooney | 23:952530fa968d | 1067 | #define RF_DIOMAPPING2_MAP_RSSI 0x00 // Default |
| tmulrooney | 23:952530fa968d | 1068 | |
| tmulrooney | 23:952530fa968d | 1069 | /*! |
| tmulrooney | 23:952530fa968d | 1070 | * RegVersion (Read Only) |
| tmulrooney | 23:952530fa968d | 1071 | */ |
| tmulrooney | 23:952530fa968d | 1072 | |
| tmulrooney | 23:952530fa968d | 1073 | /*! |
| tmulrooney | 23:952530fa968d | 1074 | * RegPllHop |
| tmulrooney | 23:952530fa968d | 1075 | */ |
| tmulrooney | 23:952530fa968d | 1076 | #define RF_PLLHOP_FASTHOP_MASK 0x7F |
| tmulrooney | 23:952530fa968d | 1077 | #define RF_PLLHOP_FASTHOP_ON 0x80 |
| tmulrooney | 23:952530fa968d | 1078 | #define RF_PLLHOP_FASTHOP_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 1079 | |
| tmulrooney | 23:952530fa968d | 1080 | /*! |
| tmulrooney | 23:952530fa968d | 1081 | * RegTcxo |
| tmulrooney | 23:952530fa968d | 1082 | */ |
| tmulrooney | 23:952530fa968d | 1083 | #define RF_TCXO_TCXOINPUT_MASK 0xEF |
| tmulrooney | 23:952530fa968d | 1084 | #define RF_TCXO_TCXOINPUT_ON 0x10 |
| tmulrooney | 23:952530fa968d | 1085 | #define RF_TCXO_TCXOINPUT_OFF 0x00 // Default |
| tmulrooney | 23:952530fa968d | 1086 | |
| tmulrooney | 23:952530fa968d | 1087 | /*! |
| tmulrooney | 23:952530fa968d | 1088 | * RegPaDac |
| tmulrooney | 23:952530fa968d | 1089 | */ |
| tmulrooney | 23:952530fa968d | 1090 | #define RF_PADAC_20DBM_MASK 0xF8 |
| tmulrooney | 23:952530fa968d | 1091 | #define RF_PADAC_20DBM_ON 0x07 |
| tmulrooney | 23:952530fa968d | 1092 | #define RF_PADAC_20DBM_OFF 0x04 // Default |
| tmulrooney | 23:952530fa968d | 1093 | |
| tmulrooney | 23:952530fa968d | 1094 | /*! |
| tmulrooney | 23:952530fa968d | 1095 | * RegFormerTemp |
| tmulrooney | 23:952530fa968d | 1096 | */ |
| tmulrooney | 23:952530fa968d | 1097 | |
| tmulrooney | 23:952530fa968d | 1098 | /*! |
| tmulrooney | 23:952530fa968d | 1099 | * RegBitrateFrac |
| tmulrooney | 23:952530fa968d | 1100 | */ |
| tmulrooney | 23:952530fa968d | 1101 | #define RF_BITRATEFRAC_MASK 0xF0 |
| tmulrooney | 23:952530fa968d | 1102 | |
| tmulrooney | 23:952530fa968d | 1103 | /*! |
| tmulrooney | 23:952530fa968d | 1104 | * RegAgcRef |
| tmulrooney | 23:952530fa968d | 1105 | */ |
| tmulrooney | 23:952530fa968d | 1106 | |
| tmulrooney | 23:952530fa968d | 1107 | /*! |
| tmulrooney | 23:952530fa968d | 1108 | * RegAgcThresh1 |
| tmulrooney | 23:952530fa968d | 1109 | */ |
| tmulrooney | 23:952530fa968d | 1110 | |
| tmulrooney | 23:952530fa968d | 1111 | /*! |
| tmulrooney | 23:952530fa968d | 1112 | * RegAgcThresh2 |
| tmulrooney | 23:952530fa968d | 1113 | */ |
| tmulrooney | 23:952530fa968d | 1114 | |
| tmulrooney | 23:952530fa968d | 1115 | /*! |
| tmulrooney | 23:952530fa968d | 1116 | * RegAgcThresh3 |
| tmulrooney | 23:952530fa968d | 1117 | */ |
| tmulrooney | 23:952530fa968d | 1118 | |
| tmulrooney | 23:952530fa968d | 1119 | /*! |
| tmulrooney | 23:952530fa968d | 1120 | * RegPll |
| tmulrooney | 23:952530fa968d | 1121 | */ |
| tmulrooney | 23:952530fa968d | 1122 | #define RF_PLL_BANDWIDTH_MASK 0x3F |
| tmulrooney | 23:952530fa968d | 1123 | #define RF_PLL_BANDWIDTH_75 0x00 |
| tmulrooney | 23:952530fa968d | 1124 | #define RF_PLL_BANDWIDTH_150 0x40 |
| tmulrooney | 23:952530fa968d | 1125 | #define RF_PLL_BANDWIDTH_225 0x80 |
| tmulrooney | 23:952530fa968d | 1126 | #define RF_PLL_BANDWIDTH_300 0xC0 // Default |
| tmulrooney | 23:952530fa968d | 1127 | |
| tmulrooney | 23:952530fa968d | 1128 | #endif // __SX1272_REGS_FSK_H__ |