Timothy Mulrooney / SX1272Lib

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Dependents:   SX1272PingPong

Fork of SX1276Lib by Semtech

sx1272/sx1272.cpp@24:9100348e6c28, 2016-02-17 (annotated)

Committer:
tmulrooney
Date:
Wed Feb 17 00:47:12 2016 +0000
Revision:
24:9100348e6c28
Parent:
23:273a2f93ae99 
pin changes for FRDK-K22F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tmulrooney 23:273a2f93ae99 1 /*
tmulrooney 23:273a2f93ae99 2 / _____) _ | |
tmulrooney 23:273a2f93ae99 3 ( (____ _____ ____ _| |_ _____ ____| |__
tmulrooney 23:273a2f93ae99 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
tmulrooney 23:273a2f93ae99 5 _____) ) ____| | | || |_| ____( (___| | | |
tmulrooney 23:273a2f93ae99 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
tmulrooney 23:273a2f93ae99 7 (C) 2014 Semtech
tmulrooney 23:273a2f93ae99 8
tmulrooney 23:273a2f93ae99 9 Description: Actual implementation of a SX1272 radio, inherits Radio
tmulrooney 23:273a2f93ae99 10
tmulrooney 23:273a2f93ae99 11 License: Revised BSD License, see LICENSE.TXT file include in the project
tmulrooney 23:273a2f93ae99 12
tmulrooney 23:273a2f93ae99 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
tmulrooney 23:273a2f93ae99 14 */
tmulrooney 23:273a2f93ae99 15 #include "sx1272.h"
tmulrooney 23:273a2f93ae99 16 #include "debug.h"
tmulrooney 23:273a2f93ae99 17
tmulrooney 23:273a2f93ae99 18 const FskBandwidth_t SX1272::FskBandwidths[] =
tmulrooney 23:273a2f93ae99 19 {
tmulrooney 23:273a2f93ae99 20 { 2600 , 0x17 },
tmulrooney 23:273a2f93ae99 21 { 3100 , 0x0F },
tmulrooney 23:273a2f93ae99 22 { 3900 , 0x07 },
tmulrooney 23:273a2f93ae99 23 { 5200 , 0x16 },
tmulrooney 23:273a2f93ae99 24 { 6300 , 0x0E },
tmulrooney 23:273a2f93ae99 25 { 7800 , 0x06 },
tmulrooney 23:273a2f93ae99 26 { 10400 , 0x15 },
tmulrooney 23:273a2f93ae99 27 { 12500 , 0x0D },
tmulrooney 23:273a2f93ae99 28 { 15600 , 0x05 },
tmulrooney 23:273a2f93ae99 29 { 20800 , 0x14 },
tmulrooney 23:273a2f93ae99 30 { 25000 , 0x0C },
tmulrooney 23:273a2f93ae99 31 { 31300 , 0x04 },
tmulrooney 23:273a2f93ae99 32 { 41700 , 0x13 },
tmulrooney 23:273a2f93ae99 33 { 50000 , 0x0B },
tmulrooney 23:273a2f93ae99 34 { 62500 , 0x03 },
tmulrooney 23:273a2f93ae99 35 { 83333 , 0x12 },
tmulrooney 23:273a2f93ae99 36 { 100000, 0x0A },
tmulrooney 23:273a2f93ae99 37 { 125000, 0x02 },
tmulrooney 23:273a2f93ae99 38 { 166700, 0x11 },
tmulrooney 23:273a2f93ae99 39 { 200000, 0x09 },
tmulrooney 23:273a2f93ae99 40 { 250000, 0x01 },
tmulrooney 23:273a2f93ae99 41 { 300000, 0x00 }, // Invalid Badwidth
tmulrooney 23:273a2f93ae99 42 };
tmulrooney 23:273a2f93ae99 43
tmulrooney 23:273a2f93ae99 44
tmulrooney 23:273a2f93ae99 45 SX1272::SX1272( RadioEvents_t *events,
tmulrooney 23:273a2f93ae99 46 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
tmulrooney 23:273a2f93ae99 47 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
tmulrooney 23:273a2f93ae99 48 : Radio( events ),
tmulrooney 23:273a2f93ae99 49 // spi( mosi, miso, sclk ),
tmulrooney 23:273a2f93ae99 50 // nss( nss ),
tmulrooney 23:273a2f93ae99 51 spi( PTD6, PTD7, PTD5 ),
tmulrooney 23:273a2f93ae99 52 nss( PTD4 ),
tmulrooney 23:273a2f93ae99 53 reset( reset ),
tmulrooney 23:273a2f93ae99 54 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
tmulrooney 23:273a2f93ae99 55 isRadioActive( false )
tmulrooney 23:273a2f93ae99 56 {
tmulrooney 23:273a2f93ae99 57 debug("SX1272 constructor\r\n");
tmulrooney 23:273a2f93ae99 58 wait_ms( 10 );
tmulrooney 23:273a2f93ae99 59 this->rxTx = 0;
tmulrooney 23:273a2f93ae99 60 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
tmulrooney 23:273a2f93ae99 61 previousOpMode = RF_OPMODE_STANDBY;
tmulrooney 23:273a2f93ae99 62
tmulrooney 23:273a2f93ae99 63 this->RadioEvents = events;
tmulrooney 23:273a2f93ae99 64
tmulrooney 23:273a2f93ae99 65 this->dioIrq = new DioIrqHandler[6];
tmulrooney 23:273a2f93ae99 66
tmulrooney 23:273a2f93ae99 67 this->dioIrq[0] = &SX1272::OnDio0Irq;
tmulrooney 23:273a2f93ae99 68 this->dioIrq[1] = &SX1272::OnDio1Irq;
tmulrooney 23:273a2f93ae99 69 this->dioIrq[2] = &SX1272::OnDio2Irq;
tmulrooney 23:273a2f93ae99 70 this->dioIrq[3] = &SX1272::OnDio3Irq;
tmulrooney 23:273a2f93ae99 71 this->dioIrq[4] = &SX1272::OnDio4Irq;
tmulrooney 23:273a2f93ae99 72 this->dioIrq[5] = NULL;
tmulrooney 23:273a2f93ae99 73
tmulrooney 23:273a2f93ae99 74 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 75 }
tmulrooney 23:273a2f93ae99 76
tmulrooney 23:273a2f93ae99 77 SX1272::~SX1272( )
tmulrooney 23:273a2f93ae99 78 {
tmulrooney 23:273a2f93ae99 79 debug("SX1272x destructor\r\n");
tmulrooney 23:273a2f93ae99 80 delete this->rxBuffer;
tmulrooney 23:273a2f93ae99 81 delete this->dioIrq;
tmulrooney 23:273a2f93ae99 82 }
tmulrooney 23:273a2f93ae99 83
tmulrooney 23:273a2f93ae99 84 void SX1272::Init( RadioEvents_t *events )
tmulrooney 23:273a2f93ae99 85 {
tmulrooney 23:273a2f93ae99 86 debug("SX1272 Init\r\n");
tmulrooney 23:273a2f93ae99 87 this->RadioEvents = events;
tmulrooney 23:273a2f93ae99 88 }
tmulrooney 23:273a2f93ae99 89
tmulrooney 23:273a2f93ae99 90 RadioState SX1272::GetStatus( void )
tmulrooney 23:273a2f93ae99 91 {
tmulrooney 23:273a2f93ae99 92 debug("GetStatus\r\n");
tmulrooney 23:273a2f93ae99 93 return this->settings.State;
tmulrooney 23:273a2f93ae99 94 }
tmulrooney 23:273a2f93ae99 95
tmulrooney 23:273a2f93ae99 96 void SX1272::SetChannel( uint32_t freq )
tmulrooney 23:273a2f93ae99 97 {
tmulrooney 23:273a2f93ae99 98 debug("SetChannel %d\r\n",freq);
tmulrooney 23:273a2f93ae99 99 this->settings.Channel = freq;
tmulrooney 23:273a2f93ae99 100 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
tmulrooney 23:273a2f93ae99 101 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
tmulrooney 23:273a2f93ae99 102 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
tmulrooney 23:273a2f93ae99 103 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
tmulrooney 23:273a2f93ae99 104 }
tmulrooney 23:273a2f93ae99 105
tmulrooney 23:273a2f93ae99 106 bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
tmulrooney 23:273a2f93ae99 107 {
tmulrooney 23:273a2f93ae99 108 debug("IsChannelFree\r\n");
tmulrooney 23:273a2f93ae99 109 int16_t rssi = 0;
tmulrooney 23:273a2f93ae99 110
tmulrooney 23:273a2f93ae99 111 SetModem( modem );
tmulrooney 23:273a2f93ae99 112
tmulrooney 23:273a2f93ae99 113 SetChannel( freq );
tmulrooney 23:273a2f93ae99 114
tmulrooney 23:273a2f93ae99 115 SetOpMode( RF_OPMODE_RECEIVER );
tmulrooney 23:273a2f93ae99 116
tmulrooney 23:273a2f93ae99 117 wait_ms( 1 );
tmulrooney 23:273a2f93ae99 118
tmulrooney 23:273a2f93ae99 119 rssi = GetRssi( modem );
tmulrooney 23:273a2f93ae99 120
tmulrooney 23:273a2f93ae99 121 Sleep( );
tmulrooney 23:273a2f93ae99 122
tmulrooney 23:273a2f93ae99 123 if( rssi > rssiThresh )
tmulrooney 23:273a2f93ae99 124 {
tmulrooney 23:273a2f93ae99 125 return false;
tmulrooney 23:273a2f93ae99 126 }
tmulrooney 23:273a2f93ae99 127 return true;
tmulrooney 23:273a2f93ae99 128 }
tmulrooney 23:273a2f93ae99 129
tmulrooney 23:273a2f93ae99 130 uint32_t SX1272::Random( void )
tmulrooney 23:273a2f93ae99 131 {
tmulrooney 23:273a2f93ae99 132 debug("Random\r\n");
tmulrooney 23:273a2f93ae99 133 uint8_t i;
tmulrooney 23:273a2f93ae99 134 uint32_t rnd = 0;
tmulrooney 23:273a2f93ae99 135
tmulrooney 23:273a2f93ae99 136 /*
tmulrooney 23:273a2f93ae99 137 * Radio setup for random number generation
tmulrooney 23:273a2f93ae99 138 */
tmulrooney 23:273a2f93ae99 139 // Set LoRa modem ON
tmulrooney 23:273a2f93ae99 140 SetModem( MODEM_LORA );
tmulrooney 23:273a2f93ae99 141
tmulrooney 23:273a2f93ae99 142 // Disable LoRa modem interrupts
tmulrooney 23:273a2f93ae99 143 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:273a2f93ae99 144 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:273a2f93ae99 145 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:273a2f93ae99 146 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:273a2f93ae99 147 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:273a2f93ae99 148 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:273a2f93ae99 149 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:273a2f93ae99 150 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:273a2f93ae99 151
tmulrooney 23:273a2f93ae99 152 // Set radio in continuous reception
tmulrooney 23:273a2f93ae99 153 SetOpMode( RF_OPMODE_RECEIVER );
tmulrooney 23:273a2f93ae99 154
tmulrooney 23:273a2f93ae99 155 for( i = 0; i < 32; i++ )
tmulrooney 23:273a2f93ae99 156 {
tmulrooney 23:273a2f93ae99 157 wait_ms( 1 );
tmulrooney 23:273a2f93ae99 158 // Unfiltered RSSI value reading. Only takes the LSB value
tmulrooney 23:273a2f93ae99 159 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
tmulrooney 23:273a2f93ae99 160 }
tmulrooney 23:273a2f93ae99 161
tmulrooney 23:273a2f93ae99 162 Sleep( );
tmulrooney 23:273a2f93ae99 163
tmulrooney 23:273a2f93ae99 164 return rnd;
tmulrooney 23:273a2f93ae99 165 }
tmulrooney 23:273a2f93ae99 166
tmulrooney 23:273a2f93ae99 167 /*!
tmulrooney 23:273a2f93ae99 168 * Performs the Rx chain calibration for LF and HF bands
tmulrooney 23:273a2f93ae99 169 * \remark Must be called just after the reset so all registers are at their
tmulrooney 23:273a2f93ae99 170 * default values
tmulrooney 23:273a2f93ae99 171 */
tmulrooney 23:273a2f93ae99 172 void SX1272::RxChainCalibration( void )
tmulrooney 23:273a2f93ae99 173 {
tmulrooney 23:273a2f93ae99 174 debug("RxChainCalibration\r\n");
tmulrooney 23:273a2f93ae99 175 uint8_t regPaConfigInitVal;
tmulrooney 23:273a2f93ae99 176 uint32_t initialFreq;
tmulrooney 23:273a2f93ae99 177
tmulrooney 23:273a2f93ae99 178 // Save context
tmulrooney 23:273a2f93ae99 179 regPaConfigInitVal = this->Read( REG_PACONFIG );
tmulrooney 23:273a2f93ae99 180 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
tmulrooney 23:273a2f93ae99 181 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
tmulrooney 23:273a2f93ae99 182 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
tmulrooney 23:273a2f93ae99 183 debug("Initial Freq: %d\r\n", initialFreq);
tmulrooney 23:273a2f93ae99 184
tmulrooney 23:273a2f93ae99 185 // Cut the PA just in case, RFO output, power = -1 dBm
tmulrooney 23:273a2f93ae99 186 this->Write( REG_PACONFIG, 0x00 );
tmulrooney 23:273a2f93ae99 187
tmulrooney 23:273a2f93ae99 188 // Launch Rx chain calibration for LF band
tmulrooney 23:273a2f93ae99 189 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
tmulrooney 23:273a2f93ae99 190 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
tmulrooney 23:273a2f93ae99 191 {
tmulrooney 23:273a2f93ae99 192 }
tmulrooney 23:273a2f93ae99 193
tmulrooney 23:273a2f93ae99 194 // Sets a Frequency in HF band
tmulrooney 23:273a2f93ae99 195 SetChannel( 868000000 );
tmulrooney 23:273a2f93ae99 196
tmulrooney 23:273a2f93ae99 197 // Launch Rx chain calibration for HF band
tmulrooney 23:273a2f93ae99 198 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
tmulrooney 23:273a2f93ae99 199 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
tmulrooney 23:273a2f93ae99 200 {
tmulrooney 23:273a2f93ae99 201 }
tmulrooney 23:273a2f93ae99 202
tmulrooney 23:273a2f93ae99 203 // Restore context
tmulrooney 23:273a2f93ae99 204 this->Write( REG_PACONFIG, regPaConfigInitVal );
tmulrooney 23:273a2f93ae99 205 SetChannel( initialFreq );
tmulrooney 23:273a2f93ae99 206 }
tmulrooney 23:273a2f93ae99 207
tmulrooney 23:273a2f93ae99 208 /*!
tmulrooney 23:273a2f93ae99 209 * Returns the known FSK bandwidth registers value
tmulrooney 23:273a2f93ae99 210 *
tmulrooney 23:273a2f93ae99 211 * \param [IN] bandwidth Bandwidth value in Hz
tmulrooney 23:273a2f93ae99 212 * \retval regValue Bandwidth register value.
tmulrooney 23:273a2f93ae99 213 */
tmulrooney 23:273a2f93ae99 214 uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth )
tmulrooney 23:273a2f93ae99 215 {
tmulrooney 23:273a2f93ae99 216 debug("GetFskBandwidthRegValue\r\n");
tmulrooney 23:273a2f93ae99 217 uint8_t i;
tmulrooney 23:273a2f93ae99 218
tmulrooney 23:273a2f93ae99 219 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
tmulrooney 23:273a2f93ae99 220 {
tmulrooney 23:273a2f93ae99 221 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
tmulrooney 23:273a2f93ae99 222 {
tmulrooney 23:273a2f93ae99 223 return FskBandwidths[i].RegValue;
tmulrooney 23:273a2f93ae99 224 }
tmulrooney 23:273a2f93ae99 225 }
tmulrooney 23:273a2f93ae99 226 // ERROR: Value not found
tmulrooney 23:273a2f93ae99 227 while( 1 );
tmulrooney 23:273a2f93ae99 228 }
tmulrooney 23:273a2f93ae99 229
tmulrooney 23:273a2f93ae99 230 void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
tmulrooney 23:273a2f93ae99 231 uint32_t datarate, uint8_t coderate,
tmulrooney 23:273a2f93ae99 232 uint32_t bandwidthAfc, uint16_t preambleLen,
tmulrooney 23:273a2f93ae99 233 uint16_t symbTimeout, bool fixLen,
tmulrooney 23:273a2f93ae99 234 uint8_t payloadLen,
tmulrooney 23:273a2f93ae99 235 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
tmulrooney 23:273a2f93ae99 236 bool iqInverted, bool rxContinuous )
tmulrooney 23:273a2f93ae99 237 {
tmulrooney 23:273a2f93ae99 238 debug("SetRxConfig\r\n");
tmulrooney 23:273a2f93ae99 239 SetModem( modem );
tmulrooney 23:273a2f93ae99 240
tmulrooney 23:273a2f93ae99 241 switch( modem )
tmulrooney 23:273a2f93ae99 242 {
tmulrooney 23:273a2f93ae99 243 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 244 {
tmulrooney 23:273a2f93ae99 245 this->settings.Fsk.Bandwidth = bandwidth;
tmulrooney 23:273a2f93ae99 246 this->settings.Fsk.Datarate = datarate;
tmulrooney 23:273a2f93ae99 247 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
tmulrooney 23:273a2f93ae99 248 this->settings.Fsk.FixLen = fixLen;
tmulrooney 23:273a2f93ae99 249 this->settings.Fsk.PayloadLen = payloadLen;
tmulrooney 23:273a2f93ae99 250 this->settings.Fsk.CrcOn = crcOn;
tmulrooney 23:273a2f93ae99 251 this->settings.Fsk.IqInverted = iqInverted;
tmulrooney 23:273a2f93ae99 252 this->settings.Fsk.RxContinuous = rxContinuous;
tmulrooney 23:273a2f93ae99 253 this->settings.Fsk.PreambleLen = preambleLen;
tmulrooney 23:273a2f93ae99 254
tmulrooney 23:273a2f93ae99 255 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
tmulrooney 23:273a2f93ae99 256 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
tmulrooney 23:273a2f93ae99 257 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
tmulrooney 23:273a2f93ae99 258
tmulrooney 23:273a2f93ae99 259 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
tmulrooney 23:273a2f93ae99 260 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
tmulrooney 23:273a2f93ae99 261
tmulrooney 23:273a2f93ae99 262 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
tmulrooney 23:273a2f93ae99 263 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
tmulrooney 23:273a2f93ae99 264
tmulrooney 23:273a2f93ae99 265 if( fixLen == 1 )
tmulrooney 23:273a2f93ae99 266 {
tmulrooney 23:273a2f93ae99 267 Write( REG_PAYLOADLENGTH, payloadLen );
tmulrooney 23:273a2f93ae99 268 }
tmulrooney 23:273a2f93ae99 269
tmulrooney 23:273a2f93ae99 270 Write( REG_PACKETCONFIG1,
tmulrooney 23:273a2f93ae99 271 ( Read( REG_PACKETCONFIG1 ) &
tmulrooney 23:273a2f93ae99 272 RF_PACKETCONFIG1_CRC_MASK &
tmulrooney 23:273a2f93ae99 273 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
tmulrooney 23:273a2f93ae99 274 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
tmulrooney 23:273a2f93ae99 275 ( crcOn << 4 ) );
tmulrooney 23:273a2f93ae99 276 }
tmulrooney 23:273a2f93ae99 277 break;
tmulrooney 23:273a2f93ae99 278 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 279 {
tmulrooney 23:273a2f93ae99 280 if( bandwidth > 2 )
tmulrooney 23:273a2f93ae99 281 {
tmulrooney 23:273a2f93ae99 282 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
tmulrooney 23:273a2f93ae99 283 while( 1 );
tmulrooney 23:273a2f93ae99 284 }
tmulrooney 23:273a2f93ae99 285 bandwidth += 7;
tmulrooney 23:273a2f93ae99 286 this->settings.LoRa.Bandwidth = bandwidth;
tmulrooney 23:273a2f93ae99 287 this->settings.LoRa.Datarate = datarate;
tmulrooney 23:273a2f93ae99 288 this->settings.LoRa.Coderate = coderate;
tmulrooney 23:273a2f93ae99 289 this->settings.LoRa.PreambleLen = preambleLen;
tmulrooney 23:273a2f93ae99 290 this->settings.LoRa.FixLen = fixLen;
tmulrooney 23:273a2f93ae99 291 this->settings.LoRa.PayloadLen = payloadLen;
tmulrooney 23:273a2f93ae99 292 this->settings.LoRa.CrcOn = crcOn;
tmulrooney 23:273a2f93ae99 293 this->settings.LoRa.FreqHopOn = freqHopOn;
tmulrooney 23:273a2f93ae99 294 this->settings.LoRa.HopPeriod = hopPeriod;
tmulrooney 23:273a2f93ae99 295 this->settings.LoRa.IqInverted = iqInverted;
tmulrooney 23:273a2f93ae99 296 this->settings.LoRa.RxContinuous = rxContinuous;
tmulrooney 23:273a2f93ae99 297
tmulrooney 23:273a2f93ae99 298 if( datarate > 12 )
tmulrooney 23:273a2f93ae99 299 {
tmulrooney 23:273a2f93ae99 300 datarate = 12;
tmulrooney 23:273a2f93ae99 301 }
tmulrooney 23:273a2f93ae99 302 else if( datarate < 6 )
tmulrooney 23:273a2f93ae99 303 {
tmulrooney 23:273a2f93ae99 304 datarate = 6;
tmulrooney 23:273a2f93ae99 305 }
tmulrooney 23:273a2f93ae99 306
tmulrooney 23:273a2f93ae99 307 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
tmulrooney 23:273a2f93ae99 308 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
tmulrooney 23:273a2f93ae99 309 {
tmulrooney 23:273a2f93ae99 310 this->settings.LoRa.LowDatarateOptimize = 0x01;
tmulrooney 23:273a2f93ae99 311 }
tmulrooney 23:273a2f93ae99 312 else
tmulrooney 23:273a2f93ae99 313 {
tmulrooney 23:273a2f93ae99 314 this->settings.LoRa.LowDatarateOptimize = 0x00;
tmulrooney 23:273a2f93ae99 315 }
tmulrooney 23:273a2f93ae99 316
tmulrooney 23:273a2f93ae99 317 Write( REG_LR_MODEMCONFIG1,
tmulrooney 23:273a2f93ae99 318 ( Read( REG_LR_MODEMCONFIG1 ) &
tmulrooney 23:273a2f93ae99 319 RFLR_MODEMCONFIG1_BW_MASK &
tmulrooney 23:273a2f93ae99 320 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
tmulrooney 23:273a2f93ae99 321 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
tmulrooney 23:273a2f93ae99 322 ( bandwidth << 4 ) | ( coderate << 1 ) |
tmulrooney 23:273a2f93ae99 323 fixLen );
tmulrooney 23:273a2f93ae99 324
tmulrooney 23:273a2f93ae99 325 Write( REG_LR_MODEMCONFIG2,
tmulrooney 23:273a2f93ae99 326 ( Read( REG_LR_MODEMCONFIG2 ) &
tmulrooney 23:273a2f93ae99 327 RFLR_MODEMCONFIG2_SF_MASK &
tmulrooney 23:273a2f93ae99 328 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
tmulrooney 23:273a2f93ae99 329 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
tmulrooney 23:273a2f93ae99 330 ( datarate << 4 ) | ( crcOn << 2 ) |
tmulrooney 23:273a2f93ae99 331 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
tmulrooney 23:273a2f93ae99 332
tmulrooney 23:273a2f93ae99 333 Write( REG_LR_MODEMCONFIG3,
tmulrooney 23:273a2f93ae99 334 ( Read( REG_LR_MODEMCONFIG3 ) &
tmulrooney 23:273a2f93ae99 335 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
tmulrooney 23:273a2f93ae99 336 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
tmulrooney 23:273a2f93ae99 337
tmulrooney 23:273a2f93ae99 338 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
tmulrooney 23:273a2f93ae99 339
tmulrooney 23:273a2f93ae99 340 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
tmulrooney 23:273a2f93ae99 341 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
tmulrooney 23:273a2f93ae99 342
tmulrooney 23:273a2f93ae99 343 if( fixLen == 1 )
tmulrooney 23:273a2f93ae99 344 {
tmulrooney 23:273a2f93ae99 345 Write( REG_LR_PAYLOADLENGTH, payloadLen );
tmulrooney 23:273a2f93ae99 346 }
tmulrooney 23:273a2f93ae99 347
tmulrooney 23:273a2f93ae99 348 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:273a2f93ae99 349 {
tmulrooney 23:273a2f93ae99 350 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
tmulrooney 23:273a2f93ae99 351 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
tmulrooney 23:273a2f93ae99 352 }
tmulrooney 23:273a2f93ae99 353
tmulrooney 23:273a2f93ae99 354 if( ( bandwidth == 9 ) && ( RF_MID_BAND_THRESH ) )
tmulrooney 23:273a2f93ae99 355 {
tmulrooney 23:273a2f93ae99 356 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
tmulrooney 23:273a2f93ae99 357 Write( REG_LR_TEST36, 0x02 );
tmulrooney 23:273a2f93ae99 358 Write( REG_LR_TEST3A, 0x64 );
tmulrooney 23:273a2f93ae99 359 }
tmulrooney 23:273a2f93ae99 360 else if( bandwidth == 9 )
tmulrooney 23:273a2f93ae99 361 {
tmulrooney 23:273a2f93ae99 362 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
tmulrooney 23:273a2f93ae99 363 Write( REG_LR_TEST36, 0x02 );
tmulrooney 23:273a2f93ae99 364 Write( REG_LR_TEST3A, 0x7F );
tmulrooney 23:273a2f93ae99 365 }
tmulrooney 23:273a2f93ae99 366 else
tmulrooney 23:273a2f93ae99 367 {
tmulrooney 23:273a2f93ae99 368 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
tmulrooney 23:273a2f93ae99 369 Write( REG_LR_TEST36, 0x03 );
tmulrooney 23:273a2f93ae99 370 }
tmulrooney 23:273a2f93ae99 371
tmulrooney 23:273a2f93ae99 372 if( datarate == 6 )
tmulrooney 23:273a2f93ae99 373 {
tmulrooney 23:273a2f93ae99 374 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:273a2f93ae99 375 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:273a2f93ae99 376 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:273a2f93ae99 377 RFLR_DETECTIONOPTIMIZE_SF6 );
tmulrooney 23:273a2f93ae99 378 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:273a2f93ae99 379 RFLR_DETECTIONTHRESH_SF6 );
tmulrooney 23:273a2f93ae99 380 }
tmulrooney 23:273a2f93ae99 381 else
tmulrooney 23:273a2f93ae99 382 {
tmulrooney 23:273a2f93ae99 383 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:273a2f93ae99 384 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:273a2f93ae99 385 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:273a2f93ae99 386 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
tmulrooney 23:273a2f93ae99 387 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:273a2f93ae99 388 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
tmulrooney 23:273a2f93ae99 389 }
tmulrooney 23:273a2f93ae99 390 }
tmulrooney 23:273a2f93ae99 391 break;
tmulrooney 23:273a2f93ae99 392 }
tmulrooney 23:273a2f93ae99 393 }
tmulrooney 23:273a2f93ae99 394
tmulrooney 23:273a2f93ae99 395 void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
tmulrooney 23:273a2f93ae99 396 uint32_t bandwidth, uint32_t datarate,
tmulrooney 23:273a2f93ae99 397 uint8_t coderate, uint16_t preambleLen,
tmulrooney 23:273a2f93ae99 398 bool fixLen, bool crcOn, bool freqHopOn,
tmulrooney 23:273a2f93ae99 399 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
tmulrooney 23:273a2f93ae99 400 {
tmulrooney 23:273a2f93ae99 401 debug("SetTxConfig\r\n");
tmulrooney 23:273a2f93ae99 402 uint8_t paConfig = 0;
tmulrooney 23:273a2f93ae99 403 uint8_t paDac = 0;
tmulrooney 23:273a2f93ae99 404
tmulrooney 23:273a2f93ae99 405 SetModem( modem );
tmulrooney 23:273a2f93ae99 406
tmulrooney 23:273a2f93ae99 407 paConfig = Read( REG_PACONFIG );
tmulrooney 23:273a2f93ae99 408 paDac = Read( REG_PADAC );
tmulrooney 23:273a2f93ae99 409
tmulrooney 23:273a2f93ae99 410 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
tmulrooney 23:273a2f93ae99 411 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
tmulrooney 23:273a2f93ae99 412
tmulrooney 23:273a2f93ae99 413 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
tmulrooney 23:273a2f93ae99 414 {
tmulrooney 23:273a2f93ae99 415 if( power > 17 )
tmulrooney 23:273a2f93ae99 416 {
tmulrooney 23:273a2f93ae99 417 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
tmulrooney 23:273a2f93ae99 418 }
tmulrooney 23:273a2f93ae99 419 else
tmulrooney 23:273a2f93ae99 420 {
tmulrooney 23:273a2f93ae99 421 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
tmulrooney 23:273a2f93ae99 422 }
tmulrooney 23:273a2f93ae99 423 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
tmulrooney 23:273a2f93ae99 424 {
tmulrooney 23:273a2f93ae99 425 if( power < 5 )
tmulrooney 23:273a2f93ae99 426 {
tmulrooney 23:273a2f93ae99 427 power = 5;
tmulrooney 23:273a2f93ae99 428 }
tmulrooney 23:273a2f93ae99 429 if( power > 20 )
tmulrooney 23:273a2f93ae99 430 {
tmulrooney 23:273a2f93ae99 431 power = 20;
tmulrooney 23:273a2f93ae99 432 }
tmulrooney 23:273a2f93ae99 433 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
tmulrooney 23:273a2f93ae99 434 }
tmulrooney 23:273a2f93ae99 435 else
tmulrooney 23:273a2f93ae99 436 {
tmulrooney 23:273a2f93ae99 437 if( power < 2 )
tmulrooney 23:273a2f93ae99 438 {
tmulrooney 23:273a2f93ae99 439 power = 2;
tmulrooney 23:273a2f93ae99 440 }
tmulrooney 23:273a2f93ae99 441 if( power > 17 )
tmulrooney 23:273a2f93ae99 442 {
tmulrooney 23:273a2f93ae99 443 power = 17;
tmulrooney 23:273a2f93ae99 444 }
tmulrooney 23:273a2f93ae99 445 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
tmulrooney 23:273a2f93ae99 446 }
tmulrooney 23:273a2f93ae99 447 }
tmulrooney 23:273a2f93ae99 448 else
tmulrooney 23:273a2f93ae99 449 {
tmulrooney 23:273a2f93ae99 450 if( power < -1 )
tmulrooney 23:273a2f93ae99 451 {
tmulrooney 23:273a2f93ae99 452 power = -1;
tmulrooney 23:273a2f93ae99 453 }
tmulrooney 23:273a2f93ae99 454 if( power > 14 )
tmulrooney 23:273a2f93ae99 455 {
tmulrooney 23:273a2f93ae99 456 power = 14;
tmulrooney 23:273a2f93ae99 457 }
tmulrooney 23:273a2f93ae99 458 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
tmulrooney 23:273a2f93ae99 459 }
tmulrooney 23:273a2f93ae99 460 Write( REG_PACONFIG, paConfig );
tmulrooney 23:273a2f93ae99 461 Write( REG_PADAC, paDac );
tmulrooney 23:273a2f93ae99 462
tmulrooney 23:273a2f93ae99 463 switch( modem )
tmulrooney 23:273a2f93ae99 464 {
tmulrooney 23:273a2f93ae99 465 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 466 {
tmulrooney 23:273a2f93ae99 467 this->settings.Fsk.Power = power;
tmulrooney 23:273a2f93ae99 468 this->settings.Fsk.Fdev = fdev;
tmulrooney 23:273a2f93ae99 469 this->settings.Fsk.Bandwidth = bandwidth;
tmulrooney 23:273a2f93ae99 470 this->settings.Fsk.Datarate = datarate;
tmulrooney 23:273a2f93ae99 471 this->settings.Fsk.PreambleLen = preambleLen;
tmulrooney 23:273a2f93ae99 472 this->settings.Fsk.FixLen = fixLen;
tmulrooney 23:273a2f93ae99 473 this->settings.Fsk.CrcOn = crcOn;
tmulrooney 23:273a2f93ae99 474 this->settings.Fsk.IqInverted = iqInverted;
tmulrooney 23:273a2f93ae99 475 this->settings.Fsk.TxTimeout = timeout;
tmulrooney 23:273a2f93ae99 476
tmulrooney 23:273a2f93ae99 477 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
tmulrooney 23:273a2f93ae99 478 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
tmulrooney 23:273a2f93ae99 479 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
tmulrooney 23:273a2f93ae99 480
tmulrooney 23:273a2f93ae99 481 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
tmulrooney 23:273a2f93ae99 482 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
tmulrooney 23:273a2f93ae99 483 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
tmulrooney 23:273a2f93ae99 484
tmulrooney 23:273a2f93ae99 485 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
tmulrooney 23:273a2f93ae99 486 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
tmulrooney 23:273a2f93ae99 487
tmulrooney 23:273a2f93ae99 488 Write( REG_PACKETCONFIG1,
tmulrooney 23:273a2f93ae99 489 ( Read( REG_PACKETCONFIG1 ) &
tmulrooney 23:273a2f93ae99 490 RF_PACKETCONFIG1_CRC_MASK &
tmulrooney 23:273a2f93ae99 491 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
tmulrooney 23:273a2f93ae99 492 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
tmulrooney 23:273a2f93ae99 493 ( crcOn << 4 ) );
tmulrooney 23:273a2f93ae99 494
tmulrooney 23:273a2f93ae99 495 }
tmulrooney 23:273a2f93ae99 496 break;
tmulrooney 23:273a2f93ae99 497 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 498 {
tmulrooney 23:273a2f93ae99 499 this->settings.LoRa.Power = power;
tmulrooney 23:273a2f93ae99 500 if( bandwidth > 2 )
tmulrooney 23:273a2f93ae99 501 {
tmulrooney 23:273a2f93ae99 502 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
tmulrooney 23:273a2f93ae99 503 while( 1 );
tmulrooney 23:273a2f93ae99 504 }
tmulrooney 23:273a2f93ae99 505 bandwidth += 7;
tmulrooney 23:273a2f93ae99 506 this->settings.LoRa.Bandwidth = bandwidth;
tmulrooney 23:273a2f93ae99 507 this->settings.LoRa.Datarate = datarate;
tmulrooney 23:273a2f93ae99 508 this->settings.LoRa.Coderate = coderate;
tmulrooney 23:273a2f93ae99 509 this->settings.LoRa.PreambleLen = preambleLen;
tmulrooney 23:273a2f93ae99 510 this->settings.LoRa.FixLen = fixLen;
tmulrooney 23:273a2f93ae99 511 this->settings.LoRa.FreqHopOn = freqHopOn;
tmulrooney 23:273a2f93ae99 512 this->settings.LoRa.HopPeriod = hopPeriod;
tmulrooney 23:273a2f93ae99 513 this->settings.LoRa.CrcOn = crcOn;
tmulrooney 23:273a2f93ae99 514 this->settings.LoRa.IqInverted = iqInverted;
tmulrooney 23:273a2f93ae99 515 this->settings.LoRa.TxTimeout = timeout;
tmulrooney 23:273a2f93ae99 516
tmulrooney 23:273a2f93ae99 517 if( datarate > 12 )
tmulrooney 23:273a2f93ae99 518 {
tmulrooney 23:273a2f93ae99 519 datarate = 12;
tmulrooney 23:273a2f93ae99 520 }
tmulrooney 23:273a2f93ae99 521 else if( datarate < 6 )
tmulrooney 23:273a2f93ae99 522 {
tmulrooney 23:273a2f93ae99 523 datarate = 6;
tmulrooney 23:273a2f93ae99 524 }
tmulrooney 23:273a2f93ae99 525 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
tmulrooney 23:273a2f93ae99 526 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
tmulrooney 23:273a2f93ae99 527 {
tmulrooney 23:273a2f93ae99 528 this->settings.LoRa.LowDatarateOptimize = 0x01;
tmulrooney 23:273a2f93ae99 529 }
tmulrooney 23:273a2f93ae99 530 else
tmulrooney 23:273a2f93ae99 531 {
tmulrooney 23:273a2f93ae99 532 this->settings.LoRa.LowDatarateOptimize = 0x00;
tmulrooney 23:273a2f93ae99 533 }
tmulrooney 23:273a2f93ae99 534
tmulrooney 23:273a2f93ae99 535 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:273a2f93ae99 536 {
tmulrooney 23:273a2f93ae99 537 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
tmulrooney 23:273a2f93ae99 538 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
tmulrooney 23:273a2f93ae99 539 }
tmulrooney 23:273a2f93ae99 540
tmulrooney 23:273a2f93ae99 541 Write( REG_LR_MODEMCONFIG1,
tmulrooney 23:273a2f93ae99 542 ( Read( REG_LR_MODEMCONFIG1 ) &
tmulrooney 23:273a2f93ae99 543 RFLR_MODEMCONFIG1_BW_MASK &
tmulrooney 23:273a2f93ae99 544 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
tmulrooney 23:273a2f93ae99 545 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
tmulrooney 23:273a2f93ae99 546 ( bandwidth << 4 ) | ( coderate << 1 ) |
tmulrooney 23:273a2f93ae99 547 fixLen );
tmulrooney 23:273a2f93ae99 548
tmulrooney 23:273a2f93ae99 549 Write( REG_LR_MODEMCONFIG2,
tmulrooney 23:273a2f93ae99 550 ( Read( REG_LR_MODEMCONFIG2 ) &
tmulrooney 23:273a2f93ae99 551 RFLR_MODEMCONFIG2_SF_MASK &
tmulrooney 23:273a2f93ae99 552 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
tmulrooney 23:273a2f93ae99 553 ( datarate << 4 ) | ( crcOn << 2 ) );
tmulrooney 23:273a2f93ae99 554
tmulrooney 23:273a2f93ae99 555 Write( REG_LR_MODEMCONFIG3,
tmulrooney 23:273a2f93ae99 556 ( Read( REG_LR_MODEMCONFIG3 ) &
tmulrooney 23:273a2f93ae99 557 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
tmulrooney 23:273a2f93ae99 558 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
tmulrooney 23:273a2f93ae99 559
tmulrooney 23:273a2f93ae99 560 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
tmulrooney 23:273a2f93ae99 561 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
tmulrooney 23:273a2f93ae99 562
tmulrooney 23:273a2f93ae99 563 if( datarate == 6 )
tmulrooney 23:273a2f93ae99 564 {
tmulrooney 23:273a2f93ae99 565 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:273a2f93ae99 566 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:273a2f93ae99 567 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:273a2f93ae99 568 RFLR_DETECTIONOPTIMIZE_SF6 );
tmulrooney 23:273a2f93ae99 569 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:273a2f93ae99 570 RFLR_DETECTIONTHRESH_SF6 );
tmulrooney 23:273a2f93ae99 571 }
tmulrooney 23:273a2f93ae99 572 else
tmulrooney 23:273a2f93ae99 573 {
tmulrooney 23:273a2f93ae99 574 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:273a2f93ae99 575 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:273a2f93ae99 576 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:273a2f93ae99 577 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
tmulrooney 23:273a2f93ae99 578 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:273a2f93ae99 579 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
tmulrooney 23:273a2f93ae99 580 }
tmulrooney 23:273a2f93ae99 581 }
tmulrooney 23:273a2f93ae99 582 break;
tmulrooney 23:273a2f93ae99 583 }
tmulrooney 23:273a2f93ae99 584 }
tmulrooney 23:273a2f93ae99 585
tmulrooney 23:273a2f93ae99 586 double SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
tmulrooney 23:273a2f93ae99 587 {
tmulrooney 23:273a2f93ae99 588 debug("TimeOnAir\r\n");
tmulrooney 23:273a2f93ae99 589 uint32_t airTime = 0;
tmulrooney 23:273a2f93ae99 590
tmulrooney 23:273a2f93ae99 591 switch( modem )
tmulrooney 23:273a2f93ae99 592 {
tmulrooney 23:273a2f93ae99 593 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 594 {
tmulrooney 23:273a2f93ae99 595 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:273a2f93ae99 596 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
tmulrooney 23:273a2f93ae99 597 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
tmulrooney 23:273a2f93ae99 598 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
tmulrooney 23:273a2f93ae99 599 pktLen +
tmulrooney 23:273a2f93ae99 600 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
tmulrooney 23:273a2f93ae99 601 this->settings.Fsk.Datarate ) * 1e6 );
tmulrooney 23:273a2f93ae99 602 }
tmulrooney 23:273a2f93ae99 603 break;
tmulrooney 23:273a2f93ae99 604 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 605 {
tmulrooney 23:273a2f93ae99 606 double bw = 0.0;
tmulrooney 23:273a2f93ae99 607 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
tmulrooney 23:273a2f93ae99 608 switch( this->settings.LoRa.Bandwidth )
tmulrooney 23:273a2f93ae99 609 {
tmulrooney 23:273a2f93ae99 610 //case 0: // 7.8 kHz
tmulrooney 23:273a2f93ae99 611 // bw = 78e2;
tmulrooney 23:273a2f93ae99 612 // break;
tmulrooney 23:273a2f93ae99 613 //case 1: // 10.4 kHz
tmulrooney 23:273a2f93ae99 614 // bw = 104e2;
tmulrooney 23:273a2f93ae99 615 // break;
tmulrooney 23:273a2f93ae99 616 //case 2: // 15.6 kHz
tmulrooney 23:273a2f93ae99 617 // bw = 156e2;
tmulrooney 23:273a2f93ae99 618 // break;
tmulrooney 23:273a2f93ae99 619 //case 3: // 20.8 kHz
tmulrooney 23:273a2f93ae99 620 // bw = 208e2;
tmulrooney 23:273a2f93ae99 621 // break;
tmulrooney 23:273a2f93ae99 622 //case 4: // 31.2 kHz
tmulrooney 23:273a2f93ae99 623 // bw = 312e2;
tmulrooney 23:273a2f93ae99 624 // break;
tmulrooney 23:273a2f93ae99 625 //case 5: // 41.4 kHz
tmulrooney 23:273a2f93ae99 626 // bw = 414e2;
tmulrooney 23:273a2f93ae99 627 // break;
tmulrooney 23:273a2f93ae99 628 //case 6: // 62.5 kHz
tmulrooney 23:273a2f93ae99 629 // bw = 625e2;
tmulrooney 23:273a2f93ae99 630 // break;
tmulrooney 23:273a2f93ae99 631 case 7: // 125 kHz
tmulrooney 23:273a2f93ae99 632 bw = 125e3;
tmulrooney 23:273a2f93ae99 633 break;
tmulrooney 23:273a2f93ae99 634 case 8: // 250 kHz
tmulrooney 23:273a2f93ae99 635 bw = 250e3;
tmulrooney 23:273a2f93ae99 636 break;
tmulrooney 23:273a2f93ae99 637 case 9: // 500 kHz
tmulrooney 23:273a2f93ae99 638 bw = 500e3;
tmulrooney 23:273a2f93ae99 639 break;
tmulrooney 23:273a2f93ae99 640 }
tmulrooney 23:273a2f93ae99 641
tmulrooney 23:273a2f93ae99 642 // Symbol rate : time for one symbol (secs)
tmulrooney 23:273a2f93ae99 643 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
tmulrooney 23:273a2f93ae99 644 double ts = 1 / rs;
tmulrooney 23:273a2f93ae99 645 // time of preamble
tmulrooney 23:273a2f93ae99 646 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
tmulrooney 23:273a2f93ae99 647 // Symbol length of payload and time
tmulrooney 23:273a2f93ae99 648 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
tmulrooney 23:273a2f93ae99 649 28 + 16 * this->settings.LoRa.CrcOn -
tmulrooney 23:273a2f93ae99 650 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
tmulrooney 23:273a2f93ae99 651 ( double )( 4 * this->settings.LoRa.Datarate -
tmulrooney 23:273a2f93ae99 652 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
tmulrooney 23:273a2f93ae99 653 ( this->settings.LoRa.Coderate + 4 );
tmulrooney 23:273a2f93ae99 654 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
tmulrooney 23:273a2f93ae99 655 double tPayload = nPayload * ts;
tmulrooney 23:273a2f93ae99 656 // Time on air
tmulrooney 23:273a2f93ae99 657 double tOnAir = tPreamble + tPayload;
tmulrooney 23:273a2f93ae99 658 // return us secs
tmulrooney 23:273a2f93ae99 659 airTime = floor( tOnAir * 1e6 + 0.999 );
tmulrooney 23:273a2f93ae99 660 }
tmulrooney 23:273a2f93ae99 661 break;
tmulrooney 23:273a2f93ae99 662 }
tmulrooney 23:273a2f93ae99 663 return airTime;
tmulrooney 23:273a2f93ae99 664 }
tmulrooney 23:273a2f93ae99 665
tmulrooney 23:273a2f93ae99 666 void SX1272::Send( uint8_t *buffer, uint8_t size )
tmulrooney 23:273a2f93ae99 667 {
tmulrooney 23:273a2f93ae99 668 debug("Send\r\n");
tmulrooney 23:273a2f93ae99 669 uint32_t txTimeout = 0;
tmulrooney 23:273a2f93ae99 670
tmulrooney 23:273a2f93ae99 671 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 672 {
tmulrooney 23:273a2f93ae99 673 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 674 {
tmulrooney 23:273a2f93ae99 675 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:273a2f93ae99 676 this->settings.FskPacketHandler.Size = size;
tmulrooney 23:273a2f93ae99 677
tmulrooney 23:273a2f93ae99 678 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:273a2f93ae99 679 {
tmulrooney 23:273a2f93ae99 680 WriteFifo( ( uint8_t* )&size, 1 );
tmulrooney 23:273a2f93ae99 681 }
tmulrooney 23:273a2f93ae99 682 else
tmulrooney 23:273a2f93ae99 683 {
tmulrooney 23:273a2f93ae99 684 Write( REG_PAYLOADLENGTH, size );
tmulrooney 23:273a2f93ae99 685 }
tmulrooney 23:273a2f93ae99 686
tmulrooney 23:273a2f93ae99 687 if( ( size > 0 ) && ( size <= 64 ) )
tmulrooney 23:273a2f93ae99 688 {
tmulrooney 23:273a2f93ae99 689 this->settings.FskPacketHandler.ChunkSize = size;
tmulrooney 23:273a2f93ae99 690 }
tmulrooney 23:273a2f93ae99 691 else
tmulrooney 23:273a2f93ae99 692 {
tmulrooney 23:273a2f93ae99 693 this->settings.FskPacketHandler.ChunkSize = 32;
tmulrooney 23:273a2f93ae99 694 }
tmulrooney 23:273a2f93ae99 695
tmulrooney 23:273a2f93ae99 696 // Write payload buffer
tmulrooney 23:273a2f93ae99 697 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
tmulrooney 23:273a2f93ae99 698 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
tmulrooney 23:273a2f93ae99 699 txTimeout = this->settings.Fsk.TxTimeout;
tmulrooney 23:273a2f93ae99 700 }
tmulrooney 23:273a2f93ae99 701 break;
tmulrooney 23:273a2f93ae99 702 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 703 {
tmulrooney 23:273a2f93ae99 704 if( this->settings.LoRa.IqInverted == true )
tmulrooney 23:273a2f93ae99 705 {
tmulrooney 23:273a2f93ae99 706 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
tmulrooney 23:273a2f93ae99 707 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
tmulrooney 23:273a2f93ae99 708 }
tmulrooney 23:273a2f93ae99 709 else
tmulrooney 23:273a2f93ae99 710 {
tmulrooney 23:273a2f93ae99 711 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
tmulrooney 23:273a2f93ae99 712 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
tmulrooney 23:273a2f93ae99 713 }
tmulrooney 23:273a2f93ae99 714
tmulrooney 23:273a2f93ae99 715 this->settings.LoRaPacketHandler.Size = size;
tmulrooney 23:273a2f93ae99 716
tmulrooney 23:273a2f93ae99 717 // Initializes the payload size
tmulrooney 23:273a2f93ae99 718 Write( REG_LR_PAYLOADLENGTH, size );
tmulrooney 23:273a2f93ae99 719
tmulrooney 23:273a2f93ae99 720 // Full buffer used for Tx
tmulrooney 23:273a2f93ae99 721 Write( REG_LR_FIFOTXBASEADDR, 0 );
tmulrooney 23:273a2f93ae99 722 Write( REG_LR_FIFOADDRPTR, 0 );
tmulrooney 23:273a2f93ae99 723
tmulrooney 23:273a2f93ae99 724 // FIFO operations can not take place in Sleep mode
tmulrooney 23:273a2f93ae99 725 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
tmulrooney 23:273a2f93ae99 726 {
tmulrooney 23:273a2f93ae99 727 Standby( );
tmulrooney 23:273a2f93ae99 728 wait_ms( 1 );
tmulrooney 23:273a2f93ae99 729 }
tmulrooney 23:273a2f93ae99 730 // Write payload buffer
tmulrooney 23:273a2f93ae99 731 WriteFifo( buffer, size );
tmulrooney 23:273a2f93ae99 732 txTimeout = this->settings.LoRa.TxTimeout;
tmulrooney 23:273a2f93ae99 733 }
tmulrooney 23:273a2f93ae99 734 break;
tmulrooney 23:273a2f93ae99 735 }
tmulrooney 23:273a2f93ae99 736
tmulrooney 23:273a2f93ae99 737 Tx( txTimeout );
tmulrooney 23:273a2f93ae99 738 }
tmulrooney 23:273a2f93ae99 739
tmulrooney 23:273a2f93ae99 740 void SX1272::Sleep( void )
tmulrooney 23:273a2f93ae99 741 {
tmulrooney 23:273a2f93ae99 742 debug("Sleep\r\n");
tmulrooney 23:273a2f93ae99 743 txTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 744 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 745
tmulrooney 23:273a2f93ae99 746 SetOpMode( RF_OPMODE_SLEEP );
tmulrooney 23:273a2f93ae99 747 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 748 }
tmulrooney 23:273a2f93ae99 749
tmulrooney 23:273a2f93ae99 750 void SX1272::Standby( void )
tmulrooney 23:273a2f93ae99 751 {
tmulrooney 23:273a2f93ae99 752 debug("Standby\r\n");
tmulrooney 23:273a2f93ae99 753 txTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 754 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 755
tmulrooney 23:273a2f93ae99 756 SetOpMode( RF_OPMODE_STANDBY );
tmulrooney 23:273a2f93ae99 757 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 758 }
tmulrooney 23:273a2f93ae99 759
tmulrooney 23:273a2f93ae99 760 void SX1272::Rx( uint32_t timeout )
tmulrooney 23:273a2f93ae99 761 {
tmulrooney 23:273a2f93ae99 762 debug("Rx\r\n");
tmulrooney 23:273a2f93ae99 763 bool rxContinuous = false;
tmulrooney 23:273a2f93ae99 764
tmulrooney 23:273a2f93ae99 765 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 766 {
tmulrooney 23:273a2f93ae99 767 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 768 {
tmulrooney 23:273a2f93ae99 769 rxContinuous = this->settings.Fsk.RxContinuous;
tmulrooney 23:273a2f93ae99 770
tmulrooney 23:273a2f93ae99 771 // DIO0=PayloadReady
tmulrooney 23:273a2f93ae99 772 // DIO1=FifoLevel
tmulrooney 23:273a2f93ae99 773 // DIO2=SyncAddr
tmulrooney 23:273a2f93ae99 774 // DIO3=FifoEmpty
tmulrooney 23:273a2f93ae99 775 // DIO4=Preamble
tmulrooney 23:273a2f93ae99 776 // DIO5=ModeReady
tmulrooney 23:273a2f93ae99 777 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
tmulrooney 23:273a2f93ae99 778 RF_DIOMAPPING1_DIO2_MASK ) |
tmulrooney 23:273a2f93ae99 779 RF_DIOMAPPING1_DIO0_00 |
tmulrooney 23:273a2f93ae99 780 RF_DIOMAPPING1_DIO2_11 );
tmulrooney 23:273a2f93ae99 781
tmulrooney 23:273a2f93ae99 782 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
tmulrooney 23:273a2f93ae99 783 RF_DIOMAPPING2_MAP_MASK ) |
tmulrooney 23:273a2f93ae99 784 RF_DIOMAPPING2_DIO4_11 |
tmulrooney 23:273a2f93ae99 785 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
tmulrooney 23:273a2f93ae99 786
tmulrooney 23:273a2f93ae99 787 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
tmulrooney 23:273a2f93ae99 788
tmulrooney 23:273a2f93ae99 789 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:273a2f93ae99 790 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:273a2f93ae99 791 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:273a2f93ae99 792 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:273a2f93ae99 793 }
tmulrooney 23:273a2f93ae99 794 break;
tmulrooney 23:273a2f93ae99 795 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 796 {
tmulrooney 23:273a2f93ae99 797 if( this->settings.LoRa.IqInverted == true )
tmulrooney 23:273a2f93ae99 798 {
tmulrooney 23:273a2f93ae99 799 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
tmulrooney 23:273a2f93ae99 800 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
tmulrooney 23:273a2f93ae99 801 }
tmulrooney 23:273a2f93ae99 802 else
tmulrooney 23:273a2f93ae99 803 {
tmulrooney 23:273a2f93ae99 804 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
tmulrooney 23:273a2f93ae99 805 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
tmulrooney 23:273a2f93ae99 806 }
tmulrooney 23:273a2f93ae99 807
tmulrooney 23:273a2f93ae99 808
tmulrooney 23:273a2f93ae99 809 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
tmulrooney 23:273a2f93ae99 810 if( this->settings.LoRa.Bandwidth < 9 )
tmulrooney 23:273a2f93ae99 811 {
tmulrooney 23:273a2f93ae99 812 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
tmulrooney 23:273a2f93ae99 813 Write( REG_LR_TEST30, 0x00 );
tmulrooney 23:273a2f93ae99 814 switch( this->settings.LoRa.Bandwidth )
tmulrooney 23:273a2f93ae99 815 {
tmulrooney 23:273a2f93ae99 816 case 0: // 7.8 kHz
tmulrooney 23:273a2f93ae99 817 Write( REG_LR_TEST2F, 0x48 );
tmulrooney 23:273a2f93ae99 818 SetChannel(this->settings.Channel + 7.81e3 );
tmulrooney 23:273a2f93ae99 819 break;
tmulrooney 23:273a2f93ae99 820 case 1: // 10.4 kHz
tmulrooney 23:273a2f93ae99 821 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:273a2f93ae99 822 SetChannel(this->settings.Channel + 10.42e3 );
tmulrooney 23:273a2f93ae99 823 break;
tmulrooney 23:273a2f93ae99 824 case 2: // 15.6 kHz
tmulrooney 23:273a2f93ae99 825 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:273a2f93ae99 826 SetChannel(this->settings.Channel + 15.62e3 );
tmulrooney 23:273a2f93ae99 827 break;
tmulrooney 23:273a2f93ae99 828 case 3: // 20.8 kHz
tmulrooney 23:273a2f93ae99 829 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:273a2f93ae99 830 SetChannel(this->settings.Channel + 20.83e3 );
tmulrooney 23:273a2f93ae99 831 break;
tmulrooney 23:273a2f93ae99 832 case 4: // 31.2 kHz
tmulrooney 23:273a2f93ae99 833 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:273a2f93ae99 834 SetChannel(this->settings.Channel + 31.25e3 );
tmulrooney 23:273a2f93ae99 835 break;
tmulrooney 23:273a2f93ae99 836 case 5: // 41.4 kHz
tmulrooney 23:273a2f93ae99 837 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:273a2f93ae99 838 SetChannel(this->settings.Channel + 41.67e3 );
tmulrooney 23:273a2f93ae99 839 break;
tmulrooney 23:273a2f93ae99 840 case 6: // 62.5 kHz
tmulrooney 23:273a2f93ae99 841 Write( REG_LR_TEST2F, 0x40 );
tmulrooney 23:273a2f93ae99 842 break;
tmulrooney 23:273a2f93ae99 843 case 7: // 125 kHz
tmulrooney 23:273a2f93ae99 844 Write( REG_LR_TEST2F, 0x40 );
tmulrooney 23:273a2f93ae99 845 break;
tmulrooney 23:273a2f93ae99 846 case 8: // 250 kHz
tmulrooney 23:273a2f93ae99 847 Write( REG_LR_TEST2F, 0x40 );
tmulrooney 23:273a2f93ae99 848 break;
tmulrooney 23:273a2f93ae99 849 }
tmulrooney 23:273a2f93ae99 850 }
tmulrooney 23:273a2f93ae99 851 else
tmulrooney 23:273a2f93ae99 852 {
tmulrooney 23:273a2f93ae99 853 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
tmulrooney 23:273a2f93ae99 854 }
tmulrooney 23:273a2f93ae99 855
tmulrooney 23:273a2f93ae99 856 rxContinuous = this->settings.LoRa.RxContinuous;
tmulrooney 23:273a2f93ae99 857
tmulrooney 23:273a2f93ae99 858 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:273a2f93ae99 859 {
tmulrooney 23:273a2f93ae99 860 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:273a2f93ae99 861 //RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:273a2f93ae99 862 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:273a2f93ae99 863 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:273a2f93ae99 864 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:273a2f93ae99 865 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:273a2f93ae99 866 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:273a2f93ae99 867 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:273a2f93ae99 868
tmulrooney 23:273a2f93ae99 869 // DIO0=RxDone, DIO2=FhssChangeChannel
tmulrooney 23:273a2f93ae99 870 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
tmulrooney 23:273a2f93ae99 871 }
tmulrooney 23:273a2f93ae99 872 else
tmulrooney 23:273a2f93ae99 873 {
tmulrooney 23:273a2f93ae99 874 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:273a2f93ae99 875 //RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:273a2f93ae99 876 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:273a2f93ae99 877 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:273a2f93ae99 878 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:273a2f93ae99 879 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:273a2f93ae99 880 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:273a2f93ae99 881 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:273a2f93ae99 882
tmulrooney 23:273a2f93ae99 883 // DIO0=RxDone
tmulrooney 23:273a2f93ae99 884 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
tmulrooney 23:273a2f93ae99 885 }
tmulrooney 23:273a2f93ae99 886 Write( REG_LR_FIFORXBASEADDR, 0 );
tmulrooney 23:273a2f93ae99 887 Write( REG_LR_FIFOADDRPTR, 0 );
tmulrooney 23:273a2f93ae99 888 }
tmulrooney 23:273a2f93ae99 889 break;
tmulrooney 23:273a2f93ae99 890 }
tmulrooney 23:273a2f93ae99 891
tmulrooney 23:273a2f93ae99 892 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
tmulrooney 23:273a2f93ae99 893
tmulrooney 23:273a2f93ae99 894 this->settings.State = RF_RX_RUNNING;
tmulrooney 23:273a2f93ae99 895 if( timeout != 0 )
tmulrooney 23:273a2f93ae99 896 {
tmulrooney 23:273a2f93ae99 897 rxTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
tmulrooney 23:273a2f93ae99 898 }
tmulrooney 23:273a2f93ae99 899
tmulrooney 23:273a2f93ae99 900 if( this->settings.Modem == MODEM_FSK )
tmulrooney 23:273a2f93ae99 901 {
tmulrooney 23:273a2f93ae99 902 SetOpMode( RF_OPMODE_RECEIVER );
tmulrooney 23:273a2f93ae99 903
tmulrooney 23:273a2f93ae99 904 if( rxContinuous == false )
tmulrooney 23:273a2f93ae99 905 {
tmulrooney 23:273a2f93ae99 906 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:273a2f93ae99 907 ( ( Read( REG_SYNCCONFIG ) &
tmulrooney 23:273a2f93ae99 908 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
tmulrooney 23:273a2f93ae99 909 1.0 ) + 10.0 ) /
tmulrooney 23:273a2f93ae99 910 ( double )this->settings.Fsk.Datarate ) * 1e6 );
tmulrooney 23:273a2f93ae99 911 }
tmulrooney 23:273a2f93ae99 912 }
tmulrooney 23:273a2f93ae99 913 else
tmulrooney 23:273a2f93ae99 914 {
tmulrooney 23:273a2f93ae99 915 if( rxContinuous == true )
tmulrooney 23:273a2f93ae99 916 {
tmulrooney 23:273a2f93ae99 917 SetOpMode( RFLR_OPMODE_RECEIVER );
tmulrooney 23:273a2f93ae99 918 }
tmulrooney 23:273a2f93ae99 919 else
tmulrooney 23:273a2f93ae99 920 {
tmulrooney 23:273a2f93ae99 921 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
tmulrooney 23:273a2f93ae99 922 }
tmulrooney 23:273a2f93ae99 923 }
tmulrooney 23:273a2f93ae99 924 }
tmulrooney 23:273a2f93ae99 925
tmulrooney 23:273a2f93ae99 926 void SX1272::Tx( uint32_t timeout )
tmulrooney 23:273a2f93ae99 927 {
tmulrooney 23:273a2f93ae99 928 debug("Tx\r\n");
tmulrooney 23:273a2f93ae99 929
tmulrooney 23:273a2f93ae99 930 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 931 {
tmulrooney 23:273a2f93ae99 932 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 933 {
tmulrooney 23:273a2f93ae99 934 // DIO0=PacketSent
tmulrooney 23:273a2f93ae99 935 // DIO1=FifoLevel
tmulrooney 23:273a2f93ae99 936 // DIO2=FifoFull
tmulrooney 23:273a2f93ae99 937 // DIO3=FifoEmpty
tmulrooney 23:273a2f93ae99 938 // DIO4=LowBat
tmulrooney 23:273a2f93ae99 939 // DIO5=ModeReady
tmulrooney 23:273a2f93ae99 940 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
tmulrooney 23:273a2f93ae99 941 RF_DIOMAPPING1_DIO2_MASK ) );
tmulrooney 23:273a2f93ae99 942
tmulrooney 23:273a2f93ae99 943 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
tmulrooney 23:273a2f93ae99 944 RF_DIOMAPPING2_MAP_MASK ) );
tmulrooney 23:273a2f93ae99 945 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
tmulrooney 23:273a2f93ae99 946 }
tmulrooney 23:273a2f93ae99 947 break;
tmulrooney 23:273a2f93ae99 948 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 949 {
tmulrooney 23:273a2f93ae99 950 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:273a2f93ae99 951 {
tmulrooney 23:273a2f93ae99 952 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:273a2f93ae99 953 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:273a2f93ae99 954 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:273a2f93ae99 955 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:273a2f93ae99 956 //RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:273a2f93ae99 957 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:273a2f93ae99 958 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:273a2f93ae99 959 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:273a2f93ae99 960
tmulrooney 23:273a2f93ae99 961 // DIO0=TxDone, DIO2=FhssChangeChannel
tmulrooney 23:273a2f93ae99 962 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
tmulrooney 23:273a2f93ae99 963 }
tmulrooney 23:273a2f93ae99 964 else
tmulrooney 23:273a2f93ae99 965 {
tmulrooney 23:273a2f93ae99 966 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:273a2f93ae99 967 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:273a2f93ae99 968 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:273a2f93ae99 969 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:273a2f93ae99 970 //RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:273a2f93ae99 971 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:273a2f93ae99 972 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:273a2f93ae99 973 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:273a2f93ae99 974
tmulrooney 23:273a2f93ae99 975 // DIO0=TxDone
tmulrooney 23:273a2f93ae99 976 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
tmulrooney 23:273a2f93ae99 977 }
tmulrooney 23:273a2f93ae99 978 }
tmulrooney 23:273a2f93ae99 979 break;
tmulrooney 23:273a2f93ae99 980 }
tmulrooney 23:273a2f93ae99 981
tmulrooney 23:273a2f93ae99 982 this->settings.State = RF_TX_RUNNING;
tmulrooney 23:273a2f93ae99 983 txTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
tmulrooney 23:273a2f93ae99 984 SetOpMode( RF_OPMODE_TRANSMITTER );
tmulrooney 23:273a2f93ae99 985 }
tmulrooney 23:273a2f93ae99 986
tmulrooney 23:273a2f93ae99 987 void SX1272::StartCad( void )
tmulrooney 23:273a2f93ae99 988 {
tmulrooney 23:273a2f93ae99 989 debug("StartCad\r\n");
tmulrooney 23:273a2f93ae99 990 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 991 {
tmulrooney 23:273a2f93ae99 992 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 993 {
tmulrooney 23:273a2f93ae99 994
tmulrooney 23:273a2f93ae99 995 }
tmulrooney 23:273a2f93ae99 996 break;
tmulrooney 23:273a2f93ae99 997 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 998 {
tmulrooney 23:273a2f93ae99 999 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:273a2f93ae99 1000 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:273a2f93ae99 1001 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:273a2f93ae99 1002 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:273a2f93ae99 1003 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:273a2f93ae99 1004 //RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:273a2f93ae99 1005 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
tmulrooney 23:273a2f93ae99 1006 //RFLR_IRQFLAGS_CADDETECTED
tmulrooney 23:273a2f93ae99 1007 );
tmulrooney 23:273a2f93ae99 1008
tmulrooney 23:273a2f93ae99 1009 // DIO3=CADDone
tmulrooney 23:273a2f93ae99 1010 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
tmulrooney 23:273a2f93ae99 1011
tmulrooney 23:273a2f93ae99 1012 this->settings.State = RF_CAD;
tmulrooney 23:273a2f93ae99 1013 SetOpMode( RFLR_OPMODE_CAD );
tmulrooney 23:273a2f93ae99 1014 }
tmulrooney 23:273a2f93ae99 1015 break;
tmulrooney 23:273a2f93ae99 1016 default:
tmulrooney 23:273a2f93ae99 1017 break;
tmulrooney 23:273a2f93ae99 1018 }
tmulrooney 23:273a2f93ae99 1019 }
tmulrooney 23:273a2f93ae99 1020
tmulrooney 23:273a2f93ae99 1021 int16_t SX1272::GetRssi( RadioModems_t modem )
tmulrooney 23:273a2f93ae99 1022 {
tmulrooney 23:273a2f93ae99 1023 debug("GetRssi\r\n");
tmulrooney 23:273a2f93ae99 1024 int16_t rssi = 0;
tmulrooney 23:273a2f93ae99 1025
tmulrooney 23:273a2f93ae99 1026 switch( modem )
tmulrooney 23:273a2f93ae99 1027 {
tmulrooney 23:273a2f93ae99 1028 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1029 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
tmulrooney 23:273a2f93ae99 1030 break;
tmulrooney 23:273a2f93ae99 1031 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1032 if( this->settings.Channel > RF_MID_BAND_THRESH )
tmulrooney 23:273a2f93ae99 1033 {
tmulrooney 23:273a2f93ae99 1034 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
tmulrooney 23:273a2f93ae99 1035 }
tmulrooney 23:273a2f93ae99 1036 else
tmulrooney 23:273a2f93ae99 1037 {
tmulrooney 23:273a2f93ae99 1038 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
tmulrooney 23:273a2f93ae99 1039 }
tmulrooney 23:273a2f93ae99 1040 break;
tmulrooney 23:273a2f93ae99 1041 default:
tmulrooney 23:273a2f93ae99 1042 rssi = -1;
tmulrooney 23:273a2f93ae99 1043 break;
tmulrooney 23:273a2f93ae99 1044 }
tmulrooney 23:273a2f93ae99 1045 return rssi;
tmulrooney 23:273a2f93ae99 1046 }
tmulrooney 23:273a2f93ae99 1047
tmulrooney 23:273a2f93ae99 1048 void SX1272::SetOpMode( uint8_t opMode )
tmulrooney 23:273a2f93ae99 1049 {
tmulrooney 23:273a2f93ae99 1050 debug("SetOpMode %02X\r\n",opMode);
tmulrooney 23:273a2f93ae99 1051 if( opMode != previousOpMode )
tmulrooney 23:273a2f93ae99 1052 {
tmulrooney 23:273a2f93ae99 1053 previousOpMode = opMode;
tmulrooney 23:273a2f93ae99 1054 if( opMode == RF_OPMODE_SLEEP )
tmulrooney 23:273a2f93ae99 1055 {
tmulrooney 23:273a2f93ae99 1056 SetAntSwLowPower( true );
tmulrooney 23:273a2f93ae99 1057 }
tmulrooney 23:273a2f93ae99 1058 else
tmulrooney 23:273a2f93ae99 1059 {
tmulrooney 23:273a2f93ae99 1060 SetAntSwLowPower( false );
tmulrooney 23:273a2f93ae99 1061 if( opMode == RF_OPMODE_TRANSMITTER )
tmulrooney 23:273a2f93ae99 1062 {
tmulrooney 23:273a2f93ae99 1063 SetAntSw( 1 );
tmulrooney 23:273a2f93ae99 1064 }
tmulrooney 23:273a2f93ae99 1065 else
tmulrooney 23:273a2f93ae99 1066 {
tmulrooney 23:273a2f93ae99 1067 SetAntSw( 0 );
tmulrooney 23:273a2f93ae99 1068 }
tmulrooney 23:273a2f93ae99 1069 }
tmulrooney 23:273a2f93ae99 1070 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
tmulrooney 23:273a2f93ae99 1071 }
tmulrooney 23:273a2f93ae99 1072 }
tmulrooney 23:273a2f93ae99 1073
tmulrooney 23:273a2f93ae99 1074 void SX1272::SetModem( RadioModems_t modem )
tmulrooney 23:273a2f93ae99 1075 {
tmulrooney 23:273a2f93ae99 1076 debug("SetModem %d\r\n",modem);
tmulrooney 23:273a2f93ae99 1077 if( this->settings.Modem == modem )
tmulrooney 23:273a2f93ae99 1078 {
tmulrooney 23:273a2f93ae99 1079 return;
tmulrooney 23:273a2f93ae99 1080 }
tmulrooney 23:273a2f93ae99 1081
tmulrooney 23:273a2f93ae99 1082 this->settings.Modem = modem;
tmulrooney 23:273a2f93ae99 1083 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1084 {
tmulrooney 23:273a2f93ae99 1085 default:
tmulrooney 23:273a2f93ae99 1086 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1087 SetOpMode( RF_OPMODE_SLEEP );
tmulrooney 23:273a2f93ae99 1088 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
tmulrooney 23:273a2f93ae99 1089
tmulrooney 23:273a2f93ae99 1090 Write( REG_DIOMAPPING1, 0x00 );
tmulrooney 23:273a2f93ae99 1091 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
tmulrooney 23:273a2f93ae99 1092 break;
tmulrooney 23:273a2f93ae99 1093 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1094 SetOpMode( RF_OPMODE_SLEEP );
tmulrooney 23:273a2f93ae99 1095 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
tmulrooney 23:273a2f93ae99 1096
tmulrooney 23:273a2f93ae99 1097 Write( REG_DIOMAPPING1, 0x00 );
tmulrooney 23:273a2f93ae99 1098 Write( REG_DIOMAPPING2, 0x00 );
tmulrooney 23:273a2f93ae99 1099 break;
tmulrooney 23:273a2f93ae99 1100 }
tmulrooney 23:273a2f93ae99 1101 }
tmulrooney 23:273a2f93ae99 1102
tmulrooney 23:273a2f93ae99 1103 void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
tmulrooney 23:273a2f93ae99 1104 {
tmulrooney 23:273a2f93ae99 1105 debug("SetMaxPayloadLength\r\n");
tmulrooney 23:273a2f93ae99 1106 this->SetModem( modem );
tmulrooney 23:273a2f93ae99 1107
tmulrooney 23:273a2f93ae99 1108 switch( modem )
tmulrooney 23:273a2f93ae99 1109 {
tmulrooney 23:273a2f93ae99 1110 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1111 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:273a2f93ae99 1112 {
tmulrooney 23:273a2f93ae99 1113 this->Write( REG_PAYLOADLENGTH, max );
tmulrooney 23:273a2f93ae99 1114 }
tmulrooney 23:273a2f93ae99 1115 break;
tmulrooney 23:273a2f93ae99 1116 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1117 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
tmulrooney 23:273a2f93ae99 1118 break;
tmulrooney 23:273a2f93ae99 1119 }
tmulrooney 23:273a2f93ae99 1120 }
tmulrooney 23:273a2f93ae99 1121
tmulrooney 23:273a2f93ae99 1122 void SX1272::OnTimeoutIrq( void )
tmulrooney 23:273a2f93ae99 1123 {
tmulrooney 23:273a2f93ae99 1124 debug("OnTimeoutIrq\r\n");
tmulrooney 23:273a2f93ae99 1125 switch( this->settings.State )
tmulrooney 23:273a2f93ae99 1126 {
tmulrooney 23:273a2f93ae99 1127 case RF_RX_RUNNING:
tmulrooney 23:273a2f93ae99 1128 if( this->settings.Modem == MODEM_FSK )
tmulrooney 23:273a2f93ae99 1129 {
tmulrooney 23:273a2f93ae99 1130 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:273a2f93ae99 1131 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:273a2f93ae99 1132 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:273a2f93ae99 1133 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:273a2f93ae99 1134
tmulrooney 23:273a2f93ae99 1135 // Clear Irqs
tmulrooney 23:273a2f93ae99 1136 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
tmulrooney 23:273a2f93ae99 1137 RF_IRQFLAGS1_PREAMBLEDETECT |
tmulrooney 23:273a2f93ae99 1138 RF_IRQFLAGS1_SYNCADDRESSMATCH );
tmulrooney 23:273a2f93ae99 1139 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
tmulrooney 23:273a2f93ae99 1140
tmulrooney 23:273a2f93ae99 1141 if( this->settings.Fsk.RxContinuous == true )
tmulrooney 23:273a2f93ae99 1142 {
tmulrooney 23:273a2f93ae99 1143 // Continuous mode restart Rx chain
tmulrooney 23:273a2f93ae99 1144 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
tmulrooney 23:273a2f93ae99 1145 }
tmulrooney 23:273a2f93ae99 1146 else
tmulrooney 23:273a2f93ae99 1147 {
tmulrooney 23:273a2f93ae99 1148 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1149 rxTimeoutSyncWord.detach( );
tmulrooney 23:273a2f93ae99 1150 }
tmulrooney 23:273a2f93ae99 1151 }
tmulrooney 23:273a2f93ae99 1152 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
tmulrooney 23:273a2f93ae99 1153 {
tmulrooney 23:273a2f93ae99 1154 this->RadioEvents->RxTimeout( );
tmulrooney 23:273a2f93ae99 1155 }
tmulrooney 23:273a2f93ae99 1156 break;
tmulrooney 23:273a2f93ae99 1157 case RF_TX_RUNNING:
tmulrooney 23:273a2f93ae99 1158 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1159 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
tmulrooney 23:273a2f93ae99 1160 {
tmulrooney 23:273a2f93ae99 1161 this->RadioEvents->TxTimeout( );
tmulrooney 23:273a2f93ae99 1162 }
tmulrooney 23:273a2f93ae99 1163 break;
tmulrooney 23:273a2f93ae99 1164 default:
tmulrooney 23:273a2f93ae99 1165 break;
tmulrooney 23:273a2f93ae99 1166 }
tmulrooney 23:273a2f93ae99 1167 }
tmulrooney 23:273a2f93ae99 1168
tmulrooney 23:273a2f93ae99 1169 void SX1272::OnDio0Irq( void )
tmulrooney 23:273a2f93ae99 1170 {
tmulrooney 23:273a2f93ae99 1171 debug("OnDio0Irq\r\n");
tmulrooney 23:273a2f93ae99 1172 volatile uint8_t irqFlags = 0;
tmulrooney 23:273a2f93ae99 1173
tmulrooney 23:273a2f93ae99 1174 switch( this->settings.State )
tmulrooney 23:273a2f93ae99 1175 {
tmulrooney 23:273a2f93ae99 1176 case RF_RX_RUNNING:
tmulrooney 23:273a2f93ae99 1177 //TimerStop( &RxTimeoutTimer );
tmulrooney 23:273a2f93ae99 1178 // RxDone interrupt
tmulrooney 23:273a2f93ae99 1179 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1180 {
tmulrooney 23:273a2f93ae99 1181 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1182 if( this->settings.Fsk.CrcOn == true )
tmulrooney 23:273a2f93ae99 1183 {
tmulrooney 23:273a2f93ae99 1184 irqFlags = Read( REG_IRQFLAGS2 );
tmulrooney 23:273a2f93ae99 1185 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
tmulrooney 23:273a2f93ae99 1186 {
tmulrooney 23:273a2f93ae99 1187 // Clear Irqs
tmulrooney 23:273a2f93ae99 1188 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
tmulrooney 23:273a2f93ae99 1189 RF_IRQFLAGS1_PREAMBLEDETECT |
tmulrooney 23:273a2f93ae99 1190 RF_IRQFLAGS1_SYNCADDRESSMATCH );
tmulrooney 23:273a2f93ae99 1191 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
tmulrooney 23:273a2f93ae99 1192
tmulrooney 23:273a2f93ae99 1193 if( this->settings.Fsk.RxContinuous == false )
tmulrooney 23:273a2f93ae99 1194 {
tmulrooney 23:273a2f93ae99 1195 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1196 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:273a2f93ae99 1197 ( ( Read( REG_SYNCCONFIG ) &
tmulrooney 23:273a2f93ae99 1198 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
tmulrooney 23:273a2f93ae99 1199 1.0 ) + 10.0 ) /
tmulrooney 23:273a2f93ae99 1200 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
tmulrooney 23:273a2f93ae99 1201 }
tmulrooney 23:273a2f93ae99 1202 else
tmulrooney 23:273a2f93ae99 1203 {
tmulrooney 23:273a2f93ae99 1204 // Continuous mode restart Rx chain
tmulrooney 23:273a2f93ae99 1205 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
tmulrooney 23:273a2f93ae99 1206 }
tmulrooney 23:273a2f93ae99 1207 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 1208
tmulrooney 23:273a2f93ae99 1209 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
tmulrooney 23:273a2f93ae99 1210 {
tmulrooney 23:273a2f93ae99 1211 this->RadioEvents->RxError( );
tmulrooney 23:273a2f93ae99 1212 }
tmulrooney 23:273a2f93ae99 1213 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:273a2f93ae99 1214 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:273a2f93ae99 1215 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:273a2f93ae99 1216 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:273a2f93ae99 1217 break;
tmulrooney 23:273a2f93ae99 1218 }
tmulrooney 23:273a2f93ae99 1219 }
tmulrooney 23:273a2f93ae99 1220
tmulrooney 23:273a2f93ae99 1221 // Read received packet size
tmulrooney 23:273a2f93ae99 1222 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
tmulrooney 23:273a2f93ae99 1223 {
tmulrooney 23:273a2f93ae99 1224 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:273a2f93ae99 1225 {
tmulrooney 23:273a2f93ae99 1226 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
tmulrooney 23:273a2f93ae99 1227 }
tmulrooney 23:273a2f93ae99 1228 else
tmulrooney 23:273a2f93ae99 1229 {
tmulrooney 23:273a2f93ae99 1230 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
tmulrooney 23:273a2f93ae99 1231 }
tmulrooney 23:273a2f93ae99 1232 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1233 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1234 }
tmulrooney 23:273a2f93ae99 1235 else
tmulrooney 23:273a2f93ae99 1236 {
tmulrooney 23:273a2f93ae99 1237 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1238 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1239 }
tmulrooney 23:273a2f93ae99 1240
tmulrooney 23:273a2f93ae99 1241 if( this->settings.Fsk.RxContinuous == false )
tmulrooney 23:273a2f93ae99 1242 {
tmulrooney 23:273a2f93ae99 1243 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1244 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:273a2f93ae99 1245 ( ( Read( REG_SYNCCONFIG ) &
tmulrooney 23:273a2f93ae99 1246 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
tmulrooney 23:273a2f93ae99 1247 1.0 ) + 10.0 ) /
tmulrooney 23:273a2f93ae99 1248 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
tmulrooney 23:273a2f93ae99 1249 }
tmulrooney 23:273a2f93ae99 1250 else
tmulrooney 23:273a2f93ae99 1251 {
tmulrooney 23:273a2f93ae99 1252 // Continuous mode restart Rx chain
tmulrooney 23:273a2f93ae99 1253 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
tmulrooney 23:273a2f93ae99 1254 }
tmulrooney 23:273a2f93ae99 1255 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 1256
tmulrooney 23:273a2f93ae99 1257 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
tmulrooney 23:273a2f93ae99 1258 {
tmulrooney 23:273a2f93ae99 1259 this->RadioEvents->RxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
tmulrooney 23:273a2f93ae99 1260 }
tmulrooney 23:273a2f93ae99 1261 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:273a2f93ae99 1262 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:273a2f93ae99 1263 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:273a2f93ae99 1264 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:273a2f93ae99 1265 break;
tmulrooney 23:273a2f93ae99 1266 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1267 {
tmulrooney 23:273a2f93ae99 1268 int8_t snr = 0;
tmulrooney 23:273a2f93ae99 1269
tmulrooney 23:273a2f93ae99 1270 // Clear Irq
tmulrooney 23:273a2f93ae99 1271 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
tmulrooney 23:273a2f93ae99 1272
tmulrooney 23:273a2f93ae99 1273 irqFlags = Read( REG_LR_IRQFLAGS );
tmulrooney 23:273a2f93ae99 1274 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
tmulrooney 23:273a2f93ae99 1275 {
tmulrooney 23:273a2f93ae99 1276 // Clear Irq
tmulrooney 23:273a2f93ae99 1277 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
tmulrooney 23:273a2f93ae99 1278
tmulrooney 23:273a2f93ae99 1279 if( this->settings.LoRa.RxContinuous == false )
tmulrooney 23:273a2f93ae99 1280 {
tmulrooney 23:273a2f93ae99 1281 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1282 }
tmulrooney 23:273a2f93ae99 1283 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 1284
tmulrooney 23:273a2f93ae99 1285 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
tmulrooney 23:273a2f93ae99 1286 {
tmulrooney 23:273a2f93ae99 1287 this->RadioEvents->RxError( );
tmulrooney 23:273a2f93ae99 1288 }
tmulrooney 23:273a2f93ae99 1289 break;
tmulrooney 23:273a2f93ae99 1290 }
tmulrooney 23:273a2f93ae99 1291
tmulrooney 23:273a2f93ae99 1292 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
tmulrooney 23:273a2f93ae99 1293 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
tmulrooney 23:273a2f93ae99 1294 {
tmulrooney 23:273a2f93ae99 1295 // Invert and divide by 4
tmulrooney 23:273a2f93ae99 1296 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
tmulrooney 23:273a2f93ae99 1297 snr = -snr;
tmulrooney 23:273a2f93ae99 1298 }
tmulrooney 23:273a2f93ae99 1299 else
tmulrooney 23:273a2f93ae99 1300 {
tmulrooney 23:273a2f93ae99 1301 // Divide by 4
tmulrooney 23:273a2f93ae99 1302 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
tmulrooney 23:273a2f93ae99 1303 }
tmulrooney 23:273a2f93ae99 1304
tmulrooney 23:273a2f93ae99 1305 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
tmulrooney 23:273a2f93ae99 1306 if( snr < 0 )
tmulrooney 23:273a2f93ae99 1307 {
tmulrooney 23:273a2f93ae99 1308 if( this->settings.Channel > RF_MID_BAND_THRESH )
tmulrooney 23:273a2f93ae99 1309 {
tmulrooney 23:273a2f93ae99 1310 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
tmulrooney 23:273a2f93ae99 1311 snr;
tmulrooney 23:273a2f93ae99 1312 }
tmulrooney 23:273a2f93ae99 1313 else
tmulrooney 23:273a2f93ae99 1314 {
tmulrooney 23:273a2f93ae99 1315 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
tmulrooney 23:273a2f93ae99 1316 snr;
tmulrooney 23:273a2f93ae99 1317 }
tmulrooney 23:273a2f93ae99 1318 }
tmulrooney 23:273a2f93ae99 1319 else
tmulrooney 23:273a2f93ae99 1320 {
tmulrooney 23:273a2f93ae99 1321 if( this->settings.Channel > RF_MID_BAND_THRESH )
tmulrooney 23:273a2f93ae99 1322 {
tmulrooney 23:273a2f93ae99 1323 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
tmulrooney 23:273a2f93ae99 1324 }
tmulrooney 23:273a2f93ae99 1325 else
tmulrooney 23:273a2f93ae99 1326 {
tmulrooney 23:273a2f93ae99 1327 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
tmulrooney 23:273a2f93ae99 1328 }
tmulrooney 23:273a2f93ae99 1329 }
tmulrooney 23:273a2f93ae99 1330
tmulrooney 23:273a2f93ae99 1331 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
tmulrooney 23:273a2f93ae99 1332 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
tmulrooney 23:273a2f93ae99 1333
tmulrooney 23:273a2f93ae99 1334 if( this->settings.LoRa.RxContinuous == false )
tmulrooney 23:273a2f93ae99 1335 {
tmulrooney 23:273a2f93ae99 1336 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1337 }
tmulrooney 23:273a2f93ae99 1338 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 1339
tmulrooney 23:273a2f93ae99 1340 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
tmulrooney 23:273a2f93ae99 1341 {
tmulrooney 23:273a2f93ae99 1342 this->RadioEvents->RxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
tmulrooney 23:273a2f93ae99 1343 }
tmulrooney 23:273a2f93ae99 1344 }
tmulrooney 23:273a2f93ae99 1345 break;
tmulrooney 23:273a2f93ae99 1346 default:
tmulrooney 23:273a2f93ae99 1347 break;
tmulrooney 23:273a2f93ae99 1348 }
tmulrooney 23:273a2f93ae99 1349 break;
tmulrooney 23:273a2f93ae99 1350 case RF_TX_RUNNING:
tmulrooney 23:273a2f93ae99 1351 txTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 1352 // TxDone interrupt
tmulrooney 23:273a2f93ae99 1353 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1354 {
tmulrooney 23:273a2f93ae99 1355 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1356 // Clear Irq
tmulrooney 23:273a2f93ae99 1357 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
tmulrooney 23:273a2f93ae99 1358 // Intentional fall through
tmulrooney 23:273a2f93ae99 1359 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1360 default:
tmulrooney 23:273a2f93ae99 1361 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1362 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
tmulrooney 23:273a2f93ae99 1363 {
tmulrooney 23:273a2f93ae99 1364 this->RadioEvents->TxDone( );
tmulrooney 23:273a2f93ae99 1365 }
tmulrooney 23:273a2f93ae99 1366 break;
tmulrooney 23:273a2f93ae99 1367 }
tmulrooney 23:273a2f93ae99 1368 break;
tmulrooney 23:273a2f93ae99 1369 default:
tmulrooney 23:273a2f93ae99 1370 break;
tmulrooney 23:273a2f93ae99 1371 }
tmulrooney 23:273a2f93ae99 1372 }
tmulrooney 23:273a2f93ae99 1373
tmulrooney 23:273a2f93ae99 1374 void SX1272::OnDio1Irq( void )
tmulrooney 23:273a2f93ae99 1375 {
tmulrooney 23:273a2f93ae99 1376 debug("OnDio1Irq\r\n");
tmulrooney 23:273a2f93ae99 1377 switch( this->settings.State )
tmulrooney 23:273a2f93ae99 1378 {
tmulrooney 23:273a2f93ae99 1379 case RF_RX_RUNNING:
tmulrooney 23:273a2f93ae99 1380 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1381 {
tmulrooney 23:273a2f93ae99 1382 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1383 // FifoLevel interrupt
tmulrooney 23:273a2f93ae99 1384 // Read received packet size
tmulrooney 23:273a2f93ae99 1385 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
tmulrooney 23:273a2f93ae99 1386 {
tmulrooney 23:273a2f93ae99 1387 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:273a2f93ae99 1388 {
tmulrooney 23:273a2f93ae99 1389 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
tmulrooney 23:273a2f93ae99 1390 }
tmulrooney 23:273a2f93ae99 1391 else
tmulrooney 23:273a2f93ae99 1392 {
tmulrooney 23:273a2f93ae99 1393 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
tmulrooney 23:273a2f93ae99 1394 }
tmulrooney 23:273a2f93ae99 1395 }
tmulrooney 23:273a2f93ae99 1396
tmulrooney 23:273a2f93ae99 1397 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
tmulrooney 23:273a2f93ae99 1398 {
tmulrooney 23:273a2f93ae99 1399 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
tmulrooney 23:273a2f93ae99 1400 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
tmulrooney 23:273a2f93ae99 1401 }
tmulrooney 23:273a2f93ae99 1402 else
tmulrooney 23:273a2f93ae99 1403 {
tmulrooney 23:273a2f93ae99 1404 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1405 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1406 }
tmulrooney 23:273a2f93ae99 1407 break;
tmulrooney 23:273a2f93ae99 1408 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1409 // Sync time out
tmulrooney 23:273a2f93ae99 1410 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 1411 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1412 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
tmulrooney 23:273a2f93ae99 1413 {
tmulrooney 23:273a2f93ae99 1414 this->RadioEvents->RxTimeout( );
tmulrooney 23:273a2f93ae99 1415 }
tmulrooney 23:273a2f93ae99 1416 break;
tmulrooney 23:273a2f93ae99 1417 default:
tmulrooney 23:273a2f93ae99 1418 break;
tmulrooney 23:273a2f93ae99 1419 }
tmulrooney 23:273a2f93ae99 1420 break;
tmulrooney 23:273a2f93ae99 1421 case RF_TX_RUNNING:
tmulrooney 23:273a2f93ae99 1422 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1423 {
tmulrooney 23:273a2f93ae99 1424 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1425 // FifoLevel interrupt
tmulrooney 23:273a2f93ae99 1426 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
tmulrooney 23:273a2f93ae99 1427 {
tmulrooney 23:273a2f93ae99 1428 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
tmulrooney 23:273a2f93ae99 1429 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
tmulrooney 23:273a2f93ae99 1430 }
tmulrooney 23:273a2f93ae99 1431 else
tmulrooney 23:273a2f93ae99 1432 {
tmulrooney 23:273a2f93ae99 1433 // Write the last chunk of data
tmulrooney 23:273a2f93ae99 1434 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1435 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
tmulrooney 23:273a2f93ae99 1436 }
tmulrooney 23:273a2f93ae99 1437 break;
tmulrooney 23:273a2f93ae99 1438 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1439 break;
tmulrooney 23:273a2f93ae99 1440 default:
tmulrooney 23:273a2f93ae99 1441 break;
tmulrooney 23:273a2f93ae99 1442 }
tmulrooney 23:273a2f93ae99 1443 break;
tmulrooney 23:273a2f93ae99 1444 default:
tmulrooney 23:273a2f93ae99 1445 break;
tmulrooney 23:273a2f93ae99 1446 }
tmulrooney 23:273a2f93ae99 1447 }
tmulrooney 23:273a2f93ae99 1448
tmulrooney 23:273a2f93ae99 1449 void SX1272::OnDio2Irq( void )
tmulrooney 23:273a2f93ae99 1450 {
tmulrooney 23:273a2f93ae99 1451 debug("OnDio2Irq\r\n");
tmulrooney 23:273a2f93ae99 1452 switch( this->settings.State )
tmulrooney 23:273a2f93ae99 1453 {
tmulrooney 23:273a2f93ae99 1454 case RF_RX_RUNNING:
tmulrooney 23:273a2f93ae99 1455 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1456 {
tmulrooney 23:273a2f93ae99 1457 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1458 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
tmulrooney 23:273a2f93ae99 1459 {
tmulrooney 23:273a2f93ae99 1460 rxTimeoutSyncWord.detach( );
tmulrooney 23:273a2f93ae99 1461
tmulrooney 23:273a2f93ae99 1462 this->settings.FskPacketHandler.SyncWordDetected = true;
tmulrooney 23:273a2f93ae99 1463
tmulrooney 23:273a2f93ae99 1464 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
tmulrooney 23:273a2f93ae99 1465
tmulrooney 23:273a2f93ae99 1466 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
tmulrooney 23:273a2f93ae99 1467 ( uint16_t )Read( REG_AFCLSB ) ) *
tmulrooney 23:273a2f93ae99 1468 ( double )FREQ_STEP;
tmulrooney 23:273a2f93ae99 1469 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
tmulrooney 23:273a2f93ae99 1470 }
tmulrooney 23:273a2f93ae99 1471 break;
tmulrooney 23:273a2f93ae99 1472 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1473 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:273a2f93ae99 1474 {
tmulrooney 23:273a2f93ae99 1475 // Clear Irq
tmulrooney 23:273a2f93ae99 1476 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
tmulrooney 23:273a2f93ae99 1477
tmulrooney 23:273a2f93ae99 1478 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
tmulrooney 23:273a2f93ae99 1479 {
tmulrooney 23:273a2f93ae99 1480 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
tmulrooney 23:273a2f93ae99 1481 }
tmulrooney 23:273a2f93ae99 1482 }
tmulrooney 23:273a2f93ae99 1483 break;
tmulrooney 23:273a2f93ae99 1484 default:
tmulrooney 23:273a2f93ae99 1485 break;
tmulrooney 23:273a2f93ae99 1486 }
tmulrooney 23:273a2f93ae99 1487 break;
tmulrooney 23:273a2f93ae99 1488 case RF_TX_RUNNING:
tmulrooney 23:273a2f93ae99 1489 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1490 {
tmulrooney 23:273a2f93ae99 1491 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1492 break;
tmulrooney 23:273a2f93ae99 1493 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1494 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:273a2f93ae99 1495 {
tmulrooney 23:273a2f93ae99 1496 // Clear Irq
tmulrooney 23:273a2f93ae99 1497 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
tmulrooney 23:273a2f93ae99 1498
tmulrooney 23:273a2f93ae99 1499 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
tmulrooney 23:273a2f93ae99 1500 {
tmulrooney 23:273a2f93ae99 1501 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
tmulrooney 23:273a2f93ae99 1502 }
tmulrooney 23:273a2f93ae99 1503 }
tmulrooney 23:273a2f93ae99 1504 break;
tmulrooney 23:273a2f93ae99 1505 default:
tmulrooney 23:273a2f93ae99 1506 break;
tmulrooney 23:273a2f93ae99 1507 }
tmulrooney 23:273a2f93ae99 1508 break;
tmulrooney 23:273a2f93ae99 1509 default:
tmulrooney 23:273a2f93ae99 1510 break;
tmulrooney 23:273a2f93ae99 1511 }
tmulrooney 23:273a2f93ae99 1512 }
tmulrooney 23:273a2f93ae99 1513
tmulrooney 23:273a2f93ae99 1514 void SX1272::OnDio3Irq( void )
tmulrooney 23:273a2f93ae99 1515 {
tmulrooney 23:273a2f93ae99 1516 debug("OnDio3Irq\r\n");
tmulrooney 23:273a2f93ae99 1517 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1518 {
tmulrooney 23:273a2f93ae99 1519 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1520 break;
tmulrooney 23:273a2f93ae99 1521 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1522 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
tmulrooney 23:273a2f93ae99 1523 {
tmulrooney 23:273a2f93ae99 1524 // Clear Irq
tmulrooney 23:273a2f93ae99 1525 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
tmulrooney 23:273a2f93ae99 1526 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
tmulrooney 23:273a2f93ae99 1527 {
tmulrooney 23:273a2f93ae99 1528 this->RadioEvents->CadDone( true );
tmulrooney 23:273a2f93ae99 1529 }
tmulrooney 23:273a2f93ae99 1530 }
tmulrooney 23:273a2f93ae99 1531 else
tmulrooney 23:273a2f93ae99 1532 {
tmulrooney 23:273a2f93ae99 1533 // Clear Irq
tmulrooney 23:273a2f93ae99 1534 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
tmulrooney 23:273a2f93ae99 1535 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
tmulrooney 23:273a2f93ae99 1536 {
tmulrooney 23:273a2f93ae99 1537 this->RadioEvents->CadDone( false );
tmulrooney 23:273a2f93ae99 1538 }
tmulrooney 23:273a2f93ae99 1539 }
tmulrooney 23:273a2f93ae99 1540 break;
tmulrooney 23:273a2f93ae99 1541 default:
tmulrooney 23:273a2f93ae99 1542 break;
tmulrooney 23:273a2f93ae99 1543 }
tmulrooney 23:273a2f93ae99 1544 }
tmulrooney 23:273a2f93ae99 1545
tmulrooney 23:273a2f93ae99 1546 void SX1272::OnDio4Irq( void )
tmulrooney 23:273a2f93ae99 1547 {
tmulrooney 23:273a2f93ae99 1548 debug("OnDio4Irq\r\n");
tmulrooney 23:273a2f93ae99 1549 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1550 {
tmulrooney 23:273a2f93ae99 1551 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1552 {
tmulrooney 23:273a2f93ae99 1553 if( this->settings.FskPacketHandler.PreambleDetected == false )
tmulrooney 23:273a2f93ae99 1554 {
tmulrooney 23:273a2f93ae99 1555 this->settings.FskPacketHandler.PreambleDetected = true;
tmulrooney 23:273a2f93ae99 1556 }
tmulrooney 23:273a2f93ae99 1557 }
tmulrooney 23:273a2f93ae99 1558 break;
tmulrooney 23:273a2f93ae99 1559 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1560 break;
tmulrooney 23:273a2f93ae99 1561 default:
tmulrooney 23:273a2f93ae99 1562 break;
tmulrooney 23:273a2f93ae99 1563 }
tmulrooney 23:273a2f93ae99 1564 }
tmulrooney 23:273a2f93ae99 1565
tmulrooney 23:273a2f93ae99 1566 void SX1272::OnDio5Irq( void )
tmulrooney 23:273a2f93ae99 1567 {
tmulrooney 23:273a2f93ae99 1568 debug("OnDio5Irq\r\n");
tmulrooney 23:273a2f93ae99 1569 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1570 {
tmulrooney 23:273a2f93ae99 1571 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1572 break;
tmulrooney 23:273a2f93ae99 1573 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1574 break;
tmulrooney 23:273a2f93ae99 1575 default:
tmulrooney 23:273a2f93ae99 1576 break;
tmulrooney 23:273a2f93ae99 1577 }
tmulrooney 23:273a2f93ae99 1578 }