ethernet_api.c

00001 /* mbed Microcontroller Library
00002  * Copyright (c) 2006-2013 ARM Limited
00003  *
00004  * Licensed under the Apache License, Version 2.0 (the "License");
00005  * you may not use this file except in compliance with the License.
00006  * You may obtain a copy of the License at
00007  *
00008  *     http://www.apache.org/licenses/LICENSE-2.0
00009  *
00010  * Unless required by applicable law or agreed to in writing, software
00011  * distributed under the License is distributed on an "AS IS" BASIS,
00012  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00013  * See the License for the specific language governing permissions and
00014  * limitations under the License.
00015  */
00016 #include "ethernet_api.h"
00017 
00018 #if DEVICE_ETHERNET
00019 
00020 #include <string.h>
00021 #include "cmsis.h"
00022 #include "mbed_interface.h"
00023 #include "toolchain.h"
00024 
00025 #define NEW_LOGIC       0
00026 #define NEW_ETH_BUFFER  0
00027 
00028 #if NEW_ETH_BUFFER
00029 
00030 #define NUM_RX_FRAG         4           // Number of Rx Fragments (== packets)
00031 #define NUM_TX_FRAG         3           // Number of Tx Fragments (== packets)
00032 
00033 #define ETH_MAX_FLEN        1536         // Maximum Ethernet Frame Size
00034 #define ETH_FRAG_SIZE       ETH_MAX_FLEN // Packet Fragment size (same as packet length)
00035 
00036 #else
00037 
00038 // Memfree calculation:
00039 // (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
00040 //                (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
00041 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
00042 #define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
00043 #define NUM_TX_FRAG         3           /* Num.of TX Fragments 3*1536= 4.6kB */
00044 //#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
00045 
00046 //#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
00047 #define ETH_FRAG_SIZE       0x300       /* Packet Fragment size 1536/2 Bytes   */
00048 #define ETH_MAX_FLEN        0x300       /* Max. Ethernet Frame Size          */
00049 
00050 const int ethernet_MTU_SIZE  = 0x300;
00051 
00052 #endif
00053 
00054 #define ETHERNET_ADDR_SIZE 6
00055 
00056 PACKED struct RX_DESC_TypeDef {                        /* RX Descriptor struct              */
00057    unsigned int Packet;
00058    unsigned int Ctrl;
00059 };
00060 typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
00061 
00062 PACKED struct RX_STAT_TypeDef {                        /* RX Status struct                  */
00063    unsigned int Info;
00064    unsigned int HashCRC;
00065 };
00066 typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
00067 
00068 PACKED struct TX_DESC_TypeDef {                        /* TX Descriptor struct              */
00069    unsigned int Packet;
00070    unsigned int Ctrl;
00071 };
00072 typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
00073 
00074 PACKED struct TX_STAT_TypeDef {                        /* TX Status struct                  */
00075    unsigned int Info;
00076 };
00077 typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
00078 
00079 /* MAC Configuration Register 1 */
00080 #define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
00081 #define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
00082 #define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
00083 #define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
00084 #define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
00085 #define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
00086 #define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
00087 #define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
00088 #define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
00089 #define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
00090 #define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
00091 
00092 /* MAC Configuration Register 2 */
00093 #define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
00094 #define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
00095 #define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
00096 #define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
00097 #define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
00098 #define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
00099 #define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
00100 #define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
00101 #define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
00102 #define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
00103 #define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
00104 #define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
00105 #define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
00106 
00107 /* Back-to-Back Inter-Packet-Gap Register */
00108 #define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
00109 #define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
00110 
00111 /* Non Back-to-Back Inter-Packet-Gap Register */
00112 #define IPGR_DEF            0x00000012  /* Recommended value                 */
00113 
00114 /* Collision Window/Retry Register */
00115 #define CLRT_DEF            0x0000370F  /* Default value                     */
00116 
00117 /* PHY Support Register */
00118 #define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
00119 //#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
00120 #define SUPP_RES_RMII       0x00000000  /* Reset Reduced MII Logic           */
00121 
00122 /* Test Register */
00123 #define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
00124 #define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
00125 #define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
00126 
00127 /* MII Management Configuration Register */
00128 #define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
00129 #define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
00130 #define MCFG_CLK_SEL        0x0000001C  /* Clock Select Mask                 */
00131 #define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
00132 
00133 /* MII Management Command Register */
00134 #define MCMD_READ           0x00000001  /* MII Read                          */
00135 #define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
00136 
00137 #define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
00138 #define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
00139 
00140 /* MII Management Address Register */
00141 #define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
00142 #define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
00143 
00144 /* MII Management Indicators Register */
00145 #define MIND_BUSY           0x00000001  /* MII is Busy                       */
00146 #define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
00147 #define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
00148 #define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
00149 
00150 /* Command Register */
00151 #define CR_RX_EN            0x00000001  /* Enable Receive                    */
00152 #define CR_TX_EN            0x00000002  /* Enable Transmit                   */
00153 #define CR_REG_RES          0x00000008  /* Reset Host Registers              */
00154 #define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
00155 #define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
00156 #define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
00157 #define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
00158 #define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
00159 #define CR_RMII             0x00000200  /* Reduced MII Interface             */
00160 #define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
00161 
00162 /* Status Register */
00163 #define SR_RX_EN            0x00000001  /* Enable Receive                    */
00164 #define SR_TX_EN            0x00000002  /* Enable Transmit                   */
00165 
00166 /* Transmit Status Vector 0 Register */
00167 #define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
00168 #define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
00169 #define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
00170 #define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
00171 #define TSV0_MCAST          0x00000010  /* Multicast Destination             */
00172 #define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
00173 #define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
00174 #define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
00175 #define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
00176 #define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
00177 #define TSV0_GIANT          0x00000400  /* Giant Frame                       */
00178 #define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
00179 #define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
00180 #define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
00181 #define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
00182 #define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
00183 #define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
00184 
00185 /* Transmit Status Vector 1 Register */
00186 #define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
00187 #define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
00188 
00189 /* Receive Status Vector Register */
00190 #define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
00191 #define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
00192 #define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
00193 #define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
00194 #define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
00195 #define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
00196 #define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
00197 #define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
00198 #define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
00199 #define RSV_MCAST           0x01000000  /* Multicast Frame                   */
00200 #define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
00201 #define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
00202 #define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
00203 #define RSV_PAUSE           0x10000000  /* Pause Frame                       */
00204 #define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
00205 #define RSV_VLAN            0x40000000  /* VLAN Frame                        */
00206 
00207 /* Flow Control Counter Register */
00208 #define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
00209 #define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
00210 
00211 /* Flow Control Status Register */
00212 #define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
00213 
00214 /* Receive Filter Control Register */
00215 #define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
00216 #define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
00217 #define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
00218 #define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
00219 #define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
00220 #define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
00221 #define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
00222 #define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
00223 
00224 /* Receive Filter WoL Status/Clear Registers */
00225 #define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
00226 #define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
00227 #define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
00228 #define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
00229 #define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
00230 #define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
00231 #define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
00232 #define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
00233 
00234 /* Interrupt Status/Enable/Clear/Set Registers */
00235 #define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
00236 #define INT_RX_ERR          0x00000002  /* Receive Error                     */
00237 #define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
00238 #define INT_RX_DONE         0x00000008  /* Receive Done                      */
00239 #define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
00240 #define INT_TX_ERR          0x00000020  /* Transmit Error                    */
00241 #define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
00242 #define INT_TX_DONE         0x00000080  /* Transmit Done                     */
00243 #define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
00244 #define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
00245 
00246 /* Power Down Register */
00247 #define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
00248 
00249 /* RX Descriptor Control Word */
00250 #define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
00251 #define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
00252 
00253 /* RX Status Hash CRC Word */
00254 #define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
00255 #define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
00256 
00257 /* RX Status Information Word */
00258 #define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
00259 #define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
00260 #define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
00261 #define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
00262 #define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
00263 #define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
00264 #define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
00265 #define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
00266 #define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
00267 #define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
00268 #define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
00269 #define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
00270 #define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
00271 #define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
00272 #define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
00273 
00274 //#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
00275 #define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
00276                             RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
00277 
00278 
00279 /* TX Descriptor Control Word */
00280 #define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
00281 #define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
00282 #define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
00283 #define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
00284 #define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
00285 #define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
00286 #define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
00287 
00288 /* TX Status Information Word */
00289 #define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
00290 #define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
00291 #define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
00292 #define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
00293 #define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
00294 #define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
00295 #define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
00296 #define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
00297 
00298 /* ENET Device Revision ID */
00299 #define OLD_EMAC_MODULE_ID  0x39022000  /* Rev. ID for first rev '-'         */
00300 
00301 /* DP83848C PHY Registers */
00302 #define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
00303 #define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
00304 #define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
00305 #define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
00306 #define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
00307 #define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
00308 #define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
00309 #define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
00310 
00311 /* PHY Extended Registers */
00312 #define PHY_REG_STS         0x10        /* Status Register                   */
00313 #define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
00314 #define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
00315 #define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
00316 #define PHY_REG_RECR        0x15        /* Receive Error Counter             */
00317 #define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
00318 #define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
00319 #define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
00320 #define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
00321 #define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
00322 #define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
00323 #define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
00324 
00325 #define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
00326 #define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
00327 #define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
00328 #define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
00329 #define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
00330 
00331 #define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */
00332 #define DP83848C_ID         0x20005C90  /* PHY Identifier                    */
00333 
00334 #define PHY_STS_LINK        0x0001      /* PHY Status Link Mask              */
00335 #define PHY_STS_SPEED       0x0002      /* PHY Status Speed Mask             */
00336 #define PHY_STS_DUPLEX      0x0004      /* PHY Status Duplex Mask            */
00337 
00338 #define PHY_BMCR_RESET      0x8000      /* PHY Reset                         */
00339 
00340 static int phy_read(unsigned int PhyReg);
00341 static int phy_write(unsigned int PhyReg, unsigned short Data);
00342 
00343 static void txdscr_init(void);
00344 static void rxdscr_init(void);
00345 
00346 #if defined (__ICCARM__)
00347 #   define AHBSRAM1
00348 #else
00349 #   define AHBSRAM1     __attribute__((section("AHBSRAM1"),aligned))
00350 #endif
00351 
00352 AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
00353 AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
00354 AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
00355 AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
00356 AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
00357 AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
00358 
00359 
00360 #if NEW_LOGIC
00361 static int rx_consume_offset = -1;
00362 static int tx_produce_offset = -1;
00363 #else
00364 static int send_doff =  0;
00365 static int send_idx  = -1;
00366 static int send_size =  0;
00367 
00368 static int receive_soff =  0;
00369 static int receive_idx  = -1;
00370 #endif
00371 
00372 static inline int rinc(int idx, int mod) {
00373   ++idx;
00374   idx %= mod;
00375   return idx;
00376 }
00377 
00378 //extern unsigned int SystemFrequency;
00379 static inline unsigned int clockselect() {
00380   if(SystemCoreClock  < 10000000) {
00381     return 1;
00382   } else if(SystemCoreClock  <  15000000) {
00383     return 2;
00384   } else if(SystemCoreClock  <  20000000) {
00385     return 3;
00386   } else if(SystemCoreClock  <  25000000) {
00387     return 4;
00388   } else if(SystemCoreClock  <  35000000) {
00389     return 5;
00390   } else if(SystemCoreClock  <  50000000) {
00391     return 6;
00392   } else if(SystemCoreClock  <  70000000) {
00393     return 7;
00394   } else if(SystemCoreClock  <  80000000) {
00395     return 8;
00396   } else if(SystemCoreClock  <  90000000) {
00397     return 9;
00398   } else if(SystemCoreClock  < 100000000) {
00399     return 10;
00400   } else if(SystemCoreClock  < 120000000) {
00401     return 11;
00402   } else if(SystemCoreClock  < 130000000) {
00403     return 12;
00404   } else if(SystemCoreClock  < 140000000) {
00405     return 13;
00406   } else if(SystemCoreClock  < 150000000) {
00407     return 15;
00408   } else if(SystemCoreClock  < 160000000) {
00409     return 16;
00410   } else {
00411     return 0;
00412   }
00413 }
00414 
00415 #ifndef min
00416 #define min(x, y) (((x)<(y))?(x):(y))
00417 #endif
00418 
00419 /*----------------------------------------------------------------------------
00420   Ethernet Device initialize
00421  *----------------------------------------------------------------------------*/
00422 int ethernet_init() {
00423   int regv, tout;
00424   char mac[ETHERNET_ADDR_SIZE];
00425   unsigned int clock = clockselect();
00426 
00427   LPC_SC->PCONP |= 0x40000000;                       /* Power Up the EMAC controller. */
00428 
00429 
00430   LPC_PINCON->PINSEL2 = 0x50150105;                  /* Enable P1 Ethernet Pins. */
00431   LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
00432 
00433    /* Reset all EMAC internal modules. */
00434   LPC_EMAC->MAC1    = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
00435                       MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
00436   LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
00437 
00438   for(tout = 100; tout; tout--) __NOP();             /* A short delay after reset. */
00439 
00440   LPC_EMAC->MAC1 = MAC1_PASS_ALL;                    /* Initialize MAC control registers. */
00441   LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
00442   LPC_EMAC->MAXF = ETH_MAX_FLEN;
00443   LPC_EMAC->CLRT = CLRT_DEF;
00444   LPC_EMAC->IPGR = IPGR_DEF;
00445 
00446   LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;    /* Enable Reduced MII interface. */
00447 
00448   LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;    /* Set clock */
00449   LPC_EMAC->MCFG |= MCFG_RES_MII;                    /* and reset */
00450 
00451   for(tout = 100; tout; tout--) __NOP();             /* A short delay */
00452 
00453   LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
00454   LPC_EMAC->MCMD = 0;
00455 
00456   LPC_EMAC->SUPP = SUPP_RES_RMII;                    /* Reset Reduced MII Logic. */
00457 
00458   for (tout = 100; tout; tout--) __NOP();            /* A short delay */
00459 
00460   LPC_EMAC->SUPP = 0;
00461 
00462   phy_write(PHY_REG_BMCR, PHY_BMCR_RESET);           /* perform PHY reset */
00463   for(tout = 0x20000; ; tout--) {                    /* Wait for hardware reset to end. */
00464     regv = phy_read(PHY_REG_BMCR);
00465     if(regv < 0 || tout == 0) {
00466        return -1;                                    /* Error */
00467     }
00468     if(!(regv & PHY_BMCR_RESET)) {
00469        break;                                        /* Reset complete. */
00470     }
00471   }
00472 
00473   ethernet_set_link(-1, 0);
00474 
00475   /* Set the Ethernet MAC Address registers */
00476   ethernet_address(mac);
00477   LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
00478   LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
00479   LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
00480 
00481   txdscr_init();                                      /* initialize DMA TX Descriptor */
00482   rxdscr_init();                                      /* initialize DMA RX Descriptor */
00483 
00484   LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
00485                                                       /* Receive Broadcast, Perfect Match Packets */
00486 
00487   LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;    /* Enable EMAC interrupts. */
00488   LPC_EMAC->IntClear  = 0xFFFF;                       /* Reset all interrupts */
00489 
00490 
00491   LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);        /* Enable receive and transmit mode of MAC Ethernet core */
00492   LPC_EMAC->MAC1     |= MAC1_REC_EN;
00493 
00494 #if NEW_LOGIC
00495   rx_consume_offset = -1;
00496   tx_produce_offset = -1;
00497 #else
00498   send_doff =  0;
00499   send_idx  = -1;
00500   send_size =  0;
00501 
00502   receive_soff =  0;
00503   receive_idx  = -1;
00504 #endif
00505 
00506   return 0;
00507 }
00508 
00509 /*----------------------------------------------------------------------------
00510   Ethernet Device Uninitialize
00511  *----------------------------------------------------------------------------*/
00512 void ethernet_free() {
00513 
00514   LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
00515   LPC_EMAC->IntClear   =  0xFFFF;
00516 
00517   LPC_SC->PCONP   &= ~0x40000000;       /* Power down the EMAC controller. */
00518   LPC_PINCON->PINSEL2 &= ~0x50150105;   /* Disable P1 ethernet pins. */
00519   LPC_PINCON->PINSEL3  = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000000;
00520 }
00521 
00522 // if(TxProduceIndex == TxConsumeIndex) buffer array is empty
00523 // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
00524 // TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
00525 // TxConsumeIndex - The buffer that will/is beign sent by hardware
00526 
00527 int ethernet_write(const char *data, int slen) {
00528 
00529 #if NEW_LOGIC
00530 
00531    if(tx_produce_offset < 0) { // mark as active if not already
00532      tx_produce_offset = 0;
00533    }
00534 
00535    int index = LPC_EMAC->TxProduceIndex;
00536 
00537    int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
00538    int requested = slen;
00539    int ncopy = min(remaining, requested);
00540 
00541    void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
00542    void *psrc = (void *)(data);
00543 
00544    if(ncopy > 0 ){
00545      if(data != NULL) {
00546        memcpy(pdst, psrc, ncopy);
00547      } else {
00548        memset(pdst, 0, ncopy);
00549      }
00550    }
00551 
00552    tx_produce_offset += ncopy;
00553 
00554    return ncopy;
00555 
00556 #else
00557     void       *pdst, *psrc;
00558     const int   dlen = ETH_FRAG_SIZE;
00559     int         copy = 0;
00560     int         soff = 0;
00561 
00562     if(send_idx == -1) {
00563         send_idx = LPC_EMAC->TxProduceIndex;
00564     }
00565 
00566     if(slen + send_doff > ethernet_MTU_SIZE) {
00567        return -1;
00568     }
00569 
00570     do {
00571         copy = min(slen - soff, dlen - send_doff);
00572         pdst = (void *)(txdesc[send_idx].Packet + send_doff);
00573         psrc = (void *)(data + soff);
00574         if(send_doff + copy > ETH_FRAG_SIZE) {
00575             txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
00576             send_idx = rinc(send_idx, NUM_TX_FRAG);
00577             send_doff = 0;
00578         }
00579 
00580         if(data != NULL) {
00581             memcpy(pdst, psrc, copy);
00582         } else {
00583             memset(pdst, 0, copy);
00584         }
00585 
00586         soff += copy;
00587         send_doff += copy;
00588         send_size += copy;
00589     } while(soff != slen);
00590 
00591     return soff;
00592 #endif
00593 }
00594 
00595 int ethernet_send() {
00596 
00597 #if NEW_LOGIC
00598   if(tx_produce_offset < 0) { // no buffer active
00599     return -1;
00600   }
00601 
00602   // ensure there is a link
00603   if(!ethernet_link()) {
00604     return -2;
00605   }
00606 
00607   // we have been writing in to a buffer, so finalise it
00608   int size = tx_produce_offset;
00609   int index = LPC_EMAC->TxProduceIndex;
00610   txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
00611 
00612   // Increment ProduceIndex to allow it to be sent
00613   // We can only do this if the next slot is free
00614   int next = rinc(index, NUM_TX_FRAG);
00615   while(next == LPC_EMAC->TxConsumeIndex) {
00616     for(int i=0; i<1000; i++) { __NOP(); }
00617   }
00618 
00619   LPC_EMAC->TxProduceIndex = next;
00620   tx_produce_offset = -1;
00621   return size;
00622 
00623 #else
00624     int s = send_size;
00625     txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
00626     send_idx  = rinc(send_idx, NUM_TX_FRAG);
00627     LPC_EMAC->TxProduceIndex = send_idx;
00628     send_doff =  0;
00629     send_idx  = -1;
00630     send_size =  0;
00631     return s;
00632 #endif
00633 }
00634 
00635 // RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
00636 // RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
00637 //
00638 // if(RxConsumeIndex == RxProduceIndex) buffer array is empty
00639 // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
00640 
00641 // Recevies an arrived ethernet packet.
00642 // Receiving an ethernet packet will drop the last received ethernet packet
00643 // and make a new ethernet packet ready to read.
00644 // Returns size of packet, else 0 if nothing to receive
00645 
00646 // We read from RxConsumeIndex from position rx_consume_offset
00647 // if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
00648 // rx_consume_offset = -1 // no frame
00649 // rx_consume_offset = 0  // start of frame
00650 // Assumption: A fragment should alway be a whole frame
00651 
00652 int ethernet_receive() {
00653 #if NEW_LOGIC
00654 
00655   // if we are currently reading a valid RxConsume buffer, increment to the next one
00656   if(rx_consume_offset >= 0) {
00657     LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
00658   }
00659 
00660   // if the buffer is empty, mark it as no valid buffer
00661   if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
00662     rx_consume_offset = -1;
00663     return 0;
00664   }
00665 
00666   uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
00667   rx_consume_offset = 0;
00668 
00669   // check if it is not marked as last or for errors
00670   if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
00671     return -1;
00672   }
00673 
00674   int size = (info & RINFO_SIZE) + 1;
00675   return size - 4; // don't include checksum bytes
00676 
00677 #else
00678     if(receive_idx == -1) {
00679       receive_idx = LPC_EMAC->RxConsumeIndex;
00680     } else {
00681         while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && (receive_idx != LPC_EMAC->RxProduceIndex)) {
00682             receive_idx  = rinc(receive_idx, NUM_RX_FRAG);
00683         }
00684         unsigned int info =   rxstat[receive_idx].Info;
00685         int slen =  (info & RINFO_SIZE) + 1;
00686 
00687         if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
00688             /* Invalid frame, ignore it and free buffer. */
00689             receive_idx = rinc(receive_idx, NUM_RX_FRAG);
00690         }
00691         receive_idx = rinc(receive_idx, NUM_RX_FRAG);
00692         receive_soff = 0;
00693 
00694         LPC_EMAC->RxConsumeIndex = receive_idx;
00695     }
00696 
00697     if(receive_idx == LPC_EMAC->RxProduceIndex) {
00698         receive_idx = -1;
00699         return 0;
00700     }
00701 
00702     return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
00703 #endif
00704 }
00705 
00706 // Read from an recevied ethernet packet.
00707 // After receive returnd a number bigger than 0 it is
00708 // possible to read bytes from this packet.
00709 // Read will write up to size bytes into data.
00710 // It is possible to use read multible times.
00711 // Each time read will start reading after the last read byte before.
00712 
00713 int ethernet_read(char *data, int dlen) {
00714 #if NEW_LOGIC
00715   // Check we have a valid buffer to read
00716   if(rx_consume_offset < 0) {
00717     return 0;
00718   }
00719 
00720   // Assume 1 fragment block
00721   uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
00722   int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
00723 
00724   int remaining = size - rx_consume_offset;
00725   int requested = dlen;
00726   int ncopy = min(remaining, requested);
00727 
00728   void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
00729   void *pdst = (void *)(data);
00730 
00731   if(data != NULL && ncopy > 0) {
00732     memcpy(pdst, psrc, ncopy);
00733   }
00734 
00735   rx_consume_offset += ncopy;
00736 
00737   return ncopy;
00738 #else
00739     int          slen;
00740     int          copy   = 0;
00741     unsigned int more;
00742     unsigned int info;
00743     void        *pdst, *psrc;
00744     int          doff = 0;
00745 
00746     if(receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
00747         return 0;
00748     }
00749 
00750     do {
00751         info =   rxstat[receive_idx].Info;
00752         more = !(info & RINFO_LAST_FLAG);
00753         slen =  (info & RINFO_SIZE) + 1;
00754 
00755         if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
00756             /* Invalid frame, ignore it and free buffer. */
00757             receive_idx = rinc(receive_idx, NUM_RX_FRAG);
00758         } else {
00759 
00760             copy = min(slen - receive_soff, dlen - doff);
00761             psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
00762             pdst = (void *)(data + doff);
00763 
00764             if(data != NULL) {
00765                 /* check if Buffer available */
00766                 memcpy(pdst, psrc, copy);
00767             }
00768 
00769             receive_soff += copy;
00770             doff += copy;
00771 
00772             if((more && (receive_soff == slen))) {
00773                 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
00774                 receive_soff = 0;
00775             }
00776         }
00777     } while(more && !(doff == dlen) && !receive_soff);
00778 
00779     return doff;
00780 #endif
00781 }
00782 
00783 int ethernet_link(void) {
00784     return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
00785 }
00786 
00787 static int phy_write(unsigned int PhyReg, unsigned short Data) {
00788     unsigned int timeOut;
00789 
00790     LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
00791     LPC_EMAC->MWTD = Data;
00792 
00793     for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) {     /* Wait until operation completed */
00794         if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
00795             return 0;
00796         }
00797     }
00798 
00799     return -1;
00800 }
00801 
00802 
00803 static int phy_read(unsigned int PhyReg) {
00804     unsigned int timeOut;
00805 
00806     LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
00807     LPC_EMAC->MCMD = MCMD_READ;
00808 
00809     for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) {     /* Wait until operation completed */
00810         if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
00811             LPC_EMAC->MCMD = 0;
00812             return LPC_EMAC->MRDD;                           /* Return a 16-bit value. */
00813         }
00814     }
00815 
00816     return -1;
00817 }
00818 
00819 
00820 static void txdscr_init() {
00821     int i;
00822 
00823     for(i = 0; i < NUM_TX_FRAG; i++) {
00824         txdesc[i].Packet = (uint32_t)&txbuf[i];
00825         txdesc[i].Ctrl   = 0;
00826         txstat[i].Info   = 0;
00827     }
00828 
00829     LPC_EMAC->TxDescriptor       = (uint32_t)txdesc;         /* Set EMAC Transmit Descriptor Registers. */
00830     LPC_EMAC->TxStatus           = (uint32_t)txstat;
00831     LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
00832 
00833     LPC_EMAC->TxProduceIndex  = 0;                           /* Tx Descriptors Point to 0 */
00834 }
00835 
00836 
00837 static void rxdscr_init() {
00838     int i;
00839 
00840     for(i = 0; i < NUM_RX_FRAG; i++) {
00841         rxdesc[i].Packet  = (uint32_t)&rxbuf[i];
00842         rxdesc[i].Ctrl    = RCTRL_INT | (ETH_FRAG_SIZE-1);
00843         rxstat[i].Info    = 0;
00844         rxstat[i].HashCRC = 0;
00845     }
00846 
00847     LPC_EMAC->RxDescriptor       = (uint32_t)rxdesc;        /* Set EMAC Receive Descriptor Registers. */
00848     LPC_EMAC->RxStatus           = (uint32_t)rxstat;
00849     LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
00850 
00851     LPC_EMAC->RxConsumeIndex  = 0;                          /* Rx Descriptors Point to 0 */
00852 }
00853 
00854 void ethernet_address(char *mac) {
00855     mbed_mac_address(mac);
00856 }
00857 
00858 void ethernet_set_link(int speed, int duplex) {
00859     unsigned short phy_data;
00860     int tout;
00861 
00862     if((speed < 0) || (speed > 1)) {
00863 
00864         phy_data = PHY_AUTO_NEG;
00865 
00866     } else {
00867 
00868         phy_data = (((unsigned short) speed << 13) |
00869                     ((unsigned short) duplex << 8));
00870     }
00871 
00872     phy_write(PHY_REG_BMCR, phy_data);
00873 
00874     for(tout = 100; tout; tout--) { __NOP(); }     /* A short delay */
00875 
00876     phy_data = phy_read(PHY_REG_STS);
00877 
00878     if(phy_data & PHY_STS_DUPLEX) {
00879         LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
00880         LPC_EMAC->Command |= CR_FULL_DUP;
00881         LPC_EMAC->IPGT = IPGT_FULL_DUP;
00882     } else {
00883     LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
00884         LPC_EMAC->Command &= ~CR_FULL_DUP;
00885         LPC_EMAC->IPGT = IPGT_HALF_DUP;
00886     }
00887 
00888     if(phy_data & PHY_STS_SPEED) {
00889         LPC_EMAC->SUPP &= ~SUPP_SPEED;
00890     } else {
00891         LPC_EMAC->SUPP |= SUPP_SPEED;
00892     }
00893 }
00894 
00895 #endif