Ted Grosch
/
Nucleo_TOF_I2C
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Embed:
(wiki syntax)
Show/hide line numbers
OPT3101device_RegisterMap.cpp
Go to the documentation of this file.
00001 /*! 00002 * \file OPT3101device_RegisterMap.cpp 00003 * \author Karthik Rajagopal <krthik@ti.com> 00004 * \version 0.9.1 00005 * 00006 * \section COPYRIGHT 00007 * TEXAS INSTRUMENTS TEXT FILE LICENSE 00008 * Copyright (c) 2018 Texas Instruments Incorporated 00009 * All rights reserved not granted herein. 00010 * Limited License. 00011 * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive license under copyrights and patents it now or hereafter owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") this software subject to the terms herein. With respect to the foregoing patent license, such license is granted solely to the extent that any such patent is necessary to Utilize the software alone. The patent license shall not apply to any combinations which include this software, other than combinations with devices manufactured by or for TI ("TI Devices"). No hardware patent is licensed hereunder. 00012 * Redistributions must preserve existing copyright notices and reproduce this license (including the above copyright notice and the disclaimer and (if applicable) source code license limitations below) in the documentation and/or other materials provided with the distribution 00013 * Redistribution and use in binary form, without modification, are permitted provided that the following conditions are met: 00014 * * No reverse engineering, decompilation, or disassembly of this software is permitted with respect to any software provided in binary form. 00015 * * any redistribution and use are licensed by TI for use only with TI Devices. 00016 * * Nothing shall obligate TI to provide you with source code for the software licensed and provided to you in object code. 00017 * If software source code is provided to you, modification and redistribution of the source code are permitted provided that the following conditions are met: 00018 * * any redistribution and use of the source code, including any resulting derivative works, are licensed by TI for use only with TI Devices. 00019 * * any redistribution and use of any object code compiled from the source code and any resulting derivative works, are licensed by TI for use only with TI Devices. 00020 * Neither the name of Texas Instruments Incorporated nor the names of its suppliers may be used to endorse or promote products derived from this software without specific prior written permission. 00021 * DISCLAIMER. 00022 * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00023 * 00024 * \section DESCRIPTION 00025 * The file contains OPT3101::registers class constructor and assignment 00026 */ 00027 00028 #include "OPT3101RegisterDefinition.h " 00029 00030 OPT3101::registers::registers() : 00031 dig_gpo_sel0(1), ///< dig_gpo_sel0;Register Addresses: 11[3:0]; 00032 dig_gpo_sel1(1), ///< dig_gpo_sel1;Register Addresses: 11[7:4]; 00033 dig_gpo_sel2(1), ///< dig_gpo_sel2;Register Addresses: 11[13:10]; 00034 dis_ovl_gating(1), ///< dis_ovl_gating;Register Addresses: 17[15:15]; 00035 phase_out(1), ///< phase_out;Register Addresses: 8[15:0]; 00036 phase_overflow(1), ///< phase_overflow;Register Addresses: 8[16:16]; 00037 hdr_mode(1), ///< hdr_mode;Register Addresses: 8[17:17]; 00038 tx_channel(1), ///< tx_channel;Register Addresses: 8[19:18]; 00039 frame_status(1), ///< frame_status;Register Addresses: 8[20:20]; 00040 mod_freq(1), ///< mod_freq;Register Addresses: 8[21:21]; 00041 frame_count0(1), ///< frame_count0;Register Addresses: 8[23:23]; 00042 amp_out(1), ///< amp_out;Register Addresses: 9[15:0]; 00043 frame_count1(1), ///< frame_count1;Register Addresses: 9[17:16]; 00044 sig_ovl_flag(1), ///< sig_ovl_flag;Register Addresses: 9[18:18]; 00045 dealias_bin(1), ///< dealias_bin;Register Addresses: 9[23:20]; 00046 frame_count2(1), ///< frame_count2;Register Addresses: 10[1:0]; 00047 amb_data(1), ///< amb_data;Register Addresses: 10[11:2]; 00048 tmain(1), ///< tmain;Register Addresses: 10[23:12]; 00049 amplitude_min_thr(2), ///< amplitude_min_thr;Register Addresses: 16[23:16], 17[23:16]; 00050 amb_ovl_flag(1), ///< amb_ovl_flag;Register Addresses: 8[22:22]; 00051 phase_overflow_f2(1), ///< phase_overflow_f2;Register Addresses: 9[19:19]; 00052 ref_count_limit(1), ///< ref_count_limit;Register Addresses: 15[14:0];this sets the limit of ref-clock count when meth1 is used. By programming this we no longer require frequencies which are multiples of powers of 2.;;The default is calculated for 32.768 Khz. 00053 start_freq_calib(1), ///< start_freq_calib;Register Addresses: 15[16:16];starts the freq_calib 00054 sys_clk_divider(1), ///< sys_clk_divider;Register Addresses: 15[20:17];The divider can be set according to the ratio b/w ref_clk and tg_clk. The default is 2 which means default ref_clk is assumed at 10 Mhz. ie 40Mhz/4 00055 freq_count_read_reg(1), ///< freq_count_read_reg;Register Addresses: 16[14:0];read register which holds the value of freq_loop. 00056 freq_count_reg(1), ///< freq_count_reg;Register Addresses: 17[14:0];The register which is used for frequency correction when enable_auto_freq_count = '0' 00057 en_auto_freq_count(1), ///< en_auto_freq_count;Register Addresses: 15[21:21];When this is '1' internally computed values is used. Else register value is used. 00058 en_floop(1), ///< en_floop;Register Addresses: 15[22:22];Enables the freq_loop block. If this is '0', the clock to the freq_loop is gated. 00059 en_freq_corr(1), ///< en_freq_corr;Register Addresses: 15[23:23];This bit applies frequency correction on the phase data either from register or auto_freq. 00060 en_cont_fcalib(1), ///< en_cont_fcalib;Register Addresses: 16[15:15]; 00061 monoshot_bit(1), ///< monoshot_bit;Register Addresses: 0[23:23];In monoshot mode the register to trigger a measurement. 00062 monoshot_mode(1), ///< monoshot_mode;Register Addresses: 39[1:0];LSB: Enters monoshot mode.;;MSB: If this is set monoshot mode shutdown the oscclk. This has to be used together with monoshot_mode. 00063 powerup_delay(1), ///< powerup_delay;Register Addresses: 38[23:10];The synchronous counter delay after the ripple counter expires before ungating the clock. About 256*25ns*2^6 ~ 400 us. 00064 monoshot_numframe(1), ///< monoshot_numframe;Register Addresses: 39[7:2];The number of frames of TG to be run after a trigger before shutting down the TG. The default is kept as 6 allowing a led cycle. 00065 monoshot_fz_clkcnt(1), ///< monoshot_fz_clkcnt;Register Addresses: 39[23:8];The pix_cnt at which a monoshot operation freezes. By default just freezes 100 cycles before a frame boundary. 00066 en_tx_switch(1), ///< en_tx_switch;Register Addresses: 42[0:0];Enable switching of led drivers. 00067 sel_tx_ch(1), ///< sel_tx_ch;Register Addresses: 42[2:1];choses the fix_reg value when switching is disabled. 00068 tx_seq_reg(1), ///< tx_seq_reg;Register Addresses: 42[14:3];Stores the sequence of led switching in this register.;2-1-0-2-1-0. The sequence will come as 0-1-2-0-1-2 00069 en_adaptive_hdr(1), ///< en_adaptive_hdr;Register Addresses: 42[15:15];enable the adaptive hdr. The num_avg_frame in this case should be programmed one more than the normal case. 00070 sel_hdr_mode(1), ///< sel_hdr_mode;Register Addresses: 42[16:16];choses which current to use when enable_adaptive_hdr = '0' 00071 hdr_thr_low(1), ///< hdr_thr_low;Register Addresses: 44[15:0];The low threshold of the hysterisis loop. Equivalent to ~64 confidence. 00072 hdr_thr_high(1), ///< hdr_thr_high;Register Addresses: 43[15:0];the high threshold of the hyserisis loop. Default equivalent to confidence of 256 in 16 bit level. 00073 illum_scale_l_tx0(1), ///< illum_scale_l_tx0;Register Addresses: 43[18:16]; 00074 illum_dac_l_tx0(1), ///< illum_dac_l_tx0;Register Addresses: 41[4:0]; 00075 illum_scale_h_tx0(1), ///< illum_scale_h_tx0;Register Addresses: 43[21:19]; 00076 illum_dac_h_tx0(1), ///< illum_dac_h_tx0;Register Addresses: 41[9:5]; 00077 illum_scale_l_tx1(1), ///< illum_scale_l_tx1;Register Addresses: 44[18:16]; 00078 illum_dac_l_tx1(1), ///< illum_dac_l_tx1;Register Addresses: 41[14:10]; 00079 illum_scale_h_tx1(1), ///< illum_scale_h_tx1;Register Addresses: 44[21:19]; 00080 illum_dac_h_tx1(1), ///< illum_dac_h_tx1;Register Addresses: 41[19:15]; 00081 illum_scale_l_tx2(1), ///< illum_scale_l_tx2;Register Addresses: 185[20:18]; 00082 illum_dac_l_tx2(2), ///< illum_dac_l_tx2;Register Addresses: 41[23:20], 42[23:23]; 00083 illum_scale_h_tx2(1), ///< illum_scale_h_tx2;Register Addresses: 185[23:21]; 00084 illum_dac_h_tx2(1), ///< illum_dac_h_tx2;Register Addresses: 42[22:18]; 00085 amb_adc_in_tx0(1), ///< amb_adc_in_tx0;Register Addresses: 185[13:12]; 00086 amb_adc_in_tx1(1), ///< amb_adc_in_tx1;Register Addresses: 185[15:14]; 00087 amb_adc_in_tx2(1), ///< amb_adc_in_tx2;Register Addresses: 185[17:16]; 00088 give_dealias_data(1), ///< give_dealias_data;Register Addresses: 184[20:20]; 00089 en_dealias_meas(1), ///< en_dealias_meas;Register Addresses: 64[0:0];enables dealias calculation.;Normally with enable_dealiased_measurement set and enable_multi_freq_phase is unset a combined distance and kb is given out. In the normal phase register, phase of the high frequency itself is given.; 00090 ncr_config(1), ///< ncr_config;Register Addresses: 64[21:21];option to chose ncr configuration, that is 6/7 (0) or 6/5 (1). Chooses higher frequency by default. 00091 alpha0_dealias_scale(1), ///< alpha0_dealias_scale;Register Addresses: 64[14:9];indicates the vector multiplication in intrinsic-xtalk component for the dealias frequency. Default is '1'. 00092 beta0_dealias_scale(1), ///< beta0_dealias_scale;Register Addresses: 64[20:15]; 00093 alpha1_dealias_scale(1), ///< alpha1_dealias_scale;Register Addresses: 65[5:0];indicates the vector multiplication in optical-xtalk component for the dealias frequency. Default is '1'. 00094 beta1_dealias_scale(1), ///< beta1_dealias_scale;Register Addresses: 65[11:6]; 00095 en_multi_freq_phase(1), ///< en_multi_freq_phase;Register Addresses: 64[22:22];With this bit set along with enable_dealiased_measurement, the usual phase register will have both the frequency information. The frequency of the phase will be indicated in one of the status bit. 00096 temp_avg_main(1), ///< temp_avg_main;Register Addresses: 3[23:22]; 00097 dis_ovl_for_hdr_meth1(1), ///< dis_ovl_for_hdr_meth1;Register Addresses: 184[21:21]; 00098 en_ovl_for_hdr_meth2(1), ///< en_ovl_for_hdr_meth2;Register Addresses: 184[22:22]; 00099 en_tx1_on_tx0(1), ///< en_tx1_on_tx0;Register Addresses: 185[10:10]; 00100 en_tx2_on_tx0(1), ///< en_tx2_on_tx0;Register Addresses: 185[11:11]; 00101 clip_mode_fc(1), ///< clip_mode_fc;Register Addresses: 80[0:0];chooses either rounding off or clipping or wrap around when applying freq-correction. Default is kept as rounding. 00102 clip_mode_nl(1), ///< clip_mode_nl;Register Addresses: 80[1:1];chooses either rounding off or clipping or wrap around when applying harmonic correction. Default is kept as rounding. 00103 clip_mode_temp(1), ///< clip_mode_temp;Register Addresses: 80[2:2];chooses either rounding off or clipping or wrap around when applying temp correction. Default is kept as rounding. 00104 clip_mode_offset(1), ///< clip_mode_offset;Register Addresses: 80[3:3];chooses either rounding off or clipping or wrap around when applying offset. Default is kept as rounding. 00105 disable_syncing(1), ///< disable_syncing;Register Addresses: 80[21:21];Normally calc clock and afe_clk are synchronized to avoid reset to reset variation in spur levels. This option is to disable the syncing of dividers (of calc_clk). The default is now changed to '1' because we don't use divided clock for calc-clk from PG3P0 by default. If syncing is used frequency loop will have issues. 00106 force_en_slave(1), ///< force_en_slave;Register Addresses: 0[22:22];Enable i2c slave for any address forcefully. That is whether auto_load completed or not. 00107 force_en_bypass(1), ///< force_en_bypass;Register Addresses: 0[21:21];This bit allows the slave to write directly to the efuse. This is gated with stop condition at the port level to avoid transition signals at scl/sda. 00108 override_clkgen_reg(1), ///< override_clkgen_reg;Register Addresses: 80[22:22];Setting this register '1' allows user to independenly control tm_clkgen(2:1) which controls dealias settings. 00109 software_reset(1), ///< software_reset;Register Addresses: 0[0:0]; 00110 dis_tg_aconf(1), ///< dis_tg_aconf;Register Addresses: 128[23:23];Some of the tg registers are automatically configured such as pdn*_dyn_tg signal, capture_tg_channel etc. if these signals need to be configured by user this bit may be used as an override. 00111 capture_clk_cnt(1), ///< capture_clk_cnt;Register Addresses: 160[15:0];This is where early_fvd/svd starts. early_fvd only comes in the frame which is equal num_avg. This is the subframe in which computation results comes up. Programm this to 10600 if planning to use lower frequency. 00112 tg_en(1), ///< tg_en;Register Addresses: 128[0:0];gates the tg_clk with this bit. 00113 num_sub_frames(1), ///< num_sub_frames;Register Addresses: 159[11:0];The numbef of subframes in a frame. This number should be greater than or equal to num_avg. 00114 num_avg_sub_frames(1), ///< num_avg_sub_frames;Register Addresses: 159[23:12];The number of averages for the iq. Used in TG to generate early_fvd and some other TG signals. 00115 sub_vd_clk_cnt(1), ///< sub_vd_clk_cnt;Register Addresses: 128[16:1];the number of pixels in a subframe. In PG3P0 the default is changed to support 4ksps. The number is also made a multiple of 32+16. 00116 tg_illumen_start(1), ///< tg_illumen_start;Register Addresses: 143[15:0];spare2_tg. This is used for illum_en. Enabled throughout a subframe. 00117 tg_illumen_end(1), ///< tg_illumen_end;Register Addresses: 144[15:0];Ending after the 8192+ 250 samples apx. 00118 tg_illumen_mask_start(1), ///< tg_illumen_mask_start;Register Addresses: 156[11:0];spare2_mask. By default the mask is programmed till num_avg_iq only. 00119 tg_illumen_mask_end(1), ///< tg_illumen_mask_end;Register Addresses: 156[23:12]; 00120 tg_afe_rst_start(1), ///< tg_afe_rst_start;Register Addresses: 131[15:0];demod_reset. Mask is programmed such that it comes every subframe. 00121 tg_afe_rst_end(1), ///< tg_afe_rst_end;Register Addresses: 132[15:0]; 00122 tg_seq_int_start(1), ///< tg_seq_int_start;Register Addresses: 133[15:0];interrupt. Only happens in first subframe due to the mask programming 00123 tg_seq_int_end(1), ///< tg_seq_int_end;Register Addresses: 134[15:0]; 00124 tg_capture_start(1), ///< tg_capture_start;Register Addresses: 135[15:0];capture_tg_channel. Internal TG signal. This signal need to be changed when you go to slower dealias mode. Program this to 11300 and 11800 00125 tg_capture_end(1), ///< tg_capture_end;Register Addresses: 136[15:0]; 00126 tg_ovl_window_start(1), ///< tg_ovl_window_start;Register Addresses: 137[15:0];ovl_sample. During this time period only ovl is sampled. This exists for only for subframes till the num_avg. 00127 tg_ovl_window_end(1), ///< tg_ovl_window_end;Register Addresses: 138[15:0]; 00128 tg_calc_start(1), ///< tg_calc_start;Register Addresses: 145[15:0];pdn_dyn_tg. This signal exists roughly from early_fvd start till end of the computation. The mask is programmed such that this only comes in the num_avg sub-frame. Programmed such that it will work even if the frequency changes in both direction. 00129 tg_calc_end(1), ///< tg_calc_end;Register Addresses: 146[15:0]; 00130 tg_dynpdn_start(1), ///< tg_dynpdn_start;Register Addresses: 147[15:0];pdn_dyn1_tg. Used to power down less power intensive digital blocks and analog if tm_frame_vd_sub_cnt greater than num_avg_iq. 00131 tg_dynpdn_end(1), ///< tg_dynpdn_end;Register Addresses: 148[15:0]; 00132 tg_seq_int_mask_start(1), ///< tg_seq_int_mask_start;Register Addresses: 151[11:0];interrupt. Comes only in first (num:0) subframe. 00133 tg_seq_int_mask_end(1), ///< tg_seq_int_mask_end;Register Addresses: 151[23:12]; 00134 tg_capture_mask_start(1), ///< tg_capture_mask_start;Register Addresses: 152[11:0];capture_tg_channel. By default comes only in the num_avg subchannel. This mask is configurable by user only if dis_tg_aconf = '1'. 00135 tg_capture_mask_end(1), ///< tg_capture_mask_end;Register Addresses: 152[23:12]; 00136 tg_ovl_window_mask_start(1), ///< tg_ovl_window_mask_start;Register Addresses: 153[11:0];ovl_sample. This exits till num_avg subframe. 00137 tg_ovl_window_mask_end(1), ///< tg_ovl_window_mask_end;Register Addresses: 153[23:12]; 00138 tg_calc_mask_start(1), ///< tg_calc_mask_start;Register Addresses: 157[11:0];Mask for pdn_dyn_tg. Only enabled during num_avg subframe. 00139 tg_calc_mask_end(1), ///< tg_calc_mask_end;Register Addresses: 157[23:12]; 00140 tg_dynpdn_mask_start(1), ///< tg_dynpdn_mask_start;Register Addresses: 158[11:0];Mask for pdn_dyn1_tg. Used to power down less power intensive digital blocks and analog if tm_frame_vd_sub_cnt greater than num_avg_iq. Enabled till num_avg subframe. 00141 tg_dynpdn_mask_end(1), ///< tg_dynpdn_mask_end;Register Addresses: 158[23:12]; 00142 en_sequencer(1), ///< en_sequencer;Register Addresses: 20[16:16];clock gates the logic for sequencer normally. This bit is used to enable sequencer. 00143 en_processor_values(1), ///< en_processor_values;Register Addresses: 20[17:17];Uses processor values instead of register values. 00144 status_in_reg(1), ///< status_in_reg;Register Addresses: 20[18:18];the register is used to control the program flow in CPU 00145 mux_sel_compin(1), ///< mux_sel_compin;Register Addresses: 19[2:0];choses the value used for comp_a register in cpu.;Following are the choices.;phase_out_fsm;dealiased_kb_fsm;dealiased_distance;confidence 00146 compare_reg1(1), ///< compare_reg1;Register Addresses: 19[18:3]; 00147 compare_reg2(1), ///< compare_reg2;Register Addresses: 20[15:0]; 00148 dis_interrupt(1), ///< dis_interrupt;Register Addresses: 20[19:19];Disables the interrupt which triggers processor. Does not clock gate processor though. 00149 command0(1), ///< command0;Register Addresses: 21[11:0];NOP for 99 cycles 00150 command1(1), ///< command1;Register Addresses: 21[23:12];enable intrinsic-xtalk 00151 command2(1), ///< command2;Register Addresses: 22[11:0];disable intrinsic xtalk 00152 command3(1), ///< command3;Register Addresses: 22[23:12];Direct go to the first line 00153 command4(1), ///< command4;Register Addresses: 23[11:0]; 00154 command5(1), ///< command5;Register Addresses: 23[23:12]; 00155 command6(1), ///< command6;Register Addresses: 24[11:0]; 00156 command7(1), ///< command7;Register Addresses: 24[23:12]; 00157 command8(1), ///< command8;Register Addresses: 25[11:0]; 00158 command9(1), ///< command9;Register Addresses: 25[23:12]; 00159 command10(1), ///< command10;Register Addresses: 26[11:0]; 00160 command11(1), ///< command11;Register Addresses: 26[23:12]; 00161 command12(1), ///< command12;Register Addresses: 27[11:0]; 00162 command13(1), ///< command13;Register Addresses: 27[23:12]; 00163 command14(1), ///< command14;Register Addresses: 28[11:0]; 00164 command15(1), ///< command15;Register Addresses: 28[23:12]; 00165 command16(1), ///< command16;Register Addresses: 29[11:0]; 00166 command17(1), ///< command17;Register Addresses: 29[23:12]; 00167 command18(1), ///< command18;Register Addresses: 30[11:0]; 00168 command19(1), ///< command19;Register Addresses: 30[23:12]; 00169 force_scale_val(1), ///< force_scale_val;Register Addresses: 46[2:0];Uses this scale value if disable_auto_scale is programmed. This scale value is also used during any xtalk calibration even if disable_auto_scale is not applied. Default is '0', which means 24bit demod is taken as it is giving maximum accuracy. 00170 dis_auto_scale(1), ///< dis_auto_scale;Register Addresses: 46[3:3]; 00171 disable_conf_rescale(1), ///< disable_conf_rescale;Register Addresses: 46[13:13];This a mostly a debug register.. When this is set auto_scaled confidence doesn't rescale back. Even when force_scale_val is there, it doesn't rescale. This bit may be set along with force_scale_val to see the effect of confidence scaling. 00172 int_xtalk_calib(1), ///< int_xtalk_calib;Register Addresses: 46[4:4];Puts the device into intrinsic calibration mode. 00173 xtalk_filt_time_const(1), ///< xtalk_filt_time_const;Register Addresses: 46[23:20];Time constant during crosstalk filtering. Higher the time constant slower the filtering is. 00174 use_xtalk_filt_int(1), ///< use_xtalk_filt_int;Register Addresses: 46[5:5];Whehter to use filter or direct sampling for intrinsic crosstalk. 00175 use_xtalk_reg_int(1), ///< use_xtalk_reg_int;Register Addresses: 46[6:6];Whether to use register or filter/sample for intrinsic. 00176 iq_read_data_sel(1), ///< iq_read_data_sel;Register Addresses: 46[11:9];mux used to chose which of the xtalk register is being read out.;;010 -- raw_i/q;000 -- intrinsic_xtalk;001 -- optical_xtalk 00177 iphase_xtalk(1), ///< iphase_xtalk;Register Addresses: 59[23:0]; 00178 qphase_xtalk(1), ///< qphase_xtalk;Register Addresses: 60[23:0]; 00179 int_xtalk_reg_scale(1), ///< int_xtalk_reg_scale;Register Addresses: 46[16:14];allows scaling of the meaning of ixtalk register. 0- 2^0, 2^1, 2^2, 2^3 etc. 00180 iphase_xtalk_int_reg(1), ///< iphase_xtalk_int_reg;Register Addresses: 61[15:0];inphase component for intrinsic xtalk 00181 qphase_xtalk_int_reg(1), ///< qphase_xtalk_int_reg;Register Addresses: 62[15:0];quadrature component for intrinsic xtalk 00182 illum_xtalk_calib(1), ///< illum_xtalk_calib;Register Addresses: 46[12:12];puts the device into optical calibration mode. 00183 illum_xtalk_reg_scale(1), ///< illum_xtalk_reg_scale;Register Addresses: 46[19:17];allows scaling of the meaning of oxtalk register. 0- 2^0, 2^2, 2^4, 2^8. 00184 use_xtalk_filt_illum(1), ///< use_xtalk_filt_illum;Register Addresses: 46[7:7]; 00185 use_xtalk_reg_illum(1), ///< use_xtalk_reg_illum;Register Addresses: 46[8:8];For optical default is to use the register values. 00186 iphase_xtalk_reg_hdr0_tx0(1), ///< iphase_xtalk_reg_hdr0_tx0;Register Addresses: 47[15:0];inphase component of the xtalk for hdr0/led0 00187 qphase_xtalk_reg_hdr0_tx0(1), ///< qphase_xtalk_reg_hdr0_tx0;Register Addresses: 48[15:0];quadrature component of the xtalk for hdr0/led0 00188 iphase_xtalk_reg_hdr1_tx0(1), ///< iphase_xtalk_reg_hdr1_tx0;Register Addresses: 49[15:0]; 00189 qphase_xtalk_reg_hdr1_tx0(1), ///< qphase_xtalk_reg_hdr1_tx0;Register Addresses: 50[15:0]; 00190 iphase_xtalk_reg_hdr0_tx1(1), ///< iphase_xtalk_reg_hdr0_tx1;Register Addresses: 51[15:0]; 00191 qphase_xtalk_reg_hdr0_tx1(1), ///< qphase_xtalk_reg_hdr0_tx1;Register Addresses: 52[15:0]; 00192 iphase_xtalk_reg_hdr1_tx1(1), ///< iphase_xtalk_reg_hdr1_tx1;Register Addresses: 53[15:0]; 00193 qphase_xtalk_reg_hdr1_tx1(1), ///< qphase_xtalk_reg_hdr1_tx1;Register Addresses: 54[15:0]; 00194 iphase_xtalk_reg_hdr0_tx2(1), ///< iphase_xtalk_reg_hdr0_tx2;Register Addresses: 55[15:0]; 00195 qphase_xtalk_reg_hdr0_tx2(1), ///< qphase_xtalk_reg_hdr0_tx2;Register Addresses: 56[15:0]; 00196 iphase_xtalk_reg_hdr1_tx2(1), ///< iphase_xtalk_reg_hdr1_tx2;Register Addresses: 57[15:0]; 00197 qphase_xtalk_reg_hdr1_tx2(1), ///< qphase_xtalk_reg_hdr1_tx2;Register Addresses: 58[15:0]; 00198 en_temp_xtalk_corr(1), ///< en_temp_xtalk_corr;Register Addresses: 58[16:16]; 00199 scale_temp_coeff_xtalk(1), ///< scale_temp_coeff_xtalk;Register Addresses: 58[19:17];Allows programmability on the temp_coefficients range and precision. 00200 temp_coeff_xtalk_iphase_hdr0_tx0(1), ///< temp_coeff_xtalk_iphase_hdr0_tx0;Register Addresses: 56[23:16]; 00201 temp_coeff_xtalk_qphase_hdr0_tx0(1), ///< temp_coeff_xtalk_qphase_hdr0_tx0;Register Addresses: 57[23:16]; 00202 temp_coeff_xtalk_iphase_hdr1_tx0(1), ///< temp_coeff_xtalk_iphase_hdr1_tx0;Register Addresses: 94[15:8]; 00203 temp_coeff_xtalk_qphase_hdr1_tx0(1), ///< temp_coeff_xtalk_qphase_hdr1_tx0;Register Addresses: 96[7:0]; 00204 temp_coeff_xtalk_iphase_hdr0_tx1(1), ///< temp_coeff_xtalk_iphase_hdr0_tx1;Register Addresses: 94[23:16]; 00205 temp_coeff_xtalk_qphase_hdr0_tx1(1), ///< temp_coeff_xtalk_qphase_hdr0_tx1;Register Addresses: 96[15:8]; 00206 temp_coeff_xtalk_iphase_hdr1_tx1(1), ///< temp_coeff_xtalk_iphase_hdr1_tx1;Register Addresses: 95[7:0]; 00207 temp_coeff_xtalk_qphase_hdr1_tx1(1), ///< temp_coeff_xtalk_qphase_hdr1_tx1;Register Addresses: 96[23:16]; 00208 temp_coeff_xtalk_iphase_hdr0_tx2(1), ///< temp_coeff_xtalk_iphase_hdr0_tx2;Register Addresses: 95[15:8]; 00209 temp_coeff_xtalk_qphase_hdr0_tx2(1), ///< temp_coeff_xtalk_qphase_hdr0_tx2;Register Addresses: 97[7:0]; 00210 temp_coeff_xtalk_iphase_hdr1_tx2(1), ///< temp_coeff_xtalk_iphase_hdr1_tx2;Register Addresses: 95[23:16]; 00211 temp_coeff_xtalk_qphase_hdr1_tx2(1), ///< temp_coeff_xtalk_qphase_hdr1_tx2;Register Addresses: 97[15:8]; 00212 temp_coeff_illum_xtalk_iphase_hdr0_tx0(1), ///< temp_coeff_illum_xtalk_iphase_hdr0_tx0;Register Addresses: 54[23:16]; 00213 temp_coeff_illum_xtalk_qphase_hdr0_tx0(1), ///< temp_coeff_illum_xtalk_qphase_hdr0_tx0;Register Addresses: 55[23:16]; 00214 temp_coeff_illum_xtalk_iphase_hdr1_tx0(1), ///< temp_coeff_illum_xtalk_iphase_hdr1_tx0;Register Addresses: 91[7:0]; 00215 temp_coeff_illum_xtalk_iphase_hdr0_tx1(1), ///< temp_coeff_illum_xtalk_iphase_hdr0_tx1;Register Addresses: 91[15:8]; 00216 temp_coeff_illum_xtalk_iphase_hdr1_tx1(1), ///< temp_coeff_illum_xtalk_iphase_hdr1_tx1;Register Addresses: 91[23:16]; 00217 temp_coeff_illum_xtalk_iphase_hdr0_tx2(1), ///< temp_coeff_illum_xtalk_iphase_hdr0_tx2;Register Addresses: 92[7:0]; 00218 temp_coeff_illum_xtalk_iphase_hdr1_tx2(1), ///< temp_coeff_illum_xtalk_iphase_hdr1_tx2;Register Addresses: 92[15:8]; 00219 temp_coeff_illum_xtalk_qphase_hdr1_tx0(1), ///< temp_coeff_illum_xtalk_qphase_hdr1_tx0;Register Addresses: 92[23:16]; 00220 temp_coeff_illum_xtalk_qphase_hdr0_tx1(1), ///< temp_coeff_illum_xtalk_qphase_hdr0_tx1;Register Addresses: 93[7:0]; 00221 temp_coeff_illum_xtalk_qphase_hdr1_tx1(1), ///< temp_coeff_illum_xtalk_qphase_hdr1_tx1;Register Addresses: 93[15:8]; 00222 temp_coeff_illum_xtalk_qphase_hdr0_tx2(1), ///< temp_coeff_illum_xtalk_qphase_hdr0_tx2;Register Addresses: 93[23:16]; 00223 temp_coeff_illum_xtalk_qphase_hdr1_tx2(1), ///< temp_coeff_illum_xtalk_qphase_hdr1_tx2;Register Addresses: 94[7:0]; 00224 amb_xtalk_qphase_coeff(1), ///< amb_xtalk_qphase_coeff;Register Addresses: 12[15:8];reflects the variation of quad component. 00225 amb_xtalk_iphase_coeff(1), ///< amb_xtalk_iphase_coeff;Register Addresses: 12[7:0];reflect the variation of optical crosstalk inphase component. 00226 scale_amb_coeff_xtalk(1), ///< scale_amb_coeff_xtalk;Register Addresses: 58[22:20];Ambient xtalk mode. Provides range/precision for ambient correction. 00227 en_phase_corr(1), ///< en_phase_corr;Register Addresses: 67[0:0];enables phase correction from the values programmed. 00228 phase_offset_hdr0_tx0(1), ///< phase_offset_hdr0_tx0;Register Addresses: 66[15:0];phase_offset for freq1 00229 phase_offset_hdr1_tx0(1), ///< phase_offset_hdr1_tx0;Register Addresses: 81[15:0]; 00230 phase_offset_hdr0_tx1(1), ///< phase_offset_hdr0_tx1;Register Addresses: 82[15:0]; 00231 phase_offset_hdr1_tx1(1), ///< phase_offset_hdr1_tx1;Register Addresses: 83[15:0]; 00232 phase_offset_hdr0_tx2(1), ///< phase_offset_hdr0_tx2;Register Addresses: 84[15:0]; 00233 phase_offset_hdr1_tx2(1), ///< phase_offset_hdr1_tx2;Register Addresses: 85[15:0]; 00234 reverse_phase_before_offset(1), ///< reverse_phase_before_offset;Register Addresses: 67[9:9]; 00235 phase2_offset_hdr0_tx0(1), ///< phase2_offset_hdr0_tx0;Register Addresses: 68[15:0];phase offset for freq2 00236 phase2_offset_hdr1_tx0(1), ///< phase2_offset_hdr1_tx0;Register Addresses: 86[15:0]; 00237 phase2_offset_hdr0_tx1(1), ///< phase2_offset_hdr0_tx1;Register Addresses: 87[15:0]; 00238 phase2_offset_hdr1_tx1(1), ///< phase2_offset_hdr1_tx1;Register Addresses: 88[15:0]; 00239 phase2_offset_hdr0_tx2(1), ///< phase2_offset_hdr0_tx2;Register Addresses: 89[15:0]; 00240 phase2_offset_hdr1_tx2(1), ///< phase2_offset_hdr1_tx2;Register Addresses: 90[15:0]; 00241 en_temp_corr(1), ///< en_temp_corr;Register Addresses: 67[1:1];enables temperature correction for phase 00242 scale_phase_temp_coeff(1), ///< scale_phase_temp_coeff;Register Addresses: 67[8:6];changes the meaning of coefficients related to phase correction. 00243 tmain_calib_hdr0_tx0(1), ///< tmain_calib_hdr0_tx0;Register Addresses: 71[11:0];calibrated temperature for main temp sensor.Default is 2048 because internally it is treated as offset binary 00244 temp_coeff_main_hdr0_tx0(1), ///< temp_coeff_main_hdr0_tx0;Register Addresses: 69[11:0];temperature coefficient for phase correction for main temp. By default means phase change for 64 degrees of temperature. 00245 tmain_calib_hdr1_tx0(1), ///< tmain_calib_hdr1_tx0;Register Addresses: 72[11:0]; 00246 temp_coeff_main_hdr1_tx0(1), ///< temp_coeff_main_hdr1_tx0;Register Addresses: 45[11:0]; 00247 tmain_calib_hdr0_tx1(1), ///< tmain_calib_hdr0_tx1;Register Addresses: 73[11:0]; 00248 temp_coeff_main_hdr0_tx1(1), ///< temp_coeff_main_hdr0_tx1;Register Addresses: 45[23:12]; 00249 tmain_calib_hdr1_tx1(1), ///< tmain_calib_hdr1_tx1;Register Addresses: 65[23:12]; 00250 temp_coeff_main_hdr1_tx1(2), ///< temp_coeff_main_hdr1_tx1;Register Addresses: 47[23:16], 48[23:20]; 00251 tmain_calib_hdr0_tx2(1), ///< tmain_calib_hdr0_tx2;Register Addresses: 63[11:0]; 00252 temp_coeff_main_hdr0_tx2(2), ///< temp_coeff_main_hdr0_tx2;Register Addresses: 49[23:16], 50[23:20]; 00253 tmain_calib_hdr1_tx2(1), ///< tmain_calib_hdr1_tx2;Register Addresses: 69[23:12]; 00254 temp_coeff_main_hdr1_tx2(2), ///< temp_coeff_main_hdr1_tx2;Register Addresses: 51[23:16], 52[23:20]; 00255 tillum_calib_hdr0_tx0(1), ///< tillum_calib_hdr0_tx0;Register Addresses: 71[23:12];calibrated temp for tillum. Default is 2048 because internally it is treated as offset binary 00256 temp_coeff_illum_hdr0_tx0(1), ///< temp_coeff_illum_hdr0_tx0;Register Addresses: 70[11:0];temperature coefficient for phase correction for illum temp. By default means phase change for 64 degrees of temperature. 00257 tillum_calib_hdr1_tx0(1), ///< tillum_calib_hdr1_tx0;Register Addresses: 72[23:12]; 00258 temp_coeff_illum_hdr1_tx0(2), ///< temp_coeff_illum_hdr1_tx0;Register Addresses: 81[23:16], 82[23:20]; 00259 tillum_calib_hdr0_tx1(1), ///< tillum_calib_hdr0_tx1;Register Addresses: 73[23:12]; 00260 temp_coeff_illum_hdr0_tx1(2), ///< temp_coeff_illum_hdr0_tx1;Register Addresses: 83[23:16], 84[23:20]; 00261 tillum_calib_hdr1_tx1(1), ///< tillum_calib_hdr1_tx1;Register Addresses: 67[23:12]; 00262 temp_coeff_illum_hdr1_tx1(2), ///< temp_coeff_illum_hdr1_tx1;Register Addresses: 85[23:16], 86[23:20]; 00263 tillum_calib_hdr0_tx2(1), ///< tillum_calib_hdr0_tx2;Register Addresses: 63[23:12]; 00264 temp_coeff_illum_hdr0_tx2(2), ///< temp_coeff_illum_hdr0_tx2;Register Addresses: 87[23:16], 88[23:20]; 00265 tillum_calib_hdr1_tx2(1), ///< tillum_calib_hdr1_tx2;Register Addresses: 70[23:12]; 00266 temp_coeff_illum_hdr1_tx2(2), ///< temp_coeff_illum_hdr1_tx2;Register Addresses: 89[23:16], 90[23:20]; 00267 amb_sat_thr(1), ///< amb_sat_thr;Register Addresses: 13[16:7];the threshold which is used to detect the ambient overload. Default is kept at highest.;Threshold set for 1v on the ambient dac resistor. 512x3/8xIR. 00268 amb_calib(1), ///< amb_calib;Register Addresses: 11[23:14];the ambient at which device is calibrated for optical xtalk/phase offset etc. 00269 amb_phase_corr_pwl_coeff0(1), ///< amb_phase_corr_pwl_coeff0;Register Addresses: 12[23:16];Captures the drift in the phase wrto ambient. Can be a negative number to reflect inverse relationship. The number is divided by 2^5 to get the actual value. 00270 amb_phase_corr_pwl_x0(1), ///< amb_phase_corr_pwl_x0;Register Addresses: 184[9:0]; 00271 amb_phase_corr_pwl_x1(1), ///< amb_phase_corr_pwl_x1;Register Addresses: 184[19:10]; 00272 amb_phase_corr_pwl_x2(1), ///< amb_phase_corr_pwl_x2;Register Addresses: 185[9:0]; 00273 amb_phase_corr_pwl_coeff1(1), ///< amb_phase_corr_pwl_coeff1;Register Addresses: 180[7:0];The first coefficient is assumed to be the original one 00274 amb_phase_corr_pwl_coeff2(1), ///< amb_phase_corr_pwl_coeff2;Register Addresses: 180[15:8]; 00275 amb_phase_corr_pwl_coeff3(1), ///< amb_phase_corr_pwl_coeff3;Register Addresses: 180[23:16]; 00276 scale_amb_phase_corr_coeff(1), ///< scale_amb_phase_corr_coeff;Register Addresses: 181[2:0];Scales the gain/vs accuracy. 00277 temp_coeff_illum_square_hdr0(1), ///< temp_coeff_illum_square_hdr0;Register Addresses: 182[7:0]; 00278 temp_coeff_illum_square_hdr1(1), ///< temp_coeff_illum_square_hdr1;Register Addresses: 182[15:8]; 00279 temp_coeff_main_square_hdr0(1), ///< temp_coeff_main_square_hdr0;Register Addresses: 183[7:0]; 00280 temp_coeff_main_square_hdr1(1), ///< temp_coeff_main_square_hdr1;Register Addresses: 183[15:8]; 00281 scale_phase_temp_corr_square(1), ///< scale_phase_temp_corr_square;Register Addresses: 181[5:3];scales square correction range/accuracy. 00282 en_nl_corr(1), ///< en_nl_corr;Register Addresses: 74[0:0];enables harmonic/nonlinear correction for phase. 00283 a1_coeff_hdr0_tx0(1), ///< a1_coeff_hdr0_tx0;Register Addresses: 75[15:0]; 00284 a2_coeff_hdr0_tx0(1), ///< a2_coeff_hdr0_tx0;Register Addresses: 76[15:0]; 00285 a3_coeff_hdr0_tx0(1), ///< a3_coeff_hdr0_tx0;Register Addresses: 77[15:0]; 00286 a4_coeff_hdr0_tx0(1), ///< a4_coeff_hdr0_tx0;Register Addresses: 78[15:0]; 00287 scale_nl_corr_coeff(1), ///< scale_nl_corr_coeff;Register Addresses: 74[19:18];changes the meaning of the nonlinear coefficients.; 00288 a0_coeff_hdr0_tx0(1), ///< a0_coeff_hdr0_tx0;Register Addresses: 74[17:2]; 00289 a0_coeff_hdr1_tx0(1), ///< a0_coeff_hdr1_tx0;Register Addresses: 162[15:0]; 00290 a0_coeff_hdr0_tx1(1), ///< a0_coeff_hdr0_tx1;Register Addresses: 163[15:0]; 00291 a0_coeff_hdr1_tx1(1), ///< a0_coeff_hdr1_tx1;Register Addresses: 164[15:0]; 00292 a0_coeff_hdr0_tx2(1), ///< a0_coeff_hdr0_tx2;Register Addresses: 165[15:0]; 00293 a0_coeff_hdr1_tx2(1), ///< a0_coeff_hdr1_tx2;Register Addresses: 166[15:0]; 00294 a1_coeff_hdr1_tx0(1), ///< a1_coeff_hdr1_tx0;Register Addresses: 167[15:0]; 00295 a1_coeff_hdr0_tx1(1), ///< a1_coeff_hdr0_tx1;Register Addresses: 168[15:0]; 00296 a1_coeff_hdr1_tx1(1), ///< a1_coeff_hdr1_tx1;Register Addresses: 169[15:0]; 00297 a1_coeff_hdr0_tx2(1), ///< a1_coeff_hdr0_tx2;Register Addresses: 170[15:0]; 00298 a1_coeff_hdr1_tx2(1), ///< a1_coeff_hdr1_tx2;Register Addresses: 171[15:0]; 00299 a2_coeff_hdr1_tx0(1), ///< a2_coeff_hdr1_tx0;Register Addresses: 172[15:0]; 00300 a2_coeff_hdr0_tx1(1), ///< a2_coeff_hdr0_tx1;Register Addresses: 173[15:0]; 00301 a2_coeff_hdr1_tx1(1), ///< a2_coeff_hdr1_tx1;Register Addresses: 174[15:0]; 00302 a2_coeff_hdr0_tx2(1), ///< a2_coeff_hdr0_tx2;Register Addresses: 175[15:0]; 00303 a2_coeff_hdr1_tx2(1), ///< a2_coeff_hdr1_tx2;Register Addresses: 176[15:0]; 00304 a3_coeff_hdr1_tx0(1), ///< a3_coeff_hdr1_tx0;Register Addresses: 177[15:0]; 00305 a3_coeff_hdr0_tx1(2), ///< a3_coeff_hdr0_tx1;Register Addresses: 162[23:16], 163[23:16]; 00306 a3_coeff_hdr1_tx1(2), ///< a3_coeff_hdr1_tx1;Register Addresses: 164[23:16], 165[23:16]; 00307 a3_coeff_hdr0_tx2(2), ///< a3_coeff_hdr0_tx2;Register Addresses: 166[23:16], 167[23:16]; 00308 a3_coeff_hdr1_tx2(2), ///< a3_coeff_hdr1_tx2;Register Addresses: 168[23:16], 169[23:16]; 00309 a4_coeff_hdr1_tx0(2), ///< a4_coeff_hdr1_tx0;Register Addresses: 170[23:16], 171[23:16]; 00310 a4_coeff_hdr0_tx1(2), ///< a4_coeff_hdr0_tx1;Register Addresses: 172[23:16], 173[23:16]; 00311 a4_coeff_hdr1_tx1(2), ///< a4_coeff_hdr1_tx1;Register Addresses: 174[23:16], 175[23:16]; 00312 a4_coeff_hdr0_tx2(2), ///< a4_coeff_hdr0_tx2;Register Addresses: 176[23:16], 177[23:16]; 00313 a4_coeff_hdr1_tx2(1), ///< a4_coeff_hdr1_tx2;Register Addresses: 178[15:0]; 00314 tillum(1), ///< tillum;Register Addresses: 4[19:8];The value of illum-temperature register. 00315 tsens_slave0(1), ///< tsens_slave0;Register Addresses: 2[6:0];slave address of the led0 tsensor 00316 tsens_slave1(1), ///< tsens_slave1;Register Addresses: 2[13:7];slave address of the led1 tsensor 00317 tsens_slave2(1), ///< tsens_slave2;Register Addresses: 2[20:14];slave address of the led2 tsensor 00318 config_tillum_msb(1), ///< config_tillum_msb;Register Addresses: 7[23:20]; 00319 en_tillum_12b(1), ///< en_tillum_12b;Register Addresses: 13[23:23];While interfacing with the TMP02 type tempsensor, this bit needs to be set to swap bytes to allow different read format. 00320 tillum_unsigned(1), ///< tillum_unsigned;Register Addresses: 4[23:23];This bit is set '1' when temperature given by tmain/tillum sensor is in unsigned format. 00321 temp_avg_illum(1), ///< temp_avg_illum;Register Addresses: 2[23:22];Based on this, temperature is averaged to remove quantization errors on temperature. 00322 en_tsens_read_fvd(1), ///< en_tsens_read_fvd;Register Addresses: 3[18:18];If this bit is set tmain temperature is read every frame. Other wise it is read based on a register trigger. 00323 en_tillum_read(1), ///< en_tillum_read;Register Addresses: 2[21:21];Enable i2c read of appropriate illum led. If this bit is not set illumination driver temperature is not read. 00324 eeprom_read_trig(1), ///< eeprom_read_trig;Register Addresses: 1[0:0];Used to read efuse values into the chain using register trigger 00325 swap_read_data(1), ///< swap_read_data;Register Addresses: 1[1:1];swaps/reverse the data read by i2c-host. 00326 eeprom_start_reg_addr(1), ///< eeprom_start_reg_addr;Register Addresses: 1[16:9];The first byte written while reading from the efuse. This will typically be 0. At startup there is no way to program this. 00327 frame_vd_trig(1), ///< frame_vd_trig;Register Addresses: 1[17:17];when this bit is '1' i2c host is triggered every frame vd. Else it is triggered based on the i2c_trig_reg. 00328 i2c_trig_reg(1), ///< i2c_trig_reg;Register Addresses: 1[18:18];The trigger register for i2c transaction. 00329 i2c_en(1), ///< i2c_en;Register Addresses: 1[19:19];Enables the i2c host operation. Does not control the init load. 00330 i2c_rw(1), ///< i2c_rw;Register Addresses: 1[21:20];Choses the r/w for i2c host operation.;By default it reads temperature sensor. 00331 i2c_read_data(1), ///< i2c_read_data;Register Addresses: 3[7:0];The hosts read data. 00332 i2c_write_data1(1), ///< i2c_write_data1;Register Addresses: 3[16:9];The address where the read would start. Normally in temperature sensor read this is not required to be programmed. 00333 i2c_num_tran(1), ///< i2c_num_tran;Register Addresses: 3[17:17];The number of transactions. Either 1 or 2. 00334 en_eeprom_read(1), ///< en_eeprom_read;Register Addresses: 1[23:23];Disables the gating of auto_load clock after init_load_done. Should be used if register triggering has to work. 00335 init_load_done(1), ///< init_load_done;Register Addresses: 3[8:8];Can be used to check whether initial auto_load is successful or not. 00336 addr_slave_eeprom(1), ///< addr_slave_eeprom;Register Addresses: 1[8:2]; 00337 i2c_num_bytes_tran1(1), ///< i2c_num_bytes_tran1;Register Addresses: 7[17:16];Number of bytes used in the tran2 of i2c transaction. 00338 i2c_num_bytes_tran2(1), ///< i2c_num_bytes_tran2;Register Addresses: 5[23:22];Number of bytes used in the tran2 of i2c transaction. 00339 i2c_write_data2(1), ///< i2c_write_data2;Register Addresses: 7[7:0]; 00340 i2c_sel_read_bytes(1), ///< i2c_sel_read_bytes;Register Addresses: 7[19:18];choses which byte of i2c_read register to be read. 00341 i2c_cont_rw(1), ///< i2c_cont_rw;Register Addresses: 0[6:6]; 00342 dis_ovldet(1), ///< dis_ovldet;Register Addresses: 101[23:23];to disable overload detection 00343 prog_ovldet_refp(1), ///< prog_ovldet_refp;Register Addresses: 100[20:18];To program OVL_DET REFP 00344 prog_ovldet_refm(1), ///< prog_ovldet_refm;Register Addresses: 100[23:21];To program OVL_DET REFM 00345 iamb_max_sel(1), ///< iamb_max_sel;Register Addresses: 114[7:4];selects the value of DAC resistor 00346 tm_vrefp_diode(1), ///< tm_vrefp_diode;Register Addresses: 109[2:0];To program the bias voltage INP 00347 tm_vrefm_diode(1), ///< tm_vrefm_diode;Register Addresses: 109[5:3];To program the bias voltage INM 00348 gpo1_mux_sel(1), ///< gpo1_mux_sel;Register Addresses: 120[8:6]; 00349 gpio1_obuf_en(1), ///< gpio1_obuf_en;Register Addresses: 120[12:12]; 00350 gpio1_ibuf_en(1), ///< gpio1_ibuf_en;Register Addresses: 120[13:13]; 00351 gpo2_mux_sel(1), ///< gpo2_mux_sel;Register Addresses: 120[11:9]; 00352 gpio2_obuf_en(1), ///< gpio2_obuf_en;Register Addresses: 120[15:15]; 00353 gpio2_ibuf_en(1), ///< gpio2_ibuf_en;Register Addresses: 120[16:16]; 00354 gpo3_mux_sel(1), ///< gpo3_mux_sel;Register Addresses: 120[2:0]; 00355 sel_gp3_on_sdam(1), ///< sel_gp3_on_sdam;Register Addresses: 120[22:22]; 00356 dealias_en(1), ///< dealias_en;Register Addresses: 113[1:1];To enable Dealias mode to get different Modulation freq close to 40MHz, ;34.3 MHz & 48 MHz. 00357 dealias_freq(1), ///< dealias_freq;Register Addresses: 113[2:2];Changes o/p freq in dealias mode;- only when dealais mode is enabled (TM_CLKGENless than2greater than is set to '1'). 00358 shift_illum_phase(1), ///< shift_illum_phase;Register Addresses: 113[6:3];Shift bits to get different LED_CLK phases in calib mode.;;80M mode:16phases, 22.5 deg separation(360/16)-6.25n separation;;40M mode:16phases, 45 deg separation(360/8)-12.5n separation;;Basically 40M mode MSB bit is unused. 00359 shut_clocks(1), ///< shut_clocks;Register Addresses: 113[8:8];to shut down all 20M, 10M clock switching 00360 invert_tg_clk(1), ///< invert_tg_clk;Register Addresses: 113[9:9];to invert tg_clk for timing requirements 00361 invert_afe_clk(1), ///< invert_afe_clk;Register Addresses: 113[11:11]; 00362 dis_illum_clk_tx(1), ///< dis_illum_clk_tx;Register Addresses: 113[12:12];Disable LED clk going to transmitter 00363 en_illum_clk_gpio(1), ///< en_illum_clk_gpio;Register Addresses: 113[16:16];Disable LED CLK going to GPIO 00364 illum_clk_gpio_mode(1), ///< illum_clk_gpio_mode;Register Addresses: 113[15:15];When this bit is '1', illum_en gating led_clk going to GPIO is masked.; 00365 unmask_illumen_intxtalk(1), ///< unmask_illumen_intxtalk;Register Addresses: 113[17:17];Mask internal crosstalk signal gating illum_en. 00366 temp_offset(1), ///< temp_offset;Register Addresses: 110[16:8];temperature offset 00367 en_temp_conv(1), ///< en_temp_conv;Register Addresses: 110[19:19];To enable temperature conversion 00368 calib_curr1_DAC_I(1), ///< calib_curr1_DAC_I; Register Address 116[3:0] 00369 calib_curr1_DAC_Q(1), ///< calib_curr1_DAC_Q; Register Address 116[7:4] 00370 calib_curr1_en_I(1), ///< calib_curr1_en_I; Register Address 116[8:8] 00371 calib_curr1_en_Q(1), ///< calib_curr1_en_Q; Register Address 116[9:9] 00372 calib_curr1_inv_CLK_I(1), ///< calib_curr1_inv_CLK_I; Register Address 116[10:10] 00373 calib_curr1_inv_CLK_Q(1), ///< calib_curr1_inv_CLK_Q; Register Address 116[11:11] 00374 calib_curr1_sel_CLK_I(1), ///< calib_curr1_sel_CLK_I; Register Address 116[12:12] 00375 calib_curr1_gain_sel(1), ///< calib_curr1_gain_sel; Register Address 116[14:13] 00376 calib_curr1_spare(1), ///< calib_curr1_spare; Register Address 116[15:15] 00377 dis_glb_pd_refsys(1), ///< dis_glb_pd_refsys;Register Addresses: 118[0:0]; 00378 dis_glb_pd_temp_sens(1), ///< dis_glb_pd_temp_sens;Register Addresses: 118[1:1]; 00379 dis_glb_pd_illum_drv(1), ///< dis_glb_pd_illum_drv;Register Addresses: 118[2:2]; 00380 dis_glb_pd_afe(1), ///< dis_glb_pd_afe;Register Addresses: 118[3:3]; 00381 dis_glb_pd_afe_dac(1), ///< dis_glb_pd_afe_dac;Register Addresses: 118[4:4]; 00382 dis_glb_pd_amb_dac(1), ///< dis_glb_pd_amb_dac;Register Addresses: 118[5:5]; 00383 dis_glb_pd_amb_adc(1), ///< dis_glb_pd_amb_adc;Register Addresses: 118[6:6]; 00384 dis_glb_pd_test_curr(1), ///< dis_glb_pd_test_curr;Register Addresses: 118[7:7]; 00385 dis_glb_pd_osc(1), ///< dis_glb_pd_osc;Register Addresses: 118[8:8]; 00386 dis_glb_pd_i2chost(1), ///< dis_glb_pd_i2chost;Register Addresses: 118[9:9]; 00387 pdn_global(1), ///< pdn_global;Register Addresses: 118[11:11]; 00388 en_dyn_pd_refsys(1), ///< en_dyn_pd_refsys;Register Addresses: 119[0:0]; 00389 en_dyn_pd_temp_sens(1), ///< en_dyn_pd_temp_sens;Register Addresses: 119[1:1]; 00390 en_dyn_pd_illum_drv(1), ///< en_dyn_pd_illum_drv;Register Addresses: 119[2:2]; 00391 en_dyn_pd_afe(1), ///< en_dyn_pd_afe;Register Addresses: 119[3:3]; 00392 en_dyn_pd_afe_dac(1), ///< en_dyn_pd_afe_dac;Register Addresses: 119[4:4]; 00393 en_dyn_pd_amb_dac(1), ///< en_dyn_pd_amb_dac;Register Addresses: 119[5:5]; 00394 en_dyn_pd_amb_adc(1), ///< en_dyn_pd_amb_adc;Register Addresses: 119[6:6]; 00395 en_dyn_pd_test_curr(1), ///< en_dyn_pd_test_curr;Register Addresses: 119[7:7]; 00396 en_dyn_pd_osc(1), ///< en_dyn_pd_osc;Register Addresses: 119[8:8]; 00397 en_dyn_pd_i2chost_osc(1), ///< en_dyn_pd_i2chost_osc;Register Addresses: 119[9:9]; 00398 TX0_PIN_CONFIG(1), ///< TX0_PIN_CONFIG;Register Addresses: 122[5:4]; 00399 TX1_PIN_CONFIG(1), ///< TX1_PIN_CONFIG;Register Addresses: 122[1:0]; 00400 TX2_PIN_CONFIG(1), ///< TX2_PIN_CONFIG;Register Addresses: 122[3:2]; 00401 EN_TX_CLKB(1), ///< EN_TX_CLKB;Register Addresses: 121[0:0]; 00402 EN_TX_CLKZ(1), ///< EN_TX_CLKZ;Register Addresses: 121[2:2]; 00403 sel_illum_tx0_on_tx1(1), ///< sel_illum_tx0_on_tx1;Register Addresses: 121[3:3];Force ILLUM_EN_0 (TX0) onto ILLUM_EN_1 (TX1). This mode is required to enable static LED drive mode. 00404 ILLUM_DC_CURR_DAC(1), ///< ILLUM_DC_CURR_DAC;Register Addresses: 121[11:8];0.5mA*register setting 00405 PDN_ILLUM_DC_CURR(1), ///< PDN_ILLUM_DC_CURR;Register Addresses: 121[12:12]; 00406 FEEDBACK_CONT_MODE(1), ///< FEEDBACK_CONT_MODE;Register Addresses: 121[13:13]; 00407 PDN_ILLUM_DRV(1), ///< PDN_ILLUM_DRV;Register Addresses: 121[19:19]; 00408 EN_TX_DC_CURR_ALL(1), ///< EN_TX_DC_CURR_ALL;Register Addresses: 121[4:4]; 00409 EN_CTALK_FB_CLK(1), ///< EN_CTALK_FB_CLK; Register Address 122[11:11] 00410 EN_CALIB_CLK(1) ///< EN_CALIB_CLK; Register Address 122[1:1] 00411 { 00412 //Initialization for register dig_gpo_sel0 00413 this->dig_gpo_sel0.address[0] = 0x0b; ///< Address=11 00414 this->dig_gpo_sel0.msb[0] = 3; 00415 this->dig_gpo_sel0.lsb[0] = 0; 00416 00417 //Initialization for register dig_gpo_sel1 00418 this->dig_gpo_sel1.address[0] = 0x0b; ///< Address=11 00419 this->dig_gpo_sel1.msb[0] = 7; 00420 this->dig_gpo_sel1.lsb[0] = 4; 00421 00422 //Initialization for register dig_gpo_sel2 00423 this->dig_gpo_sel2.address[0] = 0x0b; ///< Address=11 00424 this->dig_gpo_sel2.msb[0] = 13; 00425 this->dig_gpo_sel2.lsb[0] = 10; 00426 00427 //Initialization for register dis_ovl_gating 00428 this->dis_ovl_gating.address[0] = 0x11; ///< Address=17 00429 this->dis_ovl_gating.msb[0] = 15; 00430 this->dis_ovl_gating.lsb[0] = 15; 00431 00432 //Initialization for register phase_out 00433 this->phase_out.address[0] = 0x08; ///< Address=8 00434 this->phase_out.msb[0] = 15; 00435 this->phase_out.lsb[0] = 0; 00436 00437 //Initialization for register phase_overflow 00438 this->phase_overflow.address[0] = 0x08; ///< Address=8 00439 this->phase_overflow.msb[0] = 16; 00440 this->phase_overflow.lsb[0] = 16; 00441 00442 //Initialization for register hdr_mode 00443 this->hdr_mode.address[0] = 0x08; ///< Address=8 00444 this->hdr_mode.msb[0] = 17; 00445 this->hdr_mode.lsb[0] = 17; 00446 00447 //Initialization for register tx_channel 00448 this->tx_channel.address[0] = 0x08; ///< Address=8 00449 this->tx_channel.msb[0] = 19; 00450 this->tx_channel.lsb[0] = 18; 00451 00452 //Initialization for register frame_status 00453 this->frame_status.address[0] = 0x08; ///< Address=8 00454 this->frame_status.msb[0] = 20; 00455 this->frame_status.lsb[0] = 20; 00456 00457 //Initialization for register mod_freq 00458 this->mod_freq.address[0] = 0x08; ///< Address=8 00459 this->mod_freq.msb[0] = 21; 00460 this->mod_freq.lsb[0] = 21; 00461 00462 //Initialization for register frame_count0 00463 this->frame_count0.address[0] = 0x08; ///< Address=8 00464 this->frame_count0.msb[0] = 23; 00465 this->frame_count0.lsb[0] = 23; 00466 00467 //Initialization for register amp_out 00468 this->amp_out.address[0] = 0x09; ///< Address=9 00469 this->amp_out.msb[0] = 15; 00470 this->amp_out.lsb[0] = 0; 00471 00472 //Initialization for register frame_count1 00473 this->frame_count1.address[0] = 0x09; ///< Address=9 00474 this->frame_count1.msb[0] = 17; 00475 this->frame_count1.lsb[0] = 16; 00476 00477 //Initialization for register sig_ovl_flag 00478 this->sig_ovl_flag.address[0] = 0x09; ///< Address=9 00479 this->sig_ovl_flag.msb[0] = 18; 00480 this->sig_ovl_flag.lsb[0] = 18; 00481 00482 //Initialization for register dealias_bin 00483 this->dealias_bin.address[0] = 0x09; ///< Address=9 00484 this->dealias_bin.msb[0] = 23; 00485 this->dealias_bin.lsb[0] = 20; 00486 00487 //Initialization for register frame_count2 00488 this->frame_count2.address[0] = 0x0a; ///< Address=10 00489 this->frame_count2.msb[0] = 1; 00490 this->frame_count2.lsb[0] = 0; 00491 00492 //Initialization for register amb_data 00493 this->amb_data.address[0] = 0x0a; ///< Address=10 00494 this->amb_data.msb[0] = 11; 00495 this->amb_data.lsb[0] = 2; 00496 00497 //Initialization for register tmain 00498 this->tmain.address[0] = 0x0a; ///< Address=10 00499 this->tmain.msb[0] = 23; 00500 this->tmain.lsb[0] = 12; 00501 00502 //Initialization for register amplitude_min_thr 00503 this->amplitude_min_thr.address[1] = 0x10; ///< Address=16 00504 this->amplitude_min_thr.msb[1] = 23; 00505 this->amplitude_min_thr.lsb[1] = 16; 00506 this->amplitude_min_thr.address[0] = 0x11; ///< Address=17 00507 this->amplitude_min_thr.msb[0] = 23; 00508 this->amplitude_min_thr.lsb[0] = 16; 00509 00510 //Initialization for register amb_ovl_flag 00511 this->amb_ovl_flag.address[0] = 0x08; ///< Address=8 00512 this->amb_ovl_flag.msb[0] = 22; 00513 this->amb_ovl_flag.lsb[0] = 22; 00514 00515 //Initialization for register phase_overflow_f2 00516 this->phase_overflow_f2.address[0] = 0x09; ///< Address=9 00517 this->phase_overflow_f2.msb[0] = 19; 00518 this->phase_overflow_f2.lsb[0] = 19; 00519 00520 //Initialization for register ref_count_limit 00521 this->ref_count_limit.address[0] = 0x0f; ///< Address=15 00522 this->ref_count_limit.msb[0] = 14; 00523 this->ref_count_limit.lsb[0] = 0; 00524 00525 //Initialization for register start_freq_calib 00526 this->start_freq_calib.address[0] = 0x0f; ///< Address=15 00527 this->start_freq_calib.msb[0] = 16; 00528 this->start_freq_calib.lsb[0] = 16; 00529 00530 //Initialization for register sys_clk_divider 00531 this->sys_clk_divider.address[0] = 0x0f; ///< Address=15 00532 this->sys_clk_divider.msb[0] = 20; 00533 this->sys_clk_divider.lsb[0] = 17; 00534 00535 //Initialization for register freq_count_read_reg 00536 this->freq_count_read_reg.address[0] = 0x10; ///< Address=16 00537 this->freq_count_read_reg.msb[0] = 14; 00538 this->freq_count_read_reg.lsb[0] = 0; 00539 00540 //Initialization for register freq_count_reg 00541 this->freq_count_reg.address[0] = 0x11; ///< Address=17 00542 this->freq_count_reg.msb[0] = 14; 00543 this->freq_count_reg.lsb[0] = 0; 00544 00545 //Initialization for register en_auto_freq_count 00546 this->en_auto_freq_count.address[0] = 0x0f; ///< Address=15 00547 this->en_auto_freq_count.msb[0] = 21; 00548 this->en_auto_freq_count.lsb[0] = 21; 00549 00550 //Initialization for register en_floop 00551 this->en_floop.address[0] = 0x0f; ///< Address=15 00552 this->en_floop.msb[0] = 22; 00553 this->en_floop.lsb[0] = 22; 00554 00555 //Initialization for register en_freq_corr 00556 this->en_freq_corr.address[0] = 0x0f; ///< Address=15 00557 this->en_freq_corr.msb[0] = 23; 00558 this->en_freq_corr.lsb[0] = 23; 00559 00560 //Initialization for register en_cont_fcalib 00561 this->en_cont_fcalib.address[0] = 0x10; ///< Address=16 00562 this->en_cont_fcalib.msb[0] = 15; 00563 this->en_cont_fcalib.lsb[0] = 15; 00564 00565 //Initialization for register monoshot_bit 00566 this->monoshot_bit.address[0] = 0x00; ///< Address=0 00567 this->monoshot_bit.msb[0] = 23; 00568 this->monoshot_bit.lsb[0] = 23; 00569 00570 //Initialization for register monoshot_mode 00571 this->monoshot_mode.address[0] = 0x27; ///< Address=39 00572 this->monoshot_mode.msb[0] = 1; 00573 this->monoshot_mode.lsb[0] = 0; 00574 00575 //Initialization for register powerup_delay 00576 this->powerup_delay.address[0] = 0x26; ///< Address=38 00577 this->powerup_delay.msb[0] = 23; 00578 this->powerup_delay.lsb[0] = 10; 00579 00580 //Initialization for register monoshot_numframe 00581 this->monoshot_numframe.address[0] = 0x27; ///< Address=39 00582 this->monoshot_numframe.msb[0] = 7; 00583 this->monoshot_numframe.lsb[0] = 2; 00584 00585 //Initialization for register monoshot_fz_clkcnt 00586 this->monoshot_fz_clkcnt.address[0] = 0x27; ///< Address=39 00587 this->monoshot_fz_clkcnt.msb[0] = 23; 00588 this->monoshot_fz_clkcnt.lsb[0] = 8; 00589 00590 //Initialization for register en_tx_switch 00591 this->en_tx_switch.address[0] = 0x2a; ///< Address=42 00592 this->en_tx_switch.msb[0] = 0; 00593 this->en_tx_switch.lsb[0] = 0; 00594 00595 //Initialization for register sel_tx_ch 00596 this->sel_tx_ch.address[0] = 0x2a; ///< Address=42 00597 this->sel_tx_ch.msb[0] = 2; 00598 this->sel_tx_ch.lsb[0] = 1; 00599 00600 //Initialization for register tx_seq_reg 00601 this->tx_seq_reg.address[0] = 0x2a; ///< Address=42 00602 this->tx_seq_reg.msb[0] = 14; 00603 this->tx_seq_reg.lsb[0] = 3; 00604 00605 //Initialization for register en_adaptive_hdr 00606 this->en_adaptive_hdr.address[0] = 0x2a; ///< Address=42 00607 this->en_adaptive_hdr.msb[0] = 15; 00608 this->en_adaptive_hdr.lsb[0] = 15; 00609 00610 //Initialization for register sel_hdr_mode 00611 this->sel_hdr_mode.address[0] = 0x2a; ///< Address=42 00612 this->sel_hdr_mode.msb[0] = 16; 00613 this->sel_hdr_mode.lsb[0] = 16; 00614 00615 //Initialization for register hdr_thr_low 00616 this->hdr_thr_low.address[0] = 0x2c; ///< Address=44 00617 this->hdr_thr_low.msb[0] = 15; 00618 this->hdr_thr_low.lsb[0] = 0; 00619 00620 //Initialization for register hdr_thr_high 00621 this->hdr_thr_high.address[0] = 0x2b; ///< Address=43 00622 this->hdr_thr_high.msb[0] = 15; 00623 this->hdr_thr_high.lsb[0] = 0; 00624 00625 //Initialization for register illum_scale_l_tx0 00626 this->illum_scale_l_tx0.address[0] = 0x2b; ///< Address=43 00627 this->illum_scale_l_tx0.msb[0] = 18; 00628 this->illum_scale_l_tx0.lsb[0] = 16; 00629 00630 //Initialization for register illum_dac_l_tx0 00631 this->illum_dac_l_tx0.address[0] = 0x29; ///< Address=41 00632 this->illum_dac_l_tx0.msb[0] = 4; 00633 this->illum_dac_l_tx0.lsb[0] = 0; 00634 00635 //Initialization for register illum_scale_h_tx0 00636 this->illum_scale_h_tx0.address[0] = 0x2b; ///< Address=43 00637 this->illum_scale_h_tx0.msb[0] = 21; 00638 this->illum_scale_h_tx0.lsb[0] = 19; 00639 00640 //Initialization for register illum_dac_h_tx0 00641 this->illum_dac_h_tx0.address[0] = 0x29; ///< Address=41 00642 this->illum_dac_h_tx0.msb[0] = 9; 00643 this->illum_dac_h_tx0.lsb[0] = 5; 00644 00645 //Initialization for register illum_scale_l_tx1 00646 this->illum_scale_l_tx1.address[0] = 0x2c; ///< Address=44 00647 this->illum_scale_l_tx1.msb[0] = 18; 00648 this->illum_scale_l_tx1.lsb[0] = 16; 00649 00650 //Initialization for register illum_dac_l_tx1 00651 this->illum_dac_l_tx1.address[0] = 0x29; ///< Address=41 00652 this->illum_dac_l_tx1.msb[0] = 14; 00653 this->illum_dac_l_tx1.lsb[0] = 10; 00654 00655 //Initialization for register illum_scale_h_tx1 00656 this->illum_scale_h_tx1.address[0] = 0x2c; ///< Address=44 00657 this->illum_scale_h_tx1.msb[0] = 21; 00658 this->illum_scale_h_tx1.lsb[0] = 19; 00659 00660 //Initialization for register illum_dac_h_tx1 00661 this->illum_dac_h_tx1.address[0] = 0x29; ///< Address=41 00662 this->illum_dac_h_tx1.msb[0] = 19; 00663 this->illum_dac_h_tx1.lsb[0] = 15; 00664 00665 //Initialization for register illum_scale_l_tx2 00666 this->illum_scale_l_tx2.address[0] = 0xb9; ///< Address=185 00667 this->illum_scale_l_tx2.msb[0] = 20; 00668 this->illum_scale_l_tx2.lsb[0] = 18; 00669 00670 //Initialization for register illum_dac_l_tx2 00671 this->illum_dac_l_tx2.address[1] = 0x29; ///< Address=41 00672 this->illum_dac_l_tx2.msb[1] = 23; 00673 this->illum_dac_l_tx2.lsb[1] = 20; 00674 this->illum_dac_l_tx2.address[0] = 0x2a; ///< Address=42 00675 this->illum_dac_l_tx2.msb[0] = 23; 00676 this->illum_dac_l_tx2.lsb[0] = 23; 00677 00678 //Initialization for register illum_scale_h_tx2 00679 this->illum_scale_h_tx2.address[0] = 0xb9; ///< Address=185 00680 this->illum_scale_h_tx2.msb[0] = 23; 00681 this->illum_scale_h_tx2.lsb[0] = 21; 00682 00683 //Initialization for register illum_dac_h_tx2 00684 this->illum_dac_h_tx2.address[0] = 0x2a; ///< Address=42 00685 this->illum_dac_h_tx2.msb[0] = 22; 00686 this->illum_dac_h_tx2.lsb[0] = 18; 00687 00688 //Initialization for register amb_adc_in_tx0 00689 this->amb_adc_in_tx0.address[0] = 0xb9; ///< Address=185 00690 this->amb_adc_in_tx0.msb[0] = 13; 00691 this->amb_adc_in_tx0.lsb[0] = 12; 00692 00693 //Initialization for register amb_adc_in_tx1 00694 this->amb_adc_in_tx1.address[0] = 0xb9; ///< Address=185 00695 this->amb_adc_in_tx1.msb[0] = 15; 00696 this->amb_adc_in_tx1.lsb[0] = 14; 00697 00698 //Initialization for register amb_adc_in_tx2 00699 this->amb_adc_in_tx2.address[0] = 0xb9; ///< Address=185 00700 this->amb_adc_in_tx2.msb[0] = 17; 00701 this->amb_adc_in_tx2.lsb[0] = 16; 00702 00703 //Initialization for register give_dealias_data 00704 this->give_dealias_data.address[0] = 0xb8; ///< Address=184 00705 this->give_dealias_data.msb[0] = 20; 00706 this->give_dealias_data.lsb[0] = 20; 00707 00708 //Initialization for register en_dealias_meas 00709 this->en_dealias_meas.address[0] = 0x40; ///< Address=64 00710 this->en_dealias_meas.msb[0] = 0; 00711 this->en_dealias_meas.lsb[0] = 0; 00712 00713 //Initialization for register ncr_config 00714 this->ncr_config.address[0] = 0x40; ///< Address=64 00715 this->ncr_config.msb[0] = 21; 00716 this->ncr_config.lsb[0] = 21; 00717 00718 //Initialization for register alpha0_dealias_scale 00719 this->alpha0_dealias_scale.address[0] = 0x40; ///< Address=64 00720 this->alpha0_dealias_scale.msb[0] = 14; 00721 this->alpha0_dealias_scale.lsb[0] = 9; 00722 00723 //Initialization for register beta0_dealias_scale 00724 this->beta0_dealias_scale.address[0] = 0x40; ///< Address=64 00725 this->beta0_dealias_scale.msb[0] = 20; 00726 this->beta0_dealias_scale.lsb[0] = 15; 00727 00728 //Initialization for register alpha1_dealias_scale 00729 this->alpha1_dealias_scale.address[0] = 0x41; ///< Address=65 00730 this->alpha1_dealias_scale.msb[0] = 5; 00731 this->alpha1_dealias_scale.lsb[0] = 0; 00732 00733 //Initialization for register beta1_dealias_scale 00734 this->beta1_dealias_scale.address[0] = 0x41; ///< Address=65 00735 this->beta1_dealias_scale.msb[0] = 11; 00736 this->beta1_dealias_scale.lsb[0] = 6; 00737 00738 //Initialization for register en_multi_freq_phase 00739 this->en_multi_freq_phase.address[0] = 0x40; ///< Address=64 00740 this->en_multi_freq_phase.msb[0] = 22; 00741 this->en_multi_freq_phase.lsb[0] = 22; 00742 00743 //Initialization for register temp_avg_main 00744 this->temp_avg_main.address[0] = 0x03; ///< Address=3 00745 this->temp_avg_main.msb[0] = 23; 00746 this->temp_avg_main.lsb[0] = 22; 00747 00748 //Initialization for register dis_ovl_for_hdr_meth1 00749 this->dis_ovl_for_hdr_meth1.address[0] = 0xb8; ///< Address=184 00750 this->dis_ovl_for_hdr_meth1.msb[0] = 21; 00751 this->dis_ovl_for_hdr_meth1.lsb[0] = 21; 00752 00753 //Initialization for register en_ovl_for_hdr_meth2 00754 this->en_ovl_for_hdr_meth2.address[0] = 0xb8; ///< Address=184 00755 this->en_ovl_for_hdr_meth2.msb[0] = 22; 00756 this->en_ovl_for_hdr_meth2.lsb[0] = 22; 00757 00758 //Initialization for register en_tx1_on_tx0 00759 this->en_tx1_on_tx0.address[0] = 0xb9; ///< Address=185 00760 this->en_tx1_on_tx0.msb[0] = 10; 00761 this->en_tx1_on_tx0.lsb[0] = 10; 00762 00763 //Initialization for register en_tx2_on_tx0 00764 this->en_tx2_on_tx0.address[0] = 0xb9; ///< Address=185 00765 this->en_tx2_on_tx0.msb[0] = 11; 00766 this->en_tx2_on_tx0.lsb[0] = 11; 00767 00768 //Initialization for register clip_mode_fc 00769 this->clip_mode_fc.address[0] = 0x50; ///< Address=80 00770 this->clip_mode_fc.msb[0] = 0; 00771 this->clip_mode_fc.lsb[0] = 0; 00772 00773 //Initialization for register clip_mode_nl 00774 this->clip_mode_nl.address[0] = 0x50; ///< Address=80 00775 this->clip_mode_nl.msb[0] = 1; 00776 this->clip_mode_nl.lsb[0] = 1; 00777 00778 //Initialization for register clip_mode_temp 00779 this->clip_mode_temp.address[0] = 0x50; ///< Address=80 00780 this->clip_mode_temp.msb[0] = 2; 00781 this->clip_mode_temp.lsb[0] = 2; 00782 00783 //Initialization for register clip_mode_offset 00784 this->clip_mode_offset.address[0] = 0x50; ///< Address=80 00785 this->clip_mode_offset.msb[0] = 3; 00786 this->clip_mode_offset.lsb[0] = 3; 00787 00788 //Initialization for register disable_syncing 00789 this->disable_syncing.address[0] = 0x50; ///< Address=80 00790 this->disable_syncing.msb[0] = 21; 00791 this->disable_syncing.lsb[0] = 21; 00792 00793 //Initialization for register force_en_slave 00794 this->force_en_slave.address[0] = 0x00; ///< Address=0 00795 this->force_en_slave.msb[0] = 22; 00796 this->force_en_slave.lsb[0] = 22; 00797 00798 //Initialization for register force_en_bypass 00799 this->force_en_bypass.address[0] = 0x00; ///< Address=0 00800 this->force_en_bypass.msb[0] = 21; 00801 this->force_en_bypass.lsb[0] = 21; 00802 00803 //Initialization for register override_clkgen_reg 00804 this->override_clkgen_reg.address[0] = 0x50; ///< Address=80 00805 this->override_clkgen_reg.msb[0] = 22; 00806 this->override_clkgen_reg.lsb[0] = 22; 00807 00808 //Initialization for register software_reset 00809 this->software_reset.address[0] = 0x00; ///< Address=0 00810 this->software_reset.msb[0] = 0; 00811 this->software_reset.lsb[0] = 0; 00812 00813 //Initialization for register dis_tg_aconf 00814 this->dis_tg_aconf.address[0] = 0x80; ///< Address=128 00815 this->dis_tg_aconf.msb[0] = 23; 00816 this->dis_tg_aconf.lsb[0] = 23; 00817 00818 //Initialization for register capture_clk_cnt 00819 this->capture_clk_cnt.address[0] = 0xa0; ///< Address=160 00820 this->capture_clk_cnt.msb[0] = 15; 00821 this->capture_clk_cnt.lsb[0] = 0; 00822 00823 //Initialization for register tg_en 00824 this->tg_en.address[0] = 0x80; ///< Address=128 00825 this->tg_en.msb[0] = 0; 00826 this->tg_en.lsb[0] = 0; 00827 00828 //Initialization for register num_sub_frames 00829 this->num_sub_frames.address[0] = 0x9f; ///< Address=159 00830 this->num_sub_frames.msb[0] = 11; 00831 this->num_sub_frames.lsb[0] = 0; 00832 00833 //Initialization for register num_avg_sub_frames 00834 this->num_avg_sub_frames.address[0] = 0x9f; ///< Address=159 00835 this->num_avg_sub_frames.msb[0] = 23; 00836 this->num_avg_sub_frames.lsb[0] = 12; 00837 00838 //Initialization for register sub_vd_clk_cnt 00839 this->sub_vd_clk_cnt.address[0] = 0x80; ///< Address=128 00840 this->sub_vd_clk_cnt.msb[0] = 16; 00841 this->sub_vd_clk_cnt.lsb[0] = 1; 00842 00843 //Initialization for register tg_illumen_start 00844 this->tg_illumen_start.address[0] = 0x8f; ///< Address=143 00845 this->tg_illumen_start.msb[0] = 15; 00846 this->tg_illumen_start.lsb[0] = 0; 00847 00848 //Initialization for register tg_illumen_end 00849 this->tg_illumen_end.address[0] = 0x90; ///< Address=144 00850 this->tg_illumen_end.msb[0] = 15; 00851 this->tg_illumen_end.lsb[0] = 0; 00852 00853 //Initialization for register tg_illumen_mask_start 00854 this->tg_illumen_mask_start.address[0] = 0x9c; ///< Address=156 00855 this->tg_illumen_mask_start.msb[0] = 11; 00856 this->tg_illumen_mask_start.lsb[0] = 0; 00857 00858 //Initialization for register tg_illumen_mask_end 00859 this->tg_illumen_mask_end.address[0] = 0x9c; ///< Address=156 00860 this->tg_illumen_mask_end.msb[0] = 23; 00861 this->tg_illumen_mask_end.lsb[0] = 12; 00862 00863 //Initialization for register tg_afe_rst_start 00864 this->tg_afe_rst_start.address[0] = 0x83; ///< Address=131 00865 this->tg_afe_rst_start.msb[0] = 15; 00866 this->tg_afe_rst_start.lsb[0] = 0; 00867 00868 //Initialization for register tg_afe_rst_end 00869 this->tg_afe_rst_end.address[0] = 0x84; ///< Address=132 00870 this->tg_afe_rst_end.msb[0] = 15; 00871 this->tg_afe_rst_end.lsb[0] = 0; 00872 00873 //Initialization for register tg_seq_int_start 00874 this->tg_seq_int_start.address[0] = 0x85; ///< Address=133 00875 this->tg_seq_int_start.msb[0] = 15; 00876 this->tg_seq_int_start.lsb[0] = 0; 00877 00878 //Initialization for register tg_seq_int_end 00879 this->tg_seq_int_end.address[0] = 0x86; ///< Address=134 00880 this->tg_seq_int_end.msb[0] = 15; 00881 this->tg_seq_int_end.lsb[0] = 0; 00882 00883 //Initialization for register tg_capture_start 00884 this->tg_capture_start.address[0] = 0x87; ///< Address=135 00885 this->tg_capture_start.msb[0] = 15; 00886 this->tg_capture_start.lsb[0] = 0; 00887 00888 //Initialization for register tg_capture_end 00889 this->tg_capture_end.address[0] = 0x88; ///< Address=136 00890 this->tg_capture_end.msb[0] = 15; 00891 this->tg_capture_end.lsb[0] = 0; 00892 00893 //Initialization for register tg_ovl_window_start 00894 this->tg_ovl_window_start.address[0] = 0x89; ///< Address=137 00895 this->tg_ovl_window_start.msb[0] = 15; 00896 this->tg_ovl_window_start.lsb[0] = 0; 00897 00898 //Initialization for register tg_ovl_window_end 00899 this->tg_ovl_window_end.address[0] = 0x8a; ///< Address=138 00900 this->tg_ovl_window_end.msb[0] = 15; 00901 this->tg_ovl_window_end.lsb[0] = 0; 00902 00903 //Initialization for register tg_calc_start 00904 this->tg_calc_start.address[0] = 0x91; ///< Address=145 00905 this->tg_calc_start.msb[0] = 15; 00906 this->tg_calc_start.lsb[0] = 0; 00907 00908 //Initialization for register tg_calc_end 00909 this->tg_calc_end.address[0] = 0x92; ///< Address=146 00910 this->tg_calc_end.msb[0] = 15; 00911 this->tg_calc_end.lsb[0] = 0; 00912 00913 //Initialization for register tg_dynpdn_start 00914 this->tg_dynpdn_start.address[0] = 0x93; ///< Address=147 00915 this->tg_dynpdn_start.msb[0] = 15; 00916 this->tg_dynpdn_start.lsb[0] = 0; 00917 00918 //Initialization for register tg_dynpdn_end 00919 this->tg_dynpdn_end.address[0] = 0x94; ///< Address=148 00920 this->tg_dynpdn_end.msb[0] = 15; 00921 this->tg_dynpdn_end.lsb[0] = 0; 00922 00923 //Initialization for register tg_seq_int_mask_start 00924 this->tg_seq_int_mask_start.address[0] = 0x97; ///< Address=151 00925 this->tg_seq_int_mask_start.msb[0] = 11; 00926 this->tg_seq_int_mask_start.lsb[0] = 0; 00927 00928 //Initialization for register tg_seq_int_mask_end 00929 this->tg_seq_int_mask_end.address[0] = 0x97; ///< Address=151 00930 this->tg_seq_int_mask_end.msb[0] = 23; 00931 this->tg_seq_int_mask_end.lsb[0] = 12; 00932 00933 //Initialization for register tg_capture_mask_start 00934 this->tg_capture_mask_start.address[0] = 0x98; ///< Address=152 00935 this->tg_capture_mask_start.msb[0] = 11; 00936 this->tg_capture_mask_start.lsb[0] = 0; 00937 00938 //Initialization for register tg_capture_mask_end 00939 this->tg_capture_mask_end.address[0] = 0x98; ///< Address=152 00940 this->tg_capture_mask_end.msb[0] = 23; 00941 this->tg_capture_mask_end.lsb[0] = 12; 00942 00943 //Initialization for register tg_ovl_window_mask_start 00944 this->tg_ovl_window_mask_start.address[0] = 0x99; ///< Address=153 00945 this->tg_ovl_window_mask_start.msb[0] = 11; 00946 this->tg_ovl_window_mask_start.lsb[0] = 0; 00947 00948 //Initialization for register tg_ovl_window_mask_end 00949 this->tg_ovl_window_mask_end.address[0] = 0x99; ///< Address=153 00950 this->tg_ovl_window_mask_end.msb[0] = 23; 00951 this->tg_ovl_window_mask_end.lsb[0] = 12; 00952 00953 //Initialization for register tg_calc_mask_start 00954 this->tg_calc_mask_start.address[0] = 0x9d; ///< Address=157 00955 this->tg_calc_mask_start.msb[0] = 11; 00956 this->tg_calc_mask_start.lsb[0] = 0; 00957 00958 //Initialization for register tg_calc_mask_end 00959 this->tg_calc_mask_end.address[0] = 0x9d; ///< Address=157 00960 this->tg_calc_mask_end.msb[0] = 23; 00961 this->tg_calc_mask_end.lsb[0] = 12; 00962 00963 //Initialization for register tg_dynpdn_mask_start 00964 this->tg_dynpdn_mask_start.address[0] = 0x9e; ///< Address=158 00965 this->tg_dynpdn_mask_start.msb[0] = 11; 00966 this->tg_dynpdn_mask_start.lsb[0] = 0; 00967 00968 //Initialization for register tg_dynpdn_mask_end 00969 this->tg_dynpdn_mask_end.address[0] = 0x9e; ///< Address=158 00970 this->tg_dynpdn_mask_end.msb[0] = 23; 00971 this->tg_dynpdn_mask_end.lsb[0] = 12; 00972 00973 //Initialization for register en_sequencer 00974 this->en_sequencer.address[0] = 0x14; ///< Address=20 00975 this->en_sequencer.msb[0] = 16; 00976 this->en_sequencer.lsb[0] = 16; 00977 00978 //Initialization for register en_processor_values 00979 this->en_processor_values.address[0] = 0x14; ///< Address=20 00980 this->en_processor_values.msb[0] = 17; 00981 this->en_processor_values.lsb[0] = 17; 00982 00983 //Initialization for register status_in_reg 00984 this->status_in_reg.address[0] = 0x14; ///< Address=20 00985 this->status_in_reg.msb[0] = 18; 00986 this->status_in_reg.lsb[0] = 18; 00987 00988 //Initialization for register mux_sel_compin 00989 this->mux_sel_compin.address[0] = 0x13; ///< Address=19 00990 this->mux_sel_compin.msb[0] = 2; 00991 this->mux_sel_compin.lsb[0] = 0; 00992 00993 //Initialization for register compare_reg1 00994 this->compare_reg1.address[0] = 0x13; ///< Address=19 00995 this->compare_reg1.msb[0] = 18; 00996 this->compare_reg1.lsb[0] = 3; 00997 00998 //Initialization for register compare_reg2 00999 this->compare_reg2.address[0] = 0x14; ///< Address=20 01000 this->compare_reg2.msb[0] = 15; 01001 this->compare_reg2.lsb[0] = 0; 01002 01003 //Initialization for register dis_interrupt 01004 this->dis_interrupt.address[0] = 0x14; ///< Address=20 01005 this->dis_interrupt.msb[0] = 19; 01006 this->dis_interrupt.lsb[0] = 19; 01007 01008 //Initialization for register command0 01009 this->command0.address[0] = 0x15; ///< Address=21 01010 this->command0.msb[0] = 11; 01011 this->command0.lsb[0] = 0; 01012 01013 //Initialization for register command1 01014 this->command1.address[0] = 0x15; ///< Address=21 01015 this->command1.msb[0] = 23; 01016 this->command1.lsb[0] = 12; 01017 01018 //Initialization for register command2 01019 this->command2.address[0] = 0x16; ///< Address=22 01020 this->command2.msb[0] = 11; 01021 this->command2.lsb[0] = 0; 01022 01023 //Initialization for register command3 01024 this->command3.address[0] = 0x16; ///< Address=22 01025 this->command3.msb[0] = 23; 01026 this->command3.lsb[0] = 12; 01027 01028 //Initialization for register command4 01029 this->command4.address[0] = 0x17; ///< Address=23 01030 this->command4.msb[0] = 11; 01031 this->command4.lsb[0] = 0; 01032 01033 //Initialization for register command5 01034 this->command5.address[0] = 0x17; ///< Address=23 01035 this->command5.msb[0] = 23; 01036 this->command5.lsb[0] = 12; 01037 01038 //Initialization for register command6 01039 this->command6.address[0] = 0x18; ///< Address=24 01040 this->command6.msb[0] = 11; 01041 this->command6.lsb[0] = 0; 01042 01043 //Initialization for register command7 01044 this->command7.address[0] = 0x18; ///< Address=24 01045 this->command7.msb[0] = 23; 01046 this->command7.lsb[0] = 12; 01047 01048 //Initialization for register command8 01049 this->command8.address[0] = 0x19; ///< Address=25 01050 this->command8.msb[0] = 11; 01051 this->command8.lsb[0] = 0; 01052 01053 //Initialization for register command9 01054 this->command9.address[0] = 0x19; ///< Address=25 01055 this->command9.msb[0] = 23; 01056 this->command9.lsb[0] = 12; 01057 01058 //Initialization for register command10 01059 this->command10.address[0] = 0x1a; ///< Address=26 01060 this->command10.msb[0] = 11; 01061 this->command10.lsb[0] = 0; 01062 01063 //Initialization for register command11 01064 this->command11.address[0] = 0x1a; ///< Address=26 01065 this->command11.msb[0] = 23; 01066 this->command11.lsb[0] = 12; 01067 01068 //Initialization for register command12 01069 this->command12.address[0] = 0x1b; ///< Address=27 01070 this->command12.msb[0] = 11; 01071 this->command12.lsb[0] = 0; 01072 01073 //Initialization for register command13 01074 this->command13.address[0] = 0x1b; ///< Address=27 01075 this->command13.msb[0] = 23; 01076 this->command13.lsb[0] = 12; 01077 01078 //Initialization for register command14 01079 this->command14.address[0] = 0x1c; ///< Address=28 01080 this->command14.msb[0] = 11; 01081 this->command14.lsb[0] = 0; 01082 01083 //Initialization for register command15 01084 this->command15.address[0] = 0x1c; ///< Address=28 01085 this->command15.msb[0] = 23; 01086 this->command15.lsb[0] = 12; 01087 01088 //Initialization for register command16 01089 this->command16.address[0] = 0x1d; ///< Address=29 01090 this->command16.msb[0] = 11; 01091 this->command16.lsb[0] = 0; 01092 01093 //Initialization for register command17 01094 this->command17.address[0] = 0x1d; ///< Address=29 01095 this->command17.msb[0] = 23; 01096 this->command17.lsb[0] = 12; 01097 01098 //Initialization for register command18 01099 this->command18.address[0] = 0x1e; ///< Address=30 01100 this->command18.msb[0] = 11; 01101 this->command18.lsb[0] = 0; 01102 01103 //Initialization for register command19 01104 this->command19.address[0] = 0x1e; ///< Address=30 01105 this->command19.msb[0] = 23; 01106 this->command19.lsb[0] = 12; 01107 01108 //Initialization for register force_scale_val 01109 this->force_scale_val.address[0] = 0x2e; ///< Address=46 01110 this->force_scale_val.msb[0] = 2; 01111 this->force_scale_val.lsb[0] = 0; 01112 01113 //Initialization for register dis_auto_scale 01114 this->dis_auto_scale.address[0] = 0x2e; ///< Address=46 01115 this->dis_auto_scale.msb[0] = 3; 01116 this->dis_auto_scale.lsb[0] = 3; 01117 01118 //Initialization for register disable_conf_rescale 01119 this->disable_conf_rescale.address[0] = 0x2e; ///< Address=46 01120 this->disable_conf_rescale.msb[0] = 13; 01121 this->disable_conf_rescale.lsb[0] = 13; 01122 01123 //Initialization for register int_xtalk_calib 01124 this->int_xtalk_calib.address[0] = 0x2e; ///< Address=46 01125 this->int_xtalk_calib.msb[0] = 4; 01126 this->int_xtalk_calib.lsb[0] = 4; 01127 01128 //Initialization for register xtalk_filt_time_const 01129 this->xtalk_filt_time_const.address[0] = 0x2e; ///< Address=46 01130 this->xtalk_filt_time_const.msb[0] = 23; 01131 this->xtalk_filt_time_const.lsb[0] = 20; 01132 01133 //Initialization for register use_xtalk_filt_int 01134 this->use_xtalk_filt_int.address[0] = 0x2e; ///< Address=46 01135 this->use_xtalk_filt_int.msb[0] = 5; 01136 this->use_xtalk_filt_int.lsb[0] = 5; 01137 01138 //Initialization for register use_xtalk_reg_int 01139 this->use_xtalk_reg_int.address[0] = 0x2e; ///< Address=46 01140 this->use_xtalk_reg_int.msb[0] = 6; 01141 this->use_xtalk_reg_int.lsb[0] = 6; 01142 01143 //Initialization for register iq_read_data_sel 01144 this->iq_read_data_sel.address[0] = 0x2e; ///< Address=46 01145 this->iq_read_data_sel.msb[0] = 11; 01146 this->iq_read_data_sel.lsb[0] = 9; 01147 01148 //Initialization for register iphase_xtalk 01149 this->iphase_xtalk.address[0] = 0x3b; ///< Address=59 01150 this->iphase_xtalk.msb[0] = 23; 01151 this->iphase_xtalk.lsb[0] = 0; 01152 01153 //Initialization for register qphase_xtalk 01154 this->qphase_xtalk.address[0] = 0x3c; ///< Address=60 01155 this->qphase_xtalk.msb[0] = 23; 01156 this->qphase_xtalk.lsb[0] = 0; 01157 01158 //Initialization for register int_xtalk_reg_scale 01159 this->int_xtalk_reg_scale.address[0] = 0x2e; ///< Address=46 01160 this->int_xtalk_reg_scale.msb[0] = 16; 01161 this->int_xtalk_reg_scale.lsb[0] = 14; 01162 01163 //Initialization for register iphase_xtalk_int_reg 01164 this->iphase_xtalk_int_reg.address[0] = 0x3d; ///< Address=61 01165 this->iphase_xtalk_int_reg.msb[0] = 15; 01166 this->iphase_xtalk_int_reg.lsb[0] = 0; 01167 01168 //Initialization for register qphase_xtalk_int_reg 01169 this->qphase_xtalk_int_reg.address[0] = 0x3e; ///< Address=62 01170 this->qphase_xtalk_int_reg.msb[0] = 15; 01171 this->qphase_xtalk_int_reg.lsb[0] = 0; 01172 01173 //Initialization for register illum_xtalk_calib 01174 this->illum_xtalk_calib.address[0] = 0x2e; ///< Address=46 01175 this->illum_xtalk_calib.msb[0] = 12; 01176 this->illum_xtalk_calib.lsb[0] = 12; 01177 01178 //Initialization for register illum_xtalk_reg_scale 01179 this->illum_xtalk_reg_scale.address[0] = 0x2e; ///< Address=46 01180 this->illum_xtalk_reg_scale.msb[0] = 19; 01181 this->illum_xtalk_reg_scale.lsb[0] = 17; 01182 01183 //Initialization for register use_xtalk_filt_illum 01184 this->use_xtalk_filt_illum.address[0] = 0x2e; ///< Address=46 01185 this->use_xtalk_filt_illum.msb[0] = 7; 01186 this->use_xtalk_filt_illum.lsb[0] = 7; 01187 01188 //Initialization for register use_xtalk_reg_illum 01189 this->use_xtalk_reg_illum.address[0] = 0x2e; ///< Address=46 01190 this->use_xtalk_reg_illum.msb[0] = 8; 01191 this->use_xtalk_reg_illum.lsb[0] = 8; 01192 01193 //Initialization for register iphase_xtalk_reg_hdr0_tx0 01194 this->iphase_xtalk_reg_hdr0_tx0.address[0] = 0x2f; ///< Address=47 01195 this->iphase_xtalk_reg_hdr0_tx0.msb[0] = 15; 01196 this->iphase_xtalk_reg_hdr0_tx0.lsb[0] = 0; 01197 01198 //Initialization for register qphase_xtalk_reg_hdr0_tx0 01199 this->qphase_xtalk_reg_hdr0_tx0.address[0] = 0x30; ///< Address=48 01200 this->qphase_xtalk_reg_hdr0_tx0.msb[0] = 15; 01201 this->qphase_xtalk_reg_hdr0_tx0.lsb[0] = 0; 01202 01203 //Initialization for register iphase_xtalk_reg_hdr1_tx0 01204 this->iphase_xtalk_reg_hdr1_tx0.address[0] = 0x31; ///< Address=49 01205 this->iphase_xtalk_reg_hdr1_tx0.msb[0] = 15; 01206 this->iphase_xtalk_reg_hdr1_tx0.lsb[0] = 0; 01207 01208 //Initialization for register qphase_xtalk_reg_hdr1_tx0 01209 this->qphase_xtalk_reg_hdr1_tx0.address[0] = 0x32; ///< Address=50 01210 this->qphase_xtalk_reg_hdr1_tx0.msb[0] = 15; 01211 this->qphase_xtalk_reg_hdr1_tx0.lsb[0] = 0; 01212 01213 //Initialization for register iphase_xtalk_reg_hdr0_tx1 01214 this->iphase_xtalk_reg_hdr0_tx1.address[0] = 0x33; ///< Address=51 01215 this->iphase_xtalk_reg_hdr0_tx1.msb[0] = 15; 01216 this->iphase_xtalk_reg_hdr0_tx1.lsb[0] = 0; 01217 01218 //Initialization for register qphase_xtalk_reg_hdr0_tx1 01219 this->qphase_xtalk_reg_hdr0_tx1.address[0] = 0x34; ///< Address=52 01220 this->qphase_xtalk_reg_hdr0_tx1.msb[0] = 15; 01221 this->qphase_xtalk_reg_hdr0_tx1.lsb[0] = 0; 01222 01223 //Initialization for register iphase_xtalk_reg_hdr1_tx1 01224 this->iphase_xtalk_reg_hdr1_tx1.address[0] = 0x35; ///< Address=53 01225 this->iphase_xtalk_reg_hdr1_tx1.msb[0] = 15; 01226 this->iphase_xtalk_reg_hdr1_tx1.lsb[0] = 0; 01227 01228 //Initialization for register qphase_xtalk_reg_hdr1_tx1 01229 this->qphase_xtalk_reg_hdr1_tx1.address[0] = 0x36; ///< Address=54 01230 this->qphase_xtalk_reg_hdr1_tx1.msb[0] = 15; 01231 this->qphase_xtalk_reg_hdr1_tx1.lsb[0] = 0; 01232 01233 //Initialization for register iphase_xtalk_reg_hdr0_tx2 01234 this->iphase_xtalk_reg_hdr0_tx2.address[0] = 0x37; ///< Address=55 01235 this->iphase_xtalk_reg_hdr0_tx2.msb[0] = 15; 01236 this->iphase_xtalk_reg_hdr0_tx2.lsb[0] = 0; 01237 01238 //Initialization for register qphase_xtalk_reg_hdr0_tx2 01239 this->qphase_xtalk_reg_hdr0_tx2.address[0] = 0x38; ///< Address=56 01240 this->qphase_xtalk_reg_hdr0_tx2.msb[0] = 15; 01241 this->qphase_xtalk_reg_hdr0_tx2.lsb[0] = 0; 01242 01243 //Initialization for register iphase_xtalk_reg_hdr1_tx2 01244 this->iphase_xtalk_reg_hdr1_tx2.address[0] = 0x39; ///< Address=57 01245 this->iphase_xtalk_reg_hdr1_tx2.msb[0] = 15; 01246 this->iphase_xtalk_reg_hdr1_tx2.lsb[0] = 0; 01247 01248 //Initialization for register qphase_xtalk_reg_hdr1_tx2 01249 this->qphase_xtalk_reg_hdr1_tx2.address[0] = 0x3a; ///< Address=58 01250 this->qphase_xtalk_reg_hdr1_tx2.msb[0] = 15; 01251 this->qphase_xtalk_reg_hdr1_tx2.lsb[0] = 0; 01252 01253 //Initialization for register en_temp_xtalk_corr 01254 this->en_temp_xtalk_corr.address[0] = 0x3a; ///< Address=58 01255 this->en_temp_xtalk_corr.msb[0] = 16; 01256 this->en_temp_xtalk_corr.lsb[0] = 16; 01257 01258 //Initialization for register scale_temp_coeff_xtalk 01259 this->scale_temp_coeff_xtalk.address[0] = 0x3a; ///< Address=58 01260 this->scale_temp_coeff_xtalk.msb[0] = 19; 01261 this->scale_temp_coeff_xtalk.lsb[0] = 17; 01262 01263 //Initialization for register temp_coeff_xtalk_iphase_hdr0_tx0 01264 this->temp_coeff_xtalk_iphase_hdr0_tx0.address[0] = 0x38; ///< Address=56 01265 this->temp_coeff_xtalk_iphase_hdr0_tx0.msb[0] = 23; 01266 this->temp_coeff_xtalk_iphase_hdr0_tx0.lsb[0] = 16; 01267 01268 //Initialization for register temp_coeff_xtalk_qphase_hdr0_tx0 01269 this->temp_coeff_xtalk_qphase_hdr0_tx0.address[0] = 0x39; ///< Address=57 01270 this->temp_coeff_xtalk_qphase_hdr0_tx0.msb[0] = 23; 01271 this->temp_coeff_xtalk_qphase_hdr0_tx0.lsb[0] = 16; 01272 01273 //Initialization for register temp_coeff_xtalk_iphase_hdr1_tx0 01274 this->temp_coeff_xtalk_iphase_hdr1_tx0.address[0] = 0x5e; ///< Address=94 01275 this->temp_coeff_xtalk_iphase_hdr1_tx0.msb[0] = 15; 01276 this->temp_coeff_xtalk_iphase_hdr1_tx0.lsb[0] = 8; 01277 01278 //Initialization for register temp_coeff_xtalk_qphase_hdr1_tx0 01279 this->temp_coeff_xtalk_qphase_hdr1_tx0.address[0] = 0x60; ///< Address=96 01280 this->temp_coeff_xtalk_qphase_hdr1_tx0.msb[0] = 7; 01281 this->temp_coeff_xtalk_qphase_hdr1_tx0.lsb[0] = 0; 01282 01283 //Initialization for register temp_coeff_xtalk_iphase_hdr0_tx1 01284 this->temp_coeff_xtalk_iphase_hdr0_tx1.address[0] = 0x5e; ///< Address=94 01285 this->temp_coeff_xtalk_iphase_hdr0_tx1.msb[0] = 23; 01286 this->temp_coeff_xtalk_iphase_hdr0_tx1.lsb[0] = 16; 01287 01288 //Initialization for register temp_coeff_xtalk_qphase_hdr0_tx1 01289 this->temp_coeff_xtalk_qphase_hdr0_tx1.address[0] = 0x60; ///< Address=96 01290 this->temp_coeff_xtalk_qphase_hdr0_tx1.msb[0] = 15; 01291 this->temp_coeff_xtalk_qphase_hdr0_tx1.lsb[0] = 8; 01292 01293 //Initialization for register temp_coeff_xtalk_iphase_hdr1_tx1 01294 this->temp_coeff_xtalk_iphase_hdr1_tx1.address[0] = 0x5f; ///< Address=95 01295 this->temp_coeff_xtalk_iphase_hdr1_tx1.msb[0] = 7; 01296 this->temp_coeff_xtalk_iphase_hdr1_tx1.lsb[0] = 0; 01297 01298 //Initialization for register temp_coeff_xtalk_qphase_hdr1_tx1 01299 this->temp_coeff_xtalk_qphase_hdr1_tx1.address[0] = 0x60; ///< Address=96 01300 this->temp_coeff_xtalk_qphase_hdr1_tx1.msb[0] = 23; 01301 this->temp_coeff_xtalk_qphase_hdr1_tx1.lsb[0] = 16; 01302 01303 //Initialization for register temp_coeff_xtalk_iphase_hdr0_tx2 01304 this->temp_coeff_xtalk_iphase_hdr0_tx2.address[0] = 0x5f; ///< Address=95 01305 this->temp_coeff_xtalk_iphase_hdr0_tx2.msb[0] = 15; 01306 this->temp_coeff_xtalk_iphase_hdr0_tx2.lsb[0] = 8; 01307 01308 //Initialization for register temp_coeff_xtalk_qphase_hdr0_tx2 01309 this->temp_coeff_xtalk_qphase_hdr0_tx2.address[0] = 0x61; ///< Address=97 01310 this->temp_coeff_xtalk_qphase_hdr0_tx2.msb[0] = 7; 01311 this->temp_coeff_xtalk_qphase_hdr0_tx2.lsb[0] = 0; 01312 01313 //Initialization for register temp_coeff_xtalk_iphase_hdr1_tx2 01314 this->temp_coeff_xtalk_iphase_hdr1_tx2.address[0] = 0x5f; ///< Address=95 01315 this->temp_coeff_xtalk_iphase_hdr1_tx2.msb[0] = 23; 01316 this->temp_coeff_xtalk_iphase_hdr1_tx2.lsb[0] = 16; 01317 01318 //Initialization for register temp_coeff_xtalk_qphase_hdr1_tx2 01319 this->temp_coeff_xtalk_qphase_hdr1_tx2.address[0] = 0x61; ///< Address=97 01320 this->temp_coeff_xtalk_qphase_hdr1_tx2.msb[0] = 15; 01321 this->temp_coeff_xtalk_qphase_hdr1_tx2.lsb[0] = 8; 01322 01323 //Initialization for register temp_coeff_illum_xtalk_iphase_hdr0_tx0 01324 this->temp_coeff_illum_xtalk_iphase_hdr0_tx0.address[0] = 0x36; ///< Address=54 01325 this->temp_coeff_illum_xtalk_iphase_hdr0_tx0.msb[0] = 23; 01326 this->temp_coeff_illum_xtalk_iphase_hdr0_tx0.lsb[0] = 16; 01327 01328 //Initialization for register temp_coeff_illum_xtalk_qphase_hdr0_tx0 01329 this->temp_coeff_illum_xtalk_qphase_hdr0_tx0.address[0] = 0x37; ///< Address=55 01330 this->temp_coeff_illum_xtalk_qphase_hdr0_tx0.msb[0] = 23; 01331 this->temp_coeff_illum_xtalk_qphase_hdr0_tx0.lsb[0] = 16; 01332 01333 //Initialization for register temp_coeff_illum_xtalk_iphase_hdr1_tx0 01334 this->temp_coeff_illum_xtalk_iphase_hdr1_tx0.address[0] = 0x5b; ///< Address=91 01335 this->temp_coeff_illum_xtalk_iphase_hdr1_tx0.msb[0] = 7; 01336 this->temp_coeff_illum_xtalk_iphase_hdr1_tx0.lsb[0] = 0; 01337 01338 //Initialization for register temp_coeff_illum_xtalk_iphase_hdr0_tx1 01339 this->temp_coeff_illum_xtalk_iphase_hdr0_tx1.address[0] = 0x5b; ///< Address=91 01340 this->temp_coeff_illum_xtalk_iphase_hdr0_tx1.msb[0] = 15; 01341 this->temp_coeff_illum_xtalk_iphase_hdr0_tx1.lsb[0] = 8; 01342 01343 //Initialization for register temp_coeff_illum_xtalk_iphase_hdr1_tx1 01344 this->temp_coeff_illum_xtalk_iphase_hdr1_tx1.address[0] = 0x5b; ///< Address=91 01345 this->temp_coeff_illum_xtalk_iphase_hdr1_tx1.msb[0] = 23; 01346 this->temp_coeff_illum_xtalk_iphase_hdr1_tx1.lsb[0] = 16; 01347 01348 //Initialization for register temp_coeff_illum_xtalk_iphase_hdr0_tx2 01349 this->temp_coeff_illum_xtalk_iphase_hdr0_tx2.address[0] = 0x5c; ///< Address=92 01350 this->temp_coeff_illum_xtalk_iphase_hdr0_tx2.msb[0] = 7; 01351 this->temp_coeff_illum_xtalk_iphase_hdr0_tx2.lsb[0] = 0; 01352 01353 //Initialization for register temp_coeff_illum_xtalk_iphase_hdr1_tx2 01354 this->temp_coeff_illum_xtalk_iphase_hdr1_tx2.address[0] = 0x5c; ///< Address=92 01355 this->temp_coeff_illum_xtalk_iphase_hdr1_tx2.msb[0] = 15; 01356 this->temp_coeff_illum_xtalk_iphase_hdr1_tx2.lsb[0] = 8; 01357 01358 //Initialization for register temp_coeff_illum_xtalk_qphase_hdr1_tx0 01359 this->temp_coeff_illum_xtalk_qphase_hdr1_tx0.address[0] = 0x5c; ///< Address=92 01360 this->temp_coeff_illum_xtalk_qphase_hdr1_tx0.msb[0] = 23; 01361 this->temp_coeff_illum_xtalk_qphase_hdr1_tx0.lsb[0] = 16; 01362 01363 //Initialization for register temp_coeff_illum_xtalk_qphase_hdr0_tx1 01364 this->temp_coeff_illum_xtalk_qphase_hdr0_tx1.address[0] = 0x5d; ///< Address=93 01365 this->temp_coeff_illum_xtalk_qphase_hdr0_tx1.msb[0] = 7; 01366 this->temp_coeff_illum_xtalk_qphase_hdr0_tx1.lsb[0] = 0; 01367 01368 //Initialization for register temp_coeff_illum_xtalk_qphase_hdr1_tx1 01369 this->temp_coeff_illum_xtalk_qphase_hdr1_tx1.address[0] = 0x5d; ///< Address=93 01370 this->temp_coeff_illum_xtalk_qphase_hdr1_tx1.msb[0] = 15; 01371 this->temp_coeff_illum_xtalk_qphase_hdr1_tx1.lsb[0] = 8; 01372 01373 //Initialization for register temp_coeff_illum_xtalk_qphase_hdr0_tx2 01374 this->temp_coeff_illum_xtalk_qphase_hdr0_tx2.address[0] = 0x5d; ///< Address=93 01375 this->temp_coeff_illum_xtalk_qphase_hdr0_tx2.msb[0] = 23; 01376 this->temp_coeff_illum_xtalk_qphase_hdr0_tx2.lsb[0] = 16; 01377 01378 //Initialization for register temp_coeff_illum_xtalk_qphase_hdr1_tx2 01379 this->temp_coeff_illum_xtalk_qphase_hdr1_tx2.address[0] = 0x5e; ///< Address=94 01380 this->temp_coeff_illum_xtalk_qphase_hdr1_tx2.msb[0] = 7; 01381 this->temp_coeff_illum_xtalk_qphase_hdr1_tx2.lsb[0] = 0; 01382 01383 //Initialization for register amb_xtalk_qphase_coeff 01384 this->amb_xtalk_qphase_coeff.address[0] = 0x0c; ///< Address=12 01385 this->amb_xtalk_qphase_coeff.msb[0] = 15; 01386 this->amb_xtalk_qphase_coeff.lsb[0] = 8; 01387 01388 //Initialization for register amb_xtalk_iphase_coeff 01389 this->amb_xtalk_iphase_coeff.address[0] = 0x0c; ///< Address=12 01390 this->amb_xtalk_iphase_coeff.msb[0] = 7; 01391 this->amb_xtalk_iphase_coeff.lsb[0] = 0; 01392 01393 //Initialization for register scale_amb_coeff_xtalk 01394 this->scale_amb_coeff_xtalk.address[0] = 0x3a; ///< Address=58 01395 this->scale_amb_coeff_xtalk.msb[0] = 22; 01396 this->scale_amb_coeff_xtalk.lsb[0] = 20; 01397 01398 //Initialization for register en_phase_corr 01399 this->en_phase_corr.address[0] = 0x43; ///< Address=67 01400 this->en_phase_corr.msb[0] = 0; 01401 this->en_phase_corr.lsb[0] = 0; 01402 01403 //Initialization for register phase_offset_hdr0_tx0 01404 this->phase_offset_hdr0_tx0.address[0] = 0x42; ///< Address=66 01405 this->phase_offset_hdr0_tx0.msb[0] = 15; 01406 this->phase_offset_hdr0_tx0.lsb[0] = 0; 01407 01408 //Initialization for register phase_offset_hdr1_tx0 01409 this->phase_offset_hdr1_tx0.address[0] = 0x51; ///< Address=81 01410 this->phase_offset_hdr1_tx0.msb[0] = 15; 01411 this->phase_offset_hdr1_tx0.lsb[0] = 0; 01412 01413 //Initialization for register phase_offset_hdr0_tx1 01414 this->phase_offset_hdr0_tx1.address[0] = 0x52; ///< Address=82 01415 this->phase_offset_hdr0_tx1.msb[0] = 15; 01416 this->phase_offset_hdr0_tx1.lsb[0] = 0; 01417 01418 //Initialization for register phase_offset_hdr1_tx1 01419 this->phase_offset_hdr1_tx1.address[0] = 0x53; ///< Address=83 01420 this->phase_offset_hdr1_tx1.msb[0] = 15; 01421 this->phase_offset_hdr1_tx1.lsb[0] = 0; 01422 01423 //Initialization for register phase_offset_hdr0_tx2 01424 this->phase_offset_hdr0_tx2.address[0] = 0x54; ///< Address=84 01425 this->phase_offset_hdr0_tx2.msb[0] = 15; 01426 this->phase_offset_hdr0_tx2.lsb[0] = 0; 01427 01428 //Initialization for register phase_offset_hdr1_tx2 01429 this->phase_offset_hdr1_tx2.address[0] = 0x55; ///< Address=85 01430 this->phase_offset_hdr1_tx2.msb[0] = 15; 01431 this->phase_offset_hdr1_tx2.lsb[0] = 0; 01432 01433 //Initialization for register reverse_phase_before_offset 01434 this->reverse_phase_before_offset.address[0] = 0x43; ///< Address=67 01435 this->reverse_phase_before_offset.msb[0] = 9; 01436 this->reverse_phase_before_offset.lsb[0] = 9; 01437 01438 //Initialization for register phase2_offset_hdr0_tx0 01439 this->phase2_offset_hdr0_tx0.address[0] = 0x44; ///< Address=68 01440 this->phase2_offset_hdr0_tx0.msb[0] = 15; 01441 this->phase2_offset_hdr0_tx0.lsb[0] = 0; 01442 01443 //Initialization for register phase2_offset_hdr1_tx0 01444 this->phase2_offset_hdr1_tx0.address[0] = 0x56; ///< Address=86 01445 this->phase2_offset_hdr1_tx0.msb[0] = 15; 01446 this->phase2_offset_hdr1_tx0.lsb[0] = 0; 01447 01448 //Initialization for register phase2_offset_hdr0_tx1 01449 this->phase2_offset_hdr0_tx1.address[0] = 0x57; ///< Address=87 01450 this->phase2_offset_hdr0_tx1.msb[0] = 15; 01451 this->phase2_offset_hdr0_tx1.lsb[0] = 0; 01452 01453 //Initialization for register phase2_offset_hdr1_tx1 01454 this->phase2_offset_hdr1_tx1.address[0] = 0x58; ///< Address=88 01455 this->phase2_offset_hdr1_tx1.msb[0] = 15; 01456 this->phase2_offset_hdr1_tx1.lsb[0] = 0; 01457 01458 //Initialization for register phase2_offset_hdr0_tx2 01459 this->phase2_offset_hdr0_tx2.address[0] = 0x59; ///< Address=89 01460 this->phase2_offset_hdr0_tx2.msb[0] = 15; 01461 this->phase2_offset_hdr0_tx2.lsb[0] = 0; 01462 01463 //Initialization for register phase2_offset_hdr1_tx2 01464 this->phase2_offset_hdr1_tx2.address[0] = 0x5a; ///< Address=90 01465 this->phase2_offset_hdr1_tx2.msb[0] = 15; 01466 this->phase2_offset_hdr1_tx2.lsb[0] = 0; 01467 01468 //Initialization for register en_temp_corr 01469 this->en_temp_corr.address[0] = 0x43; ///< Address=67 01470 this->en_temp_corr.msb[0] = 1; 01471 this->en_temp_corr.lsb[0] = 1; 01472 01473 //Initialization for register scale_phase_temp_coeff 01474 this->scale_phase_temp_coeff.address[0] = 0x43; ///< Address=67 01475 this->scale_phase_temp_coeff.msb[0] = 8; 01476 this->scale_phase_temp_coeff.lsb[0] = 6; 01477 01478 //Initialization for register tmain_calib_hdr0_tx0 01479 this->tmain_calib_hdr0_tx0.address[0] = 0x47; ///< Address=71 01480 this->tmain_calib_hdr0_tx0.msb[0] = 11; 01481 this->tmain_calib_hdr0_tx0.lsb[0] = 0; 01482 01483 //Initialization for register temp_coeff_main_hdr0_tx0 01484 this->temp_coeff_main_hdr0_tx0.address[0] = 0x45; ///< Address=69 01485 this->temp_coeff_main_hdr0_tx0.msb[0] = 11; 01486 this->temp_coeff_main_hdr0_tx0.lsb[0] = 0; 01487 01488 //Initialization for register tmain_calib_hdr1_tx0 01489 this->tmain_calib_hdr1_tx0.address[0] = 0x48; ///< Address=72 01490 this->tmain_calib_hdr1_tx0.msb[0] = 11; 01491 this->tmain_calib_hdr1_tx0.lsb[0] = 0; 01492 01493 //Initialization for register temp_coeff_main_hdr1_tx0 01494 this->temp_coeff_main_hdr1_tx0.address[0] = 0x2d; ///< Address=45 01495 this->temp_coeff_main_hdr1_tx0.msb[0] = 11; 01496 this->temp_coeff_main_hdr1_tx0.lsb[0] = 0; 01497 01498 //Initialization for register tmain_calib_hdr0_tx1 01499 this->tmain_calib_hdr0_tx1.address[0] = 0x49; ///< Address=73 01500 this->tmain_calib_hdr0_tx1.msb[0] = 11; 01501 this->tmain_calib_hdr0_tx1.lsb[0] = 0; 01502 01503 //Initialization for register temp_coeff_main_hdr0_tx1 01504 this->temp_coeff_main_hdr0_tx1.address[0] = 0x2d; ///< Address=45 01505 this->temp_coeff_main_hdr0_tx1.msb[0] = 23; 01506 this->temp_coeff_main_hdr0_tx1.lsb[0] = 12; 01507 01508 //Initialization for register tmain_calib_hdr1_tx1 01509 this->tmain_calib_hdr1_tx1.address[0] = 0x41; ///< Address=65 01510 this->tmain_calib_hdr1_tx1.msb[0] = 23; 01511 this->tmain_calib_hdr1_tx1.lsb[0] = 12; 01512 01513 //Initialization for register temp_coeff_main_hdr1_tx1 01514 this->temp_coeff_main_hdr1_tx1.address[1] = 0x2f; ///< Address=47 01515 this->temp_coeff_main_hdr1_tx1.msb[1] = 23; 01516 this->temp_coeff_main_hdr1_tx1.lsb[1] = 16; 01517 this->temp_coeff_main_hdr1_tx1.address[0] = 0x30; ///< Address=48 01518 this->temp_coeff_main_hdr1_tx1.msb[0] = 23; 01519 this->temp_coeff_main_hdr1_tx1.lsb[0] = 20; 01520 01521 //Initialization for register tmain_calib_hdr0_tx2 01522 this->tmain_calib_hdr0_tx2.address[0] = 0x3f; ///< Address=63 01523 this->tmain_calib_hdr0_tx2.msb[0] = 11; 01524 this->tmain_calib_hdr0_tx2.lsb[0] = 0; 01525 01526 //Initialization for register temp_coeff_main_hdr0_tx2 01527 this->temp_coeff_main_hdr0_tx2.address[1] = 0x31; ///< Address=49 01528 this->temp_coeff_main_hdr0_tx2.msb[1] = 23; 01529 this->temp_coeff_main_hdr0_tx2.lsb[1] = 16; 01530 this->temp_coeff_main_hdr0_tx2.address[0] = 0x32; ///< Address=50 01531 this->temp_coeff_main_hdr0_tx2.msb[0] = 23; 01532 this->temp_coeff_main_hdr0_tx2.lsb[0] = 20; 01533 01534 //Initialization for register tmain_calib_hdr1_tx2 01535 this->tmain_calib_hdr1_tx2.address[0] = 0x45; ///< Address=69 01536 this->tmain_calib_hdr1_tx2.msb[0] = 23; 01537 this->tmain_calib_hdr1_tx2.lsb[0] = 12; 01538 01539 //Initialization for register temp_coeff_main_hdr1_tx2 01540 this->temp_coeff_main_hdr1_tx2.address[1] = 0x33; ///< Address=51 01541 this->temp_coeff_main_hdr1_tx2.msb[1] = 23; 01542 this->temp_coeff_main_hdr1_tx2.lsb[1] = 16; 01543 this->temp_coeff_main_hdr1_tx2.address[0] = 0x34; ///< Address=52 01544 this->temp_coeff_main_hdr1_tx2.msb[0] = 23; 01545 this->temp_coeff_main_hdr1_tx2.lsb[0] = 20; 01546 01547 //Initialization for register tillum_calib_hdr0_tx0 01548 this->tillum_calib_hdr0_tx0.address[0] = 0x47; ///< Address=71 01549 this->tillum_calib_hdr0_tx0.msb[0] = 23; 01550 this->tillum_calib_hdr0_tx0.lsb[0] = 12; 01551 01552 //Initialization for register temp_coeff_illum_hdr0_tx0 01553 this->temp_coeff_illum_hdr0_tx0.address[0] = 0x46; ///< Address=70 01554 this->temp_coeff_illum_hdr0_tx0.msb[0] = 11; 01555 this->temp_coeff_illum_hdr0_tx0.lsb[0] = 0; 01556 01557 //Initialization for register tillum_calib_hdr1_tx0 01558 this->tillum_calib_hdr1_tx0.address[0] = 0x48; ///< Address=72 01559 this->tillum_calib_hdr1_tx0.msb[0] = 23; 01560 this->tillum_calib_hdr1_tx0.lsb[0] = 12; 01561 01562 //Initialization for register temp_coeff_illum_hdr1_tx0 01563 this->temp_coeff_illum_hdr1_tx0.address[1] = 0x51; ///< Address=81 01564 this->temp_coeff_illum_hdr1_tx0.msb[1] = 23; 01565 this->temp_coeff_illum_hdr1_tx0.lsb[1] = 16; 01566 this->temp_coeff_illum_hdr1_tx0.address[0] = 0x52; ///< Address=82 01567 this->temp_coeff_illum_hdr1_tx0.msb[0] = 23; 01568 this->temp_coeff_illum_hdr1_tx0.lsb[0] = 20; 01569 01570 //Initialization for register tillum_calib_hdr0_tx1 01571 this->tillum_calib_hdr0_tx1.address[0] = 0x49; ///< Address=73 01572 this->tillum_calib_hdr0_tx1.msb[0] = 23; 01573 this->tillum_calib_hdr0_tx1.lsb[0] = 12; 01574 01575 //Initialization for register temp_coeff_illum_hdr0_tx1 01576 this->temp_coeff_illum_hdr0_tx1.address[1] = 0x53; ///< Address=83 01577 this->temp_coeff_illum_hdr0_tx1.msb[1] = 23; 01578 this->temp_coeff_illum_hdr0_tx1.lsb[1] = 16; 01579 this->temp_coeff_illum_hdr0_tx1.address[0] = 0x54; ///< Address=84 01580 this->temp_coeff_illum_hdr0_tx1.msb[0] = 23; 01581 this->temp_coeff_illum_hdr0_tx1.lsb[0] = 20; 01582 01583 //Initialization for register tillum_calib_hdr1_tx1 01584 this->tillum_calib_hdr1_tx1.address[0] = 0x43; ///< Address=67 01585 this->tillum_calib_hdr1_tx1.msb[0] = 23; 01586 this->tillum_calib_hdr1_tx1.lsb[0] = 12; 01587 01588 //Initialization for register temp_coeff_illum_hdr1_tx1 01589 this->temp_coeff_illum_hdr1_tx1.address[1] = 0x55; ///< Address=85 01590 this->temp_coeff_illum_hdr1_tx1.msb[1] = 23; 01591 this->temp_coeff_illum_hdr1_tx1.lsb[1] = 16; 01592 this->temp_coeff_illum_hdr1_tx1.address[0] = 0x56; ///< Address=86 01593 this->temp_coeff_illum_hdr1_tx1.msb[0] = 23; 01594 this->temp_coeff_illum_hdr1_tx1.lsb[0] = 20; 01595 01596 //Initialization for register tillum_calib_hdr0_tx2 01597 this->tillum_calib_hdr0_tx2.address[0] = 0x3f; ///< Address=63 01598 this->tillum_calib_hdr0_tx2.msb[0] = 23; 01599 this->tillum_calib_hdr0_tx2.lsb[0] = 12; 01600 01601 //Initialization for register temp_coeff_illum_hdr0_tx2 01602 this->temp_coeff_illum_hdr0_tx2.address[1] = 0x57; ///< Address=87 01603 this->temp_coeff_illum_hdr0_tx2.msb[1] = 23; 01604 this->temp_coeff_illum_hdr0_tx2.lsb[1] = 16; 01605 this->temp_coeff_illum_hdr0_tx2.address[0] = 0x58; ///< Address=88 01606 this->temp_coeff_illum_hdr0_tx2.msb[0] = 23; 01607 this->temp_coeff_illum_hdr0_tx2.lsb[0] = 20; 01608 01609 //Initialization for register tillum_calib_hdr1_tx2 01610 this->tillum_calib_hdr1_tx2.address[0] = 0x46; ///< Address=70 01611 this->tillum_calib_hdr1_tx2.msb[0] = 23; 01612 this->tillum_calib_hdr1_tx2.lsb[0] = 12; 01613 01614 //Initialization for register temp_coeff_illum_hdr1_tx2 01615 this->temp_coeff_illum_hdr1_tx2.address[1] = 0x59; ///< Address=89 01616 this->temp_coeff_illum_hdr1_tx2.msb[1] = 23; 01617 this->temp_coeff_illum_hdr1_tx2.lsb[1] = 16; 01618 this->temp_coeff_illum_hdr1_tx2.address[0] = 0x5a; ///< Address=90 01619 this->temp_coeff_illum_hdr1_tx2.msb[0] = 23; 01620 this->temp_coeff_illum_hdr1_tx2.lsb[0] = 20; 01621 01622 //Initialization for register amb_sat_thr 01623 this->amb_sat_thr.address[0] = 0x0d; ///< Address=13 01624 this->amb_sat_thr.msb[0] = 16; 01625 this->amb_sat_thr.lsb[0] = 7; 01626 01627 //Initialization for register amb_calib 01628 this->amb_calib.address[0] = 0x0b; ///< Address=11 01629 this->amb_calib.msb[0] = 23; 01630 this->amb_calib.lsb[0] = 14; 01631 01632 //Initialization for register amb_phase_corr_pwl_coeff0 01633 this->amb_phase_corr_pwl_coeff0.address[0] = 0x0c; ///< Address=12 01634 this->amb_phase_corr_pwl_coeff0.msb[0] = 23; 01635 this->amb_phase_corr_pwl_coeff0.lsb[0] = 16; 01636 01637 //Initialization for register amb_phase_corr_pwl_x0 01638 this->amb_phase_corr_pwl_x0.address[0] = 0xb8; ///< Address=184 01639 this->amb_phase_corr_pwl_x0.msb[0] = 9; 01640 this->amb_phase_corr_pwl_x0.lsb[0] = 0; 01641 01642 //Initialization for register amb_phase_corr_pwl_x1 01643 this->amb_phase_corr_pwl_x1.address[0] = 0xb8; ///< Address=184 01644 this->amb_phase_corr_pwl_x1.msb[0] = 19; 01645 this->amb_phase_corr_pwl_x1.lsb[0] = 10; 01646 01647 //Initialization for register amb_phase_corr_pwl_x2 01648 this->amb_phase_corr_pwl_x2.address[0] = 0xb9; ///< Address=185 01649 this->amb_phase_corr_pwl_x2.msb[0] = 9; 01650 this->amb_phase_corr_pwl_x2.lsb[0] = 0; 01651 01652 //Initialization for register amb_phase_corr_pwl_coeff1 01653 this->amb_phase_corr_pwl_coeff1.address[0] = 0xb4; ///< Address=180 01654 this->amb_phase_corr_pwl_coeff1.msb[0] = 7; 01655 this->amb_phase_corr_pwl_coeff1.lsb[0] = 0; 01656 01657 //Initialization for register amb_phase_corr_pwl_coeff2 01658 this->amb_phase_corr_pwl_coeff2.address[0] = 0xb4; ///< Address=180 01659 this->amb_phase_corr_pwl_coeff2.msb[0] = 15; 01660 this->amb_phase_corr_pwl_coeff2.lsb[0] = 8; 01661 01662 //Initialization for register amb_phase_corr_pwl_coeff3 01663 this->amb_phase_corr_pwl_coeff3.address[0] = 0xb4; ///< Address=180 01664 this->amb_phase_corr_pwl_coeff3.msb[0] = 23; 01665 this->amb_phase_corr_pwl_coeff3.lsb[0] = 16; 01666 01667 //Initialization for register scale_amb_phase_corr_coeff 01668 this->scale_amb_phase_corr_coeff.address[0] = 0xb5; ///< Address=181 01669 this->scale_amb_phase_corr_coeff.msb[0] = 2; 01670 this->scale_amb_phase_corr_coeff.lsb[0] = 0; 01671 01672 //Initialization for register temp_coeff_illum_square_hdr0 01673 this->temp_coeff_illum_square_hdr0.address[0] = 0xb6; ///< Address=182 01674 this->temp_coeff_illum_square_hdr0.msb[0] = 7; 01675 this->temp_coeff_illum_square_hdr0.lsb[0] = 0; 01676 01677 //Initialization for register temp_coeff_illum_square_hdr1 01678 this->temp_coeff_illum_square_hdr1.address[0] = 0xb6; ///< Address=182 01679 this->temp_coeff_illum_square_hdr1.msb[0] = 15; 01680 this->temp_coeff_illum_square_hdr1.lsb[0] = 8; 01681 01682 //Initialization for register temp_coeff_main_square_hdr0 01683 this->temp_coeff_main_square_hdr0.address[0] = 0xb7; ///< Address=183 01684 this->temp_coeff_main_square_hdr0.msb[0] = 7; 01685 this->temp_coeff_main_square_hdr0.lsb[0] = 0; 01686 01687 //Initialization for register temp_coeff_main_square_hdr1 01688 this->temp_coeff_main_square_hdr1.address[0] = 0xb7; ///< Address=183 01689 this->temp_coeff_main_square_hdr1.msb[0] = 15; 01690 this->temp_coeff_main_square_hdr1.lsb[0] = 8; 01691 01692 //Initialization for register scale_phase_temp_corr_square 01693 this->scale_phase_temp_corr_square.address[0] = 0xb5; ///< Address=181 01694 this->scale_phase_temp_corr_square.msb[0] = 5; 01695 this->scale_phase_temp_corr_square.lsb[0] = 3; 01696 01697 //Initialization for register en_nl_corr 01698 this->en_nl_corr.address[0] = 0x4a; ///< Address=74 01699 this->en_nl_corr.msb[0] = 0; 01700 this->en_nl_corr.lsb[0] = 0; 01701 01702 //Initialization for register a1_coeff_hdr0_tx0 01703 this->a1_coeff_hdr0_tx0.address[0] = 0x4b; ///< Address=75 01704 this->a1_coeff_hdr0_tx0.msb[0] = 15; 01705 this->a1_coeff_hdr0_tx0.lsb[0] = 0; 01706 01707 //Initialization for register a2_coeff_hdr0_tx0 01708 this->a2_coeff_hdr0_tx0.address[0] = 0x4c; ///< Address=76 01709 this->a2_coeff_hdr0_tx0.msb[0] = 15; 01710 this->a2_coeff_hdr0_tx0.lsb[0] = 0; 01711 01712 //Initialization for register a3_coeff_hdr0_tx0 01713 this->a3_coeff_hdr0_tx0.address[0] = 0x4d; ///< Address=77 01714 this->a3_coeff_hdr0_tx0.msb[0] = 15; 01715 this->a3_coeff_hdr0_tx0.lsb[0] = 0; 01716 01717 //Initialization for register a4_coeff_hdr0_tx0 01718 this->a4_coeff_hdr0_tx0.address[0] = 0x4e; ///< Address=78 01719 this->a4_coeff_hdr0_tx0.msb[0] = 15; 01720 this->a4_coeff_hdr0_tx0.lsb[0] = 0; 01721 01722 //Initialization for register scale_nl_corr_coeff 01723 this->scale_nl_corr_coeff.address[0] = 0x4a; ///< Address=74 01724 this->scale_nl_corr_coeff.msb[0] = 19; 01725 this->scale_nl_corr_coeff.lsb[0] = 18; 01726 01727 //Initialization for register a0_coeff_hdr0_tx0 01728 this->a0_coeff_hdr0_tx0.address[0] = 0x4a; ///< Address=74 01729 this->a0_coeff_hdr0_tx0.msb[0] = 17; 01730 this->a0_coeff_hdr0_tx0.lsb[0] = 2; 01731 01732 //Initialization for register a0_coeff_hdr1_tx0 01733 this->a0_coeff_hdr1_tx0.address[0] = 0xa2; ///< Address=162 01734 this->a0_coeff_hdr1_tx0.msb[0] = 15; 01735 this->a0_coeff_hdr1_tx0.lsb[0] = 0; 01736 01737 //Initialization for register a0_coeff_hdr0_tx1 01738 this->a0_coeff_hdr0_tx1.address[0] = 0xa3; ///< Address=163 01739 this->a0_coeff_hdr0_tx1.msb[0] = 15; 01740 this->a0_coeff_hdr0_tx1.lsb[0] = 0; 01741 01742 //Initialization for register a0_coeff_hdr1_tx1 01743 this->a0_coeff_hdr1_tx1.address[0] = 0xa4; ///< Address=164 01744 this->a0_coeff_hdr1_tx1.msb[0] = 15; 01745 this->a0_coeff_hdr1_tx1.lsb[0] = 0; 01746 01747 //Initialization for register a0_coeff_hdr0_tx2 01748 this->a0_coeff_hdr0_tx2.address[0] = 0xa5; ///< Address=165 01749 this->a0_coeff_hdr0_tx2.msb[0] = 15; 01750 this->a0_coeff_hdr0_tx2.lsb[0] = 0; 01751 01752 //Initialization for register a0_coeff_hdr1_tx2 01753 this->a0_coeff_hdr1_tx2.address[0] = 0xa6; ///< Address=166 01754 this->a0_coeff_hdr1_tx2.msb[0] = 15; 01755 this->a0_coeff_hdr1_tx2.lsb[0] = 0; 01756 01757 //Initialization for register a1_coeff_hdr1_tx0 01758 this->a1_coeff_hdr1_tx0.address[0] = 0xa7; ///< Address=167 01759 this->a1_coeff_hdr1_tx0.msb[0] = 15; 01760 this->a1_coeff_hdr1_tx0.lsb[0] = 0; 01761 01762 //Initialization for register a1_coeff_hdr0_tx1 01763 this->a1_coeff_hdr0_tx1.address[0] = 0xa8; ///< Address=168 01764 this->a1_coeff_hdr0_tx1.msb[0] = 15; 01765 this->a1_coeff_hdr0_tx1.lsb[0] = 0; 01766 01767 //Initialization for register a1_coeff_hdr1_tx1 01768 this->a1_coeff_hdr1_tx1.address[0] = 0xa9; ///< Address=169 01769 this->a1_coeff_hdr1_tx1.msb[0] = 15; 01770 this->a1_coeff_hdr1_tx1.lsb[0] = 0; 01771 01772 //Initialization for register a1_coeff_hdr0_tx2 01773 this->a1_coeff_hdr0_tx2.address[0] = 0xaa; ///< Address=170 01774 this->a1_coeff_hdr0_tx2.msb[0] = 15; 01775 this->a1_coeff_hdr0_tx2.lsb[0] = 0; 01776 01777 //Initialization for register a1_coeff_hdr1_tx2 01778 this->a1_coeff_hdr1_tx2.address[0] = 0xab; ///< Address=171 01779 this->a1_coeff_hdr1_tx2.msb[0] = 15; 01780 this->a1_coeff_hdr1_tx2.lsb[0] = 0; 01781 01782 //Initialization for register a2_coeff_hdr1_tx0 01783 this->a2_coeff_hdr1_tx0.address[0] = 0xac; ///< Address=172 01784 this->a2_coeff_hdr1_tx0.msb[0] = 15; 01785 this->a2_coeff_hdr1_tx0.lsb[0] = 0; 01786 01787 //Initialization for register a2_coeff_hdr0_tx1 01788 this->a2_coeff_hdr0_tx1.address[0] = 0xad; ///< Address=173 01789 this->a2_coeff_hdr0_tx1.msb[0] = 15; 01790 this->a2_coeff_hdr0_tx1.lsb[0] = 0; 01791 01792 //Initialization for register a2_coeff_hdr1_tx1 01793 this->a2_coeff_hdr1_tx1.address[0] = 0xae; ///< Address=174 01794 this->a2_coeff_hdr1_tx1.msb[0] = 15; 01795 this->a2_coeff_hdr1_tx1.lsb[0] = 0; 01796 01797 //Initialization for register a2_coeff_hdr0_tx2 01798 this->a2_coeff_hdr0_tx2.address[0] = 0xaf; ///< Address=175 01799 this->a2_coeff_hdr0_tx2.msb[0] = 15; 01800 this->a2_coeff_hdr0_tx2.lsb[0] = 0; 01801 01802 //Initialization for register a2_coeff_hdr1_tx2 01803 this->a2_coeff_hdr1_tx2.address[0] = 0xb0; ///< Address=176 01804 this->a2_coeff_hdr1_tx2.msb[0] = 15; 01805 this->a2_coeff_hdr1_tx2.lsb[0] = 0; 01806 01807 //Initialization for register a3_coeff_hdr1_tx0 01808 this->a3_coeff_hdr1_tx0.address[0] = 0xb1; ///< Address=177 01809 this->a3_coeff_hdr1_tx0.msb[0] = 15; 01810 this->a3_coeff_hdr1_tx0.lsb[0] = 0; 01811 01812 //Initialization for register a3_coeff_hdr0_tx1 01813 this->a3_coeff_hdr0_tx1.address[1] = 0xa2; ///< Address=162 01814 this->a3_coeff_hdr0_tx1.msb[1] = 23; 01815 this->a3_coeff_hdr0_tx1.lsb[1] = 16; 01816 this->a3_coeff_hdr0_tx1.address[0] = 0xa3; ///< Address=163 01817 this->a3_coeff_hdr0_tx1.msb[0] = 23; 01818 this->a3_coeff_hdr0_tx1.lsb[0] = 16; 01819 01820 //Initialization for register a3_coeff_hdr1_tx1 01821 this->a3_coeff_hdr1_tx1.address[1] = 0xa4; ///< Address=164 01822 this->a3_coeff_hdr1_tx1.msb[1] = 23; 01823 this->a3_coeff_hdr1_tx1.lsb[1] = 16; 01824 this->a3_coeff_hdr1_tx1.address[0] = 0xa5; ///< Address=165 01825 this->a3_coeff_hdr1_tx1.msb[0] = 23; 01826 this->a3_coeff_hdr1_tx1.lsb[0] = 16; 01827 01828 //Initialization for register a3_coeff_hdr0_tx2 01829 this->a3_coeff_hdr0_tx2.address[1] = 0xa6; ///< Address=166 01830 this->a3_coeff_hdr0_tx2.msb[1] = 23; 01831 this->a3_coeff_hdr0_tx2.lsb[1] = 16; 01832 this->a3_coeff_hdr0_tx2.address[0] = 0xa7; ///< Address=167 01833 this->a3_coeff_hdr0_tx2.msb[0] = 23; 01834 this->a3_coeff_hdr0_tx2.lsb[0] = 16; 01835 01836 //Initialization for register a3_coeff_hdr1_tx2 01837 this->a3_coeff_hdr1_tx2.address[1] = 0xa8; ///< Address=168 01838 this->a3_coeff_hdr1_tx2.msb[1] = 23; 01839 this->a3_coeff_hdr1_tx2.lsb[1] = 16; 01840 this->a3_coeff_hdr1_tx2.address[0] = 0xa9; ///< Address=169 01841 this->a3_coeff_hdr1_tx2.msb[0] = 23; 01842 this->a3_coeff_hdr1_tx2.lsb[0] = 16; 01843 01844 //Initialization for register a4_coeff_hdr1_tx0 01845 this->a4_coeff_hdr1_tx0.address[1] = 0xaa; ///< Address=170 01846 this->a4_coeff_hdr1_tx0.msb[1] = 23; 01847 this->a4_coeff_hdr1_tx0.lsb[1] = 16; 01848 this->a4_coeff_hdr1_tx0.address[0] = 0xab; ///< Address=171 01849 this->a4_coeff_hdr1_tx0.msb[0] = 23; 01850 this->a4_coeff_hdr1_tx0.lsb[0] = 16; 01851 01852 //Initialization for register a4_coeff_hdr0_tx1 01853 this->a4_coeff_hdr0_tx1.address[1] = 0xac; ///< Address=172 01854 this->a4_coeff_hdr0_tx1.msb[1] = 23; 01855 this->a4_coeff_hdr0_tx1.lsb[1] = 16; 01856 this->a4_coeff_hdr0_tx1.address[0] = 0xad; ///< Address=173 01857 this->a4_coeff_hdr0_tx1.msb[0] = 23; 01858 this->a4_coeff_hdr0_tx1.lsb[0] = 16; 01859 01860 //Initialization for register a4_coeff_hdr1_tx1 01861 this->a4_coeff_hdr1_tx1.address[1] = 0xae; ///< Address=174 01862 this->a4_coeff_hdr1_tx1.msb[1] = 23; 01863 this->a4_coeff_hdr1_tx1.lsb[1] = 16; 01864 this->a4_coeff_hdr1_tx1.address[0] = 0xaf; ///< Address=175 01865 this->a4_coeff_hdr1_tx1.msb[0] = 23; 01866 this->a4_coeff_hdr1_tx1.lsb[0] = 16; 01867 01868 //Initialization for register a4_coeff_hdr0_tx2 01869 this->a4_coeff_hdr0_tx2.address[1] = 0xb0; ///< Address=176 01870 this->a4_coeff_hdr0_tx2.msb[1] = 23; 01871 this->a4_coeff_hdr0_tx2.lsb[1] = 16; 01872 this->a4_coeff_hdr0_tx2.address[0] = 0xb1; ///< Address=177 01873 this->a4_coeff_hdr0_tx2.msb[0] = 23; 01874 this->a4_coeff_hdr0_tx2.lsb[0] = 16; 01875 01876 //Initialization for register a4_coeff_hdr1_tx2 01877 this->a4_coeff_hdr1_tx2.address[0] = 0xb2; ///< Address=178 01878 this->a4_coeff_hdr1_tx2.msb[0] = 15; 01879 this->a4_coeff_hdr1_tx2.lsb[0] = 0; 01880 01881 //Initialization for register tillum 01882 this->tillum.address[0] = 0x04; ///< Address=4 01883 this->tillum.msb[0] = 19; 01884 this->tillum.lsb[0] = 8; 01885 01886 //Initialization for register tsens_slave0 01887 this->tsens_slave0.address[0] = 0x02; ///< Address=2 01888 this->tsens_slave0.msb[0] = 6; 01889 this->tsens_slave0.lsb[0] = 0; 01890 01891 //Initialization for register tsens_slave1 01892 this->tsens_slave1.address[0] = 0x02; ///< Address=2 01893 this->tsens_slave1.msb[0] = 13; 01894 this->tsens_slave1.lsb[0] = 7; 01895 01896 //Initialization for register tsens_slave2 01897 this->tsens_slave2.address[0] = 0x02; ///< Address=2 01898 this->tsens_slave2.msb[0] = 20; 01899 this->tsens_slave2.lsb[0] = 14; 01900 01901 //Initialization for register config_tillum_msb 01902 this->config_tillum_msb.address[0] = 0x07; ///< Address=7 01903 this->config_tillum_msb.msb[0] = 23; 01904 this->config_tillum_msb.lsb[0] = 20; 01905 01906 //Initialization for register en_tillum_12b 01907 this->en_tillum_12b.address[0] = 0x0d; ///< Address=13 01908 this->en_tillum_12b.msb[0] = 23; 01909 this->en_tillum_12b.lsb[0] = 23; 01910 01911 //Initialization for register tillum_unsigned 01912 this->tillum_unsigned.address[0] = 0x04; ///< Address=4 01913 this->tillum_unsigned.msb[0] = 23; 01914 this->tillum_unsigned.lsb[0] = 23; 01915 01916 //Initialization for register temp_avg_illum 01917 this->temp_avg_illum.address[0] = 0x02; ///< Address=2 01918 this->temp_avg_illum.msb[0] = 23; 01919 this->temp_avg_illum.lsb[0] = 22; 01920 01921 //Initialization for register en_tsens_read_fvd 01922 this->en_tsens_read_fvd.address[0] = 0x03; ///< Address=3 01923 this->en_tsens_read_fvd.msb[0] = 18; 01924 this->en_tsens_read_fvd.lsb[0] = 18; 01925 01926 //Initialization for register en_tillum_read 01927 this->en_tillum_read.address[0] = 0x02; ///< Address=2 01928 this->en_tillum_read.msb[0] = 21; 01929 this->en_tillum_read.lsb[0] = 21; 01930 01931 //Initialization for register eeprom_read_trig 01932 this->eeprom_read_trig.address[0] = 0x01; ///< Address=1 01933 this->eeprom_read_trig.msb[0] = 0; 01934 this->eeprom_read_trig.lsb[0] = 0; 01935 01936 //Initialization for register swap_read_data 01937 this->swap_read_data.address[0] = 0x01; ///< Address=1 01938 this->swap_read_data.msb[0] = 1; 01939 this->swap_read_data.lsb[0] = 1; 01940 01941 //Initialization for register eeprom_start_reg_addr 01942 this->eeprom_start_reg_addr.address[0] = 0x01; ///< Address=1 01943 this->eeprom_start_reg_addr.msb[0] = 16; 01944 this->eeprom_start_reg_addr.lsb[0] = 9; 01945 01946 //Initialization for register frame_vd_trig 01947 this->frame_vd_trig.address[0] = 0x01; ///< Address=1 01948 this->frame_vd_trig.msb[0] = 17; 01949 this->frame_vd_trig.lsb[0] = 17; 01950 01951 //Initialization for register i2c_trig_reg 01952 this->i2c_trig_reg.address[0] = 0x01; ///< Address=1 01953 this->i2c_trig_reg.msb[0] = 18; 01954 this->i2c_trig_reg.lsb[0] = 18; 01955 01956 //Initialization for register i2c_en 01957 this->i2c_en.address[0] = 0x01; ///< Address=1 01958 this->i2c_en.msb[0] = 19; 01959 this->i2c_en.lsb[0] = 19; 01960 01961 //Initialization for register i2c_rw 01962 this->i2c_rw.address[0] = 0x01; ///< Address=1 01963 this->i2c_rw.msb[0] = 21; 01964 this->i2c_rw.lsb[0] = 20; 01965 01966 //Initialization for register i2c_read_data 01967 this->i2c_read_data.address[0] = 0x03; ///< Address=3 01968 this->i2c_read_data.msb[0] = 7; 01969 this->i2c_read_data.lsb[0] = 0; 01970 01971 //Initialization for register i2c_write_data1 01972 this->i2c_write_data1.address[0] = 0x03; ///< Address=3 01973 this->i2c_write_data1.msb[0] = 16; 01974 this->i2c_write_data1.lsb[0] = 9; 01975 01976 //Initialization for register i2c_num_tran 01977 this->i2c_num_tran.address[0] = 0x03; ///< Address=3 01978 this->i2c_num_tran.msb[0] = 17; 01979 this->i2c_num_tran.lsb[0] = 17; 01980 01981 //Initialization for register en_eeprom_read 01982 this->en_eeprom_read.address[0] = 0x01; ///< Address=1 01983 this->en_eeprom_read.msb[0] = 23; 01984 this->en_eeprom_read.lsb[0] = 23; 01985 01986 //Initialization for register init_load_done 01987 this->init_load_done.address[0] = 0x03; ///< Address=3 01988 this->init_load_done.msb[0] = 8; 01989 this->init_load_done.lsb[0] = 8; 01990 01991 //Initialization for register addr_slave_eeprom 01992 this->addr_slave_eeprom.address[0] = 0x01; ///< Address=1 01993 this->addr_slave_eeprom.msb[0] = 8; 01994 this->addr_slave_eeprom.lsb[0] = 2; 01995 01996 //Initialization for register i2c_num_bytes_tran1 01997 this->i2c_num_bytes_tran1.address[0] = 0x07; ///< Address=7 01998 this->i2c_num_bytes_tran1.msb[0] = 17; 01999 this->i2c_num_bytes_tran1.lsb[0] = 16; 02000 02001 //Initialization for register i2c_num_bytes_tran2 02002 this->i2c_num_bytes_tran2.address[0] = 0x05; ///< Address=5 02003 this->i2c_num_bytes_tran2.msb[0] = 23; 02004 this->i2c_num_bytes_tran2.lsb[0] = 22; 02005 02006 //Initialization for register i2c_write_data2 02007 this->i2c_write_data2.address[0] = 0x07; ///< Address=7 02008 this->i2c_write_data2.msb[0] = 7; 02009 this->i2c_write_data2.lsb[0] = 0; 02010 02011 //Initialization for register i2c_sel_read_bytes 02012 this->i2c_sel_read_bytes.address[0] = 0x07; ///< Address=7 02013 this->i2c_sel_read_bytes.msb[0] = 19; 02014 this->i2c_sel_read_bytes.lsb[0] = 18; 02015 02016 //Initialization for register i2c_cont_rw 02017 this->i2c_cont_rw.address[0] = 0x00; ///< Address=0 02018 this->i2c_cont_rw.msb[0] = 6; 02019 this->i2c_cont_rw.lsb[0] = 6; 02020 02021 //Initialization for register dis_ovldet 02022 this->dis_ovldet.address[0] = 0x65; ///< Address=101 02023 this->dis_ovldet.msb[0] = 23; 02024 this->dis_ovldet.lsb[0] = 23; 02025 02026 //Initialization for register prog_ovldet_refp 02027 this->prog_ovldet_refp.address[0] = 0x64; ///< Address=100 02028 this->prog_ovldet_refp.msb[0] = 20; 02029 this->prog_ovldet_refp.lsb[0] = 18; 02030 02031 //Initialization for register prog_ovldet_refm 02032 this->prog_ovldet_refm.address[0] = 0x64; ///< Address=100 02033 this->prog_ovldet_refm.msb[0] = 23; 02034 this->prog_ovldet_refm.lsb[0] = 21; 02035 02036 //Initialization for register iamb_max_sel 02037 this->iamb_max_sel.address[0] = 0x72; ///< Address=114 02038 this->iamb_max_sel.msb[0] = 7; 02039 this->iamb_max_sel.lsb[0] = 4; 02040 02041 //Initialization for register tm_vrefp_diode 02042 this->tm_vrefp_diode.address[0] = 0x6d; ///< Address=109 02043 this->tm_vrefp_diode.msb[0] = 2; 02044 this->tm_vrefp_diode.lsb[0] = 0; 02045 02046 //Initialization for register tm_vrefm_diode 02047 this->tm_vrefm_diode.address[0] = 0x6d; ///< Address=109 02048 this->tm_vrefm_diode.msb[0] = 5; 02049 this->tm_vrefm_diode.lsb[0] = 3; 02050 02051 //Initialization for register gpo1_mux_sel 02052 this->gpo1_mux_sel.address[0] = 0x78; ///< Address=120 02053 this->gpo1_mux_sel.msb[0] = 8; 02054 this->gpo1_mux_sel.lsb[0] = 6; 02055 02056 //Initialization for register gpio1_obuf_en 02057 this->gpio1_obuf_en.address[0] = 0x78; ///< Address=120 02058 this->gpio1_obuf_en.msb[0] = 12; 02059 this->gpio1_obuf_en.lsb[0] = 12; 02060 02061 //Initialization for register gpio1_ibuf_en 02062 this->gpio1_ibuf_en.address[0] = 0x78; ///< Address=120 02063 this->gpio1_ibuf_en.msb[0] = 13; 02064 this->gpio1_ibuf_en.lsb[0] = 13; 02065 02066 //Initialization for register gpo2_mux_sel 02067 this->gpo2_mux_sel.address[0] = 0x78; ///< Address=120 02068 this->gpo2_mux_sel.msb[0] = 11; 02069 this->gpo2_mux_sel.lsb[0] = 9; 02070 02071 //Initialization for register gpio2_obuf_en 02072 this->gpio2_obuf_en.address[0] = 0x78; ///< Address=120 02073 this->gpio2_obuf_en.msb[0] = 15; 02074 this->gpio2_obuf_en.lsb[0] = 15; 02075 02076 //Initialization for register gpio2_ibuf_en 02077 this->gpio2_ibuf_en.address[0] = 0x78; ///< Address=120 02078 this->gpio2_ibuf_en.msb[0] = 16; 02079 this->gpio2_ibuf_en.lsb[0] = 16; 02080 02081 //Initialization for register gpo3_mux_sel 02082 this->gpo3_mux_sel.address[0] = 0x78; ///< Address=120 02083 this->gpo3_mux_sel.msb[0] = 2; 02084 this->gpo3_mux_sel.lsb[0] = 0; 02085 02086 //Initialization for register sel_gp3_on_sdam 02087 this->sel_gp3_on_sdam.address[0] = 0x78; ///< Address=120 02088 this->sel_gp3_on_sdam.msb[0] = 22; 02089 this->sel_gp3_on_sdam.lsb[0] = 22; 02090 02091 //Initialization for register dealias_en 02092 this->dealias_en.address[0] = 0x71; ///< Address=113 02093 this->dealias_en.msb[0] = 1; 02094 this->dealias_en.lsb[0] = 1; 02095 02096 //Initialization for register dealias_freq 02097 this->dealias_freq.address[0] = 0x71; ///< Address=113 02098 this->dealias_freq.msb[0] = 2; 02099 this->dealias_freq.lsb[0] = 2; 02100 02101 //Initialization for register shift_illum_phase 02102 this->shift_illum_phase.address[0] = 0x71; ///< Address=113 02103 this->shift_illum_phase.msb[0] = 6; 02104 this->shift_illum_phase.lsb[0] = 3; 02105 02106 //Initialization for register shut_clocks 02107 this->shut_clocks.address[0] = 0x71; ///< Address=113 02108 this->shut_clocks.msb[0] = 8; 02109 this->shut_clocks.lsb[0] = 8; 02110 02111 //Initialization for register invert_tg_clk 02112 this->invert_tg_clk.address[0] = 0x71; ///< Address=113 02113 this->invert_tg_clk.msb[0] = 9; 02114 this->invert_tg_clk.lsb[0] = 9; 02115 02116 //Initialization for register invert_afe_clk 02117 this->invert_afe_clk.address[0] = 0x71; ///< Address=113 02118 this->invert_afe_clk.msb[0] = 11; 02119 this->invert_afe_clk.lsb[0] = 11; 02120 02121 //Initialization for register dis_illum_clk_tx 02122 this->dis_illum_clk_tx.address[0] = 0x71; ///< Address=113 02123 this->dis_illum_clk_tx.msb[0] = 12; 02124 this->dis_illum_clk_tx.lsb[0] = 12; 02125 02126 //Initialization for register en_illum_clk_gpio 02127 this->en_illum_clk_gpio.address[0] = 0x71; ///< Address=113 02128 this->en_illum_clk_gpio.msb[0] = 16; 02129 this->en_illum_clk_gpio.lsb[0] = 16; 02130 02131 //Initialization for register illum_clk_gpio_mode 02132 this->illum_clk_gpio_mode.address[0] = 0x71; ///< Address=113 02133 this->illum_clk_gpio_mode.msb[0] = 15; 02134 this->illum_clk_gpio_mode.lsb[0] = 15; 02135 02136 //Initialization for register unmask_illumen_intxtalk 02137 this->unmask_illumen_intxtalk.address[0] = 0x71; ///< Address=113 02138 this->unmask_illumen_intxtalk.msb[0] = 17; 02139 this->unmask_illumen_intxtalk.lsb[0] = 17; 02140 02141 //Initialization for register temp_offset 02142 this->temp_offset.address[0] = 0x6e; ///< Address=110 02143 this->temp_offset.msb[0] = 16; 02144 this->temp_offset.lsb[0] = 8; 02145 02146 //Initialization for register en_temp_conv 02147 this->en_temp_conv.address[0] = 0x6e; ///< Address=110 02148 this->en_temp_conv.msb[0] = 19; 02149 this->en_temp_conv.lsb[0] = 19; 02150 02151 //Initialization for register calib_curr1_DAC_I 02152 this->calib_curr1_DAC_I.address[0] = 0x74; ///< Address=116 02153 this->calib_curr1_DAC_I.msb[0] = 3; 02154 this->calib_curr1_DAC_I.lsb[0] = 0; 02155 02156 //Initialization for register calib_curr1_DAC_Q 02157 this->calib_curr1_DAC_Q.address[0] = 0x74; ///< Address=116 02158 this->calib_curr1_DAC_Q.msb[0] = 7; 02159 this->calib_curr1_DAC_Q.lsb[0] = 4; 02160 02161 //Initialization for register calib_curr1_en_I 02162 this->calib_curr1_en_I.address[0] = 0x74; ///< Address=116 02163 this->calib_curr1_en_I.msb[0] = 8; 02164 this->calib_curr1_en_I.lsb[0] = 8; 02165 02166 //Initialization for register calib_curr1_en_Q 02167 this->calib_curr1_en_Q.address[0] = 0x74; ///< Address=116 02168 this->calib_curr1_en_Q.msb[0] = 9; 02169 this->calib_curr1_en_Q.lsb[0] = 9; 02170 02171 //Initialization for register calib_curr1_inv_CLK_I 02172 this->calib_curr1_inv_CLK_I.address[0] = 0x74; ///< Address=116 02173 this->calib_curr1_inv_CLK_I.msb[0] = 10; 02174 this->calib_curr1_inv_CLK_I.lsb[0] = 10; 02175 02176 //Initialization for register calib_curr1_inv_CLK_Q 02177 this->calib_curr1_inv_CLK_Q.address[0] = 0x74; ///< Address=116 02178 this->calib_curr1_inv_CLK_Q.msb[0] = 11; 02179 this->calib_curr1_inv_CLK_Q.lsb[0] = 11; 02180 02181 //Initialization for register calib_curr1_sel_CLK_I 02182 this->calib_curr1_sel_CLK_I.address[0] = 0x74; ///< Address=116 02183 this->calib_curr1_sel_CLK_I.msb[0] = 12; 02184 this->calib_curr1_sel_CLK_I.lsb[0] = 12; 02185 02186 //Initialization for register calib_curr1_gain_sel 02187 this->calib_curr1_gain_sel.address[0] = 0x74; ///< Address=116 02188 this->calib_curr1_gain_sel.msb[0] = 14; 02189 this->calib_curr1_gain_sel.lsb[0] = 13; 02190 02191 //Initialization for register calib_curr1_spare 02192 this->calib_curr1_spare.address[0] = 0x74; ///< Address=116 02193 this->calib_curr1_spare.msb[0] = 15; 02194 this->calib_curr1_spare.lsb[0] = 15; 02195 02196 //Initialization for register dis_glb_pd_refsys 02197 this->dis_glb_pd_refsys.address[0] = 0x76; ///< Address=118 02198 this->dis_glb_pd_refsys.msb[0] = 0; 02199 this->dis_glb_pd_refsys.lsb[0] = 0; 02200 02201 //Initialization for register dis_glb_pd_temp_sens 02202 this->dis_glb_pd_temp_sens.address[0] = 0x76; ///< Address=118 02203 this->dis_glb_pd_temp_sens.msb[0] = 1; 02204 this->dis_glb_pd_temp_sens.lsb[0] = 1; 02205 02206 //Initialization for register dis_glb_pd_illum_drv 02207 this->dis_glb_pd_illum_drv.address[0] = 0x76; ///< Address=118 02208 this->dis_glb_pd_illum_drv.msb[0] = 2; 02209 this->dis_glb_pd_illum_drv.lsb[0] = 2; 02210 02211 //Initialization for register dis_glb_pd_afe 02212 this->dis_glb_pd_afe.address[0] = 0x76; ///< Address=118 02213 this->dis_glb_pd_afe.msb[0] = 3; 02214 this->dis_glb_pd_afe.lsb[0] = 3; 02215 02216 //Initialization for register dis_glb_pd_afe_dac 02217 this->dis_glb_pd_afe_dac.address[0] = 0x76; ///< Address=118 02218 this->dis_glb_pd_afe_dac.msb[0] = 4; 02219 this->dis_glb_pd_afe_dac.lsb[0] = 4; 02220 02221 //Initialization for register dis_glb_pd_amb_dac 02222 this->dis_glb_pd_amb_dac.address[0] = 0x76; ///< Address=118 02223 this->dis_glb_pd_amb_dac.msb[0] = 5; 02224 this->dis_glb_pd_amb_dac.lsb[0] = 5; 02225 02226 //Initialization for register dis_glb_pd_amb_adc 02227 this->dis_glb_pd_amb_adc.address[0] = 0x76; ///< Address=118 02228 this->dis_glb_pd_amb_adc.msb[0] = 6; 02229 this->dis_glb_pd_amb_adc.lsb[0] = 6; 02230 02231 //Initialization for register dis_glb_pd_test_curr 02232 this->dis_glb_pd_test_curr.address[0] = 0x76; ///< Address=118 02233 this->dis_glb_pd_test_curr.msb[0] = 7; 02234 this->dis_glb_pd_test_curr.lsb[0] = 7; 02235 02236 //Initialization for register dis_glb_pd_osc 02237 this->dis_glb_pd_osc.address[0] = 0x76; ///< Address=118 02238 this->dis_glb_pd_osc.msb[0] = 8; 02239 this->dis_glb_pd_osc.lsb[0] = 8; 02240 02241 //Initialization for register dis_glb_pd_i2chost 02242 this->dis_glb_pd_i2chost.address[0] = 0x76; ///< Address=118 02243 this->dis_glb_pd_i2chost.msb[0] = 9; 02244 this->dis_glb_pd_i2chost.lsb[0] = 9; 02245 02246 //Initialization for register pdn_global 02247 this->pdn_global.address[0] = 0x76; ///< Address=118 02248 this->pdn_global.msb[0] = 11; 02249 this->pdn_global.lsb[0] = 11; 02250 02251 //Initialization for register en_dyn_pd_refsys 02252 this->en_dyn_pd_refsys.address[0] = 0x77; ///< Address=119 02253 this->en_dyn_pd_refsys.msb[0] = 0; 02254 this->en_dyn_pd_refsys.lsb[0] = 0; 02255 02256 //Initialization for register en_dyn_pd_temp_sens 02257 this->en_dyn_pd_temp_sens.address[0] = 0x77; ///< Address=119 02258 this->en_dyn_pd_temp_sens.msb[0] = 1; 02259 this->en_dyn_pd_temp_sens.lsb[0] = 1; 02260 02261 //Initialization for register en_dyn_pd_illum_drv 02262 this->en_dyn_pd_illum_drv.address[0] = 0x77; ///< Address=119 02263 this->en_dyn_pd_illum_drv.msb[0] = 2; 02264 this->en_dyn_pd_illum_drv.lsb[0] = 2; 02265 02266 //Initialization for register en_dyn_pd_afe 02267 this->en_dyn_pd_afe.address[0] = 0x77; ///< Address=119 02268 this->en_dyn_pd_afe.msb[0] = 3; 02269 this->en_dyn_pd_afe.lsb[0] = 3; 02270 02271 //Initialization for register en_dyn_pd_afe_dac 02272 this->en_dyn_pd_afe_dac.address[0] = 0x77; ///< Address=119 02273 this->en_dyn_pd_afe_dac.msb[0] = 4; 02274 this->en_dyn_pd_afe_dac.lsb[0] = 4; 02275 02276 //Initialization for register en_dyn_pd_amb_dac 02277 this->en_dyn_pd_amb_dac.address[0] = 0x77; ///< Address=119 02278 this->en_dyn_pd_amb_dac.msb[0] = 5; 02279 this->en_dyn_pd_amb_dac.lsb[0] = 5; 02280 02281 //Initialization for register en_dyn_pd_amb_adc 02282 this->en_dyn_pd_amb_adc.address[0] = 0x77; ///< Address=119 02283 this->en_dyn_pd_amb_adc.msb[0] = 6; 02284 this->en_dyn_pd_amb_adc.lsb[0] = 6; 02285 02286 //Initialization for register en_dyn_pd_test_curr 02287 this->en_dyn_pd_test_curr.address[0] = 0x77; ///< Address=119 02288 this->en_dyn_pd_test_curr.msb[0] = 7; 02289 this->en_dyn_pd_test_curr.lsb[0] = 7; 02290 02291 //Initialization for register en_dyn_pd_osc 02292 this->en_dyn_pd_osc.address[0] = 0x77; ///< Address=119 02293 this->en_dyn_pd_osc.msb[0] = 8; 02294 this->en_dyn_pd_osc.lsb[0] = 8; 02295 02296 //Initialization for register en_dyn_pd_i2chost_osc 02297 this->en_dyn_pd_i2chost_osc.address[0] = 0x77; ///< Address=119 02298 this->en_dyn_pd_i2chost_osc.msb[0] = 9; 02299 this->en_dyn_pd_i2chost_osc.lsb[0] = 9; 02300 02301 //Initialization for register TX0_PIN_CONFIG 02302 this->TX0_PIN_CONFIG.address[0] = 0x7a; ///< Address=122 02303 this->TX0_PIN_CONFIG.msb[0] = 5; 02304 this->TX0_PIN_CONFIG.lsb[0] = 4; 02305 02306 //Initialization for register TX1_PIN_CONFIG 02307 this->TX1_PIN_CONFIG.address[0] = 0x7a; ///< Address=122 02308 this->TX1_PIN_CONFIG.msb[0] = 1; 02309 this->TX1_PIN_CONFIG.lsb[0] = 0; 02310 02311 //Initialization for register TX2_PIN_CONFIG 02312 this->TX2_PIN_CONFIG.address[0] = 0x7a; ///< Address=122 02313 this->TX2_PIN_CONFIG.msb[0] = 3; 02314 this->TX2_PIN_CONFIG.lsb[0] = 2; 02315 02316 //Initialization for register EN_TX_CLKB 02317 this->EN_TX_CLKB.address[0] = 0x79; ///< Address=121 02318 this->EN_TX_CLKB.msb[0] = 0; 02319 this->EN_TX_CLKB.lsb[0] = 0; 02320 02321 //Initialization for register EN_TX_CLKZ 02322 this->EN_TX_CLKZ.address[0] = 0x79; ///< Address=121 02323 this->EN_TX_CLKZ.msb[0] = 2; 02324 this->EN_TX_CLKZ.lsb[0] = 2; 02325 02326 //Initialization for register sel_illum_tx0_on_tx1 02327 this->sel_illum_tx0_on_tx1.address[0] = 0x79; ///< Address=121 02328 this->sel_illum_tx0_on_tx1.msb[0] = 3; 02329 this->sel_illum_tx0_on_tx1.lsb[0] = 3; 02330 02331 //Initialization for register ILLUM_DC_CURR_DAC 02332 this->ILLUM_DC_CURR_DAC.address[0] = 0x79; ///< Address=121 02333 this->ILLUM_DC_CURR_DAC.msb[0] = 11; 02334 this->ILLUM_DC_CURR_DAC.lsb[0] = 8; 02335 02336 //Initialization for register PDN_ILLUM_DC_CURR 02337 this->PDN_ILLUM_DC_CURR.address[0] = 0x79; ///< Address=121 02338 this->PDN_ILLUM_DC_CURR.msb[0] = 12; 02339 this->PDN_ILLUM_DC_CURR.lsb[0] = 12; 02340 02341 //Initialization for register FEEDBACK_CONT_MODE 02342 this->FEEDBACK_CONT_MODE.address[0] = 0x79; ///< Address=121 02343 this->FEEDBACK_CONT_MODE.msb[0] = 13; 02344 this->FEEDBACK_CONT_MODE.lsb[0] = 13; 02345 02346 //Initialization for register PDN_ILLUM_DRV 02347 this->PDN_ILLUM_DRV.address[0] = 0x79; ///< Address=121 02348 this->PDN_ILLUM_DRV.msb[0] = 19; 02349 this->PDN_ILLUM_DRV.lsb[0] = 19; 02350 02351 //Initialization for register EN_TX_DC_CURR_ALL 02352 this->EN_TX_DC_CURR_ALL.address[0] = 0x79; ///< Address=121 02353 this->EN_TX_DC_CURR_ALL.msb[0] = 4; 02354 this->EN_TX_DC_CURR_ALL.lsb[0] = 4; 02355 02356 //Initialization for register EN_CTALK_FB_CLK 02357 this->EN_CTALK_FB_CLK.address[0] = 0x7A; ///< Address=122 02358 this->EN_CTALK_FB_CLK.msb[0] = 11; 02359 this->EN_CTALK_FB_CLK.lsb[0] = 11; 02360 02361 //Initialization for register EN_CALIB_CLK 02362 this->EN_CALIB_CLK.address[0] = 0x79; ///< Address=?? 02363 this->EN_CALIB_CLK.msb[0] = 1; 02364 this->EN_CALIB_CLK.lsb[0] = 1; 02365 02366 } 02367 02368
Generated on Sun Jul 17 2022 05:22:03 by
1.7.2