OPT3101_configuration.cpp

00001 /*
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00006 Redistributions must preserve existing copyright notices and reproduce this license (including the above copyright notice and the disclaimer and (if applicable) source code license limitations below) in the documentation and/or other materials provided with the distribution
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00017 */
00018 
00019 
00020 #include "OPT3101device.h "
00021 
00022 
00023 /* OPT3101 device initialization Sequence Header file written by OPT3101 Calibration tool - Version 0.8.0
00024 By: a0227156
00025 On: 2019-10-02 19:54:11
00026 Configuration Settings:
00027 {
00028     "genDeviceI2CMasterConnection": 1,
00029     "autoHDRMode": true,
00030     "monoshotMode": false,
00031     "TX0HCurrent": 0,
00032     "genDeviceI2CMasterTempSensor": false,
00033     "TXDCCurrent": 0,
00034     "superHDRMode": false,
00035     "LEDOrder": 73746,
00036     "timeStamp": 2019-10-02 19:53:28,
00037     "genDeviceAmbientSupport": 5,
00038     "freqComp": false,
00039     "user": a0227156,
00040     "autoHDRRatio": 4.0,
00041     "multiLEDMode": true,
00042     "TX1HCurrent": 0,
00043     "genDeviceEEPROMConnection": true,
00044     "toolVersion": 0.8.0,
00045     "TX2HCurrent": 0,
00046     "crc": -1193321828,
00047     "genDeviceSubFrameCount": 256,
00048     "autoHDRHThreshold": 25500,
00049     "genDeviceAvgFrameCount": 6,
00050 }
00051 */
00052 void OPT3101::device::initialize(void){
00053     // List of registers to initialize OPT3101 device after power-up
00054 
00055     this->reg.tg_ovl_window_start = 7000; // //Overload flab observation window
00056     this->reg.en_temp_conv = 1; // //Enables the internal
00057 
00058     this->reg.clip_mode_fc = 1; // //Enables Clip mode for Frequency correction
00059     this->reg.clip_mode_temp = 0; // //Disables Clip mode for Temp coff phase correction
00060     this->reg.clip_mode_offset = 0; // //Disables Clip mode for phase offset correction
00061     this->reg.iq_read_data_sel = 3; // //Enables 16 bit frame counter
00062     this->reg.iamb_max_sel = 14; // //Sets maximum ambient support
00063     this->reg.en_temp_corr = 1; // //Enables Temperature Correction
00064     this->reg.gpio1_obuf_en=1; // //Enabled output buffer on GPIO1 pin
00065     this->reg.gpo1_mux_sel=2;       // //select dig_gpo_0 on gpio1
00066     this->reg.dig_gpo_sel0 = 9;     // //Select Data Ready on dig_gpo_0
00067 
00068     this->reg.num_sub_frames = 255; // //Sub frames count
00069     this->reg.num_avg_sub_frames = 127; // //Average frames count
00070     this->reg.xtalk_filt_time_const = 3; // //Crosstalk filter time constant
00071     this->reg.tg_seq_int_start  = 9850; // //Sequence Start
00072     this->reg.tg_seq_int_end        = 9858; // //Sequence End
00073     this->reg.tg_seq_int_mask_start     = 127; // //Same as AvgFrame Count
00074     this->reg.tg_seq_int_mask_end   = 127; // //Same as AvgFrame Count
00075 
00076     this->reg.hdr_thr_high = 25500; // //High Threshold
00077     this->reg.hdr_thr_low = 5875; // //Low Threshold
00078     this->reg.en_adaptive_hdr = 1; // //Enables adaptive HDR feature
00079 
00080     this->reg.illum_dac_h_tx0 = 31; // //High Current settings [173.6mA:5.6mA X 31]
00081     this->reg.illum_scale_h_tx0 = 0; // //Illum scale for H [173.6mA:5.6mA X 31]
00082 
00083     this->reg.illum_dac_l_tx0 = 31; // //High Current settings [043.4mA:1.4mA X 31]
00084     this->reg.illum_scale_l_tx0 = 3; // //Illum scale for H [043.4mA:1.4mA X 31]
00085 
00086     this->reg.illum_dac_h_tx1 = 31; // //High Current settings [173.6mA:5.6mA X 31]
00087     this->reg.illum_scale_h_tx1 = 0; // //Illum scale for H [173.6mA:5.6mA X 31]
00088 
00089     this->reg.illum_dac_l_tx1 = 31; // //High Current settings [043.4mA:1.4mA X 31]
00090     this->reg.illum_scale_l_tx1 = 3; // //Illum scale for H [043.4mA:1.4mA X 31]
00091 
00092     this->reg.illum_dac_h_tx2 = 31; // //High Current settings [173.6mA:5.6mA X 31]
00093     this->reg.illum_scale_h_tx2 = 0; // //Illum scale for H [173.6mA:5.6mA X 31]
00094 
00095     this->reg.illum_dac_l_tx2 = 31; // //High Current settings [043.4mA:1.4mA X 31]
00096     this->reg.illum_scale_l_tx2 = 3; // //Illum scale for H [043.4mA:1.4mA X 31]
00097 
00098     this->reg.tx_seq_reg   = 2340; // //Setting TX Switching order
00099     this->reg.en_tx_switch = 1 ; // //Enable TX Switching order
00100 
00101     this->reg.tg_en = 1; // //Enables Timing Generator
00102 
00103     this->configurationFlags_xtalkFilterTau =  3; // //This is not a register but a settings flag for the SDK
00104     this->configurationFlags_monoshotMode =  false; // //This is not a register but a settings flag for the SDK
00105     this->configurationFlags_xtalkSettlingOneTauInMilliSeconds      =  512; // //This is not a register but a settings flag for the SDK
00106     this->configurationFlags_xtalkSettlingOneTauInDataReadyCounts   =  8; // //This is not a register but a settings flag for the SDK
00107     this->configurationFlags_frameTimeInMilliSeconds                =  64; // //This is not a register but a settings flag for the SDK
00108     this->configurationFlags_avgFrameCountExponentOfTwo             =  7; // //This is not a register but a settings flag for the SDK
00109 
00110     // tx2 xtalk compensation
00111     //this->reg.EN_CTALK_FB_CLK=1;
00112     //this->reg.EN_CALIB_CLK=1;
00113     //this->reg.calib_curr1_en_I=1;
00114     //this->reg.calib_curr1_gain_sel=0;
00115     //this->reg.calib_curr1_DAC_I=4;
00116     //this->reg.calib_curr1_inv_CLK_I=0;
00117 
00118 }
00119 
00120 OPT3101::device::device(void)//: TODO fix this initialization
00121 //configurationFlags_isTXChannelActive{true,true,true},
00122 //configurationFlags_isRegisterSetActive(true,true) 
00123 {
00124     configurationFlags_isTXChannelActive[0] = true; 
00125     configurationFlags_isTXChannelActive[1] = true;
00126     configurationFlags_isTXChannelActive[2] = true;
00127     configurationFlags_isRegisterSetActive[0] = true;
00128     configurationFlags_isRegisterSetActive[1] = true;
00129     }
00130 
00131 OPT3101::calibrationC::calibrationC(void)// : calibrationC(true) 
00132 {
00133     this->recordLength           = 6; // //This configuration requires 6 crosstalk and other configuration record(s)
00134     this->registerAddressListSize= 43; // //This configuration requires 43 registers [1376] bits to be stored for calibration
00135     this->EEPROM_connected       =  true; // //This configuration helps configure EEPROM
00136     this->extTempSensor_connected=  false; // //This configuration helps configure Ext temp sensor
00137     this->registerAddressList[0] = 0x2f; // //Address for register(s) iphase_xtalk_reg_hdr0_tx0,temp_coeff_main_hdr1_tx1
00138     this->registerAddressList[1] = 0x30; // //Address for register(s) qphase_xtalk_reg_hdr0_tx0,temp_coeff_main_hdr1_tx1
00139     this->registerAddressList[2] = 0x38; // //Address for register(s) temp_coeff_xtalk_iphase_hdr0_tx0,qphase_xtalk_reg_hdr0_tx2
00140     this->registerAddressList[3] = 0x39; // //Address for register(s) temp_coeff_xtalk_qphase_hdr0_tx0,iphase_xtalk_reg_hdr1_tx2
00141     this->registerAddressList[4] = 0x42; // //Address for register(s) phase_offset_hdr0_tx0
00142     this->registerAddressList[5] = 0x47; // //Address for register(s) tmain_calib_hdr0_tx0,tillum_calib_hdr0_tx0
00143     this->registerAddressList[6] = 0x45; // //Address for register(s) temp_coeff_main_hdr0_tx0,tmain_calib_hdr1_tx2
00144     this->registerAddressList[7] = 0x46; // //Address for register(s) temp_coeff_illum_hdr0_tx0,tillum_calib_hdr1_tx2
00145     this->registerAddressList[8] = 0x31; // //Address for register(s) iphase_xtalk_reg_hdr1_tx0,temp_coeff_main_hdr0_tx2
00146     this->registerAddressList[9] = 0x32; // //Address for register(s) qphase_xtalk_reg_hdr1_tx0,temp_coeff_main_hdr0_tx2
00147     this->registerAddressList[10] = 0x5e; // //Address for register(s) temp_coeff_xtalk_iphase_hdr1_tx0,temp_coeff_xtalk_iphase_hdr0_tx1
00148     this->registerAddressList[11] = 0x60; // //Address for register(s) temp_coeff_xtalk_qphase_hdr1_tx0,temp_coeff_xtalk_qphase_hdr0_tx1,temp_coeff_xtalk_qphase_hdr1_tx1
00149     this->registerAddressList[12] = 0x51; // //Address for register(s) phase_offset_hdr1_tx0,temp_coeff_illum_hdr1_tx0
00150     this->registerAddressList[13] = 0x48; // //Address for register(s) tmain_calib_hdr1_tx0,tillum_calib_hdr1_tx0
00151     this->registerAddressList[14] = 0x2d; // //Address for register(s) temp_coeff_main_hdr1_tx0,temp_coeff_main_hdr0_tx1
00152     this->registerAddressList[15] = 0x52; // //Address for register(s) temp_coeff_illum_hdr1_tx0,phase_offset_hdr0_tx1
00153     this->registerAddressList[16] = 0x33; // //Address for register(s) iphase_xtalk_reg_hdr0_tx1,temp_coeff_main_hdr1_tx2
00154     this->registerAddressList[17] = 0x34; // //Address for register(s) qphase_xtalk_reg_hdr0_tx1,temp_coeff_main_hdr1_tx2
00155     this->registerAddressList[18] = 0x49; // //Address for register(s) tmain_calib_hdr0_tx1,tillum_calib_hdr0_tx1
00156     this->registerAddressList[19] = 0x53; // //Address for register(s) temp_coeff_illum_hdr0_tx1,phase_offset_hdr1_tx1
00157     this->registerAddressList[20] = 0x54; // //Address for register(s) temp_coeff_illum_hdr0_tx1,phase_offset_hdr0_tx2
00158     this->registerAddressList[21] = 0x35; // //Address for register(s) iphase_xtalk_reg_hdr1_tx1
00159     this->registerAddressList[22] = 0x36; // //Address for register(s) qphase_xtalk_reg_hdr1_tx1
00160     this->registerAddressList[23] = 0x5f; // //Address for register(s) temp_coeff_xtalk_iphase_hdr1_tx1,temp_coeff_xtalk_iphase_hdr0_tx2,temp_coeff_xtalk_iphase_hdr1_tx2
00161     this->registerAddressList[24] = 0x41; // //Address for register(s) tmain_calib_hdr1_tx1
00162     this->registerAddressList[25] = 0x43; // //Address for register(s) tillum_calib_hdr1_tx1,en_phase_corr,en_temp_corr,scale_phase_temp_coeff
00163     this->registerAddressList[26] = 0x55; // //Address for register(s) temp_coeff_illum_hdr1_tx1,phase_offset_hdr1_tx2
00164     this->registerAddressList[27] = 0x56; // //Address for register(s) temp_coeff_illum_hdr1_tx1
00165     this->registerAddressList[28] = 0x37; // //Address for register(s) iphase_xtalk_reg_hdr0_tx2
00166     this->registerAddressList[29] = 0x61; // //Address for register(s) temp_coeff_xtalk_qphase_hdr0_tx2,temp_coeff_xtalk_qphase_hdr1_tx2
00167     this->registerAddressList[30] = 0x3f; // //Address for register(s) tmain_calib_hdr0_tx2,tillum_calib_hdr0_tx2
00168     this->registerAddressList[31] = 0x57; // //Address for register(s) temp_coeff_illum_hdr0_tx2
00169     this->registerAddressList[32] = 0x58; // //Address for register(s) temp_coeff_illum_hdr0_tx2
00170     this->registerAddressList[33] = 0x3a; // //Address for register(s) qphase_xtalk_reg_hdr1_tx2,scale_temp_coeff_xtalk
00171     this->registerAddressList[34] = 0x59; // //Address for register(s) temp_coeff_illum_hdr1_tx2
00172     this->registerAddressList[35] = 0x5a; // //Address for register(s) temp_coeff_illum_hdr1_tx2
00173     this->registerAddressList[36] = 0x2e; // //Address for register(s) illum_xtalk_reg_scale
00174     this->registerAddressList[37] = 0x71; // //Address for register(s) shift_illum_phase
00175     this->registerAddressList[38] = 0xb5; // //Address for register(s) scale_amb_phase_corr_coeff
00176     this->registerAddressList[39] = 0x0c; // //Address for register(s) amb_phase_corr_pwl_coeff0
00177     this->registerAddressList[40] = 0xb4; // //Address for register(s) amb_phase_corr_pwl_coeff1,amb_phase_corr_pwl_coeff2,amb_phase_corr_pwl_coeff3
00178     this->registerAddressList[41] = 0xb8; // //Address for register(s) amb_phase_corr_pwl_x0,amb_phase_corr_pwl_x1
00179     this->registerAddressList[42] = 0xb9; // //Address for register(s) amb_phase_corr_pwl_x2
00180 
00181 }
00182 
00183