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Jesper Taxbøl / Mbed 2 deprecated TCPSpeedTest

I have a problem getting this to work. Server only recieves half of the data being sent. Whats wrong

drv/usb/UsbInc.h@0:66300c77c6e9, 2011-03-29 (annotated)

Committer:: tax
Date:: Tue Mar 29 13:20:15 2011 +0000
Revision:: 0:66300c77c6e9

Who changed what in which revision?

User	Revision	Line number	New contents of line
tax	0:66300c77c6e9	1
tax	0:66300c77c6e9	2	/*
tax	0:66300c77c6e9	3	Copyright (c) 2010 Donatien Garnier (donatiengar [at] gmail [dot] com)
tax	0:66300c77c6e9	4
tax	0:66300c77c6e9	5	Permission is hereby granted, free of charge, to any person obtaining a copy
tax	0:66300c77c6e9	6	of this software and associated documentation files (the "Software"), to deal
tax	0:66300c77c6e9	7	in the Software without restriction, including without limitation the rights
tax	0:66300c77c6e9	8	to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
tax	0:66300c77c6e9	9	copies of the Software, and to permit persons to whom the Software is
tax	0:66300c77c6e9	10	furnished to do so, subject to the following conditions:
tax	0:66300c77c6e9	11
tax	0:66300c77c6e9	12	The above copyright notice and this permission notice shall be included in
tax	0:66300c77c6e9	13	all copies or substantial portions of the Software.
tax	0:66300c77c6e9	14
tax	0:66300c77c6e9	15	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
tax	0:66300c77c6e9	16	IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
tax	0:66300c77c6e9	17	FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
tax	0:66300c77c6e9	18	AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
tax	0:66300c77c6e9	19	LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
tax	0:66300c77c6e9	20	OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
tax	0:66300c77c6e9	21	THE SOFTWARE.
tax	0:66300c77c6e9	22	*/
tax	0:66300c77c6e9	23
tax	0:66300c77c6e9	24	#ifndef USB_INC_H
tax	0:66300c77c6e9	25	#define USB_INC_H
tax	0:66300c77c6e9	26
tax	0:66300c77c6e9	27	#include "mbed.h"
tax	0:66300c77c6e9	28
tax	0:66300c77c6e9	29	#define MIN(a,b) ((a)<(b)?(a):(b))
tax	0:66300c77c6e9	30	#define MAX(a,b) ((a)>(b)?(a):(b))
tax	0:66300c77c6e9	31
tax	0:66300c77c6e9	32	//typedef int32_t RC;
tax	0:66300c77c6e9	33
tax	0:66300c77c6e9	34	typedef uint8_t byte;
tax	0:66300c77c6e9	35	typedef uint16_t word;
tax	0:66300c77c6e9	36
tax	0:66300c77c6e9	37	enum UsbErr
tax	0:66300c77c6e9	38	{
tax	0:66300c77c6e9	39	__USBERR_MIN = -0xFFFF,
tax	0:66300c77c6e9	40	USBERR_DISCONNECTED,
tax	0:66300c77c6e9	41	USBERR_NOTFOUND,
tax	0:66300c77c6e9	42	USBERR_BADCONFIG,
tax	0:66300c77c6e9	43	USBERR_PROCESSING,
tax	0:66300c77c6e9	44	USBERR_HALTED, //Transfer on an ep is stalled
tax	0:66300c77c6e9	45	USBERR_BUSY,
tax	0:66300c77c6e9	46	USBERR_TDFAIL,
tax	0:66300c77c6e9	47	USBERR_ERROR,
tax	0:66300c77c6e9	48	USBERR_OK = 0
tax	0:66300c77c6e9	49	};
tax	0:66300c77c6e9	50
tax	0:66300c77c6e9	51
tax	0:66300c77c6e9	52	/* From NXP's USBHostLite stack's usbhost_lpc17xx.h */
tax	0:66300c77c6e9	53	/* Only the types names have been changed to avoid unecessary typedefs */
tax	0:66300c77c6e9	54
tax	0:66300c77c6e9	55
tax	0:66300c77c6e9	56	/*
tax	0:66300c77c6e9	57	**************************************************************************************************************
tax	0:66300c77c6e9	58	* NXP USB Host Stack
tax	0:66300c77c6e9	59	*
tax	0:66300c77c6e9	60	* (c) Copyright 2008, NXP SemiConductors
tax	0:66300c77c6e9	61	* (c) Copyright 2008, OnChip Technologies LLC
tax	0:66300c77c6e9	62	* All Rights Reserved
tax	0:66300c77c6e9	63	*
tax	0:66300c77c6e9	64	* www.nxp.com
tax	0:66300c77c6e9	65	* www.onchiptech.com
tax	0:66300c77c6e9	66	*
tax	0:66300c77c6e9	67	* File : usbhost_lpc17xx.h
tax	0:66300c77c6e9	68	* Programmer(s) : Ravikanth.P
tax	0:66300c77c6e9	69	* Version :
tax	0:66300c77c6e9	70	*
tax	0:66300c77c6e9	71	**************************************************************************************************************
tax	0:66300c77c6e9	72	*/
tax	0:66300c77c6e9	73
tax	0:66300c77c6e9	74
tax	0:66300c77c6e9	75
tax	0:66300c77c6e9	76	/*
tax	0:66300c77c6e9	77	**************************************************************************************************************
tax	0:66300c77c6e9	78	* OHCI OPERATIONAL REGISTER FIELD DEFINITIONS
tax	0:66300c77c6e9	79	**************************************************************************************************************
tax	0:66300c77c6e9	80	*/
tax	0:66300c77c6e9	81
tax	0:66300c77c6e9	82	/* ------------------ HcControl Register --------------------- */
tax	0:66300c77c6e9	83	#define OR_CONTROL_CLE 0x00000010
tax	0:66300c77c6e9	84	#define OR_CONTROL_BLE 0x00000020
tax	0:66300c77c6e9	85	#define OR_CONTROL_HCFS 0x000000C0
tax	0:66300c77c6e9	86	#define OR_CONTROL_HC_OPER 0x00000080
tax	0:66300c77c6e9	87	/* ----------------- HcCommandStatus Register ----------------- */
tax	0:66300c77c6e9	88	#define OR_CMD_STATUS_HCR 0x00000001
tax	0:66300c77c6e9	89	#define OR_CMD_STATUS_CLF 0x00000002
tax	0:66300c77c6e9	90	#define OR_CMD_STATUS_BLF 0x00000004
tax	0:66300c77c6e9	91	/* --------------- HcInterruptStatus Register ----------------- */
tax	0:66300c77c6e9	92	#define OR_INTR_STATUS_WDH 0x00000002
tax	0:66300c77c6e9	93	#define OR_INTR_STATUS_RHSC 0x00000040
tax	0:66300c77c6e9	94	#define OR_INTR_STATUS_UE 0x00000010
tax	0:66300c77c6e9	95	/* --------------- HcInterruptEnable Register ----------------- */
tax	0:66300c77c6e9	96	#define OR_INTR_ENABLE_WDH 0x00000002
tax	0:66300c77c6e9	97	#define OR_INTR_ENABLE_RHSC 0x00000040
tax	0:66300c77c6e9	98	#define OR_INTR_ENABLE_MIE 0x80000000
tax	0:66300c77c6e9	99	/* ---------------- HcRhDescriptorA Register ------------------ */
tax	0:66300c77c6e9	100	#define OR_RH_STATUS_LPSC 0x00010000
tax	0:66300c77c6e9	101	#define OR_RH_STATUS_DRWE 0x00008000
tax	0:66300c77c6e9	102	/* -------------- HcRhPortStatus[1:NDP] Register -------------- */
tax	0:66300c77c6e9	103	#define OR_RH_PORT_CCS 0x00000001
tax	0:66300c77c6e9	104	#define OR_RH_PORT_PRS 0x00000010
tax	0:66300c77c6e9	105	#define OR_RH_PORT_CSC 0x00010000
tax	0:66300c77c6e9	106	#define OR_RH_PORT_PRSC 0x00100000
tax	0:66300c77c6e9	107
tax	0:66300c77c6e9	108
tax	0:66300c77c6e9	109	/*
tax	0:66300c77c6e9	110	**************************************************************************************************************
tax	0:66300c77c6e9	111	* FRAME INTERVAL
tax	0:66300c77c6e9	112	**************************************************************************************************************
tax	0:66300c77c6e9	113	*/
tax	0:66300c77c6e9	114
tax	0:66300c77c6e9	115	#define FI 0x2EDF /* 12000 bits per frame (-1) */
tax	0:66300c77c6e9	116	#define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) \| FI)
tax	0:66300c77c6e9	117
tax	0:66300c77c6e9	118	/*
tax	0:66300c77c6e9	119	**************************************************************************************************************
tax	0:66300c77c6e9	120	* ENDPOINT DESCRIPTOR CONTROL FIELDS
tax	0:66300c77c6e9	121	**************************************************************************************************************
tax	0:66300c77c6e9	122	*/
tax	0:66300c77c6e9	123
tax	0:66300c77c6e9	124	#define ED_SKIP (uint32_t) (0x00001000) /* Skip this ep in queue */
tax	0:66300c77c6e9	125
tax	0:66300c77c6e9	126	/*
tax	0:66300c77c6e9	127	**************************************************************************************************************
tax	0:66300c77c6e9	128	* TRANSFER DESCRIPTOR CONTROL FIELDS
tax	0:66300c77c6e9	129	**************************************************************************************************************
tax	0:66300c77c6e9	130	*/
tax	0:66300c77c6e9	131
tax	0:66300c77c6e9	132	#define TD_ROUNDING (uint32_t) (0x00040000) /* Buffer Rounding */
tax	0:66300c77c6e9	133	#define TD_SETUP (uint32_t)(0) /* Direction of Setup Packet */
tax	0:66300c77c6e9	134	#define TD_IN (uint32_t)(0x00100000) /* Direction In */
tax	0:66300c77c6e9	135	#define TD_OUT (uint32_t)(0x00080000) /* Direction Out */
tax	0:66300c77c6e9	136	#define TD_DELAY_INT(x) (uint32_t)((x) << 21) /* Delay Interrupt */
tax	0:66300c77c6e9	137	#define TD_TOGGLE_0 (uint32_t)(0x02000000) /* Toggle 0 */
tax	0:66300c77c6e9	138	#define TD_TOGGLE_1 (uint32_t)(0x03000000) /* Toggle 1 */
tax	0:66300c77c6e9	139	#define TD_CC (uint32_t)(0xF0000000) /* Completion Code */
tax	0:66300c77c6e9	140
tax	0:66300c77c6e9	141	/*
tax	0:66300c77c6e9	142	**************************************************************************************************************
tax	0:66300c77c6e9	143	* USB STANDARD REQUEST DEFINITIONS
tax	0:66300c77c6e9	144	**************************************************************************************************************
tax	0:66300c77c6e9	145	*/
tax	0:66300c77c6e9	146
tax	0:66300c77c6e9	147	#define USB_DESCRIPTOR_TYPE_DEVICE 1
tax	0:66300c77c6e9	148	#define USB_DESCRIPTOR_TYPE_CONFIGURATION 2
tax	0:66300c77c6e9	149	#define USB_DESCRIPTOR_TYPE_INTERFACE 4
tax	0:66300c77c6e9	150	#define USB_DESCRIPTOR_TYPE_ENDPOINT 5
tax	0:66300c77c6e9	151	/* ----------- Control RequestType Fields ----------- */
tax	0:66300c77c6e9	152	#define USB_DEVICE_TO_HOST 0x80
tax	0:66300c77c6e9	153	#define USB_HOST_TO_DEVICE 0x00
tax	0:66300c77c6e9	154	#define USB_REQUEST_TYPE_CLASS 0x20
tax	0:66300c77c6e9	155	#define USB_RECIPIENT_DEVICE 0x00
tax	0:66300c77c6e9	156	#define USB_RECIPIENT_INTERFACE 0x01
tax	0:66300c77c6e9	157	/* -------------- USB Standard Requests -------------- */
tax	0:66300c77c6e9	158	#define SET_ADDRESS 5
tax	0:66300c77c6e9	159	#define GET_DESCRIPTOR 6
tax	0:66300c77c6e9	160	#define SET_CONFIGURATION 9
tax	0:66300c77c6e9	161	#define SET_INTERFACE 11
tax	0:66300c77c6e9	162
tax	0:66300c77c6e9	163	/*
tax	0:66300c77c6e9	164	**************************************************************************************************************
tax	0:66300c77c6e9	165	* TYPE DEFINITIONS
tax	0:66300c77c6e9	166	**************************************************************************************************************
tax	0:66300c77c6e9	167	*/
tax	0:66300c77c6e9	168
tax	0:66300c77c6e9	169	typedef struct hcEd { /* ----------- HostController EndPoint Descriptor ------------- */
tax	0:66300c77c6e9	170	volatile uint32_t Control; /* Endpoint descriptor control */
tax	0:66300c77c6e9	171	volatile uint32_t TailTd; /* Physical address of tail in Transfer descriptor list */
tax	0:66300c77c6e9	172	volatile uint32_t HeadTd; /* Physcial address of head in Transfer descriptor list */
tax	0:66300c77c6e9	173	volatile uint32_t Next; /* Physical address of next Endpoint descriptor */
tax	0:66300c77c6e9	174	} HCED;
tax	0:66300c77c6e9	175
tax	0:66300c77c6e9	176	typedef struct hcTd { /* ------------ HostController Transfer Descriptor ------------ */
tax	0:66300c77c6e9	177	volatile uint32_t Control; /* Transfer descriptor control */
tax	0:66300c77c6e9	178	volatile uint32_t CurrBufPtr; /* Physical address of current buffer pointer */
tax	0:66300c77c6e9	179	volatile uint32_t Next; /* Physical pointer to next Transfer Descriptor */
tax	0:66300c77c6e9	180	volatile uint32_t BufEnd; /* Physical address of end of buffer */
tax	0:66300c77c6e9	181	} HCTD;
tax	0:66300c77c6e9	182
tax	0:66300c77c6e9	183	typedef struct hcca { /* ----------- Host Controller Communication Area ------------ */
tax	0:66300c77c6e9	184	volatile uint32_t IntTable[32]; /* Interrupt Table */
tax	0:66300c77c6e9	185	volatile uint32_t FrameNumber; /* Frame Number */
tax	0:66300c77c6e9	186	volatile uint32_t DoneHead; /* Done Head */
tax	0:66300c77c6e9	187	volatile uint8_t Reserved[116]; /* Reserved for future use */
tax	0:66300c77c6e9	188	volatile uint8_t Unknown[4]; /* Unused */
tax	0:66300c77c6e9	189	} HCCA;
tax	0:66300c77c6e9	190
tax	0:66300c77c6e9	191
tax	0:66300c77c6e9	192
tax	0:66300c77c6e9	193	#endif

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	29 Mar 2011
Imports:	16
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	2

drv/usb/UsbInc.h@0:66300c77c6e9, 2011-03-29 (annotated)

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