naoki tanabe / a4960
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a4960.h

00001 #ifndef _A4960_H_
00002 #define _A4960_H_
00003 
00004 #include "mbed.h"
00005 //#include "spi_master.h"
00006 
00007 class a4960
00008 {
00009 public:
00010     a4960();
00011     void SPI_init();
00012     void write_to_a4960(uint16_t msg);
00013     void write_run();
00014     void write_brake();
00015     int read();
00016     bool motor_started;
00017     float PWM_freq; // Hz
00018     float PWM_duty; // 0 to 1
00019 private:
00020 // the default configurations of the 8 a4960 registers
00021 // 0. Config0: basic timing settings
00022 //      CB(2 bits) comm. blank time
00023 //      BT (4 bits) blank time in 400ns increments
00024 //      DT (6 bits) dead time in 50ns increments
00025 // 1. Config1: basic voltage settings
00026 //      VR (4 bits) current limit reference voltage as ratio of Vref
00027 //      VT (6 bits) drain-source thresh. voltage in 25 mV increments
00028 // 2. Config2: PWM settings
00029 //      PT (5 bits) off-time for PWM current control, limits motor current
00030 // 3. Config3: start-up hold settings
00031 //      IDS (1 bit) select current control or duty cycle control for init. holding torque
00032 //      HQ (4 bits) holding torque for initial start position
00033 //                  hold current or duty cycle in increments of 6.25%
00034 //      HT (4 bits) hold time of init. start position, increments of 8ms from 2ms
00035 // 4. Config4: start-up timing settings
00036 //      EC (4 bits) end comm. time in incr. of 200us
00037 //      SC (4 bits) start comm. time in incr. of 8ms
00038 // 5. Config5: start-up ramp settings
00039 //      PA (4 bits) phase advance in incr. of 1.875 deg
00040 //      RQ (4 bits) torque during ramp up (duty cycle or current control dep. on IDS) in 6.25% incr.
00041 //      RR (4 bits) accel. rate during forced comm. ramp up
00042 // 6. Mask: fault masking bit for each fault bit in Diagnostic register
00043 //      each bit: 1 means diagnostic is diabled
00044 // 7. Run: bits to set running conditions
00045 //      BH (2 bits) select BEMF hysteresis
00046 //      BW (3 bits) BEMF window
00047 //      ESF (1 bit) enable stop on fault
00048 //      DG (2 bits) select output routed to DIAG terminal, default general fault output flag (low if fault detected)
00049 //      RSC (1 bit) 1 to enable restart after loss of sync if RUN 1, BRK 0, else coast to stop
00050 //      BRK (1 bit) brake control
00051 //      DIR (1 bit) direction control
00052 //      RUN (1 bit) run control
00053     uint16_t _config[8];
00054     SPI spi;
00055     DigitalOut _cs_pin;
00056     DigitalOut _blink_pin;
00057     PwmOut _PWM_pin;
00058 };
00059 
00060 #endif