shinichi nakazawa
mbed library sources
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mbed-src
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mbed official
Revision 47:02833c62d054, committed 2013-11-21
- Comitter:
- mbed_official
- Date:
- Thu Nov 21 10:00:05 2013 +0000
- Parent:
- 46:bebbbd80dd87
- Child:
- 48:40454ec5d50d
- Commit message:
- Synchronized with git revision 6a5335a40ed97c7edd719e209bda5f3b5d9d997e
Full URL: https://github.com/mbedmicro/mbed/commit/6a5335a40ed97c7edd719e209bda5f3b5d9d997e/
Added sleep to LPC81x
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/LPC4330.ld Thu Nov 21 10:00:05 2013 +0000
@@ -0,0 +1,174 @@
+/* Linker script for mbed LPC4330 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ RAM0 (rwx) : ORIGIN = 0x10000114, LENGTH = (128K - 0x114)
+ RAM1 (rwx) : ORIGIN = 0x10080000, LENGTH = 72K
+
+ RAM_AHB0 (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
+ RAM_AHB1 (rwx) : ORIGIN = 0x20008000, LENGTH = 32K
+
+ SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 32M
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > SPIFI
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > SPIFI
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > SPIFI
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ Image$$RW_IRAM1$$Base = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM0
+
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ Image$$RW_IRAM1$$ZI$$Limit = . ;
+ } > RAM1
+
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM1
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM1
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM1) + LENGTH(RAM1);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Code can explicitly ask for data to be
+ placed in these higher RAM banks where
+ they will be left uninitialized.
+ */
+ .AHBSRAM0 (NOLOAD):
+ {
+ Image$$RW_IRAM2$$Base = . ;
+ *(AHBSRAM0)
+ Image$$RW_IRAM2$$ZI$$Limit = .;
+ } > RAM_AHB0
+
+ .AHBSRAM1 (NOLOAD):
+ {
+ Image$$RW_IRAM3$$Base = . ;
+ *(AHBSRAM1)
+ Image$$RW_IRAM3$$ZI$$Limit = .;
+ } > RAM_AHB1
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/startup_LPC43xx.s Thu Nov 21 10:00:05 2013 +0000 @@ -0,0 +1,292 @@ +/* File: startup_ARMCM4.S + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.4 + * Date: 20 Dezember 2012 + * + */ +/* Copyright (c) 2011 - 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +.ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +.else + .equ Stack_Size, 0x00000400 +.endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +.ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +.else + .equ Heap_Size, 0x00000C00 +.endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long DAC_IRQHandler /* 0: DAC */ + .long M0CORE_IRQHandler /* 1: M4-M0 communication */ + .long DMA_IRQHandler /* 2: - */ + .long 0 /* 3: Reserved */ + .long FLASHEEPROM_IRQHandler/* 4: ORed flash bank A/B, EEPROM int */ + .long ETHERNET_IRQHandler /* 5: Ethernet interrupt */ + .long SDIO_IRQHandler /* 6: SD/MMC interrupt */ + .long LCD_IRQHandler /* 7: - */ + .long USB0_IRQHandler /* 8: OTG interrupt */ + .long USB1_IRQHandler /* 9: - */ + .long SCT_IRQHandler /* 10: SCT combined interrupt */ + .long RITIMER_IRQHandler /* 11: - */ + .long TIMER0_IRQHandler /* 12: - */ + .long TIMER1_IRQHandler /* 13: - */ + .long TIMER2_IRQHandler /* 14: - */ + .long TIMER3_IRQHandler /* 15: - */ + .long MCPWM_IRQHandler /* 16: Motor control PWM */ + .long ADC0_IRQHandler /* 17: - */ + .long I2C0_IRQHandler /* 18: - */ + .long I2C1_IRQHandler /* 19: - */ + .long SPI_IRQHandler /* 20: - */ + .long ADC1_IRQHandler /* 21: - */ + .long SSP0_IRQHandler /* 22: - */ + .long SSP1_IRQHandler /* 23: - */ + .long USART0_IRQHandler /* 24: - */ + .long UART1_IRQHandler /* 25: Combined UART int w Modem int */ + .long USART2_IRQHandler /* 26: - */ + .long USART3_IRQHandler /* 27: combined USART int w IrDA int */ + .long I2S0_IRQHandler /* 28: - */ + .long I2S1_IRQHandler /* 29: - */ + .long SPIFI_IRQHandler /* 30: - */ + .long SGPIO_IRQHandler /* 31: - */ + .long PIN_INT0_IRQHandler /* 32: GPIO pin interrupt 0 */ + .long PIN_INT1_IRQHandler /* 33: GPIO pin interrupt 1 */ + .long PIN_INT2_IRQHandler /* 34: GPIO pin interrupt 2 */ + .long PIN_INT3_IRQHandler /* 35: GPIO pin interrupt 3 */ + .long PIN_INT4_IRQHandler /* 36: GPIO pin interrupt 4 */ + .long PIN_INT5_IRQHandler /* 37: GPIO pin interrupt 5 */ + .long PIN_INT6_IRQHandler /* 38: GPIO pin interrupt 6 */ + .long PIN_INT7_IRQHandler /* 39: GPIO pin interrupt 7 */ + .long GINT0_IRQHandler /* 40: GPIO global interrupt 0 */ + .long GINT1_IRQHandler /* 41: GPIO global interrupt 1 */ + .long EVENTROUTER_IRQHandler/* 42: Event router interrupt */ + .long C_CAN1_IRQHandler /* 43: - */ + .long 0 /* 44: Reserved */ + .long 0 /* 45: Reserved */ + .long ATIMER_IRQHandler /* 46: Alarm timer interuupt */ + .long RTC_IRQHandler /* 47: - */ + .long 0 /* 48: Reserved */ + .long WWDT_IRQHandler /* 49: - */ + .long 0 /* 50: Reserved */ + .long C_CAN0_IRQHandler /* 51: - */ + .long QEI_IRQHandler /* 52: - */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +.else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +.endif + +.ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +.endif /* __STARTUP_CLEAR_BSS */ + +.ifndef __NO_SYSTEM_INIT + bl SystemInit +.endif + +.ifndef __START +.set __START,_start +.endif + bl __START + .pool + .size Reset_Handler, . - Reset_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler Default_Handler + + def_irq_handler DAC_IRQHandler + def_irq_handler M0CORE_IRQHandler + def_irq_handler DMA_IRQHandler + def_irq_handler FLASHEEPROM_IRQHandler + def_irq_handler ETHERNET_IRQHandler + def_irq_handler SDIO_IRQHandler + def_irq_handler LCD_IRQHandler + def_irq_handler USB0_IRQHandler + def_irq_handler USB1_IRQHandler + def_irq_handler SCT_IRQHandler + def_irq_handler RITIMER_IRQHandler + def_irq_handler TIMER0_IRQHandler + def_irq_handler TIMER1_IRQHandler + def_irq_handler TIMER2_IRQHandler + def_irq_handler TIMER3_IRQHandler + def_irq_handler MCPWM_IRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler SPI_IRQHandler + def_irq_handler ADC1_IRQHandler + def_irq_handler SSP0_IRQHandler + def_irq_handler SSP1_IRQHandler + def_irq_handler USART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler USART2_IRQHandler + def_irq_handler USART3_IRQHandler + def_irq_handler I2S0_IRQHandler + def_irq_handler I2S1_IRQHandler + def_irq_handler SPIFI_IRQHandler + def_irq_handler SGPIO_IRQHandler + def_irq_handler PIN_INT0_IRQHandler + def_irq_handler PIN_INT1_IRQHandler + def_irq_handler PIN_INT2_IRQHandler + def_irq_handler PIN_INT3_IRQHandler + def_irq_handler PIN_INT4_IRQHandler + def_irq_handler PIN_INT5_IRQHandler + def_irq_handler PIN_INT6_IRQHandler + def_irq_handler PIN_INT7_IRQHandler + def_irq_handler GINT0_IRQHandler + def_irq_handler GINT1_IRQHandler + def_irq_handler EVENTROUTER_IRQHandler + def_irq_handler C_CAN1_IRQHandler + def_irq_handler ATIMER_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler WWDT_IRQHandler + def_irq_handler C_CAN0_IRQHandler + def_irq_handler QEI_IRQHandler + + .end
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c Mon Nov 11 13:30:09 2013 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c Thu Nov 21 10:00:05 2013 +0000
@@ -89,6 +89,10 @@
extern void *__vector_table;
*pSCB_VTOR = (unsigned int) &__vector_table;
+#elif defined(TOOLCHAIN_GCC_ARM)
+ extern void *__isr_vector;
+
+ *pSCB_VTOR = (unsigned int) &__isr_vector;
#else /* defined(__GNUC__) and others */
extern void *g_pfnVectors;
--- a/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h Mon Nov 11 13:30:09 2013 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h Thu Nov 21 10:00:05 2013 +0000 @@ -44,7 +44,7 @@ #define DEVICE_SEMIHOST 0 #define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_SLEEP 0 +#define DEVICE_SLEEP 1 #define DEVICE_DEBUG_AWARENESS 0
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/sleep.c Thu Nov 21 10:00:05 2013 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+
+
+//#define DEEPSLEEP
+#define POWERDOWN
+
+void sleep(void) {
+ //Normal sleep mode for PCON:
+ LPC_PMU->PCON &= ~0x03;
+
+ //Normal sleep mode for ARM core:
+ SCB->SCR = 0;
+
+ //And go to sleep
+ __WFI();
+}
+
+
+
+//Deepsleep/powerdown modes assume the device is configured to use its internal RC oscillator directly
+
+#ifdef DEEPSLEEP
+void deepsleep(void) {
+ //Deep sleep in PCON
+ LPC_PMU->PCON &= ~0x03;
+ LPC_PMU->PCON |= 0x01;
+
+ //If brownout detection and WDT are enabled, keep them enabled during sleep
+ LPC_SYSCON->PDSLEEPCFG = LPC_SYSCON->PDRUNCFG;
+
+ //After wakeup same stuff as currently enabled:
+ LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG;
+
+ //All interrupts may wake up:
+ LPC_SYSCON->STARTERP0 = 0xFF;
+ LPC_SYSCON->STARTERP1 = 0xFFFF;
+
+ //Deep sleep for ARM core:
+ SCB->SCR = 1<<2;
+
+ __WFI();
+}
+#endif
+
+#ifdef POWERDOWN
+void deepsleep(void) {
+ //Powerdown in PCON
+ LPC_PMU->PCON &= ~0x03;
+ LPC_PMU->PCON |= 0x02;
+
+ //If brownout detection and WDT are enabled, keep them enabled during sleep
+ LPC_SYSCON->PDSLEEPCFG = LPC_SYSCON->PDRUNCFG;
+
+ //After wakeup same stuff as currently enabled:
+ LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG;
+
+ //All interrupts may wake up:
+ LPC_SYSCON->STARTERP0 = 0xFF;
+ LPC_SYSCON->STARTERP1 = 0xFFFF;
+
+ //Deep sleep for ARM core:
+ SCB->SCR = 1<<2;
+
+ __WFI();
+}
+#endif