use_can_stm.cpp

00001 #ifndef USE_CAN_F303K8
00002 #include "use_can_stm.h"
00003 
00004 int CanStm::init(int baudrate){
00005     int result;
00006     CAN_TIMEOUT_VALUE = 3.0;
00007     timer.start();
00008 
00009     switch(baudrate)
00010     {
00011         case CAN_125KHZ:
00012             canHandler.Init.Prescaler = 16;
00013             break;
00014         
00015         case CAN_250KHZ:    
00016             canHandler.Init.Prescaler = 8;
00017             break;
00018             
00019         case CAN_500KHZ:
00020             canHandler.Init.Prescaler = 4;
00021             break;
00022             
00023         case CAN_1MHZ:
00024             canHandler.Init.Prescaler = 2;
00025             break;
00026     }
00027     
00028     canHandler.Instance = CAN1;                     
00029     canHandler.Init.Mode = CAN_MODE_NORMAL;        
00030     canHandler.Init.SJW = CAN_SJW_1TQ;  
00031     canHandler.Init.BS1 = CAN_BS1_11TQ; 
00032     canHandler.Init.BS2 = CAN_BS2_4TQ;  
00033     canHandler.Init.TTCM = DISABLE;                 //繧ｿ繧､繝�繝医Μ繧ｬ騾壻ｿ｡繝｢繝ｼ繝芽ｨｭ螳�
00034     canHandler.Init.ABOM = DISABLE;                  //閾ｪ蜍輔ヰ繧ｹ繧ｪ繝慕ｮ｡逅�險ｭ螳�
00035     canHandler.Init.AWUM = DISABLE;                 //閾ｪ蜍輔え繧ｧ繧､繧ｯ繧｢繝�繝励Δ繝ｼ繝芽ｨｭ螳�
00036     canHandler.Init.NART = DISABLE;                 //閾ｪ蜍募�埼�∫ｦ∵ｭ｢繝｢繝ｼ繝芽ｨｭ螳�
00037     canHandler.Init.RFLM = DISABLE;                 //FIFO繝ｭ繝�繧ｯ繝｢繝ｼ繝芽ｨｭ螳�
00038     canHandler.Init.TXFP = DISABLE;                 //騾∽ｿ｡FIFO縺ｮ蜆ｪ蜈磯��菴崎ｨｭ螳�
00039 
00040     if(CanStm::hal_can_init(&canHandler) == HAL_OK){
00041         result = SUCCESS;
00042     } else {
00043         result = ERROR;
00044     }
00045 
00046     return result;
00047 
00048 }
00049 
00050 int CanStm::transmit(uint32_t id, int format, uint8_t* tx_array){
00051 
00052     CanTxMsgTypeDef TxMsg;
00053     int result;
00054     canHandler.pTxMsg = &TxMsg;
00055         
00056     switch(format){
00057         case CAN_ID_STD:
00058             TxMsg.StdId   =id;
00059             break;
00060         case CAN_ID_EXT:
00061             TxMsg.ExtId   =id;
00062             break;
00063     }
00064 
00065     TxMsg.RTR     = CAN_RTR_DATA;
00066     TxMsg.IDE     = format;
00067     TxMsg.DLC     = 8;
00068     
00069     for(int i=0;i<8;i++){
00070         TxMsg.Data[i] = tx_array[i];
00071     }
00072     
00073     result = (CanStm::hal_can_transmit(&canHandler,0xFF) == HAL_OK) ? 1 : 0;
00074     return result;
00075 }
00076 
00077 int CanStm::attach(uint32_t id,void func(),int irq_mode){
00078     int result;
00079     CAN_FilterConfTypeDef conf;
00080 
00081     function = (uint32_t)func;
00082 
00083     switch(irq_mode){
00084         case RX_FIFO0:
00085             use_fifo = CAN_FIFO0;
00086             conf.FilterFIFOAssignment = CAN_FILTER_FIFO0;
00087             //FIFO0受信割り込み許可
00088             CanStm::setPriority(CAN_RX0_IRQn);
00089             __NVIC_EnableIRQ(CAN_RX0_IRQn);
00090             __NVIC_SetVector(CAN_RX0_IRQn,function);
00091             SET_BIT(canHandler.Instance->IER,CAN_IER_FMPIE0);
00092             break;
00093 
00094         case RX_FIFO1:
00095             use_fifo = CAN_FIFO1;
00096             conf.FilterFIFOAssignment = CAN_FILTER_FIFO1;
00097             //FIFO1受信割り込み許可
00098             CanStm::setPriority(CAN_RX1_IRQn);
00099             __NVIC_EnableIRQ(CAN_RX1_IRQn);
00100             __NVIC_SetVector(CAN_RX1_IRQn,function);
00101             SET_BIT(canHandler.Instance->IER,CAN_IER_FMPIE1);
00102             break;
00103 
00104         case TX_READY:
00105             //送信メールボックス空き割り込み許可
00106             CanStm::setPriority(CAN_TX_IRQn);
00107             __NVIC_EnableIRQ(CAN_TX_IRQn);
00108             __NVIC_SetVector(CAN_TX_IRQn,function);
00109             SET_BIT(canHandler.Instance->IER,CAN_IER_TMEIE);
00110             break;
00111     }
00112 
00113     /* setting the filter */
00114     conf.BankNumber = 0;
00115     conf.FilterNumber = 0;
00116     conf.FilterActivation = ENABLE;
00117     conf.FilterIdHigh = id<<5;
00118     conf.FilterIdLow = 0;
00119     conf.FilterMaskIdHigh = 0b11111111111<<5;
00120     conf.FilterMaskIdLow = 0;
00121     conf.FilterMode = CAN_FILTERMODE_IDMASK;
00122     conf.FilterScale = CAN_FILTERSCALE_32BIT;
00123 
00124     if(CanStm::hal_can_configfilter(&canHandler, &conf) == HAL_OK){
00125         result = SUCCESS;
00126     } else {
00127         result = ERROR;
00128     }
00129     return result;
00130 }
00131 
00132 int CanStm::receive(){
00133     uint32_t tickstart = 0U;
00134     uint32_t Timeout = 1.0;
00135     uint8_t FIFONumber;
00136 
00137     FIFONumber = use_fifo;
00138 
00139     /* Check the parameters */
00140     assert_param(IS_CAN_FIFO(FIFONumber));
00141 
00142     /* Process locked */
00143     __HAL_LOCK(&canHandler);
00144 
00145     /* Check if CAN state is not busy for RX FIFO0 */
00146     if ((FIFONumber == CAN_FIFO0) && ((canHandler.State == CAN_STATE::BUSY_RX0) ||   \
00147                                 (canHandler.State == CAN_STATE::BUSY_TX_RX0) ||      \
00148                                 (canHandler.State == CAN_STATE::BUSY_RX0_RX1) ||     \
00149                                 (canHandler.State == CAN_STATE::BUSY_TX_RX0_RX1)))
00150     {
00151         /* Process unlocked */
00152         __HAL_UNLOCK(&canHandler);
00153 
00154         return BUSY;
00155     }
00156 
00157     /* Check if CAN state is not busy for RX FIFO1 */
00158     if ((FIFONumber == CAN_FIFO1) && ((canHandler.State == CAN_STATE::BUSY_RX1) ||   \
00159                                 (canHandler.State == CAN_STATE::BUSY_TX_RX1) ||      \
00160                                 (canHandler.State == CAN_STATE::BUSY_RX0_RX1) ||     \
00161                                 (canHandler.State == CAN_STATE::BUSY_TX_RX0_RX1)))
00162     {
00163         /* Process unlocked */
00164         __HAL_UNLOCK(&canHandler);
00165 
00166         return BUSY;
00167     }
00168 
00169     /* Change CAN state */
00170     if (FIFONumber == CAN_FIFO0)
00171     {
00172         switch(canHandler.State)
00173         {
00174             case CAN_STATE::BUSY_TX:
00175                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_TX_RX0;
00176                 break;
00177             case CAN_STATE::BUSY_RX1:
00178                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_RX0_RX1;
00179                 break;
00180             case CAN_STATE::BUSY_TX_RX1:
00181                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_TX_RX0_RX1;
00182                 break;
00183             default: /* CAN_STATE::READY */
00184                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_RX0;
00185                 break;
00186         }
00187     }
00188     else /* FIFONumber == CAN_FIFO1 */
00189         {
00190         switch(canHandler.State)
00191         {
00192             case CAN_STATE::BUSY_TX:
00193                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_TX_RX1;
00194                 break;
00195             case CAN_STATE::BUSY_RX0:
00196                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_RX0_RX1;
00197                 break;
00198             case CAN_STATE::BUSY_TX_RX0:
00199                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_TX_RX0_RX1;
00200                 break;
00201             default: /* CAN_STATE::READY */
00202                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_RX1;
00203                 break;
00204         }
00205     }
00206 
00207     /* Get tick */
00208     timer.reset();
00209     tickstart = timer.read();
00210 
00211     /* Check pending message */
00212     while(__HAL_CAN_MSG_PENDING(&canHandler, FIFONumber) == 0U)
00213     {
00214         /* Check for the Timeout */
00215         if(Timeout != HAL_MAX_DELAY)
00216         {
00217             if((Timeout == 0U) || ((timer.read()-tickstart) > Timeout))
00218             {
00219                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::TIMEOUT;
00220 
00221                 /* Process unlocked */
00222                 __HAL_UNLOCK(&canHandler);
00223 
00224                 return TIMEOUT;
00225             }
00226         }
00227     }
00228 
00229     /* Set RxMsg pointer */
00230     if(FIFONumber == CAN_FIFO0){
00231         CanStm::ConvertMessage(&canHandler,&rx_data[FIFO_0],CAN_FIFO0);
00232     } else /* FIFONumber == CAN_FIFO1 */ {
00233         CanStm::ConvertMessage(&canHandler,&rx_data[FIFO_1],CAN_FIFO1);
00234     }
00235 
00236     /* Release the FIFO */
00237     if(FIFONumber == CAN_FIFO0)
00238     {
00239         /* Release FIFO0 */
00240         __HAL_CAN_FIFO_RELEASE(&canHandler, CAN_FIFO0);
00241     }
00242     else /* FIFONumber == CAN_FIFO1 */
00243     {
00244         /* Release FIFO1 */
00245         __HAL_CAN_FIFO_RELEASE(&canHandler, CAN_FIFO1);
00246     }
00247 
00248     /* Change CAN state */
00249     if (FIFONumber == CAN_FIFO0)
00250     {
00251         switch(canHandler.State)
00252         {
00253             case CAN_STATE::BUSY_TX_RX0:
00254                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_TX;
00255                 break;
00256             case CAN_STATE::BUSY_RX0_RX1:
00257                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_RX1;
00258                 break;
00259             case CAN_STATE::BUSY_TX_RX0_RX1:
00260                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_TX_RX1;
00261                 break;
00262             default: /* (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_RX0 */
00263                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::READY;
00264                 break;
00265         }
00266     }
00267     else /* FIFONumber == CAN_FIFO1 */
00268     {
00269         switch(canHandler.State)
00270         {
00271             case CAN_STATE::BUSY_TX_RX1:
00272                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_TX;
00273                 break;
00274             case CAN_STATE::BUSY_RX0_RX1:
00275                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_RX0;
00276                 break;
00277             case CAN_STATE::BUSY_TX_RX0_RX1:
00278                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_TX_RX0;
00279                 break;
00280             default: /* CAN_STATE::BUSY_RX1 */
00281                 canHandler.State = (HAL_CAN_StateTypeDef)CAN_STATE::READY;
00282                 break;
00283         }
00284     }
00285 
00286     /* Process unlocked */
00287     __HAL_UNLOCK(&canHandler);
00288 
00289     /* Return function status */
00290     return SUCCESS;
00291 }
00292 
00293 int CanStm::getData(int data_category){
00294     int output;
00295 
00296     switch(data_category){
00297         case STANDARD_ID:
00298             output = (int)rx_data[use_fifo].StdId;
00299             break;
00300         case EXTENDED_ID:
00301             output = (int)rx_data[use_fifo].ExtId;
00302             break;
00303         case IDE:
00304             output = (int)rx_data[use_fifo].IDE;
00305             break;
00306         case RTR:
00307             output = (int)rx_data[use_fifo].RTR;
00308             break;
00309         case DLC:
00310             output = (int)rx_data[use_fifo].DLC;
00311             break;
00312         case FMI:
00313             output = (int)rx_data[use_fifo].FMI;
00314             break;
00315         case FIFO_NUMBER:
00316             output = (int)rx_data[use_fifo].FIFONumber;
00317             break;
00318         case RX_DATA_0:
00319             output = (int)rx_data[use_fifo].Data[0];
00320             break;
00321         case RX_DATA_1:
00322             output = (int)rx_data[use_fifo].Data[1];
00323             break;
00324         case RX_DATA_2:
00325             output = (int)rx_data[use_fifo].Data[2];
00326             break;
00327         case RX_DATA_3:
00328             output = (int)rx_data[use_fifo].Data[3];
00329             break;
00330         case RX_DATA_4:
00331             output = (int)rx_data[use_fifo].Data[4];
00332             break;
00333         case RX_DATA_5:
00334             output = (int)rx_data[use_fifo].Data[5];
00335             break;
00336         case RX_DATA_6:
00337             output = (int)rx_data[use_fifo].Data[6];
00338             break;
00339         case RX_DATA_7:
00340             output = (int)rx_data[use_fifo].Data[7];
00341             break;
00342         default :
00343             output = 0;
00344             break;
00345     }
00346     return output;
00347 }
00348 
00349 void CanStm::exitIrqHandler(){
00350     SET_BIT(canHandler.Instance->RF0R,CAN_RF0R_RFOM0);
00351     SET_BIT(canHandler.Instance->IER,CAN_IER_FMPIE0);
00352 }
00353 
00354 HAL_StatusTypeDef CanStm::hal_can_init(CAN_HandleTypeDef* hcan){
00355 
00356       uint32_t status = CAN_INITSTATUS_FAILED;  /* Default init status */
00357       float tickstart = 0U;
00358       /* Check CAN handle */
00359       if(hcan == NULL){
00360          return HAL_ERROR;
00361       }
00362 
00363       /* Check the parameters */
00364       assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
00365       assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
00366       assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
00367       assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
00368       assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
00369       assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
00370       assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
00371       assert_param(IS_CAN_MODE(hcan->Init.Mode));
00372       assert_param(IS_CAN_SJW(hcan->Init.SJW));
00373       assert_param(IS_CAN_BS1(hcan->Init.BS1));
00374       assert_param(IS_CAN_BS2(hcan->Init.BS2));
00375       assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
00376 
00377       if(hcan->State == CAN_STATE::RESET){
00378         /* Allocate lock resource and initialize it */
00379         hcan->Lock = HAL_UNLOCKED;
00380         /* Init the low level hardware */
00381         CanStm::hal_can_mspinit(hcan);
00382       }
00383 
00384       /* Initialize the CAN state*/
00385       hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY;
00386 
00387       /* Exit from sleep mode */
00388       CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
00389 
00390       /* Request initialisation */
00391       SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
00392 
00393       /* Get tick */
00394       tickstart = timer.read();
00395 
00396       /* Wait the acknowledge */
00397       while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK)){
00398           if((timer.read()-tickstart) > CAN_TIMEOUT_VALUE){
00399               hcan->State= (HAL_CAN_StateTypeDef)CAN_STATE::TIMEOUT;
00400               /* Process unlocked */
00401               __HAL_UNLOCK(hcan);
00402               return HAL_TIMEOUT;
00403           }
00404       }
00405 
00406       /* Check acknowledge */
00407       if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
00408       {
00409         /* Set the time triggered communication mode */
00410         if (hcan->Init.TTCM == ENABLE)
00411         {
00412           SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
00413         }
00414         else
00415         {
00416           CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
00417         }
00418 
00419         /* Set the automatic bus-off management */
00420         if (hcan->Init.ABOM == ENABLE)
00421         {
00422           SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
00423         }
00424         else
00425         {
00426           CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
00427         }
00428 
00429         /* Set the automatic wake-up mode */
00430         if (hcan->Init.AWUM == ENABLE){
00431           SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
00432         } else {
00433           CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
00434         }
00435 
00436         /* Set the no automatic retransmission */
00437         if (hcan->Init.NART == ENABLE){
00438           SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
00439         } else {
00440           CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
00441         }
00442 
00443         /* Set the receive FIFO locked mode */
00444         if (hcan->Init.RFLM == ENABLE){
00445           SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
00446         } else {
00447           CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
00448         }
00449 
00450         /* Set the transmit FIFO priority */
00451         if (hcan->Init.TXFP == ENABLE){
00452           SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
00453         } else {
00454           CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
00455         }
00456 
00457         /* Set the bit timing register */
00458         WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode           |
00459                                                   hcan->Init.SJW            |
00460                                                   hcan->Init.BS1            |
00461                                                   hcan->Init.BS2            |
00462                                                   (hcan->Init.Prescaler - 1U) ));
00463 
00464         /* Request leave initialisation */
00465         CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
00466 
00467         /* Get tick */
00468         tickstart = timer.read();
00469 
00470         /* Wait the acknowledge */
00471         while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)){
00472           if((timer.read()-tickstart) > CAN_TIMEOUT_VALUE){
00473              hcan->State= (HAL_CAN_StateTypeDef)CAN_STATE::TIMEOUT;
00474 
00475              /* Process unlocked */
00476            __HAL_UNLOCK(hcan);
00477 
00478            return HAL_TIMEOUT;
00479           }
00480         }
00481 
00482         /* Check acknowledged */
00483         if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK)){
00484           status = CAN_INITSTATUS_SUCCESS;
00485         }
00486       }
00487 
00488       if(status == CAN_INITSTATUS_SUCCESS){
00489         /* Set CAN error code to none */
00490         hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00491 
00492         /* Initialize the CAN state */
00493         hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::READY;
00494 
00495         /* Return function status */
00496         return HAL_OK;
00497       } else {
00498         /* Initialize the CAN state */
00499         hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::ERROR;
00500 
00501         /* Return function status */
00502         return HAL_ERROR;
00503       }
00504 }
00505 
00506 void CanStm::hal_can_mspinit(CAN_HandleTypeDef* hcan){
00507       GPIO_InitTypeDef GPIO_InitStruct;
00508       if(hcan->Instance==CAN1){
00509         /* Peripheral clock enable */
00510         __HAL_RCC_CAN1_CLK_ENABLE();
00511 
00512         /**CAN GPIO Configuration
00513         PA11 -> CAN_RX
00514         PA12 -> CAN_TX
00515         */
00516         GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
00517         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
00518         GPIO_InitStruct.Pull = GPIO_NOPULL;
00519         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
00520         GPIO_InitStruct.Alternate = GPIO_AF9_CAN;
00521         HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
00522       }
00523 }
00524 
00525 HAL_StatusTypeDef CanStm::hal_can_transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout){
00526 
00527       uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
00528       uint32_t tickstart = 0U;
00529 
00530       /* Check the parameters */
00531       assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
00532       assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
00533       assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
00534 
00535       if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
00536          ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
00537          ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)){
00538         /* Process locked */
00539         __HAL_LOCK(hcan);
00540 
00541         /* Change CAN state */
00542         switch(hcan->State){
00543           case CAN_STATE::BUSY_RX0:
00544               hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_TX_RX0;
00545               break;
00546           case CAN_STATE::BUSY_RX1:
00547               hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_TX_RX1;
00548               break;
00549           case CAN_STATE::BUSY_RX0_RX1:
00550               hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_TX_RX0_RX1;
00551               break;
00552           default: /* CAN_STATE::READY */
00553               hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_TX;
00554               break;
00555         }
00556 
00557         /* Select one empty transmit mailbox */
00558         if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)){
00559           transmitmailbox = CAN_TXMAILBOX_0;
00560         } else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) {
00561           transmitmailbox = CAN_TXMAILBOX_1;
00562         } else {
00563           transmitmailbox = CAN_TXMAILBOX_2;
00564         }
00565 
00566         /* Set up the Id */
00567         hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
00568         if (hcan->pTxMsg->IDE == CAN_ID_STD) {
00569           assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
00570           hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
00571                                                                hcan->pTxMsg->RTR);
00572         } else {
00573           assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
00574           hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
00575                                                                hcan->pTxMsg->IDE | \
00576                                                                hcan->pTxMsg->RTR);
00577         }
00578 
00579         /* Set up the DLC */
00580         hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
00581         hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
00582         hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
00583 
00584         /* Set up the data field */
00585         WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
00586                                                                     ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
00587                                                                     ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
00588                                                                     ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
00589         WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
00590                                                                     ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
00591                                                                     ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
00592                                                                     ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
00593 
00594         /* Request transmission */
00595         SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
00596 
00597         /* Get tick */
00598         tickstart = HAL_GetTick();
00599 
00600         /* Check End of transmission flag */
00601         while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) {
00602           /* Check for the Timeout */
00603           if(Timeout != HAL_MAX_DELAY) {
00604             if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) {
00605               hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::TIMEOUT;
00606 
00607               /* Cancel transmission */
00608               __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
00609 
00610               /* Process unlocked */
00611               __HAL_UNLOCK(hcan);
00612               return HAL_TIMEOUT;
00613             }
00614           }
00615         }
00616 
00617         /* Change CAN state */
00618         switch(hcan->State) {
00619           case CAN_STATE::BUSY_TX_RX0:
00620               hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_RX0;
00621               break;
00622           case CAN_STATE::BUSY_TX_RX1:
00623               hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_RX1;
00624               break;
00625           case CAN_STATE::BUSY_TX_RX0_RX1:
00626               hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::BUSY_RX0_RX1;
00627               break;
00628           default: /* CAN_STATE::BUSY_TX */
00629               hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::READY;
00630               break;
00631         }
00632 
00633         /* Process unlocked */
00634         __HAL_UNLOCK(hcan);
00635 
00636         /* Return function status */
00637         return HAL_OK;
00638       } else {
00639         /* Change CAN state */
00640         hcan->State = (HAL_CAN_StateTypeDef)CAN_STATE::ERROR;
00641 
00642         /* Return function status */
00643         return HAL_ERROR;
00644       }
00645 }
00646 
00647 HAL_StatusTypeDef CanStm::hal_can_configfilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig){
00648       uint32_t filternbrbitpos = 0U;
00649 
00650       /* Check the parameters */
00651       assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
00652       assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
00653       assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
00654       assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
00655       assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
00656 
00657       filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
00658 
00659       /* Initialisation mode for the filter */
00660       SET_BIT(hcan->Instance->FMR, CAN_FMR_FINIT);
00661 
00662       /* Filter Deactivation */
00663       CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
00664 
00665       /* Filter Scale */
00666       if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT){
00667         /* 16-bit scale for the filter */
00668         CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
00669 
00670         /* First 16-bit identifier and First 16-bit mask */
00671         /* Or First 16-bit identifier and Second 16-bit identifier */
00672         hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
00673            ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
00674             (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
00675 
00676         /* Second 16-bit identifier and Second 16-bit mask */
00677         /* Or Third 16-bit identifier and Fourth 16-bit identifier */
00678         hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
00679            ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
00680             (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
00681       }
00682 
00683       if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT){
00684         /* 32-bit scale for the filter */
00685         SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
00686 
00687         /* 32-bit identifier or First 32-bit identifier */
00688         hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
00689            ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
00690             (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
00691 
00692         /* 32-bit mask or Second 32-bit identifier */
00693         hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
00694            ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
00695             (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
00696       }
00697 
00698       /* Filter Mode */
00699       if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
00700       {
00701         /*Id/Mask mode for the filter*/
00702         CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
00703       }
00704       else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
00705       {
00706         /*Identifier list mode for the filter*/
00707         SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
00708       }
00709 
00710       /* Filter FIFO assignment */
00711       if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
00712       {
00713         /* FIFO 0 assignation for the filter */
00714         CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
00715       }
00716       else
00717       {
00718         /* FIFO 1 assignation for the filter */
00719         SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
00720       }
00721 
00722       /* Filter activation */
00723       if (sFilterConfig->FilterActivation == ENABLE)
00724       {
00725         SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
00726       }
00727 
00728       /* Leave the initialisation mode for the filter */
00729       CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
00730 
00731       /* Return function status */
00732       return HAL_OK;
00733 }
00734 
00735 void CanStm::setPriority(IRQn_Type IRQn)
00736 {
00737       uint32_t prioritygroup = 0x00U;
00738       prioritygroup = NVIC_GetPriorityGrouping();
00739 
00740       __NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, 0, 0));
00741 }
00742 
00743 void CanStm::ConvertMessage(CAN_HandleTypeDef* hcan,CanRxMsgTypeDef* rx_message,uint32_t FIFONumber){
00744     /* Get the Id */
00745     rx_message->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
00746     if (rx_message->IDE == CAN_ID_STD)
00747     {
00748         rx_message->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
00749     }
00750     else
00751     {
00752         rx_message->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
00753     }
00754     rx_message->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
00755     /* Get the DLC */
00756     rx_message->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
00757     /* Get the FMI */
00758     rx_message->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
00759     /* Get the FIFONumber */
00760     rx_message->FIFONumber = FIFONumber;
00761     /* Get the data field */
00762     rx_message->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
00763     rx_message->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
00764     rx_message->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
00765     rx_message->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
00766     rx_message->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
00767     rx_message->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
00768     rx_message->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
00769     rx_message->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
00770 }
00771 
00772 
00773 
00774 #endif