Greg Steiert / pegasus_dev

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Dependents:   blinky_max32630fthr

targets/TARGET_Maxim/TARGET_MAX32630/mxc/spix.c@0:5c4d7b2438d3, 2016-11-11 (annotated)

Committer:
switches
Date:
Fri Nov 11 20:59:50 2016 +0000
Revision:
0:5c4d7b2438d3
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 /**
switches 0:5c4d7b2438d3 2 * @file
switches 0:5c4d7b2438d3 3 * @brief SPI execute in place driver.
switches 0:5c4d7b2438d3 4 */
switches 0:5c4d7b2438d3 5 /* *****************************************************************************
switches 0:5c4d7b2438d3 6 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
switches 0:5c4d7b2438d3 7 *
switches 0:5c4d7b2438d3 8 * Permission is hereby granted, free of charge, to any person obtaining a
switches 0:5c4d7b2438d3 9 * copy of this software and associated documentation files (the "Software"),
switches 0:5c4d7b2438d3 10 * to deal in the Software without restriction, including without limitation
switches 0:5c4d7b2438d3 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
switches 0:5c4d7b2438d3 12 * and/or sell copies of the Software, and to permit persons to whom the
switches 0:5c4d7b2438d3 13 * Software is furnished to do so, subject to the following conditions:
switches 0:5c4d7b2438d3 14 *
switches 0:5c4d7b2438d3 15 * The above copyright notice and this permission notice shall be included
switches 0:5c4d7b2438d3 16 * in all copies or substantial portions of the Software.
switches 0:5c4d7b2438d3 17 *
switches 0:5c4d7b2438d3 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
switches 0:5c4d7b2438d3 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
switches 0:5c4d7b2438d3 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
switches 0:5c4d7b2438d3 21 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
switches 0:5c4d7b2438d3 22 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
switches 0:5c4d7b2438d3 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
switches 0:5c4d7b2438d3 24 * OTHER DEALINGS IN THE SOFTWARE.
switches 0:5c4d7b2438d3 25 *
switches 0:5c4d7b2438d3 26 * Except as contained in this notice, the name of Maxim Integrated
switches 0:5c4d7b2438d3 27 * Products, Inc. shall not be used except as stated in the Maxim Integrated
switches 0:5c4d7b2438d3 28 * Products, Inc. Branding Policy.
switches 0:5c4d7b2438d3 29 *
switches 0:5c4d7b2438d3 30 * The mere transfer of this software does not imply any licenses
switches 0:5c4d7b2438d3 31 * of trade secrets, proprietary technology, copyrights, patents,
switches 0:5c4d7b2438d3 32 * trademarks, maskwork rights, or any other form of intellectual
switches 0:5c4d7b2438d3 33 * property whatsoever. Maxim Integrated Products, Inc. retains all
switches 0:5c4d7b2438d3 34 * ownership rights.
switches 0:5c4d7b2438d3 35 *
switches 0:5c4d7b2438d3 36 * $Date: 2016-09-08 17:31:41 -0500 (Thu, 08 Sep 2016) $
switches 0:5c4d7b2438d3 37 * $Revision: 24323 $
switches 0:5c4d7b2438d3 38 *
switches 0:5c4d7b2438d3 39 **************************************************************************** */
switches 0:5c4d7b2438d3 40
switches 0:5c4d7b2438d3 41 /* **** Includes **** */
switches 0:5c4d7b2438d3 42 #include <stddef.h>
switches 0:5c4d7b2438d3 43 #include "mxc_config.h"
switches 0:5c4d7b2438d3 44 #include "mxc_assert.h"
switches 0:5c4d7b2438d3 45 #include "spix.h"
switches 0:5c4d7b2438d3 46 #include "spix_regs.h"
switches 0:5c4d7b2438d3 47
switches 0:5c4d7b2438d3 48 /**
switches 0:5c4d7b2438d3 49 * @ingroup spix
switches 0:5c4d7b2438d3 50 * @{
switches 0:5c4d7b2438d3 51 */
switches 0:5c4d7b2438d3 52
switches 0:5c4d7b2438d3 53 /* **** Definitions **** */
switches 0:5c4d7b2438d3 54 #define CMD_CLOCKS 8
switches 0:5c4d7b2438d3 55 #define ADDR_3BYTE_CLOCKS 24
switches 0:5c4d7b2438d3 56 #define ADDR_4BYTE_CLOCKS 32
switches 0:5c4d7b2438d3 57
switches 0:5c4d7b2438d3 58 /***** Globals *****/
switches 0:5c4d7b2438d3 59
switches 0:5c4d7b2438d3 60 /***** Functions *****/
switches 0:5c4d7b2438d3 61
switches 0:5c4d7b2438d3 62 /******************************************************************************/
switches 0:5c4d7b2438d3 63 #if defined ( __GNUC__ )
switches 0:5c4d7b2438d3 64 #undef IAR_SPIX_PRAGMA //Make sure this is not defined for GCC
switches 0:5c4d7b2438d3 65 #endif
switches 0:5c4d7b2438d3 66
switches 0:5c4d7b2438d3 67 #if IAR_SPIX_PRAGMA
switches 0:5c4d7b2438d3 68 // IAR memory section declaration for the SPIX functions to be loaded in RAM.
switches 0:5c4d7b2438d3 69 #pragma section=".spix_config"
switches 0:5c4d7b2438d3 70 #endif
switches 0:5c4d7b2438d3 71
switches 0:5c4d7b2438d3 72 #if(MXC_SPIX_REV == 0)
switches 0:5c4d7b2438d3 73
switches 0:5c4d7b2438d3 74 #if defined ( __GNUC__ )
switches 0:5c4d7b2438d3 75 __attribute__ ((section(".spix_config"), noinline))
switches 0:5c4d7b2438d3 76 #endif /* __GNUC */
switches 0:5c4d7b2438d3 77
switches 0:5c4d7b2438d3 78 #if IAR_SPIX_PRAGMA
switches 0:5c4d7b2438d3 79 #pragma location=".spix_config" // IAR locate function in RAM section .spix_config
switches 0:5c4d7b2438d3 80 #pragma optimize=no_inline // IAR no inline optimization on this function
switches 0:5c4d7b2438d3 81 #endif /* IAR_PRAGMA */
switches 0:5c4d7b2438d3 82
switches 0:5c4d7b2438d3 83 static void SPIX_UpdateFBIgnore()
switches 0:5c4d7b2438d3 84 {
switches 0:5c4d7b2438d3 85 // Update the feedback ignore clocks
switches 0:5c4d7b2438d3 86 uint8_t clocks = 0;
switches 0:5c4d7b2438d3 87 uint8_t no_cmd_clocks = 0;
switches 0:5c4d7b2438d3 88
switches 0:5c4d7b2438d3 89 // Adjust the clocks for the command
switches 0:5c4d7b2438d3 90 if((MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH) ==
switches 0:5c4d7b2438d3 91 MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO) {
switches 0:5c4d7b2438d3 92
switches 0:5c4d7b2438d3 93 clocks += CMD_CLOCKS/4;
switches 0:5c4d7b2438d3 94 } else if((MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH) ==
switches 0:5c4d7b2438d3 95 MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO) {
switches 0:5c4d7b2438d3 96
switches 0:5c4d7b2438d3 97 clocks += CMD_CLOCKS/2;
switches 0:5c4d7b2438d3 98 } else {
switches 0:5c4d7b2438d3 99
switches 0:5c4d7b2438d3 100 clocks += CMD_CLOCKS;
switches 0:5c4d7b2438d3 101 }
switches 0:5c4d7b2438d3 102
switches 0:5c4d7b2438d3 103 // Adjust the clocks for the address
switches 0:5c4d7b2438d3 104 if((MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH) ==
switches 0:5c4d7b2438d3 105 MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO) {
switches 0:5c4d7b2438d3 106
switches 0:5c4d7b2438d3 107 if(MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR) {
switches 0:5c4d7b2438d3 108 clocks += ADDR_4BYTE_CLOCKS/4;
switches 0:5c4d7b2438d3 109 no_cmd_clocks += ADDR_4BYTE_CLOCKS/4;
switches 0:5c4d7b2438d3 110 } else {
switches 0:5c4d7b2438d3 111 clocks += ADDR_3BYTE_CLOCKS/4;
switches 0:5c4d7b2438d3 112 no_cmd_clocks += ADDR_3BYTE_CLOCKS/4;
switches 0:5c4d7b2438d3 113 }
switches 0:5c4d7b2438d3 114
switches 0:5c4d7b2438d3 115 } else if((MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH) ==
switches 0:5c4d7b2438d3 116 MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO) {
switches 0:5c4d7b2438d3 117
switches 0:5c4d7b2438d3 118 if(MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR) {
switches 0:5c4d7b2438d3 119 clocks += ADDR_4BYTE_CLOCKS/2;
switches 0:5c4d7b2438d3 120 no_cmd_clocks += ADDR_4BYTE_CLOCKS/2;
switches 0:5c4d7b2438d3 121 } else {
switches 0:5c4d7b2438d3 122 clocks += ADDR_3BYTE_CLOCKS/2;
switches 0:5c4d7b2438d3 123 no_cmd_clocks += ADDR_3BYTE_CLOCKS/2;
switches 0:5c4d7b2438d3 124 }
switches 0:5c4d7b2438d3 125 } else {
switches 0:5c4d7b2438d3 126
switches 0:5c4d7b2438d3 127 if(MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR) {
switches 0:5c4d7b2438d3 128 clocks += ADDR_4BYTE_CLOCKS;
switches 0:5c4d7b2438d3 129 no_cmd_clocks += ADDR_4BYTE_CLOCKS;
switches 0:5c4d7b2438d3 130 } else {
switches 0:5c4d7b2438d3 131 clocks += ADDR_3BYTE_CLOCKS;
switches 0:5c4d7b2438d3 132 no_cmd_clocks += ADDR_3BYTE_CLOCKS;
switches 0:5c4d7b2438d3 133 }
switches 0:5c4d7b2438d3 134 }
switches 0:5c4d7b2438d3 135
switches 0:5c4d7b2438d3 136 // Adjust for the mode clocks
switches 0:5c4d7b2438d3 137 clocks += ((MXC_SPIX->mode_ctrl & MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS) >>
switches 0:5c4d7b2438d3 138 MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS);
switches 0:5c4d7b2438d3 139
switches 0:5c4d7b2438d3 140 // Set the FB Ignore clocks
switches 0:5c4d7b2438d3 141 MXC_SPIX->sck_fb_ctrl = ((MXC_SPIX->sck_fb_ctrl & ~MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS) |
switches 0:5c4d7b2438d3 142 (clocks << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS));
switches 0:5c4d7b2438d3 143
switches 0:5c4d7b2438d3 144 MXC_SPIX->sck_fb_ctrl = ((MXC_SPIX->sck_fb_ctrl & ~MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD) |
switches 0:5c4d7b2438d3 145 (no_cmd_clocks << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS));
switches 0:5c4d7b2438d3 146 }
switches 0:5c4d7b2438d3 147 #endif /* MXC_SPIX_REV==0 */
switches 0:5c4d7b2438d3 148
switches 0:5c4d7b2438d3 149 /******************************************************************************/
switches 0:5c4d7b2438d3 150 #if defined ( __GNUC__ )
switches 0:5c4d7b2438d3 151 __attribute__ ((section(".spix_config"), noinline))
switches 0:5c4d7b2438d3 152 #endif /* __GNUC */
switches 0:5c4d7b2438d3 153
switches 0:5c4d7b2438d3 154 #if IAR_SPIX_PRAGMA
switches 0:5c4d7b2438d3 155 #pragma location=".spix_config" // IAR locate function in RAM section .spix_config
switches 0:5c4d7b2438d3 156 #pragma optimize=no_inline // IAR no inline optimization on this function
switches 0:5c4d7b2438d3 157 #endif /* IAR_SPIX_PRAGMA */
switches 0:5c4d7b2438d3 158 int SPIX_ConfigClock(const sys_cfg_spix_t *sys_cfg, uint32_t baud, uint8_t sample)
switches 0:5c4d7b2438d3 159 {
switches 0:5c4d7b2438d3 160 int err;
switches 0:5c4d7b2438d3 161 uint32_t spix_clk, clocks;
switches 0:5c4d7b2438d3 162
switches 0:5c4d7b2438d3 163 // Check the input parameters
switches 0:5c4d7b2438d3 164 if(sys_cfg == NULL) {
switches 0:5c4d7b2438d3 165 return E_NULL_PTR;
switches 0:5c4d7b2438d3 166 }
switches 0:5c4d7b2438d3 167
switches 0:5c4d7b2438d3 168 // Set system level configurations
switches 0:5c4d7b2438d3 169 if ((err = SYS_SPIX_Init(sys_cfg, baud)) != E_NO_ERROR) {
switches 0:5c4d7b2438d3 170 return err;
switches 0:5c4d7b2438d3 171 }
switches 0:5c4d7b2438d3 172
switches 0:5c4d7b2438d3 173 // Configure the mode and baud
switches 0:5c4d7b2438d3 174 spix_clk = SYS_SPIX_GetFreq();
switches 0:5c4d7b2438d3 175 if(spix_clk <= 0) {
switches 0:5c4d7b2438d3 176 return E_UNINITIALIZED;
switches 0:5c4d7b2438d3 177 }
switches 0:5c4d7b2438d3 178
switches 0:5c4d7b2438d3 179 // Make sure that we can generate this frequency
switches 0:5c4d7b2438d3 180 clocks = (spix_clk / (2*baud));
switches 0:5c4d7b2438d3 181 if((clocks <= 0) || (clocks >= 0x10)) {
switches 0:5c4d7b2438d3 182 return E_BAD_PARAM;
switches 0:5c4d7b2438d3 183 }
switches 0:5c4d7b2438d3 184
switches 0:5c4d7b2438d3 185 // Set the baud
switches 0:5c4d7b2438d3 186 MXC_SPIX->master_cfg = ((MXC_SPIX->master_cfg &
switches 0:5c4d7b2438d3 187 ~(MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK | MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK)) |
switches 0:5c4d7b2438d3 188 (clocks << MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS) |
switches 0:5c4d7b2438d3 189 (clocks << MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS));
switches 0:5c4d7b2438d3 190
switches 0:5c4d7b2438d3 191 if(sample != 0) {
switches 0:5c4d7b2438d3 192 // Use sample mode
switches 0:5c4d7b2438d3 193 MXC_SPIX->master_cfg = ((MXC_SPIX->master_cfg & ~MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT) |
switches 0:5c4d7b2438d3 194 (sample << MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS));
switches 0:5c4d7b2438d3 195
switches 0:5c4d7b2438d3 196 MXC_SPIX->sck_fb_ctrl &= ~(MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE |
switches 0:5c4d7b2438d3 197 MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK);
switches 0:5c4d7b2438d3 198 } else {
switches 0:5c4d7b2438d3 199 // Use Feedback mode
switches 0:5c4d7b2438d3 200 MXC_SPIX->master_cfg &= ~(MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT);
switches 0:5c4d7b2438d3 201
switches 0:5c4d7b2438d3 202 MXC_SPIX->sck_fb_ctrl |= (MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE |
switches 0:5c4d7b2438d3 203 MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK);
switches 0:5c4d7b2438d3 204
switches 0:5c4d7b2438d3 205
switches 0:5c4d7b2438d3 206 #if(MXC_SPIX_REV == 0)
switches 0:5c4d7b2438d3 207 SPIX_UpdateFBIgnore();
switches 0:5c4d7b2438d3 208 #endif
switches 0:5c4d7b2438d3 209 }
switches 0:5c4d7b2438d3 210
switches 0:5c4d7b2438d3 211 return E_NO_ERROR;
switches 0:5c4d7b2438d3 212 }
switches 0:5c4d7b2438d3 213
switches 0:5c4d7b2438d3 214 /******************************************************************************/
switches 0:5c4d7b2438d3 215 #if defined ( __GNUC__ )
switches 0:5c4d7b2438d3 216 __attribute__ ((section(".spix_config"), noinline))
switches 0:5c4d7b2438d3 217 #endif /* __GNUC */
switches 0:5c4d7b2438d3 218
switches 0:5c4d7b2438d3 219 #if IAR_SPIX_PRAGMA
switches 0:5c4d7b2438d3 220 #pragma location=".spix_config" // IAR locate function in RAM section .spix_config
switches 0:5c4d7b2438d3 221 #pragma optimize=no_inline // IAR no inline optimization on this function
switches 0:5c4d7b2438d3 222 #endif /* IAR_SPIX_PRAGMA */
switches 0:5c4d7b2438d3 223
switches 0:5c4d7b2438d3 224 void SPIX_ConfigSlave(uint8_t ssel, uint8_t pol, uint8_t act_delay, uint8_t inact_delay)
switches 0:5c4d7b2438d3 225 {
switches 0:5c4d7b2438d3 226
switches 0:5c4d7b2438d3 227 // Set the slave select
switches 0:5c4d7b2438d3 228 MXC_SPIX->master_cfg = ((MXC_SPIX->master_cfg & ~MXC_F_SPIX_MASTER_CFG_SLAVE_SEL) |
switches 0:5c4d7b2438d3 229 (ssel << MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS));
switches 0:5c4d7b2438d3 230
switches 0:5c4d7b2438d3 231 if(pol != 0) {
switches 0:5c4d7b2438d3 232 // Active high
switches 0:5c4d7b2438d3 233 MXC_SPIX->master_cfg &= ~(MXC_F_SPIX_MASTER_CFG_SS_ACT_LO);
switches 0:5c4d7b2438d3 234 } else {
switches 0:5c4d7b2438d3 235 // Active low
switches 0:5c4d7b2438d3 236 MXC_SPIX->master_cfg |= MXC_F_SPIX_MASTER_CFG_SS_ACT_LO;
switches 0:5c4d7b2438d3 237 }
switches 0:5c4d7b2438d3 238
switches 0:5c4d7b2438d3 239 // Set the delays
switches 0:5c4d7b2438d3 240 MXC_SPIX->master_cfg = ((MXC_SPIX->master_cfg & ~(MXC_F_SPIX_MASTER_CFG_ACT_DELAY |
switches 0:5c4d7b2438d3 241 MXC_F_SPIX_MASTER_CFG_INACT_DELAY)) |
switches 0:5c4d7b2438d3 242 (act_delay << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS) |
switches 0:5c4d7b2438d3 243 (inact_delay << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS));
switches 0:5c4d7b2438d3 244 }
switches 0:5c4d7b2438d3 245
switches 0:5c4d7b2438d3 246 /******************************************************************************/
switches 0:5c4d7b2438d3 247 #if defined ( __GNUC__ )
switches 0:5c4d7b2438d3 248 __attribute__ ((section(".spix_config"), noinline))
switches 0:5c4d7b2438d3 249 #endif /* __GNUC */
switches 0:5c4d7b2438d3 250
switches 0:5c4d7b2438d3 251 #if IAR_SPIX_PRAGMA
switches 0:5c4d7b2438d3 252 #pragma location=".spix_config" // IAR locate function in RAM section .spix_config
switches 0:5c4d7b2438d3 253 #pragma optimize=no_inline // IAR no inline optimization on this function
switches 0:5c4d7b2438d3 254 #endif /* IAR_SPIX_PRAGMA */
switches 0:5c4d7b2438d3 255
switches 0:5c4d7b2438d3 256 void SPIX_ConfigFetch(const spix_fetch_t *fetch)
switches 0:5c4d7b2438d3 257 {
switches 0:5c4d7b2438d3 258 // Configure how the SPIX fetches data
switches 0:5c4d7b2438d3 259 MXC_SPIX->fetch_ctrl = (((fetch->cmd << MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS) & MXC_F_SPIX_FETCH_CTRL_CMD_VALUE) |
switches 0:5c4d7b2438d3 260 ((fetch->cmd_width << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS) & MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH) |
switches 0:5c4d7b2438d3 261 ((fetch->addr_width << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS) & MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH) |
switches 0:5c4d7b2438d3 262 ((fetch->data_width << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS) & MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH) |
switches 0:5c4d7b2438d3 263 ((fetch->addr_size << MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS) & MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR));
switches 0:5c4d7b2438d3 264
switches 0:5c4d7b2438d3 265 // Set the command mode and clocks
switches 0:5c4d7b2438d3 266 MXC_SPIX->mode_ctrl = (((fetch->mode_clocks << MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS) & MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS) |
switches 0:5c4d7b2438d3 267 (!!fetch->no_cmd_mode << MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS));
switches 0:5c4d7b2438d3 268
switches 0:5c4d7b2438d3 269 MXC_SPIX->mode_data = (((fetch->mode_data << MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS) & MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS) |
switches 0:5c4d7b2438d3 270 MXC_F_SPIX_MODE_DATA_MODE_DATA_OE);
switches 0:5c4d7b2438d3 271
switches 0:5c4d7b2438d3 272 #if(MXC_SPIX_REV == 0)
switches 0:5c4d7b2438d3 273 SPIX_UpdateFBIgnore();
switches 0:5c4d7b2438d3 274 #endif
switches 0:5c4d7b2438d3 275 }
switches 0:5c4d7b2438d3 276
switches 0:5c4d7b2438d3 277 /******************************************************************************/
switches 0:5c4d7b2438d3 278 #if defined ( __GNUC__ )
switches 0:5c4d7b2438d3 279 __attribute__ ((section(".spix_config"), noinline))
switches 0:5c4d7b2438d3 280 #endif /* __GNUC */
switches 0:5c4d7b2438d3 281
switches 0:5c4d7b2438d3 282 #if IAR_SPIX_PRAGMA
switches 0:5c4d7b2438d3 283 #pragma location=".spix_config" // IAR locate function in RAM section .spix_config
switches 0:5c4d7b2438d3 284 #pragma optimize=no_inline // IAR no inline optimization on this function
switches 0:5c4d7b2438d3 285 #endif /* IAR_SPIX_PRAGMA */
switches 0:5c4d7b2438d3 286
switches 0:5c4d7b2438d3 287 int SPIX_Shutdown(mxc_spix_regs_t *spix)
switches 0:5c4d7b2438d3 288 {
switches 0:5c4d7b2438d3 289 int err;
switches 0:5c4d7b2438d3 290
switches 0:5c4d7b2438d3 291 // Clear system level configurations
switches 0:5c4d7b2438d3 292 if ((err = SYS_SPIX_Shutdown()) != E_NO_ERROR) {
switches 0:5c4d7b2438d3 293 return err;
switches 0:5c4d7b2438d3 294 }
switches 0:5c4d7b2438d3 295
switches 0:5c4d7b2438d3 296 return E_NO_ERROR;
switches 0:5c4d7b2438d3 297 }