Greg Steiert / pegasus_dev

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Dependents:   blinky_max32630fthr

targets/TARGET_Maxim/TARGET_MAX32630/i2c_api.c@0:5c4d7b2438d3, 2016-11-11 (annotated)

Committer:
switches
Date:
Fri Nov 11 20:59:50 2016 +0000
Revision:
0:5c4d7b2438d3
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 /*******************************************************************************
switches 0:5c4d7b2438d3 2 * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
switches 0:5c4d7b2438d3 3 *
switches 0:5c4d7b2438d3 4 * Permission is hereby granted, free of charge, to any person obtaining a
switches 0:5c4d7b2438d3 5 * copy of this software and associated documentation files (the "Software"),
switches 0:5c4d7b2438d3 6 * to deal in the Software without restriction, including without limitation
switches 0:5c4d7b2438d3 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
switches 0:5c4d7b2438d3 8 * and/or sell copies of the Software, and to permit persons to whom the
switches 0:5c4d7b2438d3 9 * Software is furnished to do so, subject to the following conditions:
switches 0:5c4d7b2438d3 10 *
switches 0:5c4d7b2438d3 11 * The above copyright notice and this permission notice shall be included
switches 0:5c4d7b2438d3 12 * in all copies or substantial portions of the Software.
switches 0:5c4d7b2438d3 13 *
switches 0:5c4d7b2438d3 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
switches 0:5c4d7b2438d3 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
switches 0:5c4d7b2438d3 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
switches 0:5c4d7b2438d3 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
switches 0:5c4d7b2438d3 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
switches 0:5c4d7b2438d3 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
switches 0:5c4d7b2438d3 20 * OTHER DEALINGS IN THE SOFTWARE.
switches 0:5c4d7b2438d3 21 *
switches 0:5c4d7b2438d3 22 * Except as contained in this notice, the name of Maxim Integrated
switches 0:5c4d7b2438d3 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
switches 0:5c4d7b2438d3 24 * Products, Inc. Branding Policy.
switches 0:5c4d7b2438d3 25 *
switches 0:5c4d7b2438d3 26 * The mere transfer of this software does not imply any licenses
switches 0:5c4d7b2438d3 27 * of trade secrets, proprietary technology, copyrights, patents,
switches 0:5c4d7b2438d3 28 * trademarks, maskwork rights, or any other form of intellectual
switches 0:5c4d7b2438d3 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
switches 0:5c4d7b2438d3 30 * ownership rights.
switches 0:5c4d7b2438d3 31 *******************************************************************************
switches 0:5c4d7b2438d3 32 */
switches 0:5c4d7b2438d3 33
switches 0:5c4d7b2438d3 34 #include "mbed_assert.h"
switches 0:5c4d7b2438d3 35 #include "i2c_api.h"
switches 0:5c4d7b2438d3 36 #include "i2cm_regs.h"
switches 0:5c4d7b2438d3 37 #include "i2cm.h"
switches 0:5c4d7b2438d3 38 #include "pinmap.h"
switches 0:5c4d7b2438d3 39 #include "PeripheralPins.h"
switches 0:5c4d7b2438d3 40
switches 0:5c4d7b2438d3 41 #ifndef MXC_I2CM_RX_TIMEOUT
switches 0:5c4d7b2438d3 42 #define MXC_I2CM_RX_TIMEOUT 0x5000
switches 0:5c4d7b2438d3 43 #endif
switches 0:5c4d7b2438d3 44
switches 0:5c4d7b2438d3 45 #define MBED_NAK 0
switches 0:5c4d7b2438d3 46 #define MBED_ACK 1
switches 0:5c4d7b2438d3 47 #define MBED_TIMEOUT 2
switches 0:5c4d7b2438d3 48
switches 0:5c4d7b2438d3 49 //******************************************************************************
switches 0:5c4d7b2438d3 50 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
switches 0:5c4d7b2438d3 51 {
switches 0:5c4d7b2438d3 52 // SDA and SCL must map to same peripheral instance
switches 0:5c4d7b2438d3 53 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
switches 0:5c4d7b2438d3 54 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
switches 0:5c4d7b2438d3 55 mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl);
switches 0:5c4d7b2438d3 56 MBED_ASSERT((int)i2c != NC);
switches 0:5c4d7b2438d3 57
switches 0:5c4d7b2438d3 58 obj->i2c = i2c;
switches 0:5c4d7b2438d3 59 obj->fifo = MXC_I2CM_GET_FIFO(MXC_I2CM_GET_IDX(i2c));
switches 0:5c4d7b2438d3 60 obj->start_pending = 0;
switches 0:5c4d7b2438d3 61
switches 0:5c4d7b2438d3 62 // Merge pin function requests for use with CMSIS init func
switches 0:5c4d7b2438d3 63 ioman_req_t io_req;
switches 0:5c4d7b2438d3 64 pin_function_t *pin_func;
switches 0:5c4d7b2438d3 65 pin_func = (pin_function_t *)pinmap_find_function(sda, PinMap_I2C_SDA);
switches 0:5c4d7b2438d3 66 io_req.value = pin_func->req_val;
switches 0:5c4d7b2438d3 67 pin_func = (pin_function_t *)pinmap_find_function(scl, PinMap_I2C_SCL);
switches 0:5c4d7b2438d3 68 io_req.value |= pin_func->req_val;
switches 0:5c4d7b2438d3 69
switches 0:5c4d7b2438d3 70 obj->sys_cfg.io_cfg.req_reg = pin_func->reg_req;
switches 0:5c4d7b2438d3 71 obj->sys_cfg.io_cfg.ack_reg = pin_func->reg_ack;
switches 0:5c4d7b2438d3 72 obj->sys_cfg.io_cfg.req_val = io_req;
switches 0:5c4d7b2438d3 73 obj->sys_cfg.clk_scale = CLKMAN_SCALE_DIV_1;
switches 0:5c4d7b2438d3 74
switches 0:5c4d7b2438d3 75 I2CM_Init(obj->i2c, &obj->sys_cfg, I2CM_SPEED_400KHZ);
switches 0:5c4d7b2438d3 76 }
switches 0:5c4d7b2438d3 77
switches 0:5c4d7b2438d3 78 //******************************************************************************
switches 0:5c4d7b2438d3 79 void i2c_frequency(i2c_t *obj, int hz)
switches 0:5c4d7b2438d3 80 {
switches 0:5c4d7b2438d3 81 I2CM_Init(obj->i2c, &obj->sys_cfg, hz);
switches 0:5c4d7b2438d3 82 }
switches 0:5c4d7b2438d3 83
switches 0:5c4d7b2438d3 84 //******************************************************************************
switches 0:5c4d7b2438d3 85 int i2c_start(i2c_t *obj)
switches 0:5c4d7b2438d3 86 {
switches 0:5c4d7b2438d3 87 obj->start_pending = 1;
switches 0:5c4d7b2438d3 88 return 0;
switches 0:5c4d7b2438d3 89 }
switches 0:5c4d7b2438d3 90
switches 0:5c4d7b2438d3 91 //******************************************************************************
switches 0:5c4d7b2438d3 92 int i2c_stop(i2c_t *obj)
switches 0:5c4d7b2438d3 93 {
switches 0:5c4d7b2438d3 94 obj->start_pending = 0;
switches 0:5c4d7b2438d3 95 I2CM_WriteTxFifo(obj->i2c, obj->fifo, MXC_S_I2CM_TRANS_TAG_STOP);
switches 0:5c4d7b2438d3 96 I2CM_TxInProgress(obj->i2c);
switches 0:5c4d7b2438d3 97 return 0;
switches 0:5c4d7b2438d3 98 }
switches 0:5c4d7b2438d3 99
switches 0:5c4d7b2438d3 100 //******************************************************************************
switches 0:5c4d7b2438d3 101 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
switches 0:5c4d7b2438d3 102 {
switches 0:5c4d7b2438d3 103 MBED_ASSERT(stop != 0);
switches 0:5c4d7b2438d3 104 return I2CM_Read(obj->i2c, address >> 1, NULL, 0, (uint8_t *)data, length);
switches 0:5c4d7b2438d3 105 }
switches 0:5c4d7b2438d3 106
switches 0:5c4d7b2438d3 107 //******************************************************************************
switches 0:5c4d7b2438d3 108 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
switches 0:5c4d7b2438d3 109 {
switches 0:5c4d7b2438d3 110 mxc_i2cm_regs_t *i2cm = obj->i2c;
switches 0:5c4d7b2438d3 111 mxc_i2cm_fifo_regs_t *fifo = obj->fifo;
switches 0:5c4d7b2438d3 112
switches 0:5c4d7b2438d3 113 if (stop) {
switches 0:5c4d7b2438d3 114 return I2CM_Write(i2cm, address >> 1, NULL, 0, (uint8_t *)data, length);
switches 0:5c4d7b2438d3 115 }
switches 0:5c4d7b2438d3 116
switches 0:5c4d7b2438d3 117 i2cm->inten = 0;
switches 0:5c4d7b2438d3 118 i2cm->intfl = i2cm->intfl;
switches 0:5c4d7b2438d3 119 if (I2CM_Tx(i2cm, fifo, address >> 1, (uint8_t *)data, length, 0) == E_NO_ERROR) {
switches 0:5c4d7b2438d3 120 return length;
switches 0:5c4d7b2438d3 121 } else {
switches 0:5c4d7b2438d3 122 return -1;
switches 0:5c4d7b2438d3 123 }
switches 0:5c4d7b2438d3 124 }
switches 0:5c4d7b2438d3 125
switches 0:5c4d7b2438d3 126 //******************************************************************************
switches 0:5c4d7b2438d3 127 void i2c_reset(i2c_t *obj)
switches 0:5c4d7b2438d3 128 {
switches 0:5c4d7b2438d3 129 I2CM_Recover(obj->i2c);
switches 0:5c4d7b2438d3 130 }
switches 0:5c4d7b2438d3 131
switches 0:5c4d7b2438d3 132 //******************************************************************************
switches 0:5c4d7b2438d3 133 int i2c_byte_read(i2c_t *obj, int last)
switches 0:5c4d7b2438d3 134 {
switches 0:5c4d7b2438d3 135 mxc_i2cm_regs_t *i2cm = obj->i2c;
switches 0:5c4d7b2438d3 136 mxc_i2cm_fifo_regs_t *fifo = obj->fifo;
switches 0:5c4d7b2438d3 137 int tmp;
switches 0:5c4d7b2438d3 138
switches 0:5c4d7b2438d3 139 // Start the transaction if it is not currently ongoing
switches 0:5c4d7b2438d3 140 if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
switches 0:5c4d7b2438d3 141 i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
switches 0:5c4d7b2438d3 142 }
switches 0:5c4d7b2438d3 143
switches 0:5c4d7b2438d3 144 if (last) {
switches 0:5c4d7b2438d3 145 // NACK the last read byte
switches 0:5c4d7b2438d3 146 if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK) != E_NO_ERROR) {
switches 0:5c4d7b2438d3 147 goto byte_read_err;
switches 0:5c4d7b2438d3 148 }
switches 0:5c4d7b2438d3 149
switches 0:5c4d7b2438d3 150 // Send the stop condition
switches 0:5c4d7b2438d3 151 if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP) != E_NO_ERROR) {
switches 0:5c4d7b2438d3 152 goto byte_read_err;
switches 0:5c4d7b2438d3 153 }
switches 0:5c4d7b2438d3 154 } else {
switches 0:5c4d7b2438d3 155 if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT) != E_NO_ERROR) {
switches 0:5c4d7b2438d3 156 goto byte_read_err;
switches 0:5c4d7b2438d3 157 }
switches 0:5c4d7b2438d3 158 }
switches 0:5c4d7b2438d3 159
switches 0:5c4d7b2438d3 160 do {
switches 0:5c4d7b2438d3 161 // Wait for data in RX FIFO
switches 0:5c4d7b2438d3 162 int timeout = MXC_I2CM_RX_TIMEOUT;
switches 0:5c4d7b2438d3 163 while (!(i2cm->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
switches 0:5c4d7b2438d3 164 ((i2cm->bb & MXC_F_I2CM_BB_RX_FIFO_CNT) == 0)) {
switches 0:5c4d7b2438d3 165
switches 0:5c4d7b2438d3 166 if((timeout-- < 0) || (i2cm->trans & MXC_F_I2CM_TRANS_TX_TIMEOUT)) {
switches 0:5c4d7b2438d3 167 goto byte_read_err;
switches 0:5c4d7b2438d3 168 }
switches 0:5c4d7b2438d3 169
switches 0:5c4d7b2438d3 170 if (i2cm->trans & (MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED)) {
switches 0:5c4d7b2438d3 171 goto byte_read_err;
switches 0:5c4d7b2438d3 172 }
switches 0:5c4d7b2438d3 173 }
switches 0:5c4d7b2438d3 174 i2cm->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
switches 0:5c4d7b2438d3 175
switches 0:5c4d7b2438d3 176 } while ((tmp = fifo->rx) & MXC_S_I2CM_RSTLS_TAG_EMPTY);
switches 0:5c4d7b2438d3 177
switches 0:5c4d7b2438d3 178 return (uint8_t)tmp;
switches 0:5c4d7b2438d3 179
switches 0:5c4d7b2438d3 180 byte_read_err:
switches 0:5c4d7b2438d3 181 i2c_reset(obj);
switches 0:5c4d7b2438d3 182 return -1;
switches 0:5c4d7b2438d3 183 }
switches 0:5c4d7b2438d3 184
switches 0:5c4d7b2438d3 185 //******************************************************************************
switches 0:5c4d7b2438d3 186 int i2c_byte_write(i2c_t *obj, int data)
switches 0:5c4d7b2438d3 187 {
switches 0:5c4d7b2438d3 188 mxc_i2cm_regs_t *i2cm = obj->i2c;
switches 0:5c4d7b2438d3 189 mxc_i2cm_fifo_regs_t *fifo = obj->fifo;
switches 0:5c4d7b2438d3 190 int result;
switches 0:5c4d7b2438d3 191
switches 0:5c4d7b2438d3 192 if (obj->start_pending) {
switches 0:5c4d7b2438d3 193 obj->start_pending = 0;
switches 0:5c4d7b2438d3 194 data |= MXC_S_I2CM_TRANS_TAG_START;
switches 0:5c4d7b2438d3 195 } else {
switches 0:5c4d7b2438d3 196 data |= MXC_S_I2CM_TRANS_TAG_TXDATA_ACK;
switches 0:5c4d7b2438d3 197 }
switches 0:5c4d7b2438d3 198
switches 0:5c4d7b2438d3 199 if ((result = I2CM_WriteTxFifo(i2cm, fifo, data)) != E_NO_ERROR) {
switches 0:5c4d7b2438d3 200 i2c_reset(obj);
switches 0:5c4d7b2438d3 201 if (result == E_COMM_ERR) {
switches 0:5c4d7b2438d3 202 return MBED_NAK;
switches 0:5c4d7b2438d3 203 }
switches 0:5c4d7b2438d3 204 return MBED_TIMEOUT;
switches 0:5c4d7b2438d3 205 }
switches 0:5c4d7b2438d3 206
switches 0:5c4d7b2438d3 207 // Start the transaction if it is not currently ongoing
switches 0:5c4d7b2438d3 208 if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
switches 0:5c4d7b2438d3 209 i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
switches 0:5c4d7b2438d3 210 }
switches 0:5c4d7b2438d3 211
switches 0:5c4d7b2438d3 212 return MBED_ACK;
switches 0:5c4d7b2438d3 213 }