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Dependents:   blinky_max32630fthr

targets/TARGET_Maxim/TARGET_MAX32625/mxc/i2cm.h@0:5c4d7b2438d3, 2016-11-11 (annotated)

Committer:
switches
Date:
Fri Nov 11 20:59:50 2016 +0000
Revision:
0:5c4d7b2438d3
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 /*******************************************************************************
switches 0:5c4d7b2438d3 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
switches 0:5c4d7b2438d3 3 *
switches 0:5c4d7b2438d3 4 * Permission is hereby granted, free of charge, to any person obtaining a
switches 0:5c4d7b2438d3 5 * copy of this software and associated documentation files (the "Software"),
switches 0:5c4d7b2438d3 6 * to deal in the Software without restriction, including without limitation
switches 0:5c4d7b2438d3 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
switches 0:5c4d7b2438d3 8 * and/or sell copies of the Software, and to permit persons to whom the
switches 0:5c4d7b2438d3 9 * Software is furnished to do so, subject to the following conditions:
switches 0:5c4d7b2438d3 10 *
switches 0:5c4d7b2438d3 11 * The above copyright notice and this permission notice shall be included
switches 0:5c4d7b2438d3 12 * in all copies or substantial portions of the Software.
switches 0:5c4d7b2438d3 13 *
switches 0:5c4d7b2438d3 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
switches 0:5c4d7b2438d3 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
switches 0:5c4d7b2438d3 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
switches 0:5c4d7b2438d3 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
switches 0:5c4d7b2438d3 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
switches 0:5c4d7b2438d3 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
switches 0:5c4d7b2438d3 20 * OTHER DEALINGS IN THE SOFTWARE.
switches 0:5c4d7b2438d3 21 *
switches 0:5c4d7b2438d3 22 * Except as contained in this notice, the name of Maxim Integrated
switches 0:5c4d7b2438d3 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
switches 0:5c4d7b2438d3 24 * Products, Inc. Branding Policy.
switches 0:5c4d7b2438d3 25 *
switches 0:5c4d7b2438d3 26 * The mere transfer of this software does not imply any licenses
switches 0:5c4d7b2438d3 27 * of trade secrets, proprietary technology, copyrights, patents,
switches 0:5c4d7b2438d3 28 * trademarks, maskwork rights, or any other form of intellectual
switches 0:5c4d7b2438d3 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
switches 0:5c4d7b2438d3 30 * ownership rights.
switches 0:5c4d7b2438d3 31 *
switches 0:5c4d7b2438d3 32 * $Date: 2016-04-27 11:55:43 -0500 (Wed, 27 Apr 2016) $
switches 0:5c4d7b2438d3 33 * $Revision: 22541 $
switches 0:5c4d7b2438d3 34 *
switches 0:5c4d7b2438d3 35 ******************************************************************************/
switches 0:5c4d7b2438d3 36
switches 0:5c4d7b2438d3 37 /**
switches 0:5c4d7b2438d3 38 * @file i2cm.h
switches 0:5c4d7b2438d3 39 * @brief I2C Master driver header file.
switches 0:5c4d7b2438d3 40 */
switches 0:5c4d7b2438d3 41
switches 0:5c4d7b2438d3 42 #ifndef _I2CM_H_
switches 0:5c4d7b2438d3 43 #define _I2CM_H_
switches 0:5c4d7b2438d3 44
switches 0:5c4d7b2438d3 45 /***** Includes *****/
switches 0:5c4d7b2438d3 46 #include "mxc_config.h"
switches 0:5c4d7b2438d3 47 #include "mxc_sys.h"
switches 0:5c4d7b2438d3 48 #include "i2cm_regs.h"
switches 0:5c4d7b2438d3 49
switches 0:5c4d7b2438d3 50 #ifdef __cplusplus
switches 0:5c4d7b2438d3 51 extern "C" {
switches 0:5c4d7b2438d3 52 #endif
switches 0:5c4d7b2438d3 53
switches 0:5c4d7b2438d3 54 /***** Definitions *****/
switches 0:5c4d7b2438d3 55
switches 0:5c4d7b2438d3 56 /// @brief I2CM frequencies.
switches 0:5c4d7b2438d3 57 typedef enum {
switches 0:5c4d7b2438d3 58 I2CM_SPEED_100KHZ = 100000,
switches 0:5c4d7b2438d3 59 I2CM_SPEED_400KHZ = 400000
switches 0:5c4d7b2438d3 60 } i2cm_speed_t;
switches 0:5c4d7b2438d3 61
switches 0:5c4d7b2438d3 62 /// @brief I2CM Transaction request.
switches 0:5c4d7b2438d3 63 typedef struct i2cm_req i2cm_req_t;
switches 0:5c4d7b2438d3 64 struct i2cm_req {
switches 0:5c4d7b2438d3 65
switches 0:5c4d7b2438d3 66 /**
switches 0:5c4d7b2438d3 67 * @details Only supports 7-bit addressing. Driver will shift the address and
switches 0:5c4d7b2438d3 68 * add the read bit when necessary.
switches 0:5c4d7b2438d3 69 */
switches 0:5c4d7b2438d3 70 uint8_t addr;
switches 0:5c4d7b2438d3 71 const uint8_t *cmd_data; ///< Optional command data to write before reading.
switches 0:5c4d7b2438d3 72 uint32_t cmd_len; ///< Number of bytes in command.
switches 0:5c4d7b2438d3 73 uint8_t *data; ///< Data to write or read.
switches 0:5c4d7b2438d3 74 uint32_t data_len; ///< Length of data.
switches 0:5c4d7b2438d3 75 uint32_t cmd_num; ///< Number of command bytes sent
switches 0:5c4d7b2438d3 76 uint32_t data_num; ///< Number of data bytes sent
switches 0:5c4d7b2438d3 77
switches 0:5c4d7b2438d3 78 /**
switches 0:5c4d7b2438d3 79 * @brief Callback for asynchronous request.
switches 0:5c4d7b2438d3 80 * @param i2cm_req_t* Pointer to the transaction request.
switches 0:5c4d7b2438d3 81 * @param int Error code.
switches 0:5c4d7b2438d3 82 */
switches 0:5c4d7b2438d3 83 void (*callback)(i2cm_req_t*, int);
switches 0:5c4d7b2438d3 84 };
switches 0:5c4d7b2438d3 85
switches 0:5c4d7b2438d3 86 /***** Globals *****/
switches 0:5c4d7b2438d3 87
switches 0:5c4d7b2438d3 88 /***** Function Prototypes *****/
switches 0:5c4d7b2438d3 89
switches 0:5c4d7b2438d3 90 /**
switches 0:5c4d7b2438d3 91 * @brief Initialize I2CM module.
switches 0:5c4d7b2438d3 92 * @param i2cm Pointer to I2CM regs.
switches 0:5c4d7b2438d3 93 * @param cfg Pointer to I2CM configuration.
switches 0:5c4d7b2438d3 94 * @param speed I2CM frequency.
switches 0:5c4d7b2438d3 95 * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
switches 0:5c4d7b2438d3 96 */
switches 0:5c4d7b2438d3 97 int I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *sys_cfg, i2cm_speed_t speed);
switches 0:5c4d7b2438d3 98
switches 0:5c4d7b2438d3 99 /**
switches 0:5c4d7b2438d3 100 * @brief Shutdown I2CM module.
switches 0:5c4d7b2438d3 101 * @param i2cm Pointer to I2CM regs.
switches 0:5c4d7b2438d3 102 * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
switches 0:5c4d7b2438d3 103 */
switches 0:5c4d7b2438d3 104 int I2CM_Shutdown(mxc_i2cm_regs_t *i2cm);
switches 0:5c4d7b2438d3 105
switches 0:5c4d7b2438d3 106 /**
switches 0:5c4d7b2438d3 107 * @brief Read I2CM data. Will block until transaction is complete.
switches 0:5c4d7b2438d3 108 * @param i2cm Pointer to I2CM regs.
switches 0:5c4d7b2438d3 109 * @param addr I2C address of the slave.
switches 0:5c4d7b2438d3 110 * @param cmd_data Data to write before reading.
switches 0:5c4d7b2438d3 111 * @param cmd_len Number of bytes to write before reading.
switches 0:5c4d7b2438d3 112 * @param data Where to store read data.
switches 0:5c4d7b2438d3 113 * @param len Number of bytes to read.
switches 0:5c4d7b2438d3 114 * @details Command is an optional feature where the master will write the cmd_data
switches 0:5c4d7b2438d3 115 * before reading from the slave. If command is undesired, leave the pointer
switches 0:5c4d7b2438d3 116 * NULL and cmd_len 0. If there is a command, the master will send a
switches 0:5c4d7b2438d3 117 repeated start before reading. Will block until transaction has completed.
switches 0:5c4d7b2438d3 118 * @returns Bytes transacted if everything is successful, error if unsuccessful.
switches 0:5c4d7b2438d3 119 */
switches 0:5c4d7b2438d3 120 int I2CM_Read(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data,
switches 0:5c4d7b2438d3 121 uint32_t cmd_len, uint8_t* data, uint32_t len);
switches 0:5c4d7b2438d3 122
switches 0:5c4d7b2438d3 123 /**
switches 0:5c4d7b2438d3 124 * @brief Write I2CM data. Will block until transaction is complete.
switches 0:5c4d7b2438d3 125 * @param i2cm Pointer to I2CM regs.
switches 0:5c4d7b2438d3 126 * @param addr I2C address of the slave.
switches 0:5c4d7b2438d3 127 * @param cmd_data Data to write before writing data.
switches 0:5c4d7b2438d3 128 * @param cmd_len Number of bytes to write before writing data.
switches 0:5c4d7b2438d3 129 * @param data Data to be written.
switches 0:5c4d7b2438d3 130 * @param len Number of bytes to Write.
switches 0:5c4d7b2438d3 131 * @details Command is an optional feature where the master will write the cmd_data
switches 0:5c4d7b2438d3 132 * before writing to the slave. If command is undesired, leave the pointer
switches 0:5c4d7b2438d3 133 * NULL and cmd_len 0. If there is a command, the master will send a
switches 0:5c4d7b2438d3 134 repeated start before writing again. Will block until transaction has completed.
switches 0:5c4d7b2438d3 135 * @returns Bytes transacted if everything is successful, error if unsuccessful.
switches 0:5c4d7b2438d3 136 */
switches 0:5c4d7b2438d3 137 int I2CM_Write(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data,
switches 0:5c4d7b2438d3 138 uint32_t cmd_len, uint8_t* data, uint32_t len);
switches 0:5c4d7b2438d3 139
switches 0:5c4d7b2438d3 140 /**
switches 0:5c4d7b2438d3 141 * @brief Asynchronously read I2CM data.
switches 0:5c4d7b2438d3 142 * @param i2cm Pointer to I2CM regs.
switches 0:5c4d7b2438d3 143 * @param req Request for an I2CM transaction.
switches 0:5c4d7b2438d3 144 * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
switches 0:5c4d7b2438d3 145 */
switches 0:5c4d7b2438d3 146 int I2CM_ReadAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req);
switches 0:5c4d7b2438d3 147
switches 0:5c4d7b2438d3 148 /**
switches 0:5c4d7b2438d3 149 * @brief Asynchronously write I2CM data.
switches 0:5c4d7b2438d3 150 * @param i2cm Pointer to I2CM regs.
switches 0:5c4d7b2438d3 151 * @param req Request for an I2CM transaction.
switches 0:5c4d7b2438d3 152 * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
switches 0:5c4d7b2438d3 153 */
switches 0:5c4d7b2438d3 154 int I2CM_WriteAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req);
switches 0:5c4d7b2438d3 155
switches 0:5c4d7b2438d3 156 /**
switches 0:5c4d7b2438d3 157 * @brief Abort asynchronous request.
switches 0:5c4d7b2438d3 158 * @param req Pointer to request for a I2CM transaction.
switches 0:5c4d7b2438d3 159 * @note Will call the callback for the request.
switches 0:5c4d7b2438d3 160 * @returns #E_NO_ERROR if request aborted, error if unsuccessful.
switches 0:5c4d7b2438d3 161 */
switches 0:5c4d7b2438d3 162 int I2CM_AbortAsync(i2cm_req_t *req);
switches 0:5c4d7b2438d3 163
switches 0:5c4d7b2438d3 164 /**
switches 0:5c4d7b2438d3 165 * @brief I2CM interrupt handler.
switches 0:5c4d7b2438d3 166 * @details This function should be called by the application from the interrupt
switches 0:5c4d7b2438d3 167 * handler if I2CM interrupts are enabled. Alternately, this function
switches 0:5c4d7b2438d3 168 * can be periodically called by the application if I2CM interrupts are
switches 0:5c4d7b2438d3 169 * disabled.
switches 0:5c4d7b2438d3 170 * @param i2cm Base address of the I2CM module.
switches 0:5c4d7b2438d3 171 */
switches 0:5c4d7b2438d3 172 void I2CM_Handler(mxc_i2cm_regs_t *i2cm);
switches 0:5c4d7b2438d3 173
switches 0:5c4d7b2438d3 174 /**
switches 0:5c4d7b2438d3 175 * @brief Checks to see if the I2CM is busy.
switches 0:5c4d7b2438d3 176 * @param i2cm Pointer to I2CM regs.
switches 0:5c4d7b2438d3 177 * @returns #E_NO_ERROR if idle, #E_BUSY if in use.
switches 0:5c4d7b2438d3 178 */
switches 0:5c4d7b2438d3 179 int I2CM_Busy(mxc_i2cm_regs_t *i2cm);
switches 0:5c4d7b2438d3 180
switches 0:5c4d7b2438d3 181 /**
switches 0:5c4d7b2438d3 182 * @brief Attempt to prepare the I2CM for sleep.
switches 0:5c4d7b2438d3 183 * @param i2cm Pointer to I2CM regs.
switches 0:5c4d7b2438d3 184 * @details Checks for any ongoing transactions. Disables interrupts if the I2CM
switches 0:5c4d7b2438d3 185 is idle.
switches 0:5c4d7b2438d3 186 * @returns #E_NO_ERROR if ready to sleep, #E_BUSY if not ready for sleep.
switches 0:5c4d7b2438d3 187 */
switches 0:5c4d7b2438d3 188 int I2CM_PrepForSleep(mxc_i2cm_regs_t *i2cm);
switches 0:5c4d7b2438d3 189
switches 0:5c4d7b2438d3 190 /**
switches 0:5c4d7b2438d3 191 * @brief Check the I2C bus.
switches 0:5c4d7b2438d3 192 * @param i2cm Pointer to I2CM regs.
switches 0:5c4d7b2438d3 193 * @details Checks the I2CM bus to determine if there is any other master using
switches 0:5c4d7b2438d3 194 * the bus.
switches 0:5c4d7b2438d3 195 * @returns #E_NO_ERROR if SCL and SDA are high, #E_BUSY otherwise.
switches 0:5c4d7b2438d3 196 */
switches 0:5c4d7b2438d3 197 int I2CM_BusCheck(mxc_i2cm_regs_t *i2cm);
switches 0:5c4d7b2438d3 198
switches 0:5c4d7b2438d3 199 /**
switches 0:5c4d7b2438d3 200 * @brief Drain all of the data in the RXFIFO.
switches 0:5c4d7b2438d3 201 * @param i2cm Pointer to UART regs.
switches 0:5c4d7b2438d3 202 */
switches 0:5c4d7b2438d3 203 __STATIC_INLINE void I2CM_DrainRX(mxc_i2cm_regs_t *i2cm)
switches 0:5c4d7b2438d3 204 {
switches 0:5c4d7b2438d3 205 i2cm->ctrl &= ~(MXC_F_I2CM_CTRL_RX_FIFO_EN);
switches 0:5c4d7b2438d3 206 i2cm->ctrl |= MXC_F_I2CM_CTRL_RX_FIFO_EN;
switches 0:5c4d7b2438d3 207 }
switches 0:5c4d7b2438d3 208
switches 0:5c4d7b2438d3 209 /**
switches 0:5c4d7b2438d3 210 * @brief Drain all of the data in the TXFIFO.
switches 0:5c4d7b2438d3 211 * @param i2cm Pointer to UART regs.
switches 0:5c4d7b2438d3 212 */
switches 0:5c4d7b2438d3 213 __STATIC_INLINE void I2CM_DrainTX(mxc_i2cm_regs_t *i2cm)
switches 0:5c4d7b2438d3 214 {
switches 0:5c4d7b2438d3 215 i2cm->ctrl &= ~(MXC_F_I2CM_CTRL_TX_FIFO_EN);
switches 0:5c4d7b2438d3 216 i2cm->ctrl |= MXC_F_I2CM_CTRL_TX_FIFO_EN;
switches 0:5c4d7b2438d3 217 }
switches 0:5c4d7b2438d3 218
switches 0:5c4d7b2438d3 219 /**
switches 0:5c4d7b2438d3 220 * @brief Clear interrupt flags.
switches 0:5c4d7b2438d3 221 * @param i2cm Pointer to I2CM regs.
switches 0:5c4d7b2438d3 222 * @param mask Mask of interrupts to clear.
switches 0:5c4d7b2438d3 223 */
switches 0:5c4d7b2438d3 224 __STATIC_INLINE void I2CM_ClearFlags(mxc_i2cm_regs_t *i2cm, uint32_t mask)
switches 0:5c4d7b2438d3 225 {
switches 0:5c4d7b2438d3 226 i2cm->intfl = mask;
switches 0:5c4d7b2438d3 227 }
switches 0:5c4d7b2438d3 228
switches 0:5c4d7b2438d3 229 /**
switches 0:5c4d7b2438d3 230 * @brief Get interrupt flags.
switches 0:5c4d7b2438d3 231 * @param i2cm Pointer to I2CM regs.
switches 0:5c4d7b2438d3 232 * @returns Mask of active flags.
switches 0:5c4d7b2438d3 233 */
switches 0:5c4d7b2438d3 234 __STATIC_INLINE unsigned I2CM_GetFlags(mxc_i2cm_regs_t *i2cm)
switches 0:5c4d7b2438d3 235 {
switches 0:5c4d7b2438d3 236 return(i2cm->intfl);
switches 0:5c4d7b2438d3 237 }
switches 0:5c4d7b2438d3 238 /**
switches 0:5c4d7b2438d3 239 * @brief Set the I2C Frequency
switches 0:5c4d7b2438d3 240 * @param i2cm Pointer to I2CM regs.
switches 0:5c4d7b2438d3 241 * @param speed speed in Hz
switches 0:5c4d7b2438d3 242 * @details sets the registers for the proper frequency
switches 0:5c4d7b2438d3 243 * @returns #E_NO_ERROR if Frequency is supported, #E_NOT_Supported otherwise.
switches 0:5c4d7b2438d3 244 */
switches 0:5c4d7b2438d3 245 int I2CM_SetFrequency(mxc_i2cm_regs_t *i2cm, int speed);
switches 0:5c4d7b2438d3 246
switches 0:5c4d7b2438d3 247 void I2CM_Recover(mxc_i2cm_regs_t *i2cm);
switches 0:5c4d7b2438d3 248 int I2CM_WriteTxFifo(mxc_i2cm_regs_t *regs, mxc_i2cm_fifo_regs_t *fifo, const uint16_t data);
switches 0:5c4d7b2438d3 249 int I2CM_TxInProgress(mxc_i2cm_regs_t *i2cm);
switches 0:5c4d7b2438d3 250 int I2CM_Tx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr, const uint8_t *data, uint32_t len, uint8_t stop);
switches 0:5c4d7b2438d3 251 int I2CM_Rx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr, uint8_t *data, uint32_t len);
switches 0:5c4d7b2438d3 252
switches 0:5c4d7b2438d3 253 #ifdef __cplusplus
switches 0:5c4d7b2438d3 254 }
switches 0:5c4d7b2438d3 255 #endif
switches 0:5c4d7b2438d3 256
switches 0:5c4d7b2438d3 257 #endif /* _I2CM_H_ */