Greg Steiert / pegasus_dev

Development mbed library for MAX32630FTHR

Dependents:   blinky_max32630fthr

rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h@3:1198227e6421, 2016-12-16 (annotated)

Committer:
switches
Date:
Fri Dec 16 16:27:57 2016 +0000
Revision:
3:1198227e6421
Parent:
0:5c4d7b2438d3 
Changed ADC scale for MAX32625 platforms to 1.2V full scale to match MAX32630 platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 /*----------------------------------------------------------------------------
switches 0:5c4d7b2438d3 2 * RL-ARM - RTX
switches 0:5c4d7b2438d3 3 *----------------------------------------------------------------------------
switches 0:5c4d7b2438d3 4 * Name: RT_HAL_CA.H
switches 0:5c4d7b2438d3 5 * Purpose: Hardware Abstraction Layer for Cortex-A definitions
switches 0:5c4d7b2438d3 6 * Rev.: 14th Jan 2014
switches 0:5c4d7b2438d3 7 *----------------------------------------------------------------------------
switches 0:5c4d7b2438d3 8 *
switches 0:5c4d7b2438d3 9 * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
switches 0:5c4d7b2438d3 10 * All rights reserved.
switches 0:5c4d7b2438d3 11 * Redistribution and use in source and binary forms, with or without
switches 0:5c4d7b2438d3 12 * modification, are permitted provided that the following conditions are met:
switches 0:5c4d7b2438d3 13 * - Redistributions of source code must retain the above copyright
switches 0:5c4d7b2438d3 14 * notice, this list of conditions and the following disclaimer.
switches 0:5c4d7b2438d3 15 * - Redistributions in binary form must reproduce the above copyright
switches 0:5c4d7b2438d3 16 * notice, this list of conditions and the following disclaimer in the
switches 0:5c4d7b2438d3 17 * documentation and/or other materials provided with the distribution.
switches 0:5c4d7b2438d3 18 * - Neither the name of ARM nor the names of its contributors may be used
switches 0:5c4d7b2438d3 19 * to endorse or promote products derived from this software without
switches 0:5c4d7b2438d3 20 * specific prior written permission.
switches 0:5c4d7b2438d3 21 *
switches 0:5c4d7b2438d3 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
switches 0:5c4d7b2438d3 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
switches 0:5c4d7b2438d3 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
switches 0:5c4d7b2438d3 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
switches 0:5c4d7b2438d3 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
switches 0:5c4d7b2438d3 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
switches 0:5c4d7b2438d3 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
switches 0:5c4d7b2438d3 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
switches 0:5c4d7b2438d3 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
switches 0:5c4d7b2438d3 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
switches 0:5c4d7b2438d3 32 * POSSIBILITY OF SUCH DAMAGE.
switches 0:5c4d7b2438d3 33 *---------------------------------------------------------------------------*/
switches 0:5c4d7b2438d3 34
switches 0:5c4d7b2438d3 35 /* Definitions */
switches 0:5c4d7b2438d3 36 #define INIT_CPSR_SYS 0x4000001F
switches 0:5c4d7b2438d3 37 #define INIT_CPSR_USER 0x40000010
switches 0:5c4d7b2438d3 38
switches 0:5c4d7b2438d3 39 #define CPSR_T_BIT 0x20
switches 0:5c4d7b2438d3 40 #define CPSR_I_BIT 0x80
switches 0:5c4d7b2438d3 41 #define CPSR_F_BIT 0x40
switches 0:5c4d7b2438d3 42
switches 0:5c4d7b2438d3 43 #define MODE_USR 0x10
switches 0:5c4d7b2438d3 44 #define MODE_FIQ 0x11
switches 0:5c4d7b2438d3 45 #define MODE_IRQ 0x12
switches 0:5c4d7b2438d3 46 #define MODE_SVC 0x13
switches 0:5c4d7b2438d3 47 #define MODE_ABT 0x17
switches 0:5c4d7b2438d3 48 #define MODE_UND 0x1B
switches 0:5c4d7b2438d3 49 #define MODE_SYS 0x1F
switches 0:5c4d7b2438d3 50
switches 0:5c4d7b2438d3 51 #define MAGIC_WORD 0xE25A2EA5
switches 0:5c4d7b2438d3 52
switches 0:5c4d7b2438d3 53 #include "core_ca9.h"
switches 0:5c4d7b2438d3 54
switches 0:5c4d7b2438d3 55 #if defined (__CC_ARM) /* ARM Compiler */
switches 0:5c4d7b2438d3 56
switches 0:5c4d7b2438d3 57 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M || __TARGET_ARCH_7_A) && !defined(NO_EXCLUSIVE_ACCESS))
switches 0:5c4d7b2438d3 58 #define __USE_EXCLUSIVE_ACCESS
switches 0:5c4d7b2438d3 59 #else
switches 0:5c4d7b2438d3 60 #undef __USE_EXCLUSIVE_ACCESS
switches 0:5c4d7b2438d3 61 #endif
switches 0:5c4d7b2438d3 62
switches 0:5c4d7b2438d3 63 /* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
switches 0:5c4d7b2438d3 64 #ifdef __USE_EXCLUSIVE_ACCESS
switches 0:5c4d7b2438d3 65 #pragma diag_suppress 3731
switches 0:5c4d7b2438d3 66 #endif
switches 0:5c4d7b2438d3 67
switches 0:5c4d7b2438d3 68 #elif defined (__GNUC__) /* GNU Compiler */
switches 0:5c4d7b2438d3 69
switches 0:5c4d7b2438d3 70 #undef __USE_EXCLUSIVE_ACCESS
switches 0:5c4d7b2438d3 71
switches 0:5c4d7b2438d3 72 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
switches 0:5c4d7b2438d3 73 #define __TARGET_FPU_VFP 1
switches 0:5c4d7b2438d3 74 #else
switches 0:5c4d7b2438d3 75 #define __TARGET_FPU_VFP 0
switches 0:5c4d7b2438d3 76 #endif
switches 0:5c4d7b2438d3 77
switches 0:5c4d7b2438d3 78 #define __inline inline
switches 0:5c4d7b2438d3 79 #define __weak __attribute__((weak))
switches 0:5c4d7b2438d3 80
switches 0:5c4d7b2438d3 81 #elif defined (__ICCARM__) /* IAR Compiler */
switches 0:5c4d7b2438d3 82
switches 0:5c4d7b2438d3 83 #endif
switches 0:5c4d7b2438d3 84
switches 0:5c4d7b2438d3 85 static U8 priority = 0xff;
switches 0:5c4d7b2438d3 86
switches 0:5c4d7b2438d3 87 extern const U32 GICDistributor_BASE;
switches 0:5c4d7b2438d3 88 extern const U32 GICInterface_BASE;
switches 0:5c4d7b2438d3 89
switches 0:5c4d7b2438d3 90 /* GIC registers - Distributor */
switches 0:5c4d7b2438d3 91 #define GICD_ICDICER0 (*((volatile U32 *)(GICDistributor_BASE + 0x180))) /* - RW - Interrupt Clear-Enable Registers */
switches 0:5c4d7b2438d3 92 #define GICD_ICDISER0 (*((volatile U32 *)(GICDistributor_BASE + 0x100))) /* - RW - Interrupt Set-Enable Registers */
switches 0:5c4d7b2438d3 93 #define GICD_ICDIPR0 (*((volatile U32 *)(GICDistributor_BASE + 0x400))) /* - RW - Interrupt Priority Registers */
switches 0:5c4d7b2438d3 94 #define GICD_ICDSGIR (*((volatile U32 *)(GICDistributor_BASE + 0xf00))) /* - RW - Interrupt Software Interrupt Register */
switches 0:5c4d7b2438d3 95 #define GICD_ICDICERx(irq) *(volatile U32 *)(&GICD_ICDICER0 + irq/32)
switches 0:5c4d7b2438d3 96 #define GICD_ICDISERx(irq) *(volatile U32 *)(&GICD_ICDISER0 + irq/32)
switches 0:5c4d7b2438d3 97
switches 0:5c4d7b2438d3 98 /* GIC register - CPU Interface */
switches 0:5c4d7b2438d3 99 #define GICI_ICCPMR (*((volatile U32 *)(GICInterface_BASE + 0x004))) /* - RW - Interrupt Priority Mask Register */
switches 0:5c4d7b2438d3 100
switches 0:5c4d7b2438d3 101 #define SGI_PENDSV 0 /* SGI0 */
switches 0:5c4d7b2438d3 102 #define SGI_PENDSV_BIT ((U32)(1 << (SGI_PENDSV & 0xf)))
switches 0:5c4d7b2438d3 103
switches 0:5c4d7b2438d3 104 //Increase priority filter to prevent timer and PendSV interrupts signaling. Guarantees that interrupts will not be forwarded.
switches 0:5c4d7b2438d3 105 #if defined (__ICCARM__)
switches 0:5c4d7b2438d3 106 #define OS_LOCK() int irq_dis = __disable_irq_iar();\
switches 0:5c4d7b2438d3 107 priority = GICI_ICCPMR; \
switches 0:5c4d7b2438d3 108 GICI_ICCPMR = 0xff; \
switches 0:5c4d7b2438d3 109 GICI_ICCPMR = GICI_ICCPMR - 1; \
switches 0:5c4d7b2438d3 110 __DSB();\
switches 0:5c4d7b2438d3 111 if(!irq_dis) __enable_irq(); \
switches 0:5c4d7b2438d3 112
switches 0:5c4d7b2438d3 113 #else
switches 0:5c4d7b2438d3 114 #define OS_LOCK() int irq_dis = __disable_irq();\
switches 0:5c4d7b2438d3 115 priority = GICI_ICCPMR; \
switches 0:5c4d7b2438d3 116 GICI_ICCPMR = 0xff; \
switches 0:5c4d7b2438d3 117 GICI_ICCPMR = GICI_ICCPMR - 1; \
switches 0:5c4d7b2438d3 118 __DSB();\
switches 0:5c4d7b2438d3 119 if(!irq_dis) __enable_irq(); \
switches 0:5c4d7b2438d3 120
switches 0:5c4d7b2438d3 121 #endif
switches 0:5c4d7b2438d3 122
switches 0:5c4d7b2438d3 123 //Restore priority filter. Re-enable timer and PendSV signaling
switches 0:5c4d7b2438d3 124 #define OS_UNLOCK() __DSB(); \
switches 0:5c4d7b2438d3 125 GICI_ICCPMR = priority; \
switches 0:5c4d7b2438d3 126
switches 0:5c4d7b2438d3 127 #define OS_PEND_IRQ() GICD_ICDSGIR = 0x0010000 | SGI_PENDSV
switches 0:5c4d7b2438d3 128 #define OS_PEND(fl,p) if(p) OS_PEND_IRQ();
switches 0:5c4d7b2438d3 129 #define OS_UNPEND(fl)
switches 0:5c4d7b2438d3 130
switches 0:5c4d7b2438d3 131 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c-
switches 0:5c4d7b2438d3 132 * OS_X_INIT enables the IRQ n in the GIC */
switches 0:5c4d7b2438d3 133 #define OS_X_INIT(n) volatile char *reg; \
switches 0:5c4d7b2438d3 134 reg = (char *)(&GICD_ICDIPR0 + n / 4); \
switches 0:5c4d7b2438d3 135 reg += n % 4; \
switches 0:5c4d7b2438d3 136 *reg = (char)0xff; \
switches 0:5c4d7b2438d3 137 *reg = *reg - 1; \
switches 0:5c4d7b2438d3 138 GICD_ICDISERx(n) = (U32)(1 << n % 32);
switches 0:5c4d7b2438d3 139 #define OS_X_LOCK(n) OS_LOCK()
switches 0:5c4d7b2438d3 140 #define OS_X_UNLOCK(n) OS_UNLOCK()
switches 0:5c4d7b2438d3 141 #define OS_X_PEND_IRQ() OS_PEND_IRQ()
switches 0:5c4d7b2438d3 142 #define OS_X_PEND(fl,p) if(p) OS_X_PEND_IRQ();
switches 0:5c4d7b2438d3 143 #define OS_X_UNPEND(fl)
switches 0:5c4d7b2438d3 144
switches 0:5c4d7b2438d3 145
switches 0:5c4d7b2438d3 146 /* Functions */
switches 0:5c4d7b2438d3 147 #ifdef __USE_EXCLUSIVE_ACCESS
switches 0:5c4d7b2438d3 148 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
switches 0:5c4d7b2438d3 149 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
switches 0:5c4d7b2438d3 150 #else
switches 0:5c4d7b2438d3 151 #if defined (__ICCARM__)
switches 0:5c4d7b2438d3 152 #define rt_inc(p) { int irq_dis = __disable_irq_iar();(*p)++;if(!irq_dis) __enable_irq(); }
switches 0:5c4d7b2438d3 153 #define rt_dec(p) { int irq_dis = __disable_irq_iar();(*p)--;if(!irq_dis) __enable_irq(); }
switches 0:5c4d7b2438d3 154 #else
switches 0:5c4d7b2438d3 155 #define rt_inc(p) { int irq_dis = __disable_irq();(*p)++;if(!irq_dis) __enable_irq(); }
switches 0:5c4d7b2438d3 156 #define rt_dec(p) { int irq_dis = __disable_irq();(*p)--;if(!irq_dis) __enable_irq(); }
switches 0:5c4d7b2438d3 157 #endif /* __ICCARM__ */
switches 0:5c4d7b2438d3 158 #endif /* __USE_EXCLUSIVE_ACCESS */
switches 0:5c4d7b2438d3 159
switches 0:5c4d7b2438d3 160 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
switches 0:5c4d7b2438d3 161 U32 cnt,c2;
switches 0:5c4d7b2438d3 162 #ifdef __USE_EXCLUSIVE_ACCESS
switches 0:5c4d7b2438d3 163 do {
switches 0:5c4d7b2438d3 164 if ((cnt = __ldrex(count)) == size) {
switches 0:5c4d7b2438d3 165 __clrex();
switches 0:5c4d7b2438d3 166 return (cnt); }
switches 0:5c4d7b2438d3 167 } while (__strex(cnt+1, count));
switches 0:5c4d7b2438d3 168 do {
switches 0:5c4d7b2438d3 169 c2 = (cnt = __ldrex(first)) + 1;
switches 0:5c4d7b2438d3 170 if (c2 == size) c2 = 0;
switches 0:5c4d7b2438d3 171 } while (__strex(c2, first));
switches 0:5c4d7b2438d3 172 #else
switches 0:5c4d7b2438d3 173 int irq_dis;
switches 0:5c4d7b2438d3 174 #if defined (__ICCARM__)
switches 0:5c4d7b2438d3 175 irq_dis = __disable_irq_iar();
switches 0:5c4d7b2438d3 176 #else
switches 0:5c4d7b2438d3 177 irq_dis = __disable_irq();
switches 0:5c4d7b2438d3 178 #endif /* __ICCARM__ */
switches 0:5c4d7b2438d3 179 if ((cnt = *count) < size) {
switches 0:5c4d7b2438d3 180 *count = cnt+1;
switches 0:5c4d7b2438d3 181 c2 = (cnt = *first) + 1;
switches 0:5c4d7b2438d3 182 if (c2 == size) c2 = 0;
switches 0:5c4d7b2438d3 183 *first = c2;
switches 0:5c4d7b2438d3 184 }
switches 0:5c4d7b2438d3 185 if(!irq_dis) __enable_irq ();
switches 0:5c4d7b2438d3 186 #endif
switches 0:5c4d7b2438d3 187 return (cnt);
switches 0:5c4d7b2438d3 188 }
switches 0:5c4d7b2438d3 189
switches 0:5c4d7b2438d3 190 __inline static void rt_systick_init (void) {
switches 0:5c4d7b2438d3 191 /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
switches 0:5c4d7b2438d3 192 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
switches 0:5c4d7b2438d3 193 }
switches 0:5c4d7b2438d3 194
switches 0:5c4d7b2438d3 195 __inline static U32 rt_systick_val (void) {
switches 0:5c4d7b2438d3 196 /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
switches 0:5c4d7b2438d3 197 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
switches 0:5c4d7b2438d3 198 return 0;
switches 0:5c4d7b2438d3 199 }
switches 0:5c4d7b2438d3 200
switches 0:5c4d7b2438d3 201 __inline static U32 rt_systick_ovf (void) {
switches 0:5c4d7b2438d3 202 /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
switches 0:5c4d7b2438d3 203 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
switches 0:5c4d7b2438d3 204 return 0;
switches 0:5c4d7b2438d3 205 }
switches 0:5c4d7b2438d3 206
switches 0:5c4d7b2438d3 207 __inline static void rt_svc_init (void) {
switches 0:5c4d7b2438d3 208 /* Register pendSV - through SGI */
switches 0:5c4d7b2438d3 209 volatile char *reg;
switches 0:5c4d7b2438d3 210
switches 0:5c4d7b2438d3 211 reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4);
switches 0:5c4d7b2438d3 212 reg += SGI_PENDSV % 4;
switches 0:5c4d7b2438d3 213 /* Write 0xff to read priority level */
switches 0:5c4d7b2438d3 214 *reg = (char)0xff;
switches 0:5c4d7b2438d3 215 /* Read priority level and set the lowest possible*/
switches 0:5c4d7b2438d3 216 *reg = *reg - 1;
switches 0:5c4d7b2438d3 217
switches 0:5c4d7b2438d3 218 GICD_ICDISERx(SGI_PENDSV) = (U32)SGI_PENDSV_BIT;
switches 0:5c4d7b2438d3 219 }
switches 0:5c4d7b2438d3 220
switches 0:5c4d7b2438d3 221 extern void rt_set_PSP (U32 stack);
switches 0:5c4d7b2438d3 222 extern U32 rt_get_PSP (void);
switches 0:5c4d7b2438d3 223 extern void os_set_env (P_TCB p_TCB);
switches 0:5c4d7b2438d3 224 extern void *_alloc_box (void *box_mem);
switches 0:5c4d7b2438d3 225 extern int _free_box (void *box_mem, void *box);
switches 0:5c4d7b2438d3 226
switches 0:5c4d7b2438d3 227 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
switches 0:5c4d7b2438d3 228 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
switches 0:5c4d7b2438d3 229 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
switches 0:5c4d7b2438d3 230
switches 0:5c4d7b2438d3 231 extern void dbg_init (void);
switches 0:5c4d7b2438d3 232 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
switches 0:5c4d7b2438d3 233 extern void dbg_task_switch (U32 task_id);
switches 0:5c4d7b2438d3 234
switches 0:5c4d7b2438d3 235 #define DBG_INIT()
switches 0:5c4d7b2438d3 236 #define DBG_TASK_NOTIFY(p_tcb,create)
switches 0:5c4d7b2438d3 237 #define DBG_TASK_SWITCH(task_id)
switches 0:5c4d7b2438d3 238
switches 0:5c4d7b2438d3 239 /*----------------------------------------------------------------------------
switches 0:5c4d7b2438d3 240 * end of file
switches 0:5c4d7b2438d3 241 *---------------------------------------------------------------------------*/
switches 0:5c4d7b2438d3 242