Greg Steiert / pegasus_dev

Development mbed library for MAX32630FTHR

Dependents:   blinky_max32630fthr

cmsis/core_cmInstr.h@3:1198227e6421, 2016-12-16 (annotated)

Committer:
switches
Date:
Fri Dec 16 16:27:57 2016 +0000
Revision:
3:1198227e6421
Parent:
0:5c4d7b2438d3 
Changed ADC scale for MAX32625 platforms to 1.2V full scale to match MAX32630 platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 /**************************************************************************//**
switches 0:5c4d7b2438d3 2 * @file core_cmInstr.h
switches 0:5c4d7b2438d3 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
switches 0:5c4d7b2438d3 4 * @version V4.10
switches 0:5c4d7b2438d3 5 * @date 18. March 2015
switches 0:5c4d7b2438d3 6 *
switches 0:5c4d7b2438d3 7 * @note
switches 0:5c4d7b2438d3 8 *
switches 0:5c4d7b2438d3 9 ******************************************************************************/
switches 0:5c4d7b2438d3 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
switches 0:5c4d7b2438d3 11
switches 0:5c4d7b2438d3 12 All rights reserved.
switches 0:5c4d7b2438d3 13 Redistribution and use in source and binary forms, with or without
switches 0:5c4d7b2438d3 14 modification, are permitted provided that the following conditions are met:
switches 0:5c4d7b2438d3 15 - Redistributions of source code must retain the above copyright
switches 0:5c4d7b2438d3 16 notice, this list of conditions and the following disclaimer.
switches 0:5c4d7b2438d3 17 - Redistributions in binary form must reproduce the above copyright
switches 0:5c4d7b2438d3 18 notice, this list of conditions and the following disclaimer in the
switches 0:5c4d7b2438d3 19 documentation and/or other materials provided with the distribution.
switches 0:5c4d7b2438d3 20 - Neither the name of ARM nor the names of its contributors may be used
switches 0:5c4d7b2438d3 21 to endorse or promote products derived from this software without
switches 0:5c4d7b2438d3 22 specific prior written permission.
switches 0:5c4d7b2438d3 23 *
switches 0:5c4d7b2438d3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
switches 0:5c4d7b2438d3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
switches 0:5c4d7b2438d3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
switches 0:5c4d7b2438d3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
switches 0:5c4d7b2438d3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
switches 0:5c4d7b2438d3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
switches 0:5c4d7b2438d3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
switches 0:5c4d7b2438d3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
switches 0:5c4d7b2438d3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
switches 0:5c4d7b2438d3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
switches 0:5c4d7b2438d3 34 POSSIBILITY OF SUCH DAMAGE.
switches 0:5c4d7b2438d3 35 ---------------------------------------------------------------------------*/
switches 0:5c4d7b2438d3 36
switches 0:5c4d7b2438d3 37
switches 0:5c4d7b2438d3 38 #ifndef __CORE_CMINSTR_H
switches 0:5c4d7b2438d3 39 #define __CORE_CMINSTR_H
switches 0:5c4d7b2438d3 40
switches 0:5c4d7b2438d3 41
switches 0:5c4d7b2438d3 42 /* ########################## Core Instruction Access ######################### */
switches 0:5c4d7b2438d3 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
switches 0:5c4d7b2438d3 44 Access to dedicated instructions
switches 0:5c4d7b2438d3 45 @{
switches 0:5c4d7b2438d3 46 */
switches 0:5c4d7b2438d3 47
switches 0:5c4d7b2438d3 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
switches 0:5c4d7b2438d3 49 /* ARM armcc specific functions */
switches 0:5c4d7b2438d3 50
switches 0:5c4d7b2438d3 51 #if (__ARMCC_VERSION < 400677)
switches 0:5c4d7b2438d3 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
switches 0:5c4d7b2438d3 53 #endif
switches 0:5c4d7b2438d3 54
switches 0:5c4d7b2438d3 55
switches 0:5c4d7b2438d3 56 /** \brief No Operation
switches 0:5c4d7b2438d3 57
switches 0:5c4d7b2438d3 58 No Operation does nothing. This instruction can be used for code alignment purposes.
switches 0:5c4d7b2438d3 59 */
switches 0:5c4d7b2438d3 60 #define __NOP __nop
switches 0:5c4d7b2438d3 61
switches 0:5c4d7b2438d3 62
switches 0:5c4d7b2438d3 63 /** \brief Wait For Interrupt
switches 0:5c4d7b2438d3 64
switches 0:5c4d7b2438d3 65 Wait For Interrupt is a hint instruction that suspends execution
switches 0:5c4d7b2438d3 66 until one of a number of events occurs.
switches 0:5c4d7b2438d3 67 */
switches 0:5c4d7b2438d3 68 #define __WFI __wfi
switches 0:5c4d7b2438d3 69
switches 0:5c4d7b2438d3 70
switches 0:5c4d7b2438d3 71 /** \brief Wait For Event
switches 0:5c4d7b2438d3 72
switches 0:5c4d7b2438d3 73 Wait For Event is a hint instruction that permits the processor to enter
switches 0:5c4d7b2438d3 74 a low-power state until one of a number of events occurs.
switches 0:5c4d7b2438d3 75 */
switches 0:5c4d7b2438d3 76 #define __WFE __wfe
switches 0:5c4d7b2438d3 77
switches 0:5c4d7b2438d3 78
switches 0:5c4d7b2438d3 79 /** \brief Send Event
switches 0:5c4d7b2438d3 80
switches 0:5c4d7b2438d3 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
switches 0:5c4d7b2438d3 82 */
switches 0:5c4d7b2438d3 83 #define __SEV __sev
switches 0:5c4d7b2438d3 84
switches 0:5c4d7b2438d3 85
switches 0:5c4d7b2438d3 86 /** \brief Instruction Synchronization Barrier
switches 0:5c4d7b2438d3 87
switches 0:5c4d7b2438d3 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
switches 0:5c4d7b2438d3 89 so that all instructions following the ISB are fetched from cache or
switches 0:5c4d7b2438d3 90 memory, after the instruction has been completed.
switches 0:5c4d7b2438d3 91 */
switches 0:5c4d7b2438d3 92 #define __ISB() do {\
switches 0:5c4d7b2438d3 93 __schedule_barrier();\
switches 0:5c4d7b2438d3 94 __isb(0xF);\
switches 0:5c4d7b2438d3 95 __schedule_barrier();\
switches 0:5c4d7b2438d3 96 } while (0)
switches 0:5c4d7b2438d3 97
switches 0:5c4d7b2438d3 98 /** \brief Data Synchronization Barrier
switches 0:5c4d7b2438d3 99
switches 0:5c4d7b2438d3 100 This function acts as a special kind of Data Memory Barrier.
switches 0:5c4d7b2438d3 101 It completes when all explicit memory accesses before this instruction complete.
switches 0:5c4d7b2438d3 102 */
switches 0:5c4d7b2438d3 103 #define __DSB() do {\
switches 0:5c4d7b2438d3 104 __schedule_barrier();\
switches 0:5c4d7b2438d3 105 __dsb(0xF);\
switches 0:5c4d7b2438d3 106 __schedule_barrier();\
switches 0:5c4d7b2438d3 107 } while (0)
switches 0:5c4d7b2438d3 108
switches 0:5c4d7b2438d3 109 /** \brief Data Memory Barrier
switches 0:5c4d7b2438d3 110
switches 0:5c4d7b2438d3 111 This function ensures the apparent order of the explicit memory operations before
switches 0:5c4d7b2438d3 112 and after the instruction, without ensuring their completion.
switches 0:5c4d7b2438d3 113 */
switches 0:5c4d7b2438d3 114 #define __DMB() do {\
switches 0:5c4d7b2438d3 115 __schedule_barrier();\
switches 0:5c4d7b2438d3 116 __dmb(0xF);\
switches 0:5c4d7b2438d3 117 __schedule_barrier();\
switches 0:5c4d7b2438d3 118 } while (0)
switches 0:5c4d7b2438d3 119
switches 0:5c4d7b2438d3 120 /** \brief Reverse byte order (32 bit)
switches 0:5c4d7b2438d3 121
switches 0:5c4d7b2438d3 122 This function reverses the byte order in integer value.
switches 0:5c4d7b2438d3 123
switches 0:5c4d7b2438d3 124 \param [in] value Value to reverse
switches 0:5c4d7b2438d3 125 \return Reversed value
switches 0:5c4d7b2438d3 126 */
switches 0:5c4d7b2438d3 127 #define __REV __rev
switches 0:5c4d7b2438d3 128
switches 0:5c4d7b2438d3 129
switches 0:5c4d7b2438d3 130 /** \brief Reverse byte order (16 bit)
switches 0:5c4d7b2438d3 131
switches 0:5c4d7b2438d3 132 This function reverses the byte order in two unsigned short values.
switches 0:5c4d7b2438d3 133
switches 0:5c4d7b2438d3 134 \param [in] value Value to reverse
switches 0:5c4d7b2438d3 135 \return Reversed value
switches 0:5c4d7b2438d3 136 */
switches 0:5c4d7b2438d3 137 #ifndef __NO_EMBEDDED_ASM
switches 0:5c4d7b2438d3 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
switches 0:5c4d7b2438d3 139 {
switches 0:5c4d7b2438d3 140 rev16 r0, r0
switches 0:5c4d7b2438d3 141 bx lr
switches 0:5c4d7b2438d3 142 }
switches 0:5c4d7b2438d3 143 #endif
switches 0:5c4d7b2438d3 144
switches 0:5c4d7b2438d3 145 /** \brief Reverse byte order in signed short value
switches 0:5c4d7b2438d3 146
switches 0:5c4d7b2438d3 147 This function reverses the byte order in a signed short value with sign extension to integer.
switches 0:5c4d7b2438d3 148
switches 0:5c4d7b2438d3 149 \param [in] value Value to reverse
switches 0:5c4d7b2438d3 150 \return Reversed value
switches 0:5c4d7b2438d3 151 */
switches 0:5c4d7b2438d3 152 #ifndef __NO_EMBEDDED_ASM
switches 0:5c4d7b2438d3 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
switches 0:5c4d7b2438d3 154 {
switches 0:5c4d7b2438d3 155 revsh r0, r0
switches 0:5c4d7b2438d3 156 bx lr
switches 0:5c4d7b2438d3 157 }
switches 0:5c4d7b2438d3 158 #endif
switches 0:5c4d7b2438d3 159
switches 0:5c4d7b2438d3 160
switches 0:5c4d7b2438d3 161 /** \brief Rotate Right in unsigned value (32 bit)
switches 0:5c4d7b2438d3 162
switches 0:5c4d7b2438d3 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
switches 0:5c4d7b2438d3 164
switches 0:5c4d7b2438d3 165 \param [in] value Value to rotate
switches 0:5c4d7b2438d3 166 \param [in] value Number of Bits to rotate
switches 0:5c4d7b2438d3 167 \return Rotated value
switches 0:5c4d7b2438d3 168 */
switches 0:5c4d7b2438d3 169 #define __ROR __ror
switches 0:5c4d7b2438d3 170
switches 0:5c4d7b2438d3 171
switches 0:5c4d7b2438d3 172 /** \brief Breakpoint
switches 0:5c4d7b2438d3 173
switches 0:5c4d7b2438d3 174 This function causes the processor to enter Debug state.
switches 0:5c4d7b2438d3 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
switches 0:5c4d7b2438d3 176
switches 0:5c4d7b2438d3 177 \param [in] value is ignored by the processor.
switches 0:5c4d7b2438d3 178 If required, a debugger can use it to store additional information about the breakpoint.
switches 0:5c4d7b2438d3 179 */
switches 0:5c4d7b2438d3 180 #define __BKPT(value) __breakpoint(value)
switches 0:5c4d7b2438d3 181
switches 0:5c4d7b2438d3 182
switches 0:5c4d7b2438d3 183 /** \brief Reverse bit order of value
switches 0:5c4d7b2438d3 184
switches 0:5c4d7b2438d3 185 This function reverses the bit order of the given value.
switches 0:5c4d7b2438d3 186
switches 0:5c4d7b2438d3 187 \param [in] value Value to reverse
switches 0:5c4d7b2438d3 188 \return Reversed value
switches 0:5c4d7b2438d3 189 */
switches 0:5c4d7b2438d3 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
switches 0:5c4d7b2438d3 191 #define __RBIT __rbit
switches 0:5c4d7b2438d3 192 #else
switches 0:5c4d7b2438d3 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
switches 0:5c4d7b2438d3 194 {
switches 0:5c4d7b2438d3 195 uint32_t result;
switches 0:5c4d7b2438d3 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
switches 0:5c4d7b2438d3 197
switches 0:5c4d7b2438d3 198 result = value; // r will be reversed bits of v; first get LSB of v
switches 0:5c4d7b2438d3 199 for (value >>= 1; value; value >>= 1)
switches 0:5c4d7b2438d3 200 {
switches 0:5c4d7b2438d3 201 result <<= 1;
switches 0:5c4d7b2438d3 202 result |= value & 1;
switches 0:5c4d7b2438d3 203 s--;
switches 0:5c4d7b2438d3 204 }
switches 0:5c4d7b2438d3 205 result <<= s; // shift when v's highest bits are zero
switches 0:5c4d7b2438d3 206 return(result);
switches 0:5c4d7b2438d3 207 }
switches 0:5c4d7b2438d3 208 #endif
switches 0:5c4d7b2438d3 209
switches 0:5c4d7b2438d3 210
switches 0:5c4d7b2438d3 211 /** \brief Count leading zeros
switches 0:5c4d7b2438d3 212
switches 0:5c4d7b2438d3 213 This function counts the number of leading zeros of a data value.
switches 0:5c4d7b2438d3 214
switches 0:5c4d7b2438d3 215 \param [in] value Value to count the leading zeros
switches 0:5c4d7b2438d3 216 \return number of leading zeros in value
switches 0:5c4d7b2438d3 217 */
switches 0:5c4d7b2438d3 218 #define __CLZ __clz
switches 0:5c4d7b2438d3 219
switches 0:5c4d7b2438d3 220
switches 0:5c4d7b2438d3 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
switches 0:5c4d7b2438d3 222
switches 0:5c4d7b2438d3 223 /** \brief LDR Exclusive (8 bit)
switches 0:5c4d7b2438d3 224
switches 0:5c4d7b2438d3 225 This function executes a exclusive LDR instruction for 8 bit value.
switches 0:5c4d7b2438d3 226
switches 0:5c4d7b2438d3 227 \param [in] ptr Pointer to data
switches 0:5c4d7b2438d3 228 \return value of type uint8_t at (*ptr)
switches 0:5c4d7b2438d3 229 */
switches 0:5c4d7b2438d3 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
switches 0:5c4d7b2438d3 231
switches 0:5c4d7b2438d3 232
switches 0:5c4d7b2438d3 233 /** \brief LDR Exclusive (16 bit)
switches 0:5c4d7b2438d3 234
switches 0:5c4d7b2438d3 235 This function executes a exclusive LDR instruction for 16 bit values.
switches 0:5c4d7b2438d3 236
switches 0:5c4d7b2438d3 237 \param [in] ptr Pointer to data
switches 0:5c4d7b2438d3 238 \return value of type uint16_t at (*ptr)
switches 0:5c4d7b2438d3 239 */
switches 0:5c4d7b2438d3 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
switches 0:5c4d7b2438d3 241
switches 0:5c4d7b2438d3 242
switches 0:5c4d7b2438d3 243 /** \brief LDR Exclusive (32 bit)
switches 0:5c4d7b2438d3 244
switches 0:5c4d7b2438d3 245 This function executes a exclusive LDR instruction for 32 bit values.
switches 0:5c4d7b2438d3 246
switches 0:5c4d7b2438d3 247 \param [in] ptr Pointer to data
switches 0:5c4d7b2438d3 248 \return value of type uint32_t at (*ptr)
switches 0:5c4d7b2438d3 249 */
switches 0:5c4d7b2438d3 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
switches 0:5c4d7b2438d3 251
switches 0:5c4d7b2438d3 252
switches 0:5c4d7b2438d3 253 /** \brief STR Exclusive (8 bit)
switches 0:5c4d7b2438d3 254
switches 0:5c4d7b2438d3 255 This function executes a exclusive STR instruction for 8 bit values.
switches 0:5c4d7b2438d3 256
switches 0:5c4d7b2438d3 257 \param [in] value Value to store
switches 0:5c4d7b2438d3 258 \param [in] ptr Pointer to location
switches 0:5c4d7b2438d3 259 \return 0 Function succeeded
switches 0:5c4d7b2438d3 260 \return 1 Function failed
switches 0:5c4d7b2438d3 261 */
switches 0:5c4d7b2438d3 262 #define __STREXB(value, ptr) __strex(value, ptr)
switches 0:5c4d7b2438d3 263
switches 0:5c4d7b2438d3 264
switches 0:5c4d7b2438d3 265 /** \brief STR Exclusive (16 bit)
switches 0:5c4d7b2438d3 266
switches 0:5c4d7b2438d3 267 This function executes a exclusive STR instruction for 16 bit values.
switches 0:5c4d7b2438d3 268
switches 0:5c4d7b2438d3 269 \param [in] value Value to store
switches 0:5c4d7b2438d3 270 \param [in] ptr Pointer to location
switches 0:5c4d7b2438d3 271 \return 0 Function succeeded
switches 0:5c4d7b2438d3 272 \return 1 Function failed
switches 0:5c4d7b2438d3 273 */
switches 0:5c4d7b2438d3 274 #define __STREXH(value, ptr) __strex(value, ptr)
switches 0:5c4d7b2438d3 275
switches 0:5c4d7b2438d3 276
switches 0:5c4d7b2438d3 277 /** \brief STR Exclusive (32 bit)
switches 0:5c4d7b2438d3 278
switches 0:5c4d7b2438d3 279 This function executes a exclusive STR instruction for 32 bit values.
switches 0:5c4d7b2438d3 280
switches 0:5c4d7b2438d3 281 \param [in] value Value to store
switches 0:5c4d7b2438d3 282 \param [in] ptr Pointer to location
switches 0:5c4d7b2438d3 283 \return 0 Function succeeded
switches 0:5c4d7b2438d3 284 \return 1 Function failed
switches 0:5c4d7b2438d3 285 */
switches 0:5c4d7b2438d3 286 #define __STREXW(value, ptr) __strex(value, ptr)
switches 0:5c4d7b2438d3 287
switches 0:5c4d7b2438d3 288
switches 0:5c4d7b2438d3 289 /** \brief Remove the exclusive lock
switches 0:5c4d7b2438d3 290
switches 0:5c4d7b2438d3 291 This function removes the exclusive lock which is created by LDREX.
switches 0:5c4d7b2438d3 292
switches 0:5c4d7b2438d3 293 */
switches 0:5c4d7b2438d3 294 #define __CLREX __clrex
switches 0:5c4d7b2438d3 295
switches 0:5c4d7b2438d3 296
switches 0:5c4d7b2438d3 297 /** \brief Signed Saturate
switches 0:5c4d7b2438d3 298
switches 0:5c4d7b2438d3 299 This function saturates a signed value.
switches 0:5c4d7b2438d3 300
switches 0:5c4d7b2438d3 301 \param [in] value Value to be saturated
switches 0:5c4d7b2438d3 302 \param [in] sat Bit position to saturate to (1..32)
switches 0:5c4d7b2438d3 303 \return Saturated value
switches 0:5c4d7b2438d3 304 */
switches 0:5c4d7b2438d3 305 #define __SSAT __ssat
switches 0:5c4d7b2438d3 306
switches 0:5c4d7b2438d3 307
switches 0:5c4d7b2438d3 308 /** \brief Unsigned Saturate
switches 0:5c4d7b2438d3 309
switches 0:5c4d7b2438d3 310 This function saturates an unsigned value.
switches 0:5c4d7b2438d3 311
switches 0:5c4d7b2438d3 312 \param [in] value Value to be saturated
switches 0:5c4d7b2438d3 313 \param [in] sat Bit position to saturate to (0..31)
switches 0:5c4d7b2438d3 314 \return Saturated value
switches 0:5c4d7b2438d3 315 */
switches 0:5c4d7b2438d3 316 #define __USAT __usat
switches 0:5c4d7b2438d3 317
switches 0:5c4d7b2438d3 318
switches 0:5c4d7b2438d3 319 /** \brief Rotate Right with Extend (32 bit)
switches 0:5c4d7b2438d3 320
switches 0:5c4d7b2438d3 321 This function moves each bit of a bitstring right by one bit.
switches 0:5c4d7b2438d3 322 The carry input is shifted in at the left end of the bitstring.
switches 0:5c4d7b2438d3 323
switches 0:5c4d7b2438d3 324 \param [in] value Value to rotate
switches 0:5c4d7b2438d3 325 \return Rotated value
switches 0:5c4d7b2438d3 326 */
switches 0:5c4d7b2438d3 327 #ifndef __NO_EMBEDDED_ASM
switches 0:5c4d7b2438d3 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
switches 0:5c4d7b2438d3 329 {
switches 0:5c4d7b2438d3 330 rrx r0, r0
switches 0:5c4d7b2438d3 331 bx lr
switches 0:5c4d7b2438d3 332 }
switches 0:5c4d7b2438d3 333 #endif
switches 0:5c4d7b2438d3 334
switches 0:5c4d7b2438d3 335
switches 0:5c4d7b2438d3 336 /** \brief LDRT Unprivileged (8 bit)
switches 0:5c4d7b2438d3 337
switches 0:5c4d7b2438d3 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
switches 0:5c4d7b2438d3 339
switches 0:5c4d7b2438d3 340 \param [in] ptr Pointer to data
switches 0:5c4d7b2438d3 341 \return value of type uint8_t at (*ptr)
switches 0:5c4d7b2438d3 342 */
switches 0:5c4d7b2438d3 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
switches 0:5c4d7b2438d3 344
switches 0:5c4d7b2438d3 345
switches 0:5c4d7b2438d3 346 /** \brief LDRT Unprivileged (16 bit)
switches 0:5c4d7b2438d3 347
switches 0:5c4d7b2438d3 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
switches 0:5c4d7b2438d3 349
switches 0:5c4d7b2438d3 350 \param [in] ptr Pointer to data
switches 0:5c4d7b2438d3 351 \return value of type uint16_t at (*ptr)
switches 0:5c4d7b2438d3 352 */
switches 0:5c4d7b2438d3 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
switches 0:5c4d7b2438d3 354
switches 0:5c4d7b2438d3 355
switches 0:5c4d7b2438d3 356 /** \brief LDRT Unprivileged (32 bit)
switches 0:5c4d7b2438d3 357
switches 0:5c4d7b2438d3 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
switches 0:5c4d7b2438d3 359
switches 0:5c4d7b2438d3 360 \param [in] ptr Pointer to data
switches 0:5c4d7b2438d3 361 \return value of type uint32_t at (*ptr)
switches 0:5c4d7b2438d3 362 */
switches 0:5c4d7b2438d3 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
switches 0:5c4d7b2438d3 364
switches 0:5c4d7b2438d3 365
switches 0:5c4d7b2438d3 366 /** \brief STRT Unprivileged (8 bit)
switches 0:5c4d7b2438d3 367
switches 0:5c4d7b2438d3 368 This function executes a Unprivileged STRT instruction for 8 bit values.
switches 0:5c4d7b2438d3 369
switches 0:5c4d7b2438d3 370 \param [in] value Value to store
switches 0:5c4d7b2438d3 371 \param [in] ptr Pointer to location
switches 0:5c4d7b2438d3 372 */
switches 0:5c4d7b2438d3 373 #define __STRBT(value, ptr) __strt(value, ptr)
switches 0:5c4d7b2438d3 374
switches 0:5c4d7b2438d3 375
switches 0:5c4d7b2438d3 376 /** \brief STRT Unprivileged (16 bit)
switches 0:5c4d7b2438d3 377
switches 0:5c4d7b2438d3 378 This function executes a Unprivileged STRT instruction for 16 bit values.
switches 0:5c4d7b2438d3 379
switches 0:5c4d7b2438d3 380 \param [in] value Value to store
switches 0:5c4d7b2438d3 381 \param [in] ptr Pointer to location
switches 0:5c4d7b2438d3 382 */
switches 0:5c4d7b2438d3 383 #define __STRHT(value, ptr) __strt(value, ptr)
switches 0:5c4d7b2438d3 384
switches 0:5c4d7b2438d3 385
switches 0:5c4d7b2438d3 386 /** \brief STRT Unprivileged (32 bit)
switches 0:5c4d7b2438d3 387
switches 0:5c4d7b2438d3 388 This function executes a Unprivileged STRT instruction for 32 bit values.
switches 0:5c4d7b2438d3 389
switches 0:5c4d7b2438d3 390 \param [in] value Value to store
switches 0:5c4d7b2438d3 391 \param [in] ptr Pointer to location
switches 0:5c4d7b2438d3 392 */
switches 0:5c4d7b2438d3 393 #define __STRT(value, ptr) __strt(value, ptr)
switches 0:5c4d7b2438d3 394
switches 0:5c4d7b2438d3 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
switches 0:5c4d7b2438d3 396
switches 0:5c4d7b2438d3 397
switches 0:5c4d7b2438d3 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
switches 0:5c4d7b2438d3 399 /* GNU gcc specific functions */
switches 0:5c4d7b2438d3 400
switches 0:5c4d7b2438d3 401 /* Define macros for porting to both thumb1 and thumb2.
switches 0:5c4d7b2438d3 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
switches 0:5c4d7b2438d3 403 * Otherwise, use general registers, specified by constrant "r" */
switches 0:5c4d7b2438d3 404 #if defined (__thumb__) && !defined (__thumb2__)
switches 0:5c4d7b2438d3 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
switches 0:5c4d7b2438d3 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
switches 0:5c4d7b2438d3 407 #else
switches 0:5c4d7b2438d3 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
switches 0:5c4d7b2438d3 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
switches 0:5c4d7b2438d3 410 #endif
switches 0:5c4d7b2438d3 411
switches 0:5c4d7b2438d3 412 /** \brief No Operation
switches 0:5c4d7b2438d3 413
switches 0:5c4d7b2438d3 414 No Operation does nothing. This instruction can be used for code alignment purposes.
switches 0:5c4d7b2438d3 415 */
switches 0:5c4d7b2438d3 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
switches 0:5c4d7b2438d3 417 {
switches 0:5c4d7b2438d3 418 __ASM volatile ("nop");
switches 0:5c4d7b2438d3 419 }
switches 0:5c4d7b2438d3 420
switches 0:5c4d7b2438d3 421
switches 0:5c4d7b2438d3 422 /** \brief Wait For Interrupt
switches 0:5c4d7b2438d3 423
switches 0:5c4d7b2438d3 424 Wait For Interrupt is a hint instruction that suspends execution
switches 0:5c4d7b2438d3 425 until one of a number of events occurs.
switches 0:5c4d7b2438d3 426 */
switches 0:5c4d7b2438d3 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
switches 0:5c4d7b2438d3 428 {
switches 0:5c4d7b2438d3 429 __ASM volatile ("wfi");
switches 0:5c4d7b2438d3 430 }
switches 0:5c4d7b2438d3 431
switches 0:5c4d7b2438d3 432
switches 0:5c4d7b2438d3 433 /** \brief Wait For Event
switches 0:5c4d7b2438d3 434
switches 0:5c4d7b2438d3 435 Wait For Event is a hint instruction that permits the processor to enter
switches 0:5c4d7b2438d3 436 a low-power state until one of a number of events occurs.
switches 0:5c4d7b2438d3 437 */
switches 0:5c4d7b2438d3 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
switches 0:5c4d7b2438d3 439 {
switches 0:5c4d7b2438d3 440 __ASM volatile ("wfe");
switches 0:5c4d7b2438d3 441 }
switches 0:5c4d7b2438d3 442
switches 0:5c4d7b2438d3 443
switches 0:5c4d7b2438d3 444 /** \brief Send Event
switches 0:5c4d7b2438d3 445
switches 0:5c4d7b2438d3 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
switches 0:5c4d7b2438d3 447 */
switches 0:5c4d7b2438d3 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
switches 0:5c4d7b2438d3 449 {
switches 0:5c4d7b2438d3 450 __ASM volatile ("sev");
switches 0:5c4d7b2438d3 451 }
switches 0:5c4d7b2438d3 452
switches 0:5c4d7b2438d3 453
switches 0:5c4d7b2438d3 454 /** \brief Instruction Synchronization Barrier
switches 0:5c4d7b2438d3 455
switches 0:5c4d7b2438d3 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
switches 0:5c4d7b2438d3 457 so that all instructions following the ISB are fetched from cache or
switches 0:5c4d7b2438d3 458 memory, after the instruction has been completed.
switches 0:5c4d7b2438d3 459 */
switches 0:5c4d7b2438d3 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
switches 0:5c4d7b2438d3 461 {
switches 0:5c4d7b2438d3 462 __ASM volatile ("isb 0xF":::"memory");
switches 0:5c4d7b2438d3 463 }
switches 0:5c4d7b2438d3 464
switches 0:5c4d7b2438d3 465
switches 0:5c4d7b2438d3 466 /** \brief Data Synchronization Barrier
switches 0:5c4d7b2438d3 467
switches 0:5c4d7b2438d3 468 This function acts as a special kind of Data Memory Barrier.
switches 0:5c4d7b2438d3 469 It completes when all explicit memory accesses before this instruction complete.
switches 0:5c4d7b2438d3 470 */
switches 0:5c4d7b2438d3 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
switches 0:5c4d7b2438d3 472 {
switches 0:5c4d7b2438d3 473 __ASM volatile ("dsb 0xF":::"memory");
switches 0:5c4d7b2438d3 474 }
switches 0:5c4d7b2438d3 475
switches 0:5c4d7b2438d3 476
switches 0:5c4d7b2438d3 477 /** \brief Data Memory Barrier
switches 0:5c4d7b2438d3 478
switches 0:5c4d7b2438d3 479 This function ensures the apparent order of the explicit memory operations before
switches 0:5c4d7b2438d3 480 and after the instruction, without ensuring their completion.
switches 0:5c4d7b2438d3 481 */
switches 0:5c4d7b2438d3 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
switches 0:5c4d7b2438d3 483 {
switches 0:5c4d7b2438d3 484 __ASM volatile ("dmb 0xF":::"memory");
switches 0:5c4d7b2438d3 485 }
switches 0:5c4d7b2438d3 486
switches 0:5c4d7b2438d3 487
switches 0:5c4d7b2438d3 488 /** \brief Reverse byte order (32 bit)
switches 0:5c4d7b2438d3 489
switches 0:5c4d7b2438d3 490 This function reverses the byte order in integer value.
switches 0:5c4d7b2438d3 491
switches 0:5c4d7b2438d3 492 \param [in] value Value to reverse
switches 0:5c4d7b2438d3 493 \return Reversed value
switches 0:5c4d7b2438d3 494 */
switches 0:5c4d7b2438d3 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
switches 0:5c4d7b2438d3 496 {
switches 0:5c4d7b2438d3 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
switches 0:5c4d7b2438d3 498 return __builtin_bswap32(value);
switches 0:5c4d7b2438d3 499 #else
switches 0:5c4d7b2438d3 500 uint32_t result;
switches 0:5c4d7b2438d3 501
switches 0:5c4d7b2438d3 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
switches 0:5c4d7b2438d3 503 return(result);
switches 0:5c4d7b2438d3 504 #endif
switches 0:5c4d7b2438d3 505 }
switches 0:5c4d7b2438d3 506
switches 0:5c4d7b2438d3 507
switches 0:5c4d7b2438d3 508 /** \brief Reverse byte order (16 bit)
switches 0:5c4d7b2438d3 509
switches 0:5c4d7b2438d3 510 This function reverses the byte order in two unsigned short values.
switches 0:5c4d7b2438d3 511
switches 0:5c4d7b2438d3 512 \param [in] value Value to reverse
switches 0:5c4d7b2438d3 513 \return Reversed value
switches 0:5c4d7b2438d3 514 */
switches 0:5c4d7b2438d3 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
switches 0:5c4d7b2438d3 516 {
switches 0:5c4d7b2438d3 517 uint32_t result;
switches 0:5c4d7b2438d3 518
switches 0:5c4d7b2438d3 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
switches 0:5c4d7b2438d3 520 return(result);
switches 0:5c4d7b2438d3 521 }
switches 0:5c4d7b2438d3 522
switches 0:5c4d7b2438d3 523
switches 0:5c4d7b2438d3 524 /** \brief Reverse byte order in signed short value
switches 0:5c4d7b2438d3 525
switches 0:5c4d7b2438d3 526 This function reverses the byte order in a signed short value with sign extension to integer.
switches 0:5c4d7b2438d3 527
switches 0:5c4d7b2438d3 528 \param [in] value Value to reverse
switches 0:5c4d7b2438d3 529 \return Reversed value
switches 0:5c4d7b2438d3 530 */
switches 0:5c4d7b2438d3 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
switches 0:5c4d7b2438d3 532 {
switches 0:5c4d7b2438d3 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
switches 0:5c4d7b2438d3 534 return (short)__builtin_bswap16(value);
switches 0:5c4d7b2438d3 535 #else
switches 0:5c4d7b2438d3 536 uint32_t result;
switches 0:5c4d7b2438d3 537
switches 0:5c4d7b2438d3 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
switches 0:5c4d7b2438d3 539 return(result);
switches 0:5c4d7b2438d3 540 #endif
switches 0:5c4d7b2438d3 541 }
switches 0:5c4d7b2438d3 542
switches 0:5c4d7b2438d3 543
switches 0:5c4d7b2438d3 544 /** \brief Rotate Right in unsigned value (32 bit)
switches 0:5c4d7b2438d3 545
switches 0:5c4d7b2438d3 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
switches 0:5c4d7b2438d3 547
switches 0:5c4d7b2438d3 548 \param [in] value Value to rotate
switches 0:5c4d7b2438d3 549 \param [in] value Number of Bits to rotate
switches 0:5c4d7b2438d3 550 \return Rotated value
switches 0:5c4d7b2438d3 551 */
switches 0:5c4d7b2438d3 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
switches 0:5c4d7b2438d3 553 {
switches 0:5c4d7b2438d3 554 return (op1 >> op2) | (op1 << (32 - op2));
switches 0:5c4d7b2438d3 555 }
switches 0:5c4d7b2438d3 556
switches 0:5c4d7b2438d3 557
switches 0:5c4d7b2438d3 558 /** \brief Breakpoint
switches 0:5c4d7b2438d3 559
switches 0:5c4d7b2438d3 560 This function causes the processor to enter Debug state.
switches 0:5c4d7b2438d3 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
switches 0:5c4d7b2438d3 562
switches 0:5c4d7b2438d3 563 \param [in] value is ignored by the processor.
switches 0:5c4d7b2438d3 564 If required, a debugger can use it to store additional information about the breakpoint.
switches 0:5c4d7b2438d3 565 */
switches 0:5c4d7b2438d3 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
switches 0:5c4d7b2438d3 567
switches 0:5c4d7b2438d3 568
switches 0:5c4d7b2438d3 569 /** \brief Reverse bit order of value
switches 0:5c4d7b2438d3 570
switches 0:5c4d7b2438d3 571 This function reverses the bit order of the given value.
switches 0:5c4d7b2438d3 572
switches 0:5c4d7b2438d3 573 \param [in] value Value to reverse
switches 0:5c4d7b2438d3 574 \return Reversed value
switches 0:5c4d7b2438d3 575 */
switches 0:5c4d7b2438d3 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
switches 0:5c4d7b2438d3 577 {
switches 0:5c4d7b2438d3 578 uint32_t result;
switches 0:5c4d7b2438d3 579
switches 0:5c4d7b2438d3 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
switches 0:5c4d7b2438d3 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
switches 0:5c4d7b2438d3 582 #else
switches 0:5c4d7b2438d3 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
switches 0:5c4d7b2438d3 584
switches 0:5c4d7b2438d3 585 result = value; // r will be reversed bits of v; first get LSB of v
switches 0:5c4d7b2438d3 586 for (value >>= 1; value; value >>= 1)
switches 0:5c4d7b2438d3 587 {
switches 0:5c4d7b2438d3 588 result <<= 1;
switches 0:5c4d7b2438d3 589 result |= value & 1;
switches 0:5c4d7b2438d3 590 s--;
switches 0:5c4d7b2438d3 591 }
switches 0:5c4d7b2438d3 592 result <<= s; // shift when v's highest bits are zero
switches 0:5c4d7b2438d3 593 #endif
switches 0:5c4d7b2438d3 594 return(result);
switches 0:5c4d7b2438d3 595 }
switches 0:5c4d7b2438d3 596
switches 0:5c4d7b2438d3 597
switches 0:5c4d7b2438d3 598 /** \brief Count leading zeros
switches 0:5c4d7b2438d3 599
switches 0:5c4d7b2438d3 600 This function counts the number of leading zeros of a data value.
switches 0:5c4d7b2438d3 601
switches 0:5c4d7b2438d3 602 \param [in] value Value to count the leading zeros
switches 0:5c4d7b2438d3 603 \return number of leading zeros in value
switches 0:5c4d7b2438d3 604 */
switches 0:5c4d7b2438d3 605 #define __CLZ __builtin_clz
switches 0:5c4d7b2438d3 606
switches 0:5c4d7b2438d3 607
switches 0:5c4d7b2438d3 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
switches 0:5c4d7b2438d3 609
switches 0:5c4d7b2438d3 610 /** \brief LDR Exclusive (8 bit)
switches 0:5c4d7b2438d3 611
switches 0:5c4d7b2438d3 612 This function executes a exclusive LDR instruction for 8 bit value.
switches 0:5c4d7b2438d3 613
switches 0:5c4d7b2438d3 614 \param [in] ptr Pointer to data
switches 0:5c4d7b2438d3 615 \return value of type uint8_t at (*ptr)
switches 0:5c4d7b2438d3 616 */
switches 0:5c4d7b2438d3 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
switches 0:5c4d7b2438d3 618 {
switches 0:5c4d7b2438d3 619 uint32_t result;
switches 0:5c4d7b2438d3 620
switches 0:5c4d7b2438d3 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
switches 0:5c4d7b2438d3 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
switches 0:5c4d7b2438d3 623 #else
switches 0:5c4d7b2438d3 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
switches 0:5c4d7b2438d3 625 accepted by assembler. So has to use following less efficient pattern.
switches 0:5c4d7b2438d3 626 */
switches 0:5c4d7b2438d3 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
switches 0:5c4d7b2438d3 628 #endif
switches 0:5c4d7b2438d3 629 return ((uint8_t) result); /* Add explicit type cast here */
switches 0:5c4d7b2438d3 630 }
switches 0:5c4d7b2438d3 631
switches 0:5c4d7b2438d3 632
switches 0:5c4d7b2438d3 633 /** \brief LDR Exclusive (16 bit)
switches 0:5c4d7b2438d3 634
switches 0:5c4d7b2438d3 635 This function executes a exclusive LDR instruction for 16 bit values.
switches 0:5c4d7b2438d3 636
switches 0:5c4d7b2438d3 637 \param [in] ptr Pointer to data
switches 0:5c4d7b2438d3 638 \return value of type uint16_t at (*ptr)
switches 0:5c4d7b2438d3 639 */
switches 0:5c4d7b2438d3 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
switches 0:5c4d7b2438d3 641 {
switches 0:5c4d7b2438d3 642 uint32_t result;
switches 0:5c4d7b2438d3 643
switches 0:5c4d7b2438d3 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
switches 0:5c4d7b2438d3 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
switches 0:5c4d7b2438d3 646 #else
switches 0:5c4d7b2438d3 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
switches 0:5c4d7b2438d3 648 accepted by assembler. So has to use following less efficient pattern.
switches 0:5c4d7b2438d3 649 */
switches 0:5c4d7b2438d3 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
switches 0:5c4d7b2438d3 651 #endif
switches 0:5c4d7b2438d3 652 return ((uint16_t) result); /* Add explicit type cast here */
switches 0:5c4d7b2438d3 653 }
switches 0:5c4d7b2438d3 654
switches 0:5c4d7b2438d3 655
switches 0:5c4d7b2438d3 656 /** \brief LDR Exclusive (32 bit)
switches 0:5c4d7b2438d3 657
switches 0:5c4d7b2438d3 658 This function executes a exclusive LDR instruction for 32 bit values.
switches 0:5c4d7b2438d3 659
switches 0:5c4d7b2438d3 660 \param [in] ptr Pointer to data
switches 0:5c4d7b2438d3 661 \return value of type uint32_t at (*ptr)
switches 0:5c4d7b2438d3 662 */
switches 0:5c4d7b2438d3 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
switches 0:5c4d7b2438d3 664 {
switches 0:5c4d7b2438d3 665 uint32_t result;
switches 0:5c4d7b2438d3 666
switches 0:5c4d7b2438d3 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
switches 0:5c4d7b2438d3 668 return(result);
switches 0:5c4d7b2438d3 669 }
switches 0:5c4d7b2438d3 670
switches 0:5c4d7b2438d3 671
switches 0:5c4d7b2438d3 672 /** \brief STR Exclusive (8 bit)
switches 0:5c4d7b2438d3 673
switches 0:5c4d7b2438d3 674 This function executes a exclusive STR instruction for 8 bit values.
switches 0:5c4d7b2438d3 675
switches 0:5c4d7b2438d3 676 \param [in] value Value to store
switches 0:5c4d7b2438d3 677 \param [in] ptr Pointer to location
switches 0:5c4d7b2438d3 678 \return 0 Function succeeded
switches 0:5c4d7b2438d3 679 \return 1 Function failed
switches 0:5c4d7b2438d3 680 */
switches 0:5c4d7b2438d3 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
switches 0:5c4d7b2438d3 682 {
switches 0:5c4d7b2438d3 683 uint32_t result;
switches 0:5c4d7b2438d3 684
switches 0:5c4d7b2438d3 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
switches 0:5c4d7b2438d3 686 return(result);
switches 0:5c4d7b2438d3 687 }
switches 0:5c4d7b2438d3 688
switches 0:5c4d7b2438d3 689
switches 0:5c4d7b2438d3 690 /** \brief STR Exclusive (16 bit)
switches 0:5c4d7b2438d3 691
switches 0:5c4d7b2438d3 692 This function executes a exclusive STR instruction for 16 bit values.
switches 0:5c4d7b2438d3 693
switches 0:5c4d7b2438d3 694 \param [in] value Value to store
switches 0:5c4d7b2438d3 695 \param [in] ptr Pointer to location
switches 0:5c4d7b2438d3 696 \return 0 Function succeeded
switches 0:5c4d7b2438d3 697 \return 1 Function failed
switches 0:5c4d7b2438d3 698 */
switches 0:5c4d7b2438d3 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
switches 0:5c4d7b2438d3 700 {
switches 0:5c4d7b2438d3 701 uint32_t result;
switches 0:5c4d7b2438d3 702
switches 0:5c4d7b2438d3 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
switches 0:5c4d7b2438d3 704 return(result);
switches 0:5c4d7b2438d3 705 }
switches 0:5c4d7b2438d3 706
switches 0:5c4d7b2438d3 707
switches 0:5c4d7b2438d3 708 /** \brief STR Exclusive (32 bit)
switches 0:5c4d7b2438d3 709
switches 0:5c4d7b2438d3 710 This function executes a exclusive STR instruction for 32 bit values.
switches 0:5c4d7b2438d3 711
switches 0:5c4d7b2438d3 712 \param [in] value Value to store
switches 0:5c4d7b2438d3 713 \param [in] ptr Pointer to location
switches 0:5c4d7b2438d3 714 \return 0 Function succeeded
switches 0:5c4d7b2438d3 715 \return 1 Function failed
switches 0:5c4d7b2438d3 716 */
switches 0:5c4d7b2438d3 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
switches 0:5c4d7b2438d3 718 {
switches 0:5c4d7b2438d3 719 uint32_t result;
switches 0:5c4d7b2438d3 720
switches 0:5c4d7b2438d3 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
switches 0:5c4d7b2438d3 722 return(result);
switches 0:5c4d7b2438d3 723 }
switches 0:5c4d7b2438d3 724
switches 0:5c4d7b2438d3 725
switches 0:5c4d7b2438d3 726 /** \brief Remove the exclusive lock
switches 0:5c4d7b2438d3 727
switches 0:5c4d7b2438d3 728 This function removes the exclusive lock which is created by LDREX.
switches 0:5c4d7b2438d3 729
switches 0:5c4d7b2438d3 730 */
switches 0:5c4d7b2438d3 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
switches 0:5c4d7b2438d3 732 {
switches 0:5c4d7b2438d3 733 __ASM volatile ("clrex" ::: "memory");
switches 0:5c4d7b2438d3 734 }
switches 0:5c4d7b2438d3 735
switches 0:5c4d7b2438d3 736
switches 0:5c4d7b2438d3 737 /** \brief Signed Saturate
switches 0:5c4d7b2438d3 738
switches 0:5c4d7b2438d3 739 This function saturates a signed value.
switches 0:5c4d7b2438d3 740
switches 0:5c4d7b2438d3 741 \param [in] value Value to be saturated
switches 0:5c4d7b2438d3 742 \param [in] sat Bit position to saturate to (1..32)
switches 0:5c4d7b2438d3 743 \return Saturated value
switches 0:5c4d7b2438d3 744 */
switches 0:5c4d7b2438d3 745 #define __SSAT(ARG1,ARG2) \
switches 0:5c4d7b2438d3 746 ({ \
switches 0:5c4d7b2438d3 747 uint32_t __RES, __ARG1 = (ARG1); \
switches 0:5c4d7b2438d3 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
switches 0:5c4d7b2438d3 749 __RES; \
switches 0:5c4d7b2438d3 750 })
switches 0:5c4d7b2438d3 751
switches 0:5c4d7b2438d3 752
switches 0:5c4d7b2438d3 753 /** \brief Unsigned Saturate
switches 0:5c4d7b2438d3 754
switches 0:5c4d7b2438d3 755 This function saturates an unsigned value.
switches 0:5c4d7b2438d3 756
switches 0:5c4d7b2438d3 757 \param [in] value Value to be saturated
switches 0:5c4d7b2438d3 758 \param [in] sat Bit position to saturate to (0..31)
switches 0:5c4d7b2438d3 759 \return Saturated value
switches 0:5c4d7b2438d3 760 */
switches 0:5c4d7b2438d3 761 #define __USAT(ARG1,ARG2) \
switches 0:5c4d7b2438d3 762 ({ \
switches 0:5c4d7b2438d3 763 uint32_t __RES, __ARG1 = (ARG1); \
switches 0:5c4d7b2438d3 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
switches 0:5c4d7b2438d3 765 __RES; \
switches 0:5c4d7b2438d3 766 })
switches 0:5c4d7b2438d3 767
switches 0:5c4d7b2438d3 768
switches 0:5c4d7b2438d3 769 /** \brief Rotate Right with Extend (32 bit)
switches 0:5c4d7b2438d3 770
switches 0:5c4d7b2438d3 771 This function moves each bit of a bitstring right by one bit.
switches 0:5c4d7b2438d3 772 The carry input is shifted in at the left end of the bitstring.
switches 0:5c4d7b2438d3 773
switches 0:5c4d7b2438d3 774 \param [in] value Value to rotate
switches 0:5c4d7b2438d3 775 \return Rotated value
switches 0:5c4d7b2438d3 776 */
switches 0:5c4d7b2438d3 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
switches 0:5c4d7b2438d3 778 {
switches 0:5c4d7b2438d3 779 uint32_t result;
switches 0:5c4d7b2438d3 780
switches 0:5c4d7b2438d3 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
switches 0:5c4d7b2438d3 782 return(result);
switches 0:5c4d7b2438d3 783 }
switches 0:5c4d7b2438d3 784
switches 0:5c4d7b2438d3 785
switches 0:5c4d7b2438d3 786 /** \brief LDRT Unprivileged (8 bit)
switches 0:5c4d7b2438d3 787
switches 0:5c4d7b2438d3 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
switches 0:5c4d7b2438d3 789
switches 0:5c4d7b2438d3 790 \param [in] ptr Pointer to data
switches 0:5c4d7b2438d3 791 \return value of type uint8_t at (*ptr)
switches 0:5c4d7b2438d3 792 */
switches 0:5c4d7b2438d3 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
switches 0:5c4d7b2438d3 794 {
switches 0:5c4d7b2438d3 795 uint32_t result;
switches 0:5c4d7b2438d3 796
switches 0:5c4d7b2438d3 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
switches 0:5c4d7b2438d3 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
switches 0:5c4d7b2438d3 799 #else
switches 0:5c4d7b2438d3 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
switches 0:5c4d7b2438d3 801 accepted by assembler. So has to use following less efficient pattern.
switches 0:5c4d7b2438d3 802 */
switches 0:5c4d7b2438d3 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
switches 0:5c4d7b2438d3 804 #endif
switches 0:5c4d7b2438d3 805 return ((uint8_t) result); /* Add explicit type cast here */
switches 0:5c4d7b2438d3 806 }
switches 0:5c4d7b2438d3 807
switches 0:5c4d7b2438d3 808
switches 0:5c4d7b2438d3 809 /** \brief LDRT Unprivileged (16 bit)
switches 0:5c4d7b2438d3 810
switches 0:5c4d7b2438d3 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
switches 0:5c4d7b2438d3 812
switches 0:5c4d7b2438d3 813 \param [in] ptr Pointer to data
switches 0:5c4d7b2438d3 814 \return value of type uint16_t at (*ptr)
switches 0:5c4d7b2438d3 815 */
switches 0:5c4d7b2438d3 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
switches 0:5c4d7b2438d3 817 {
switches 0:5c4d7b2438d3 818 uint32_t result;
switches 0:5c4d7b2438d3 819
switches 0:5c4d7b2438d3 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
switches 0:5c4d7b2438d3 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
switches 0:5c4d7b2438d3 822 #else
switches 0:5c4d7b2438d3 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
switches 0:5c4d7b2438d3 824 accepted by assembler. So has to use following less efficient pattern.
switches 0:5c4d7b2438d3 825 */
switches 0:5c4d7b2438d3 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
switches 0:5c4d7b2438d3 827 #endif
switches 0:5c4d7b2438d3 828 return ((uint16_t) result); /* Add explicit type cast here */
switches 0:5c4d7b2438d3 829 }
switches 0:5c4d7b2438d3 830
switches 0:5c4d7b2438d3 831
switches 0:5c4d7b2438d3 832 /** \brief LDRT Unprivileged (32 bit)
switches 0:5c4d7b2438d3 833
switches 0:5c4d7b2438d3 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
switches 0:5c4d7b2438d3 835
switches 0:5c4d7b2438d3 836 \param [in] ptr Pointer to data
switches 0:5c4d7b2438d3 837 \return value of type uint32_t at (*ptr)
switches 0:5c4d7b2438d3 838 */
switches 0:5c4d7b2438d3 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
switches 0:5c4d7b2438d3 840 {
switches 0:5c4d7b2438d3 841 uint32_t result;
switches 0:5c4d7b2438d3 842
switches 0:5c4d7b2438d3 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
switches 0:5c4d7b2438d3 844 return(result);
switches 0:5c4d7b2438d3 845 }
switches 0:5c4d7b2438d3 846
switches 0:5c4d7b2438d3 847
switches 0:5c4d7b2438d3 848 /** \brief STRT Unprivileged (8 bit)
switches 0:5c4d7b2438d3 849
switches 0:5c4d7b2438d3 850 This function executes a Unprivileged STRT instruction for 8 bit values.
switches 0:5c4d7b2438d3 851
switches 0:5c4d7b2438d3 852 \param [in] value Value to store
switches 0:5c4d7b2438d3 853 \param [in] ptr Pointer to location
switches 0:5c4d7b2438d3 854 */
switches 0:5c4d7b2438d3 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
switches 0:5c4d7b2438d3 856 {
switches 0:5c4d7b2438d3 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
switches 0:5c4d7b2438d3 858 }
switches 0:5c4d7b2438d3 859
switches 0:5c4d7b2438d3 860
switches 0:5c4d7b2438d3 861 /** \brief STRT Unprivileged (16 bit)
switches 0:5c4d7b2438d3 862
switches 0:5c4d7b2438d3 863 This function executes a Unprivileged STRT instruction for 16 bit values.
switches 0:5c4d7b2438d3 864
switches 0:5c4d7b2438d3 865 \param [in] value Value to store
switches 0:5c4d7b2438d3 866 \param [in] ptr Pointer to location
switches 0:5c4d7b2438d3 867 */
switches 0:5c4d7b2438d3 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
switches 0:5c4d7b2438d3 869 {
switches 0:5c4d7b2438d3 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
switches 0:5c4d7b2438d3 871 }
switches 0:5c4d7b2438d3 872
switches 0:5c4d7b2438d3 873
switches 0:5c4d7b2438d3 874 /** \brief STRT Unprivileged (32 bit)
switches 0:5c4d7b2438d3 875
switches 0:5c4d7b2438d3 876 This function executes a Unprivileged STRT instruction for 32 bit values.
switches 0:5c4d7b2438d3 877
switches 0:5c4d7b2438d3 878 \param [in] value Value to store
switches 0:5c4d7b2438d3 879 \param [in] ptr Pointer to location
switches 0:5c4d7b2438d3 880 */
switches 0:5c4d7b2438d3 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
switches 0:5c4d7b2438d3 882 {
switches 0:5c4d7b2438d3 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
switches 0:5c4d7b2438d3 884 }
switches 0:5c4d7b2438d3 885
switches 0:5c4d7b2438d3 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
switches 0:5c4d7b2438d3 887
switches 0:5c4d7b2438d3 888
switches 0:5c4d7b2438d3 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
switches 0:5c4d7b2438d3 890 /* IAR iccarm specific functions */
switches 0:5c4d7b2438d3 891 #include <cmsis_iar.h>
switches 0:5c4d7b2438d3 892
switches 0:5c4d7b2438d3 893
switches 0:5c4d7b2438d3 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
switches 0:5c4d7b2438d3 895 /* TI CCS specific functions */
switches 0:5c4d7b2438d3 896 #include <cmsis_ccs.h>
switches 0:5c4d7b2438d3 897
switches 0:5c4d7b2438d3 898
switches 0:5c4d7b2438d3 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
switches 0:5c4d7b2438d3 900 /* TASKING carm specific functions */
switches 0:5c4d7b2438d3 901 /*
switches 0:5c4d7b2438d3 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
switches 0:5c4d7b2438d3 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
switches 0:5c4d7b2438d3 904 * Including the CMSIS ones.
switches 0:5c4d7b2438d3 905 */
switches 0:5c4d7b2438d3 906
switches 0:5c4d7b2438d3 907
switches 0:5c4d7b2438d3 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
switches 0:5c4d7b2438d3 909 /* Cosmic specific functions */
switches 0:5c4d7b2438d3 910 #include <cmsis_csm.h>
switches 0:5c4d7b2438d3 911
switches 0:5c4d7b2438d3 912 #endif
switches 0:5c4d7b2438d3 913
switches 0:5c4d7b2438d3 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
switches 0:5c4d7b2438d3 915
switches 0:5c4d7b2438d3 916 #endif /* __CORE_CMINSTR_H */