Greg Steiert / pegasus_dev

Development mbed library for MAX32630FTHR

Dependents:   blinky_max32630fthr

cmsis/core_cmFunc.h@3:1198227e6421, 2016-12-16 (annotated)

Committer:
switches
Date:
Fri Dec 16 16:27:57 2016 +0000
Revision:
3:1198227e6421
Parent:
0:5c4d7b2438d3 
Changed ADC scale for MAX32625 platforms to 1.2V full scale to match MAX32630 platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 /**************************************************************************//**
switches 0:5c4d7b2438d3 2 * @file core_cmFunc.h
switches 0:5c4d7b2438d3 3 * @brief CMSIS Cortex-M Core Function Access Header File
switches 0:5c4d7b2438d3 4 * @version V4.10
switches 0:5c4d7b2438d3 5 * @date 18. March 2015
switches 0:5c4d7b2438d3 6 *
switches 0:5c4d7b2438d3 7 * @note
switches 0:5c4d7b2438d3 8 *
switches 0:5c4d7b2438d3 9 ******************************************************************************/
switches 0:5c4d7b2438d3 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
switches 0:5c4d7b2438d3 11
switches 0:5c4d7b2438d3 12 All rights reserved.
switches 0:5c4d7b2438d3 13 Redistribution and use in source and binary forms, with or without
switches 0:5c4d7b2438d3 14 modification, are permitted provided that the following conditions are met:
switches 0:5c4d7b2438d3 15 - Redistributions of source code must retain the above copyright
switches 0:5c4d7b2438d3 16 notice, this list of conditions and the following disclaimer.
switches 0:5c4d7b2438d3 17 - Redistributions in binary form must reproduce the above copyright
switches 0:5c4d7b2438d3 18 notice, this list of conditions and the following disclaimer in the
switches 0:5c4d7b2438d3 19 documentation and/or other materials provided with the distribution.
switches 0:5c4d7b2438d3 20 - Neither the name of ARM nor the names of its contributors may be used
switches 0:5c4d7b2438d3 21 to endorse or promote products derived from this software without
switches 0:5c4d7b2438d3 22 specific prior written permission.
switches 0:5c4d7b2438d3 23 *
switches 0:5c4d7b2438d3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
switches 0:5c4d7b2438d3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
switches 0:5c4d7b2438d3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
switches 0:5c4d7b2438d3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
switches 0:5c4d7b2438d3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
switches 0:5c4d7b2438d3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
switches 0:5c4d7b2438d3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
switches 0:5c4d7b2438d3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
switches 0:5c4d7b2438d3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
switches 0:5c4d7b2438d3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
switches 0:5c4d7b2438d3 34 POSSIBILITY OF SUCH DAMAGE.
switches 0:5c4d7b2438d3 35 ---------------------------------------------------------------------------*/
switches 0:5c4d7b2438d3 36
switches 0:5c4d7b2438d3 37
switches 0:5c4d7b2438d3 38 #ifndef __CORE_CMFUNC_H
switches 0:5c4d7b2438d3 39 #define __CORE_CMFUNC_H
switches 0:5c4d7b2438d3 40
switches 0:5c4d7b2438d3 41
switches 0:5c4d7b2438d3 42 /* ########################### Core Function Access ########################### */
switches 0:5c4d7b2438d3 43 /** \ingroup CMSIS_Core_FunctionInterface
switches 0:5c4d7b2438d3 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
switches 0:5c4d7b2438d3 45 @{
switches 0:5c4d7b2438d3 46 */
switches 0:5c4d7b2438d3 47
switches 0:5c4d7b2438d3 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
switches 0:5c4d7b2438d3 49 /* ARM armcc specific functions */
switches 0:5c4d7b2438d3 50
switches 0:5c4d7b2438d3 51 #if (__ARMCC_VERSION < 400677)
switches 0:5c4d7b2438d3 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
switches 0:5c4d7b2438d3 53 #endif
switches 0:5c4d7b2438d3 54
switches 0:5c4d7b2438d3 55 /* intrinsic void __enable_irq(); */
switches 0:5c4d7b2438d3 56 /* intrinsic void __disable_irq(); */
switches 0:5c4d7b2438d3 57
switches 0:5c4d7b2438d3 58 /** \brief Get Control Register
switches 0:5c4d7b2438d3 59
switches 0:5c4d7b2438d3 60 This function returns the content of the Control Register.
switches 0:5c4d7b2438d3 61
switches 0:5c4d7b2438d3 62 \return Control Register value
switches 0:5c4d7b2438d3 63 */
switches 0:5c4d7b2438d3 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
switches 0:5c4d7b2438d3 65 {
switches 0:5c4d7b2438d3 66 register uint32_t __regControl __ASM("control");
switches 0:5c4d7b2438d3 67 return(__regControl);
switches 0:5c4d7b2438d3 68 }
switches 0:5c4d7b2438d3 69
switches 0:5c4d7b2438d3 70
switches 0:5c4d7b2438d3 71 /** \brief Set Control Register
switches 0:5c4d7b2438d3 72
switches 0:5c4d7b2438d3 73 This function writes the given value to the Control Register.
switches 0:5c4d7b2438d3 74
switches 0:5c4d7b2438d3 75 \param [in] control Control Register value to set
switches 0:5c4d7b2438d3 76 */
switches 0:5c4d7b2438d3 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
switches 0:5c4d7b2438d3 78 {
switches 0:5c4d7b2438d3 79 register uint32_t __regControl __ASM("control");
switches 0:5c4d7b2438d3 80 __regControl = control;
switches 0:5c4d7b2438d3 81 }
switches 0:5c4d7b2438d3 82
switches 0:5c4d7b2438d3 83
switches 0:5c4d7b2438d3 84 /** \brief Get IPSR Register
switches 0:5c4d7b2438d3 85
switches 0:5c4d7b2438d3 86 This function returns the content of the IPSR Register.
switches 0:5c4d7b2438d3 87
switches 0:5c4d7b2438d3 88 \return IPSR Register value
switches 0:5c4d7b2438d3 89 */
switches 0:5c4d7b2438d3 90 __STATIC_INLINE uint32_t __get_IPSR(void)
switches 0:5c4d7b2438d3 91 {
switches 0:5c4d7b2438d3 92 register uint32_t __regIPSR __ASM("ipsr");
switches 0:5c4d7b2438d3 93 return(__regIPSR);
switches 0:5c4d7b2438d3 94 }
switches 0:5c4d7b2438d3 95
switches 0:5c4d7b2438d3 96
switches 0:5c4d7b2438d3 97 /** \brief Get APSR Register
switches 0:5c4d7b2438d3 98
switches 0:5c4d7b2438d3 99 This function returns the content of the APSR Register.
switches 0:5c4d7b2438d3 100
switches 0:5c4d7b2438d3 101 \return APSR Register value
switches 0:5c4d7b2438d3 102 */
switches 0:5c4d7b2438d3 103 __STATIC_INLINE uint32_t __get_APSR(void)
switches 0:5c4d7b2438d3 104 {
switches 0:5c4d7b2438d3 105 register uint32_t __regAPSR __ASM("apsr");
switches 0:5c4d7b2438d3 106 return(__regAPSR);
switches 0:5c4d7b2438d3 107 }
switches 0:5c4d7b2438d3 108
switches 0:5c4d7b2438d3 109
switches 0:5c4d7b2438d3 110 /** \brief Get xPSR Register
switches 0:5c4d7b2438d3 111
switches 0:5c4d7b2438d3 112 This function returns the content of the xPSR Register.
switches 0:5c4d7b2438d3 113
switches 0:5c4d7b2438d3 114 \return xPSR Register value
switches 0:5c4d7b2438d3 115 */
switches 0:5c4d7b2438d3 116 __STATIC_INLINE uint32_t __get_xPSR(void)
switches 0:5c4d7b2438d3 117 {
switches 0:5c4d7b2438d3 118 register uint32_t __regXPSR __ASM("xpsr");
switches 0:5c4d7b2438d3 119 return(__regXPSR);
switches 0:5c4d7b2438d3 120 }
switches 0:5c4d7b2438d3 121
switches 0:5c4d7b2438d3 122
switches 0:5c4d7b2438d3 123 /** \brief Get Process Stack Pointer
switches 0:5c4d7b2438d3 124
switches 0:5c4d7b2438d3 125 This function returns the current value of the Process Stack Pointer (PSP).
switches 0:5c4d7b2438d3 126
switches 0:5c4d7b2438d3 127 \return PSP Register value
switches 0:5c4d7b2438d3 128 */
switches 0:5c4d7b2438d3 129 __STATIC_INLINE uint32_t __get_PSP(void)
switches 0:5c4d7b2438d3 130 {
switches 0:5c4d7b2438d3 131 register uint32_t __regProcessStackPointer __ASM("psp");
switches 0:5c4d7b2438d3 132 return(__regProcessStackPointer);
switches 0:5c4d7b2438d3 133 }
switches 0:5c4d7b2438d3 134
switches 0:5c4d7b2438d3 135
switches 0:5c4d7b2438d3 136 /** \brief Set Process Stack Pointer
switches 0:5c4d7b2438d3 137
switches 0:5c4d7b2438d3 138 This function assigns the given value to the Process Stack Pointer (PSP).
switches 0:5c4d7b2438d3 139
switches 0:5c4d7b2438d3 140 \param [in] topOfProcStack Process Stack Pointer value to set
switches 0:5c4d7b2438d3 141 */
switches 0:5c4d7b2438d3 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
switches 0:5c4d7b2438d3 143 {
switches 0:5c4d7b2438d3 144 register uint32_t __regProcessStackPointer __ASM("psp");
switches 0:5c4d7b2438d3 145 __regProcessStackPointer = topOfProcStack;
switches 0:5c4d7b2438d3 146 }
switches 0:5c4d7b2438d3 147
switches 0:5c4d7b2438d3 148
switches 0:5c4d7b2438d3 149 /** \brief Get Main Stack Pointer
switches 0:5c4d7b2438d3 150
switches 0:5c4d7b2438d3 151 This function returns the current value of the Main Stack Pointer (MSP).
switches 0:5c4d7b2438d3 152
switches 0:5c4d7b2438d3 153 \return MSP Register value
switches 0:5c4d7b2438d3 154 */
switches 0:5c4d7b2438d3 155 __STATIC_INLINE uint32_t __get_MSP(void)
switches 0:5c4d7b2438d3 156 {
switches 0:5c4d7b2438d3 157 register uint32_t __regMainStackPointer __ASM("msp");
switches 0:5c4d7b2438d3 158 return(__regMainStackPointer);
switches 0:5c4d7b2438d3 159 }
switches 0:5c4d7b2438d3 160
switches 0:5c4d7b2438d3 161
switches 0:5c4d7b2438d3 162 /** \brief Set Main Stack Pointer
switches 0:5c4d7b2438d3 163
switches 0:5c4d7b2438d3 164 This function assigns the given value to the Main Stack Pointer (MSP).
switches 0:5c4d7b2438d3 165
switches 0:5c4d7b2438d3 166 \param [in] topOfMainStack Main Stack Pointer value to set
switches 0:5c4d7b2438d3 167 */
switches 0:5c4d7b2438d3 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
switches 0:5c4d7b2438d3 169 {
switches 0:5c4d7b2438d3 170 register uint32_t __regMainStackPointer __ASM("msp");
switches 0:5c4d7b2438d3 171 __regMainStackPointer = topOfMainStack;
switches 0:5c4d7b2438d3 172 }
switches 0:5c4d7b2438d3 173
switches 0:5c4d7b2438d3 174
switches 0:5c4d7b2438d3 175 /** \brief Get Priority Mask
switches 0:5c4d7b2438d3 176
switches 0:5c4d7b2438d3 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
switches 0:5c4d7b2438d3 178
switches 0:5c4d7b2438d3 179 \return Priority Mask value
switches 0:5c4d7b2438d3 180 */
switches 0:5c4d7b2438d3 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
switches 0:5c4d7b2438d3 182 {
switches 0:5c4d7b2438d3 183 register uint32_t __regPriMask __ASM("primask");
switches 0:5c4d7b2438d3 184 return(__regPriMask);
switches 0:5c4d7b2438d3 185 }
switches 0:5c4d7b2438d3 186
switches 0:5c4d7b2438d3 187
switches 0:5c4d7b2438d3 188 /** \brief Set Priority Mask
switches 0:5c4d7b2438d3 189
switches 0:5c4d7b2438d3 190 This function assigns the given value to the Priority Mask Register.
switches 0:5c4d7b2438d3 191
switches 0:5c4d7b2438d3 192 \param [in] priMask Priority Mask
switches 0:5c4d7b2438d3 193 */
switches 0:5c4d7b2438d3 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
switches 0:5c4d7b2438d3 195 {
switches 0:5c4d7b2438d3 196 register uint32_t __regPriMask __ASM("primask");
switches 0:5c4d7b2438d3 197 __regPriMask = (priMask);
switches 0:5c4d7b2438d3 198 }
switches 0:5c4d7b2438d3 199
switches 0:5c4d7b2438d3 200
switches 0:5c4d7b2438d3 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
switches 0:5c4d7b2438d3 202
switches 0:5c4d7b2438d3 203 /** \brief Enable FIQ
switches 0:5c4d7b2438d3 204
switches 0:5c4d7b2438d3 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
switches 0:5c4d7b2438d3 206 Can only be executed in Privileged modes.
switches 0:5c4d7b2438d3 207 */
switches 0:5c4d7b2438d3 208 #define __enable_fault_irq __enable_fiq
switches 0:5c4d7b2438d3 209
switches 0:5c4d7b2438d3 210
switches 0:5c4d7b2438d3 211 /** \brief Disable FIQ
switches 0:5c4d7b2438d3 212
switches 0:5c4d7b2438d3 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
switches 0:5c4d7b2438d3 214 Can only be executed in Privileged modes.
switches 0:5c4d7b2438d3 215 */
switches 0:5c4d7b2438d3 216 #define __disable_fault_irq __disable_fiq
switches 0:5c4d7b2438d3 217
switches 0:5c4d7b2438d3 218
switches 0:5c4d7b2438d3 219 /** \brief Get Base Priority
switches 0:5c4d7b2438d3 220
switches 0:5c4d7b2438d3 221 This function returns the current value of the Base Priority register.
switches 0:5c4d7b2438d3 222
switches 0:5c4d7b2438d3 223 \return Base Priority register value
switches 0:5c4d7b2438d3 224 */
switches 0:5c4d7b2438d3 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
switches 0:5c4d7b2438d3 226 {
switches 0:5c4d7b2438d3 227 register uint32_t __regBasePri __ASM("basepri");
switches 0:5c4d7b2438d3 228 return(__regBasePri);
switches 0:5c4d7b2438d3 229 }
switches 0:5c4d7b2438d3 230
switches 0:5c4d7b2438d3 231
switches 0:5c4d7b2438d3 232 /** \brief Set Base Priority
switches 0:5c4d7b2438d3 233
switches 0:5c4d7b2438d3 234 This function assigns the given value to the Base Priority register.
switches 0:5c4d7b2438d3 235
switches 0:5c4d7b2438d3 236 \param [in] basePri Base Priority value to set
switches 0:5c4d7b2438d3 237 */
switches 0:5c4d7b2438d3 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
switches 0:5c4d7b2438d3 239 {
switches 0:5c4d7b2438d3 240 register uint32_t __regBasePri __ASM("basepri");
switches 0:5c4d7b2438d3 241 __regBasePri = (basePri & 0xff);
switches 0:5c4d7b2438d3 242 }
switches 0:5c4d7b2438d3 243
switches 0:5c4d7b2438d3 244
switches 0:5c4d7b2438d3 245 /** \brief Set Base Priority with condition
switches 0:5c4d7b2438d3 246
switches 0:5c4d7b2438d3 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
switches 0:5c4d7b2438d3 248 or the new value increases the BASEPRI priority level.
switches 0:5c4d7b2438d3 249
switches 0:5c4d7b2438d3 250 \param [in] basePri Base Priority value to set
switches 0:5c4d7b2438d3 251 */
switches 0:5c4d7b2438d3 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
switches 0:5c4d7b2438d3 253 {
switches 0:5c4d7b2438d3 254 register uint32_t __regBasePriMax __ASM("basepri_max");
switches 0:5c4d7b2438d3 255 __regBasePriMax = (basePri & 0xff);
switches 0:5c4d7b2438d3 256 }
switches 0:5c4d7b2438d3 257
switches 0:5c4d7b2438d3 258
switches 0:5c4d7b2438d3 259 /** \brief Get Fault Mask
switches 0:5c4d7b2438d3 260
switches 0:5c4d7b2438d3 261 This function returns the current value of the Fault Mask register.
switches 0:5c4d7b2438d3 262
switches 0:5c4d7b2438d3 263 \return Fault Mask register value
switches 0:5c4d7b2438d3 264 */
switches 0:5c4d7b2438d3 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
switches 0:5c4d7b2438d3 266 {
switches 0:5c4d7b2438d3 267 register uint32_t __regFaultMask __ASM("faultmask");
switches 0:5c4d7b2438d3 268 return(__regFaultMask);
switches 0:5c4d7b2438d3 269 }
switches 0:5c4d7b2438d3 270
switches 0:5c4d7b2438d3 271
switches 0:5c4d7b2438d3 272 /** \brief Set Fault Mask
switches 0:5c4d7b2438d3 273
switches 0:5c4d7b2438d3 274 This function assigns the given value to the Fault Mask register.
switches 0:5c4d7b2438d3 275
switches 0:5c4d7b2438d3 276 \param [in] faultMask Fault Mask value to set
switches 0:5c4d7b2438d3 277 */
switches 0:5c4d7b2438d3 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
switches 0:5c4d7b2438d3 279 {
switches 0:5c4d7b2438d3 280 register uint32_t __regFaultMask __ASM("faultmask");
switches 0:5c4d7b2438d3 281 __regFaultMask = (faultMask & (uint32_t)1);
switches 0:5c4d7b2438d3 282 }
switches 0:5c4d7b2438d3 283
switches 0:5c4d7b2438d3 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
switches 0:5c4d7b2438d3 285
switches 0:5c4d7b2438d3 286
switches 0:5c4d7b2438d3 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
switches 0:5c4d7b2438d3 288
switches 0:5c4d7b2438d3 289 /** \brief Get FPSCR
switches 0:5c4d7b2438d3 290
switches 0:5c4d7b2438d3 291 This function returns the current value of the Floating Point Status/Control register.
switches 0:5c4d7b2438d3 292
switches 0:5c4d7b2438d3 293 \return Floating Point Status/Control register value
switches 0:5c4d7b2438d3 294 */
switches 0:5c4d7b2438d3 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
switches 0:5c4d7b2438d3 296 {
switches 0:5c4d7b2438d3 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:5c4d7b2438d3 298 register uint32_t __regfpscr __ASM("fpscr");
switches 0:5c4d7b2438d3 299 return(__regfpscr);
switches 0:5c4d7b2438d3 300 #else
switches 0:5c4d7b2438d3 301 return(0);
switches 0:5c4d7b2438d3 302 #endif
switches 0:5c4d7b2438d3 303 }
switches 0:5c4d7b2438d3 304
switches 0:5c4d7b2438d3 305
switches 0:5c4d7b2438d3 306 /** \brief Set FPSCR
switches 0:5c4d7b2438d3 307
switches 0:5c4d7b2438d3 308 This function assigns the given value to the Floating Point Status/Control register.
switches 0:5c4d7b2438d3 309
switches 0:5c4d7b2438d3 310 \param [in] fpscr Floating Point Status/Control value to set
switches 0:5c4d7b2438d3 311 */
switches 0:5c4d7b2438d3 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
switches 0:5c4d7b2438d3 313 {
switches 0:5c4d7b2438d3 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:5c4d7b2438d3 315 register uint32_t __regfpscr __ASM("fpscr");
switches 0:5c4d7b2438d3 316 __regfpscr = (fpscr);
switches 0:5c4d7b2438d3 317 #endif
switches 0:5c4d7b2438d3 318 }
switches 0:5c4d7b2438d3 319
switches 0:5c4d7b2438d3 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
switches 0:5c4d7b2438d3 321
switches 0:5c4d7b2438d3 322
switches 0:5c4d7b2438d3 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
switches 0:5c4d7b2438d3 324 /* GNU gcc specific functions */
switches 0:5c4d7b2438d3 325
switches 0:5c4d7b2438d3 326 /** \brief Enable IRQ Interrupts
switches 0:5c4d7b2438d3 327
switches 0:5c4d7b2438d3 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
switches 0:5c4d7b2438d3 329 Can only be executed in Privileged modes.
switches 0:5c4d7b2438d3 330 */
switches 0:5c4d7b2438d3 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
switches 0:5c4d7b2438d3 332 {
switches 0:5c4d7b2438d3 333 __ASM volatile ("cpsie i" : : : "memory");
switches 0:5c4d7b2438d3 334 }
switches 0:5c4d7b2438d3 335
switches 0:5c4d7b2438d3 336
switches 0:5c4d7b2438d3 337 /** \brief Disable IRQ Interrupts
switches 0:5c4d7b2438d3 338
switches 0:5c4d7b2438d3 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
switches 0:5c4d7b2438d3 340 Can only be executed in Privileged modes.
switches 0:5c4d7b2438d3 341 */
switches 0:5c4d7b2438d3 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
switches 0:5c4d7b2438d3 343 {
switches 0:5c4d7b2438d3 344 __ASM volatile ("cpsid i" : : : "memory");
switches 0:5c4d7b2438d3 345 }
switches 0:5c4d7b2438d3 346
switches 0:5c4d7b2438d3 347
switches 0:5c4d7b2438d3 348 /** \brief Get Control Register
switches 0:5c4d7b2438d3 349
switches 0:5c4d7b2438d3 350 This function returns the content of the Control Register.
switches 0:5c4d7b2438d3 351
switches 0:5c4d7b2438d3 352 \return Control Register value
switches 0:5c4d7b2438d3 353 */
switches 0:5c4d7b2438d3 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
switches 0:5c4d7b2438d3 355 {
switches 0:5c4d7b2438d3 356 uint32_t result;
switches 0:5c4d7b2438d3 357
switches 0:5c4d7b2438d3 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
switches 0:5c4d7b2438d3 359 return(result);
switches 0:5c4d7b2438d3 360 }
switches 0:5c4d7b2438d3 361
switches 0:5c4d7b2438d3 362
switches 0:5c4d7b2438d3 363 /** \brief Set Control Register
switches 0:5c4d7b2438d3 364
switches 0:5c4d7b2438d3 365 This function writes the given value to the Control Register.
switches 0:5c4d7b2438d3 366
switches 0:5c4d7b2438d3 367 \param [in] control Control Register value to set
switches 0:5c4d7b2438d3 368 */
switches 0:5c4d7b2438d3 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
switches 0:5c4d7b2438d3 370 {
switches 0:5c4d7b2438d3 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
switches 0:5c4d7b2438d3 372 }
switches 0:5c4d7b2438d3 373
switches 0:5c4d7b2438d3 374
switches 0:5c4d7b2438d3 375 /** \brief Get IPSR Register
switches 0:5c4d7b2438d3 376
switches 0:5c4d7b2438d3 377 This function returns the content of the IPSR Register.
switches 0:5c4d7b2438d3 378
switches 0:5c4d7b2438d3 379 \return IPSR Register value
switches 0:5c4d7b2438d3 380 */
switches 0:5c4d7b2438d3 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
switches 0:5c4d7b2438d3 382 {
switches 0:5c4d7b2438d3 383 uint32_t result;
switches 0:5c4d7b2438d3 384
switches 0:5c4d7b2438d3 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
switches 0:5c4d7b2438d3 386 return(result);
switches 0:5c4d7b2438d3 387 }
switches 0:5c4d7b2438d3 388
switches 0:5c4d7b2438d3 389
switches 0:5c4d7b2438d3 390 /** \brief Get APSR Register
switches 0:5c4d7b2438d3 391
switches 0:5c4d7b2438d3 392 This function returns the content of the APSR Register.
switches 0:5c4d7b2438d3 393
switches 0:5c4d7b2438d3 394 \return APSR Register value
switches 0:5c4d7b2438d3 395 */
switches 0:5c4d7b2438d3 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
switches 0:5c4d7b2438d3 397 {
switches 0:5c4d7b2438d3 398 uint32_t result;
switches 0:5c4d7b2438d3 399
switches 0:5c4d7b2438d3 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
switches 0:5c4d7b2438d3 401 return(result);
switches 0:5c4d7b2438d3 402 }
switches 0:5c4d7b2438d3 403
switches 0:5c4d7b2438d3 404
switches 0:5c4d7b2438d3 405 /** \brief Get xPSR Register
switches 0:5c4d7b2438d3 406
switches 0:5c4d7b2438d3 407 This function returns the content of the xPSR Register.
switches 0:5c4d7b2438d3 408
switches 0:5c4d7b2438d3 409 \return xPSR Register value
switches 0:5c4d7b2438d3 410 */
switches 0:5c4d7b2438d3 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
switches 0:5c4d7b2438d3 412 {
switches 0:5c4d7b2438d3 413 uint32_t result;
switches 0:5c4d7b2438d3 414
switches 0:5c4d7b2438d3 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
switches 0:5c4d7b2438d3 416 return(result);
switches 0:5c4d7b2438d3 417 }
switches 0:5c4d7b2438d3 418
switches 0:5c4d7b2438d3 419
switches 0:5c4d7b2438d3 420 /** \brief Get Process Stack Pointer
switches 0:5c4d7b2438d3 421
switches 0:5c4d7b2438d3 422 This function returns the current value of the Process Stack Pointer (PSP).
switches 0:5c4d7b2438d3 423
switches 0:5c4d7b2438d3 424 \return PSP Register value
switches 0:5c4d7b2438d3 425 */
switches 0:5c4d7b2438d3 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
switches 0:5c4d7b2438d3 427 {
switches 0:5c4d7b2438d3 428 register uint32_t result;
switches 0:5c4d7b2438d3 429
switches 0:5c4d7b2438d3 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
switches 0:5c4d7b2438d3 431 return(result);
switches 0:5c4d7b2438d3 432 }
switches 0:5c4d7b2438d3 433
switches 0:5c4d7b2438d3 434
switches 0:5c4d7b2438d3 435 /** \brief Set Process Stack Pointer
switches 0:5c4d7b2438d3 436
switches 0:5c4d7b2438d3 437 This function assigns the given value to the Process Stack Pointer (PSP).
switches 0:5c4d7b2438d3 438
switches 0:5c4d7b2438d3 439 \param [in] topOfProcStack Process Stack Pointer value to set
switches 0:5c4d7b2438d3 440 */
switches 0:5c4d7b2438d3 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
switches 0:5c4d7b2438d3 442 {
switches 0:5c4d7b2438d3 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
switches 0:5c4d7b2438d3 444 }
switches 0:5c4d7b2438d3 445
switches 0:5c4d7b2438d3 446
switches 0:5c4d7b2438d3 447 /** \brief Get Main Stack Pointer
switches 0:5c4d7b2438d3 448
switches 0:5c4d7b2438d3 449 This function returns the current value of the Main Stack Pointer (MSP).
switches 0:5c4d7b2438d3 450
switches 0:5c4d7b2438d3 451 \return MSP Register value
switches 0:5c4d7b2438d3 452 */
switches 0:5c4d7b2438d3 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
switches 0:5c4d7b2438d3 454 {
switches 0:5c4d7b2438d3 455 register uint32_t result;
switches 0:5c4d7b2438d3 456
switches 0:5c4d7b2438d3 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
switches 0:5c4d7b2438d3 458 return(result);
switches 0:5c4d7b2438d3 459 }
switches 0:5c4d7b2438d3 460
switches 0:5c4d7b2438d3 461
switches 0:5c4d7b2438d3 462 /** \brief Set Main Stack Pointer
switches 0:5c4d7b2438d3 463
switches 0:5c4d7b2438d3 464 This function assigns the given value to the Main Stack Pointer (MSP).
switches 0:5c4d7b2438d3 465
switches 0:5c4d7b2438d3 466 \param [in] topOfMainStack Main Stack Pointer value to set
switches 0:5c4d7b2438d3 467 */
switches 0:5c4d7b2438d3 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
switches 0:5c4d7b2438d3 469 {
switches 0:5c4d7b2438d3 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
switches 0:5c4d7b2438d3 471 }
switches 0:5c4d7b2438d3 472
switches 0:5c4d7b2438d3 473
switches 0:5c4d7b2438d3 474 /** \brief Get Priority Mask
switches 0:5c4d7b2438d3 475
switches 0:5c4d7b2438d3 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
switches 0:5c4d7b2438d3 477
switches 0:5c4d7b2438d3 478 \return Priority Mask value
switches 0:5c4d7b2438d3 479 */
switches 0:5c4d7b2438d3 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
switches 0:5c4d7b2438d3 481 {
switches 0:5c4d7b2438d3 482 uint32_t result;
switches 0:5c4d7b2438d3 483
switches 0:5c4d7b2438d3 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
switches 0:5c4d7b2438d3 485 return(result);
switches 0:5c4d7b2438d3 486 }
switches 0:5c4d7b2438d3 487
switches 0:5c4d7b2438d3 488
switches 0:5c4d7b2438d3 489 /** \brief Set Priority Mask
switches 0:5c4d7b2438d3 490
switches 0:5c4d7b2438d3 491 This function assigns the given value to the Priority Mask Register.
switches 0:5c4d7b2438d3 492
switches 0:5c4d7b2438d3 493 \param [in] priMask Priority Mask
switches 0:5c4d7b2438d3 494 */
switches 0:5c4d7b2438d3 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
switches 0:5c4d7b2438d3 496 {
switches 0:5c4d7b2438d3 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
switches 0:5c4d7b2438d3 498 }
switches 0:5c4d7b2438d3 499
switches 0:5c4d7b2438d3 500
switches 0:5c4d7b2438d3 501 #if (__CORTEX_M >= 0x03)
switches 0:5c4d7b2438d3 502
switches 0:5c4d7b2438d3 503 /** \brief Enable FIQ
switches 0:5c4d7b2438d3 504
switches 0:5c4d7b2438d3 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
switches 0:5c4d7b2438d3 506 Can only be executed in Privileged modes.
switches 0:5c4d7b2438d3 507 */
switches 0:5c4d7b2438d3 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
switches 0:5c4d7b2438d3 509 {
switches 0:5c4d7b2438d3 510 __ASM volatile ("cpsie f" : : : "memory");
switches 0:5c4d7b2438d3 511 }
switches 0:5c4d7b2438d3 512
switches 0:5c4d7b2438d3 513
switches 0:5c4d7b2438d3 514 /** \brief Disable FIQ
switches 0:5c4d7b2438d3 515
switches 0:5c4d7b2438d3 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
switches 0:5c4d7b2438d3 517 Can only be executed in Privileged modes.
switches 0:5c4d7b2438d3 518 */
switches 0:5c4d7b2438d3 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
switches 0:5c4d7b2438d3 520 {
switches 0:5c4d7b2438d3 521 __ASM volatile ("cpsid f" : : : "memory");
switches 0:5c4d7b2438d3 522 }
switches 0:5c4d7b2438d3 523
switches 0:5c4d7b2438d3 524
switches 0:5c4d7b2438d3 525 /** \brief Get Base Priority
switches 0:5c4d7b2438d3 526
switches 0:5c4d7b2438d3 527 This function returns the current value of the Base Priority register.
switches 0:5c4d7b2438d3 528
switches 0:5c4d7b2438d3 529 \return Base Priority register value
switches 0:5c4d7b2438d3 530 */
switches 0:5c4d7b2438d3 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
switches 0:5c4d7b2438d3 532 {
switches 0:5c4d7b2438d3 533 uint32_t result;
switches 0:5c4d7b2438d3 534
switches 0:5c4d7b2438d3 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
switches 0:5c4d7b2438d3 536 return(result);
switches 0:5c4d7b2438d3 537 }
switches 0:5c4d7b2438d3 538
switches 0:5c4d7b2438d3 539
switches 0:5c4d7b2438d3 540 /** \brief Set Base Priority
switches 0:5c4d7b2438d3 541
switches 0:5c4d7b2438d3 542 This function assigns the given value to the Base Priority register.
switches 0:5c4d7b2438d3 543
switches 0:5c4d7b2438d3 544 \param [in] basePri Base Priority value to set
switches 0:5c4d7b2438d3 545 */
switches 0:5c4d7b2438d3 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
switches 0:5c4d7b2438d3 547 {
switches 0:5c4d7b2438d3 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
switches 0:5c4d7b2438d3 549 }
switches 0:5c4d7b2438d3 550
switches 0:5c4d7b2438d3 551
switches 0:5c4d7b2438d3 552 /** \brief Set Base Priority with condition
switches 0:5c4d7b2438d3 553
switches 0:5c4d7b2438d3 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
switches 0:5c4d7b2438d3 555 or the new value increases the BASEPRI priority level.
switches 0:5c4d7b2438d3 556
switches 0:5c4d7b2438d3 557 \param [in] basePri Base Priority value to set
switches 0:5c4d7b2438d3 558 */
switches 0:5c4d7b2438d3 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
switches 0:5c4d7b2438d3 560 {
switches 0:5c4d7b2438d3 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
switches 0:5c4d7b2438d3 562 }
switches 0:5c4d7b2438d3 563
switches 0:5c4d7b2438d3 564
switches 0:5c4d7b2438d3 565 /** \brief Get Fault Mask
switches 0:5c4d7b2438d3 566
switches 0:5c4d7b2438d3 567 This function returns the current value of the Fault Mask register.
switches 0:5c4d7b2438d3 568
switches 0:5c4d7b2438d3 569 \return Fault Mask register value
switches 0:5c4d7b2438d3 570 */
switches 0:5c4d7b2438d3 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
switches 0:5c4d7b2438d3 572 {
switches 0:5c4d7b2438d3 573 uint32_t result;
switches 0:5c4d7b2438d3 574
switches 0:5c4d7b2438d3 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
switches 0:5c4d7b2438d3 576 return(result);
switches 0:5c4d7b2438d3 577 }
switches 0:5c4d7b2438d3 578
switches 0:5c4d7b2438d3 579
switches 0:5c4d7b2438d3 580 /** \brief Set Fault Mask
switches 0:5c4d7b2438d3 581
switches 0:5c4d7b2438d3 582 This function assigns the given value to the Fault Mask register.
switches 0:5c4d7b2438d3 583
switches 0:5c4d7b2438d3 584 \param [in] faultMask Fault Mask value to set
switches 0:5c4d7b2438d3 585 */
switches 0:5c4d7b2438d3 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
switches 0:5c4d7b2438d3 587 {
switches 0:5c4d7b2438d3 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
switches 0:5c4d7b2438d3 589 }
switches 0:5c4d7b2438d3 590
switches 0:5c4d7b2438d3 591 #endif /* (__CORTEX_M >= 0x03) */
switches 0:5c4d7b2438d3 592
switches 0:5c4d7b2438d3 593
switches 0:5c4d7b2438d3 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
switches 0:5c4d7b2438d3 595
switches 0:5c4d7b2438d3 596 /** \brief Get FPSCR
switches 0:5c4d7b2438d3 597
switches 0:5c4d7b2438d3 598 This function returns the current value of the Floating Point Status/Control register.
switches 0:5c4d7b2438d3 599
switches 0:5c4d7b2438d3 600 \return Floating Point Status/Control register value
switches 0:5c4d7b2438d3 601 */
switches 0:5c4d7b2438d3 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
switches 0:5c4d7b2438d3 603 {
switches 0:5c4d7b2438d3 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:5c4d7b2438d3 605 uint32_t result;
switches 0:5c4d7b2438d3 606
switches 0:5c4d7b2438d3 607 /* Empty asm statement works as a scheduling barrier */
switches 0:5c4d7b2438d3 608 __ASM volatile ("");
switches 0:5c4d7b2438d3 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
switches 0:5c4d7b2438d3 610 __ASM volatile ("");
switches 0:5c4d7b2438d3 611 return(result);
switches 0:5c4d7b2438d3 612 #else
switches 0:5c4d7b2438d3 613 return(0);
switches 0:5c4d7b2438d3 614 #endif
switches 0:5c4d7b2438d3 615 }
switches 0:5c4d7b2438d3 616
switches 0:5c4d7b2438d3 617
switches 0:5c4d7b2438d3 618 /** \brief Set FPSCR
switches 0:5c4d7b2438d3 619
switches 0:5c4d7b2438d3 620 This function assigns the given value to the Floating Point Status/Control register.
switches 0:5c4d7b2438d3 621
switches 0:5c4d7b2438d3 622 \param [in] fpscr Floating Point Status/Control value to set
switches 0:5c4d7b2438d3 623 */
switches 0:5c4d7b2438d3 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
switches 0:5c4d7b2438d3 625 {
switches 0:5c4d7b2438d3 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:5c4d7b2438d3 627 /* Empty asm statement works as a scheduling barrier */
switches 0:5c4d7b2438d3 628 __ASM volatile ("");
switches 0:5c4d7b2438d3 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
switches 0:5c4d7b2438d3 630 __ASM volatile ("");
switches 0:5c4d7b2438d3 631 #endif
switches 0:5c4d7b2438d3 632 }
switches 0:5c4d7b2438d3 633
switches 0:5c4d7b2438d3 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
switches 0:5c4d7b2438d3 635
switches 0:5c4d7b2438d3 636
switches 0:5c4d7b2438d3 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
switches 0:5c4d7b2438d3 638 /* IAR iccarm specific functions */
switches 0:5c4d7b2438d3 639 #include <cmsis_iar.h>
switches 0:5c4d7b2438d3 640
switches 0:5c4d7b2438d3 641
switches 0:5c4d7b2438d3 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
switches 0:5c4d7b2438d3 643 /* TI CCS specific functions */
switches 0:5c4d7b2438d3 644 #include <cmsis_ccs.h>
switches 0:5c4d7b2438d3 645
switches 0:5c4d7b2438d3 646
switches 0:5c4d7b2438d3 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
switches 0:5c4d7b2438d3 648 /* TASKING carm specific functions */
switches 0:5c4d7b2438d3 649 /*
switches 0:5c4d7b2438d3 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
switches 0:5c4d7b2438d3 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
switches 0:5c4d7b2438d3 652 * Including the CMSIS ones.
switches 0:5c4d7b2438d3 653 */
switches 0:5c4d7b2438d3 654
switches 0:5c4d7b2438d3 655
switches 0:5c4d7b2438d3 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
switches 0:5c4d7b2438d3 657 /* Cosmic specific functions */
switches 0:5c4d7b2438d3 658 #include <cmsis_csm.h>
switches 0:5c4d7b2438d3 659
switches 0:5c4d7b2438d3 660 #endif
switches 0:5c4d7b2438d3 661
switches 0:5c4d7b2438d3 662 /*@} end of CMSIS_Core_RegAccFunctions */
switches 0:5c4d7b2438d3 663
switches 0:5c4d7b2438d3 664 #endif /* __CORE_CMFUNC_H */