Greg Steiert / pegasus_dev

Development mbed library for MAX32630FTHR

Dependents:   blinky_max32630fthr

cmsis/core_cm4.h@3:1198227e6421, 2016-12-16 (annotated)

Committer:
switches
Date:
Fri Dec 16 16:27:57 2016 +0000
Revision:
3:1198227e6421
Parent:
0:5c4d7b2438d3 
Changed ADC scale for MAX32625 platforms to 1.2V full scale to match MAX32630 platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 /**************************************************************************//**
switches 0:5c4d7b2438d3 2 * @file core_cm4.h
switches 0:5c4d7b2438d3 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
switches 0:5c4d7b2438d3 4 * @version V4.10
switches 0:5c4d7b2438d3 5 * @date 18. March 2015
switches 0:5c4d7b2438d3 6 *
switches 0:5c4d7b2438d3 7 * @note
switches 0:5c4d7b2438d3 8 *
switches 0:5c4d7b2438d3 9 ******************************************************************************/
switches 0:5c4d7b2438d3 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
switches 0:5c4d7b2438d3 11
switches 0:5c4d7b2438d3 12 All rights reserved.
switches 0:5c4d7b2438d3 13 Redistribution and use in source and binary forms, with or without
switches 0:5c4d7b2438d3 14 modification, are permitted provided that the following conditions are met:
switches 0:5c4d7b2438d3 15 - Redistributions of source code must retain the above copyright
switches 0:5c4d7b2438d3 16 notice, this list of conditions and the following disclaimer.
switches 0:5c4d7b2438d3 17 - Redistributions in binary form must reproduce the above copyright
switches 0:5c4d7b2438d3 18 notice, this list of conditions and the following disclaimer in the
switches 0:5c4d7b2438d3 19 documentation and/or other materials provided with the distribution.
switches 0:5c4d7b2438d3 20 - Neither the name of ARM nor the names of its contributors may be used
switches 0:5c4d7b2438d3 21 to endorse or promote products derived from this software without
switches 0:5c4d7b2438d3 22 specific prior written permission.
switches 0:5c4d7b2438d3 23 *
switches 0:5c4d7b2438d3 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
switches 0:5c4d7b2438d3 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
switches 0:5c4d7b2438d3 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
switches 0:5c4d7b2438d3 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
switches 0:5c4d7b2438d3 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
switches 0:5c4d7b2438d3 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
switches 0:5c4d7b2438d3 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
switches 0:5c4d7b2438d3 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
switches 0:5c4d7b2438d3 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
switches 0:5c4d7b2438d3 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
switches 0:5c4d7b2438d3 34 POSSIBILITY OF SUCH DAMAGE.
switches 0:5c4d7b2438d3 35 ---------------------------------------------------------------------------*/
switches 0:5c4d7b2438d3 36
switches 0:5c4d7b2438d3 37
switches 0:5c4d7b2438d3 38 #if defined ( __ICCARM__ )
switches 0:5c4d7b2438d3 39 #pragma system_include /* treat file as system include file for MISRA check */
switches 0:5c4d7b2438d3 40 #endif
switches 0:5c4d7b2438d3 41
switches 0:5c4d7b2438d3 42 #ifndef __CORE_CM4_H_GENERIC
switches 0:5c4d7b2438d3 43 #define __CORE_CM4_H_GENERIC
switches 0:5c4d7b2438d3 44
switches 0:5c4d7b2438d3 45 #ifdef __cplusplus
switches 0:5c4d7b2438d3 46 extern "C" {
switches 0:5c4d7b2438d3 47 #endif
switches 0:5c4d7b2438d3 48
switches 0:5c4d7b2438d3 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
switches 0:5c4d7b2438d3 50 CMSIS violates the following MISRA-C:2004 rules:
switches 0:5c4d7b2438d3 51
switches 0:5c4d7b2438d3 52 \li Required Rule 8.5, object/function definition in header file.<br>
switches 0:5c4d7b2438d3 53 Function definitions in header files are used to allow 'inlining'.
switches 0:5c4d7b2438d3 54
switches 0:5c4d7b2438d3 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
switches 0:5c4d7b2438d3 56 Unions are used for effective representation of core registers.
switches 0:5c4d7b2438d3 57
switches 0:5c4d7b2438d3 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
switches 0:5c4d7b2438d3 59 Function-like macros are used to allow more efficient code.
switches 0:5c4d7b2438d3 60 */
switches 0:5c4d7b2438d3 61
switches 0:5c4d7b2438d3 62
switches 0:5c4d7b2438d3 63 /*******************************************************************************
switches 0:5c4d7b2438d3 64 * CMSIS definitions
switches 0:5c4d7b2438d3 65 ******************************************************************************/
switches 0:5c4d7b2438d3 66 /** \ingroup Cortex_M4
switches 0:5c4d7b2438d3 67 @{
switches 0:5c4d7b2438d3 68 */
switches 0:5c4d7b2438d3 69
switches 0:5c4d7b2438d3 70 /* CMSIS CM4 definitions */
switches 0:5c4d7b2438d3 71 #define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
switches 0:5c4d7b2438d3 72 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
switches 0:5c4d7b2438d3 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
switches 0:5c4d7b2438d3 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
switches 0:5c4d7b2438d3 75
switches 0:5c4d7b2438d3 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
switches 0:5c4d7b2438d3 77
switches 0:5c4d7b2438d3 78
switches 0:5c4d7b2438d3 79 #if defined ( __CC_ARM )
switches 0:5c4d7b2438d3 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
switches 0:5c4d7b2438d3 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
switches 0:5c4d7b2438d3 82 #define __STATIC_INLINE static __inline
switches 0:5c4d7b2438d3 83
switches 0:5c4d7b2438d3 84 #elif defined ( __GNUC__ )
switches 0:5c4d7b2438d3 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
switches 0:5c4d7b2438d3 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
switches 0:5c4d7b2438d3 87 #define __STATIC_INLINE static inline
switches 0:5c4d7b2438d3 88
switches 0:5c4d7b2438d3 89 #elif defined ( __ICCARM__ )
switches 0:5c4d7b2438d3 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
switches 0:5c4d7b2438d3 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
switches 0:5c4d7b2438d3 92 #define __STATIC_INLINE static inline
switches 0:5c4d7b2438d3 93
switches 0:5c4d7b2438d3 94 #elif defined ( __TMS470__ )
switches 0:5c4d7b2438d3 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
switches 0:5c4d7b2438d3 96 #define __STATIC_INLINE static inline
switches 0:5c4d7b2438d3 97
switches 0:5c4d7b2438d3 98 #elif defined ( __TASKING__ )
switches 0:5c4d7b2438d3 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
switches 0:5c4d7b2438d3 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
switches 0:5c4d7b2438d3 101 #define __STATIC_INLINE static inline
switches 0:5c4d7b2438d3 102
switches 0:5c4d7b2438d3 103 #elif defined ( __CSMC__ )
switches 0:5c4d7b2438d3 104 #define __packed
switches 0:5c4d7b2438d3 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
switches 0:5c4d7b2438d3 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
switches 0:5c4d7b2438d3 107 #define __STATIC_INLINE static inline
switches 0:5c4d7b2438d3 108
switches 0:5c4d7b2438d3 109 #endif
switches 0:5c4d7b2438d3 110
switches 0:5c4d7b2438d3 111 /** __FPU_USED indicates whether an FPU is used or not.
switches 0:5c4d7b2438d3 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
switches 0:5c4d7b2438d3 113 */
switches 0:5c4d7b2438d3 114 #if defined ( __CC_ARM )
switches 0:5c4d7b2438d3 115 #if defined __TARGET_FPU_VFP
switches 0:5c4d7b2438d3 116 #if (__FPU_PRESENT == 1)
switches 0:5c4d7b2438d3 117 #define __FPU_USED 1
switches 0:5c4d7b2438d3 118 #else
switches 0:5c4d7b2438d3 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:5c4d7b2438d3 120 #define __FPU_USED 0
switches 0:5c4d7b2438d3 121 #endif
switches 0:5c4d7b2438d3 122 #else
switches 0:5c4d7b2438d3 123 #define __FPU_USED 0
switches 0:5c4d7b2438d3 124 #endif
switches 0:5c4d7b2438d3 125
switches 0:5c4d7b2438d3 126 #elif defined ( __GNUC__ )
switches 0:5c4d7b2438d3 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
switches 0:5c4d7b2438d3 128 #if (__FPU_PRESENT == 1)
switches 0:5c4d7b2438d3 129 #define __FPU_USED 1
switches 0:5c4d7b2438d3 130 #else
switches 0:5c4d7b2438d3 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:5c4d7b2438d3 132 #define __FPU_USED 0
switches 0:5c4d7b2438d3 133 #endif
switches 0:5c4d7b2438d3 134 #else
switches 0:5c4d7b2438d3 135 #define __FPU_USED 0
switches 0:5c4d7b2438d3 136 #endif
switches 0:5c4d7b2438d3 137
switches 0:5c4d7b2438d3 138 #elif defined ( __ICCARM__ )
switches 0:5c4d7b2438d3 139 #if defined __ARMVFP__
switches 0:5c4d7b2438d3 140 #if (__FPU_PRESENT == 1)
switches 0:5c4d7b2438d3 141 #define __FPU_USED 1
switches 0:5c4d7b2438d3 142 #else
switches 0:5c4d7b2438d3 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:5c4d7b2438d3 144 #define __FPU_USED 0
switches 0:5c4d7b2438d3 145 #endif
switches 0:5c4d7b2438d3 146 #else
switches 0:5c4d7b2438d3 147 #define __FPU_USED 0
switches 0:5c4d7b2438d3 148 #endif
switches 0:5c4d7b2438d3 149
switches 0:5c4d7b2438d3 150 #elif defined ( __TMS470__ )
switches 0:5c4d7b2438d3 151 #if defined __TI_VFP_SUPPORT__
switches 0:5c4d7b2438d3 152 #if (__FPU_PRESENT == 1)
switches 0:5c4d7b2438d3 153 #define __FPU_USED 1
switches 0:5c4d7b2438d3 154 #else
switches 0:5c4d7b2438d3 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:5c4d7b2438d3 156 #define __FPU_USED 0
switches 0:5c4d7b2438d3 157 #endif
switches 0:5c4d7b2438d3 158 #else
switches 0:5c4d7b2438d3 159 #define __FPU_USED 0
switches 0:5c4d7b2438d3 160 #endif
switches 0:5c4d7b2438d3 161
switches 0:5c4d7b2438d3 162 #elif defined ( __TASKING__ )
switches 0:5c4d7b2438d3 163 #if defined __FPU_VFP__
switches 0:5c4d7b2438d3 164 #if (__FPU_PRESENT == 1)
switches 0:5c4d7b2438d3 165 #define __FPU_USED 1
switches 0:5c4d7b2438d3 166 #else
switches 0:5c4d7b2438d3 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:5c4d7b2438d3 168 #define __FPU_USED 0
switches 0:5c4d7b2438d3 169 #endif
switches 0:5c4d7b2438d3 170 #else
switches 0:5c4d7b2438d3 171 #define __FPU_USED 0
switches 0:5c4d7b2438d3 172 #endif
switches 0:5c4d7b2438d3 173
switches 0:5c4d7b2438d3 174 #elif defined ( __CSMC__ ) /* Cosmic */
switches 0:5c4d7b2438d3 175 #if ( __CSMC__ & 0x400) // FPU present for parser
switches 0:5c4d7b2438d3 176 #if (__FPU_PRESENT == 1)
switches 0:5c4d7b2438d3 177 #define __FPU_USED 1
switches 0:5c4d7b2438d3 178 #else
switches 0:5c4d7b2438d3 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:5c4d7b2438d3 180 #define __FPU_USED 0
switches 0:5c4d7b2438d3 181 #endif
switches 0:5c4d7b2438d3 182 #else
switches 0:5c4d7b2438d3 183 #define __FPU_USED 0
switches 0:5c4d7b2438d3 184 #endif
switches 0:5c4d7b2438d3 185 #endif
switches 0:5c4d7b2438d3 186
switches 0:5c4d7b2438d3 187 #include <stdint.h> /* standard types definitions */
switches 0:5c4d7b2438d3 188 #include <core_cmInstr.h> /* Core Instruction Access */
switches 0:5c4d7b2438d3 189 #include <core_cmFunc.h> /* Core Function Access */
switches 0:5c4d7b2438d3 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
switches 0:5c4d7b2438d3 191
switches 0:5c4d7b2438d3 192 #ifdef __cplusplus
switches 0:5c4d7b2438d3 193 }
switches 0:5c4d7b2438d3 194 #endif
switches 0:5c4d7b2438d3 195
switches 0:5c4d7b2438d3 196 #endif /* __CORE_CM4_H_GENERIC */
switches 0:5c4d7b2438d3 197
switches 0:5c4d7b2438d3 198 #ifndef __CMSIS_GENERIC
switches 0:5c4d7b2438d3 199
switches 0:5c4d7b2438d3 200 #ifndef __CORE_CM4_H_DEPENDANT
switches 0:5c4d7b2438d3 201 #define __CORE_CM4_H_DEPENDANT
switches 0:5c4d7b2438d3 202
switches 0:5c4d7b2438d3 203 #ifdef __cplusplus
switches 0:5c4d7b2438d3 204 extern "C" {
switches 0:5c4d7b2438d3 205 #endif
switches 0:5c4d7b2438d3 206
switches 0:5c4d7b2438d3 207 /* check device defines and use defaults */
switches 0:5c4d7b2438d3 208 #if defined __CHECK_DEVICE_DEFINES
switches 0:5c4d7b2438d3 209 #ifndef __CM4_REV
switches 0:5c4d7b2438d3 210 #define __CM4_REV 0x0000
switches 0:5c4d7b2438d3 211 #warning "__CM4_REV not defined in device header file; using default!"
switches 0:5c4d7b2438d3 212 #endif
switches 0:5c4d7b2438d3 213
switches 0:5c4d7b2438d3 214 #ifndef __FPU_PRESENT
switches 0:5c4d7b2438d3 215 #define __FPU_PRESENT 0
switches 0:5c4d7b2438d3 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
switches 0:5c4d7b2438d3 217 #endif
switches 0:5c4d7b2438d3 218
switches 0:5c4d7b2438d3 219 #ifndef __MPU_PRESENT
switches 0:5c4d7b2438d3 220 #define __MPU_PRESENT 0
switches 0:5c4d7b2438d3 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
switches 0:5c4d7b2438d3 222 #endif
switches 0:5c4d7b2438d3 223
switches 0:5c4d7b2438d3 224 #ifndef __NVIC_PRIO_BITS
switches 0:5c4d7b2438d3 225 #define __NVIC_PRIO_BITS 4
switches 0:5c4d7b2438d3 226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
switches 0:5c4d7b2438d3 227 #endif
switches 0:5c4d7b2438d3 228
switches 0:5c4d7b2438d3 229 #ifndef __Vendor_SysTickConfig
switches 0:5c4d7b2438d3 230 #define __Vendor_SysTickConfig 0
switches 0:5c4d7b2438d3 231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
switches 0:5c4d7b2438d3 232 #endif
switches 0:5c4d7b2438d3 233 #endif
switches 0:5c4d7b2438d3 234
switches 0:5c4d7b2438d3 235 /* IO definitions (access restrictions to peripheral registers) */
switches 0:5c4d7b2438d3 236 /**
switches 0:5c4d7b2438d3 237 \defgroup CMSIS_glob_defs CMSIS Global Defines
switches 0:5c4d7b2438d3 238
switches 0:5c4d7b2438d3 239 <strong>IO Type Qualifiers</strong> are used
switches 0:5c4d7b2438d3 240 \li to specify the access to peripheral variables.
switches 0:5c4d7b2438d3 241 \li for automatic generation of peripheral register debug information.
switches 0:5c4d7b2438d3 242 */
switches 0:5c4d7b2438d3 243 #ifdef __cplusplus
switches 0:5c4d7b2438d3 244 #define __I volatile /*!< Defines 'read only' permissions */
switches 0:5c4d7b2438d3 245 #else
switches 0:5c4d7b2438d3 246 #define __I volatile const /*!< Defines 'read only' permissions */
switches 0:5c4d7b2438d3 247 #endif
switches 0:5c4d7b2438d3 248 #define __O volatile /*!< Defines 'write only' permissions */
switches 0:5c4d7b2438d3 249 #define __IO volatile /*!< Defines 'read / write' permissions */
switches 0:5c4d7b2438d3 250
switches 0:5c4d7b2438d3 251 #ifdef __cplusplus
switches 0:5c4d7b2438d3 252 #define __IM volatile /*!< Defines 'read only' permissions */
switches 0:5c4d7b2438d3 253 #else
switches 0:5c4d7b2438d3 254 #define __IM volatile const /*!< Defines 'read only' permissions */
switches 0:5c4d7b2438d3 255 #endif
switches 0:5c4d7b2438d3 256 #define __OM volatile /*!< Defines 'write only' permissions */
switches 0:5c4d7b2438d3 257 #define __IOM volatile /*!< Defines 'read / write' permissions */
switches 0:5c4d7b2438d3 258
switches 0:5c4d7b2438d3 259 /*@} end of group Cortex_M4 */
switches 0:5c4d7b2438d3 260
switches 0:5c4d7b2438d3 261
switches 0:5c4d7b2438d3 262
switches 0:5c4d7b2438d3 263 /*******************************************************************************
switches 0:5c4d7b2438d3 264 * Register Abstraction
switches 0:5c4d7b2438d3 265 Core Register contain:
switches 0:5c4d7b2438d3 266 - Core Register
switches 0:5c4d7b2438d3 267 - Core NVIC Register
switches 0:5c4d7b2438d3 268 - Core SCB Register
switches 0:5c4d7b2438d3 269 - Core SysTick Register
switches 0:5c4d7b2438d3 270 - Core Debug Register
switches 0:5c4d7b2438d3 271 - Core MPU Register
switches 0:5c4d7b2438d3 272 - Core FPU Register
switches 0:5c4d7b2438d3 273 ******************************************************************************/
switches 0:5c4d7b2438d3 274 /** \defgroup CMSIS_core_register Defines and Type Definitions
switches 0:5c4d7b2438d3 275 \brief Type definitions and defines for Cortex-M processor based devices.
switches 0:5c4d7b2438d3 276 */
switches 0:5c4d7b2438d3 277
switches 0:5c4d7b2438d3 278 /** \ingroup CMSIS_core_register
switches 0:5c4d7b2438d3 279 \defgroup CMSIS_CORE Status and Control Registers
switches 0:5c4d7b2438d3 280 \brief Core Register type definitions.
switches 0:5c4d7b2438d3 281 @{
switches 0:5c4d7b2438d3 282 */
switches 0:5c4d7b2438d3 283
switches 0:5c4d7b2438d3 284 /** \brief Union type to access the Application Program Status Register (APSR).
switches 0:5c4d7b2438d3 285 */
switches 0:5c4d7b2438d3 286 typedef union
switches 0:5c4d7b2438d3 287 {
switches 0:5c4d7b2438d3 288 struct
switches 0:5c4d7b2438d3 289 {
switches 0:5c4d7b2438d3 290 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
switches 0:5c4d7b2438d3 291 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
switches 0:5c4d7b2438d3 292 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
switches 0:5c4d7b2438d3 293 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
switches 0:5c4d7b2438d3 294 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
switches 0:5c4d7b2438d3 295 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
switches 0:5c4d7b2438d3 296 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
switches 0:5c4d7b2438d3 297 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
switches 0:5c4d7b2438d3 298 } b; /*!< Structure used for bit access */
switches 0:5c4d7b2438d3 299 uint32_t w; /*!< Type used for word access */
switches 0:5c4d7b2438d3 300 } APSR_Type;
switches 0:5c4d7b2438d3 301
switches 0:5c4d7b2438d3 302 /* APSR Register Definitions */
switches 0:5c4d7b2438d3 303 #define APSR_N_Pos 31 /*!< APSR: N Position */
switches 0:5c4d7b2438d3 304 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
switches 0:5c4d7b2438d3 305
switches 0:5c4d7b2438d3 306 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
switches 0:5c4d7b2438d3 307 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
switches 0:5c4d7b2438d3 308
switches 0:5c4d7b2438d3 309 #define APSR_C_Pos 29 /*!< APSR: C Position */
switches 0:5c4d7b2438d3 310 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
switches 0:5c4d7b2438d3 311
switches 0:5c4d7b2438d3 312 #define APSR_V_Pos 28 /*!< APSR: V Position */
switches 0:5c4d7b2438d3 313 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
switches 0:5c4d7b2438d3 314
switches 0:5c4d7b2438d3 315 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
switches 0:5c4d7b2438d3 316 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
switches 0:5c4d7b2438d3 317
switches 0:5c4d7b2438d3 318 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
switches 0:5c4d7b2438d3 319 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
switches 0:5c4d7b2438d3 320
switches 0:5c4d7b2438d3 321
switches 0:5c4d7b2438d3 322 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
switches 0:5c4d7b2438d3 323 */
switches 0:5c4d7b2438d3 324 typedef union
switches 0:5c4d7b2438d3 325 {
switches 0:5c4d7b2438d3 326 struct
switches 0:5c4d7b2438d3 327 {
switches 0:5c4d7b2438d3 328 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
switches 0:5c4d7b2438d3 329 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
switches 0:5c4d7b2438d3 330 } b; /*!< Structure used for bit access */
switches 0:5c4d7b2438d3 331 uint32_t w; /*!< Type used for word access */
switches 0:5c4d7b2438d3 332 } IPSR_Type;
switches 0:5c4d7b2438d3 333
switches 0:5c4d7b2438d3 334 /* IPSR Register Definitions */
switches 0:5c4d7b2438d3 335 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
switches 0:5c4d7b2438d3 336 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
switches 0:5c4d7b2438d3 337
switches 0:5c4d7b2438d3 338
switches 0:5c4d7b2438d3 339 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
switches 0:5c4d7b2438d3 340 */
switches 0:5c4d7b2438d3 341 typedef union
switches 0:5c4d7b2438d3 342 {
switches 0:5c4d7b2438d3 343 struct
switches 0:5c4d7b2438d3 344 {
switches 0:5c4d7b2438d3 345 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
switches 0:5c4d7b2438d3 346 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
switches 0:5c4d7b2438d3 347 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
switches 0:5c4d7b2438d3 348 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
switches 0:5c4d7b2438d3 349 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
switches 0:5c4d7b2438d3 350 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
switches 0:5c4d7b2438d3 351 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
switches 0:5c4d7b2438d3 352 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
switches 0:5c4d7b2438d3 353 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
switches 0:5c4d7b2438d3 354 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
switches 0:5c4d7b2438d3 355 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
switches 0:5c4d7b2438d3 356 } b; /*!< Structure used for bit access */
switches 0:5c4d7b2438d3 357 uint32_t w; /*!< Type used for word access */
switches 0:5c4d7b2438d3 358 } xPSR_Type;
switches 0:5c4d7b2438d3 359
switches 0:5c4d7b2438d3 360 /* xPSR Register Definitions */
switches 0:5c4d7b2438d3 361 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
switches 0:5c4d7b2438d3 362 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
switches 0:5c4d7b2438d3 363
switches 0:5c4d7b2438d3 364 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
switches 0:5c4d7b2438d3 365 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
switches 0:5c4d7b2438d3 366
switches 0:5c4d7b2438d3 367 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
switches 0:5c4d7b2438d3 368 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
switches 0:5c4d7b2438d3 369
switches 0:5c4d7b2438d3 370 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
switches 0:5c4d7b2438d3 371 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
switches 0:5c4d7b2438d3 372
switches 0:5c4d7b2438d3 373 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
switches 0:5c4d7b2438d3 374 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
switches 0:5c4d7b2438d3 375
switches 0:5c4d7b2438d3 376 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
switches 0:5c4d7b2438d3 377 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
switches 0:5c4d7b2438d3 378
switches 0:5c4d7b2438d3 379 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
switches 0:5c4d7b2438d3 380 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
switches 0:5c4d7b2438d3 381
switches 0:5c4d7b2438d3 382 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
switches 0:5c4d7b2438d3 383 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
switches 0:5c4d7b2438d3 384
switches 0:5c4d7b2438d3 385 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
switches 0:5c4d7b2438d3 386 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
switches 0:5c4d7b2438d3 387
switches 0:5c4d7b2438d3 388
switches 0:5c4d7b2438d3 389 /** \brief Union type to access the Control Registers (CONTROL).
switches 0:5c4d7b2438d3 390 */
switches 0:5c4d7b2438d3 391 typedef union
switches 0:5c4d7b2438d3 392 {
switches 0:5c4d7b2438d3 393 struct
switches 0:5c4d7b2438d3 394 {
switches 0:5c4d7b2438d3 395 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
switches 0:5c4d7b2438d3 396 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
switches 0:5c4d7b2438d3 397 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
switches 0:5c4d7b2438d3 398 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
switches 0:5c4d7b2438d3 399 } b; /*!< Structure used for bit access */
switches 0:5c4d7b2438d3 400 uint32_t w; /*!< Type used for word access */
switches 0:5c4d7b2438d3 401 } CONTROL_Type;
switches 0:5c4d7b2438d3 402
switches 0:5c4d7b2438d3 403 /* CONTROL Register Definitions */
switches 0:5c4d7b2438d3 404 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
switches 0:5c4d7b2438d3 405 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
switches 0:5c4d7b2438d3 406
switches 0:5c4d7b2438d3 407 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
switches 0:5c4d7b2438d3 408 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
switches 0:5c4d7b2438d3 409
switches 0:5c4d7b2438d3 410 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
switches 0:5c4d7b2438d3 411 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
switches 0:5c4d7b2438d3 412
switches 0:5c4d7b2438d3 413 /*@} end of group CMSIS_CORE */
switches 0:5c4d7b2438d3 414
switches 0:5c4d7b2438d3 415
switches 0:5c4d7b2438d3 416 /** \ingroup CMSIS_core_register
switches 0:5c4d7b2438d3 417 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
switches 0:5c4d7b2438d3 418 \brief Type definitions for the NVIC Registers
switches 0:5c4d7b2438d3 419 @{
switches 0:5c4d7b2438d3 420 */
switches 0:5c4d7b2438d3 421
switches 0:5c4d7b2438d3 422 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
switches 0:5c4d7b2438d3 423 */
switches 0:5c4d7b2438d3 424 typedef struct
switches 0:5c4d7b2438d3 425 {
switches 0:5c4d7b2438d3 426 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
switches 0:5c4d7b2438d3 427 uint32_t RESERVED0[24];
switches 0:5c4d7b2438d3 428 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
switches 0:5c4d7b2438d3 429 uint32_t RSERVED1[24];
switches 0:5c4d7b2438d3 430 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
switches 0:5c4d7b2438d3 431 uint32_t RESERVED2[24];
switches 0:5c4d7b2438d3 432 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
switches 0:5c4d7b2438d3 433 uint32_t RESERVED3[24];
switches 0:5c4d7b2438d3 434 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
switches 0:5c4d7b2438d3 435 uint32_t RESERVED4[56];
switches 0:5c4d7b2438d3 436 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
switches 0:5c4d7b2438d3 437 uint32_t RESERVED5[644];
switches 0:5c4d7b2438d3 438 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
switches 0:5c4d7b2438d3 439 } NVIC_Type;
switches 0:5c4d7b2438d3 440
switches 0:5c4d7b2438d3 441 /* Software Triggered Interrupt Register Definitions */
switches 0:5c4d7b2438d3 442 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
switches 0:5c4d7b2438d3 443 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
switches 0:5c4d7b2438d3 444
switches 0:5c4d7b2438d3 445 /*@} end of group CMSIS_NVIC */
switches 0:5c4d7b2438d3 446
switches 0:5c4d7b2438d3 447
switches 0:5c4d7b2438d3 448 /** \ingroup CMSIS_core_register
switches 0:5c4d7b2438d3 449 \defgroup CMSIS_SCB System Control Block (SCB)
switches 0:5c4d7b2438d3 450 \brief Type definitions for the System Control Block Registers
switches 0:5c4d7b2438d3 451 @{
switches 0:5c4d7b2438d3 452 */
switches 0:5c4d7b2438d3 453
switches 0:5c4d7b2438d3 454 /** \brief Structure type to access the System Control Block (SCB).
switches 0:5c4d7b2438d3 455 */
switches 0:5c4d7b2438d3 456 typedef struct
switches 0:5c4d7b2438d3 457 {
switches 0:5c4d7b2438d3 458 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
switches 0:5c4d7b2438d3 459 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
switches 0:5c4d7b2438d3 460 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
switches 0:5c4d7b2438d3 461 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
switches 0:5c4d7b2438d3 462 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
switches 0:5c4d7b2438d3 463 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
switches 0:5c4d7b2438d3 464 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
switches 0:5c4d7b2438d3 465 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
switches 0:5c4d7b2438d3 466 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
switches 0:5c4d7b2438d3 467 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
switches 0:5c4d7b2438d3 468 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
switches 0:5c4d7b2438d3 469 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
switches 0:5c4d7b2438d3 470 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
switches 0:5c4d7b2438d3 471 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
switches 0:5c4d7b2438d3 472 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
switches 0:5c4d7b2438d3 473 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
switches 0:5c4d7b2438d3 474 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
switches 0:5c4d7b2438d3 475 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
switches 0:5c4d7b2438d3 476 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
switches 0:5c4d7b2438d3 477 uint32_t RESERVED0[5];
switches 0:5c4d7b2438d3 478 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
switches 0:5c4d7b2438d3 479 } SCB_Type;
switches 0:5c4d7b2438d3 480
switches 0:5c4d7b2438d3 481 /* SCB CPUID Register Definitions */
switches 0:5c4d7b2438d3 482 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
switches 0:5c4d7b2438d3 483 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
switches 0:5c4d7b2438d3 484
switches 0:5c4d7b2438d3 485 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
switches 0:5c4d7b2438d3 486 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
switches 0:5c4d7b2438d3 487
switches 0:5c4d7b2438d3 488 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
switches 0:5c4d7b2438d3 489 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
switches 0:5c4d7b2438d3 490
switches 0:5c4d7b2438d3 491 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
switches 0:5c4d7b2438d3 492 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
switches 0:5c4d7b2438d3 493
switches 0:5c4d7b2438d3 494 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
switches 0:5c4d7b2438d3 495 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
switches 0:5c4d7b2438d3 496
switches 0:5c4d7b2438d3 497 /* SCB Interrupt Control State Register Definitions */
switches 0:5c4d7b2438d3 498 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
switches 0:5c4d7b2438d3 499 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
switches 0:5c4d7b2438d3 500
switches 0:5c4d7b2438d3 501 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
switches 0:5c4d7b2438d3 502 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
switches 0:5c4d7b2438d3 503
switches 0:5c4d7b2438d3 504 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
switches 0:5c4d7b2438d3 505 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
switches 0:5c4d7b2438d3 506
switches 0:5c4d7b2438d3 507 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
switches 0:5c4d7b2438d3 508 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
switches 0:5c4d7b2438d3 509
switches 0:5c4d7b2438d3 510 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
switches 0:5c4d7b2438d3 511 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
switches 0:5c4d7b2438d3 512
switches 0:5c4d7b2438d3 513 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
switches 0:5c4d7b2438d3 514 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
switches 0:5c4d7b2438d3 515
switches 0:5c4d7b2438d3 516 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
switches 0:5c4d7b2438d3 517 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
switches 0:5c4d7b2438d3 518
switches 0:5c4d7b2438d3 519 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
switches 0:5c4d7b2438d3 520 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
switches 0:5c4d7b2438d3 521
switches 0:5c4d7b2438d3 522 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
switches 0:5c4d7b2438d3 523 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
switches 0:5c4d7b2438d3 524
switches 0:5c4d7b2438d3 525 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
switches 0:5c4d7b2438d3 526 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
switches 0:5c4d7b2438d3 527
switches 0:5c4d7b2438d3 528 /* SCB Vector Table Offset Register Definitions */
switches 0:5c4d7b2438d3 529 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
switches 0:5c4d7b2438d3 530 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
switches 0:5c4d7b2438d3 531
switches 0:5c4d7b2438d3 532 /* SCB Application Interrupt and Reset Control Register Definitions */
switches 0:5c4d7b2438d3 533 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
switches 0:5c4d7b2438d3 534 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
switches 0:5c4d7b2438d3 535
switches 0:5c4d7b2438d3 536 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
switches 0:5c4d7b2438d3 537 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
switches 0:5c4d7b2438d3 538
switches 0:5c4d7b2438d3 539 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
switches 0:5c4d7b2438d3 540 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
switches 0:5c4d7b2438d3 541
switches 0:5c4d7b2438d3 542 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
switches 0:5c4d7b2438d3 543 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
switches 0:5c4d7b2438d3 544
switches 0:5c4d7b2438d3 545 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
switches 0:5c4d7b2438d3 546 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
switches 0:5c4d7b2438d3 547
switches 0:5c4d7b2438d3 548 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
switches 0:5c4d7b2438d3 549 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
switches 0:5c4d7b2438d3 550
switches 0:5c4d7b2438d3 551 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
switches 0:5c4d7b2438d3 552 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
switches 0:5c4d7b2438d3 553
switches 0:5c4d7b2438d3 554 /* SCB System Control Register Definitions */
switches 0:5c4d7b2438d3 555 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
switches 0:5c4d7b2438d3 556 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
switches 0:5c4d7b2438d3 557
switches 0:5c4d7b2438d3 558 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
switches 0:5c4d7b2438d3 559 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
switches 0:5c4d7b2438d3 560
switches 0:5c4d7b2438d3 561 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
switches 0:5c4d7b2438d3 562 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
switches 0:5c4d7b2438d3 563
switches 0:5c4d7b2438d3 564 /* SCB Configuration Control Register Definitions */
switches 0:5c4d7b2438d3 565 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
switches 0:5c4d7b2438d3 566 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
switches 0:5c4d7b2438d3 567
switches 0:5c4d7b2438d3 568 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
switches 0:5c4d7b2438d3 569 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
switches 0:5c4d7b2438d3 570
switches 0:5c4d7b2438d3 571 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
switches 0:5c4d7b2438d3 572 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
switches 0:5c4d7b2438d3 573
switches 0:5c4d7b2438d3 574 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
switches 0:5c4d7b2438d3 575 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
switches 0:5c4d7b2438d3 576
switches 0:5c4d7b2438d3 577 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
switches 0:5c4d7b2438d3 578 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
switches 0:5c4d7b2438d3 579
switches 0:5c4d7b2438d3 580 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
switches 0:5c4d7b2438d3 581 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
switches 0:5c4d7b2438d3 582
switches 0:5c4d7b2438d3 583 /* SCB System Handler Control and State Register Definitions */
switches 0:5c4d7b2438d3 584 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
switches 0:5c4d7b2438d3 585 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
switches 0:5c4d7b2438d3 586
switches 0:5c4d7b2438d3 587 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
switches 0:5c4d7b2438d3 588 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
switches 0:5c4d7b2438d3 589
switches 0:5c4d7b2438d3 590 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
switches 0:5c4d7b2438d3 591 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
switches 0:5c4d7b2438d3 592
switches 0:5c4d7b2438d3 593 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
switches 0:5c4d7b2438d3 594 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
switches 0:5c4d7b2438d3 595
switches 0:5c4d7b2438d3 596 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
switches 0:5c4d7b2438d3 597 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
switches 0:5c4d7b2438d3 598
switches 0:5c4d7b2438d3 599 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
switches 0:5c4d7b2438d3 600 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
switches 0:5c4d7b2438d3 601
switches 0:5c4d7b2438d3 602 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
switches 0:5c4d7b2438d3 603 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
switches 0:5c4d7b2438d3 604
switches 0:5c4d7b2438d3 605 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
switches 0:5c4d7b2438d3 606 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
switches 0:5c4d7b2438d3 607
switches 0:5c4d7b2438d3 608 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
switches 0:5c4d7b2438d3 609 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
switches 0:5c4d7b2438d3 610
switches 0:5c4d7b2438d3 611 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
switches 0:5c4d7b2438d3 612 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
switches 0:5c4d7b2438d3 613
switches 0:5c4d7b2438d3 614 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
switches 0:5c4d7b2438d3 615 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
switches 0:5c4d7b2438d3 616
switches 0:5c4d7b2438d3 617 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
switches 0:5c4d7b2438d3 618 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
switches 0:5c4d7b2438d3 619
switches 0:5c4d7b2438d3 620 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
switches 0:5c4d7b2438d3 621 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
switches 0:5c4d7b2438d3 622
switches 0:5c4d7b2438d3 623 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
switches 0:5c4d7b2438d3 624 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
switches 0:5c4d7b2438d3 625
switches 0:5c4d7b2438d3 626 /* SCB Configurable Fault Status Registers Definitions */
switches 0:5c4d7b2438d3 627 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
switches 0:5c4d7b2438d3 628 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
switches 0:5c4d7b2438d3 629
switches 0:5c4d7b2438d3 630 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
switches 0:5c4d7b2438d3 631 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
switches 0:5c4d7b2438d3 632
switches 0:5c4d7b2438d3 633 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
switches 0:5c4d7b2438d3 634 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
switches 0:5c4d7b2438d3 635
switches 0:5c4d7b2438d3 636 /* SCB Hard Fault Status Registers Definitions */
switches 0:5c4d7b2438d3 637 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
switches 0:5c4d7b2438d3 638 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
switches 0:5c4d7b2438d3 639
switches 0:5c4d7b2438d3 640 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
switches 0:5c4d7b2438d3 641 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
switches 0:5c4d7b2438d3 642
switches 0:5c4d7b2438d3 643 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
switches 0:5c4d7b2438d3 644 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
switches 0:5c4d7b2438d3 645
switches 0:5c4d7b2438d3 646 /* SCB Debug Fault Status Register Definitions */
switches 0:5c4d7b2438d3 647 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
switches 0:5c4d7b2438d3 648 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
switches 0:5c4d7b2438d3 649
switches 0:5c4d7b2438d3 650 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
switches 0:5c4d7b2438d3 651 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
switches 0:5c4d7b2438d3 652
switches 0:5c4d7b2438d3 653 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
switches 0:5c4d7b2438d3 654 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
switches 0:5c4d7b2438d3 655
switches 0:5c4d7b2438d3 656 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
switches 0:5c4d7b2438d3 657 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
switches 0:5c4d7b2438d3 658
switches 0:5c4d7b2438d3 659 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
switches 0:5c4d7b2438d3 660 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
switches 0:5c4d7b2438d3 661
switches 0:5c4d7b2438d3 662 /*@} end of group CMSIS_SCB */
switches 0:5c4d7b2438d3 663
switches 0:5c4d7b2438d3 664
switches 0:5c4d7b2438d3 665 /** \ingroup CMSIS_core_register
switches 0:5c4d7b2438d3 666 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
switches 0:5c4d7b2438d3 667 \brief Type definitions for the System Control and ID Register not in the SCB
switches 0:5c4d7b2438d3 668 @{
switches 0:5c4d7b2438d3 669 */
switches 0:5c4d7b2438d3 670
switches 0:5c4d7b2438d3 671 /** \brief Structure type to access the System Control and ID Register not in the SCB.
switches 0:5c4d7b2438d3 672 */
switches 0:5c4d7b2438d3 673 typedef struct
switches 0:5c4d7b2438d3 674 {
switches 0:5c4d7b2438d3 675 uint32_t RESERVED0[1];
switches 0:5c4d7b2438d3 676 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
switches 0:5c4d7b2438d3 677 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
switches 0:5c4d7b2438d3 678 } SCnSCB_Type;
switches 0:5c4d7b2438d3 679
switches 0:5c4d7b2438d3 680 /* Interrupt Controller Type Register Definitions */
switches 0:5c4d7b2438d3 681 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
switches 0:5c4d7b2438d3 682 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
switches 0:5c4d7b2438d3 683
switches 0:5c4d7b2438d3 684 /* Auxiliary Control Register Definitions */
switches 0:5c4d7b2438d3 685 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
switches 0:5c4d7b2438d3 686 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
switches 0:5c4d7b2438d3 687
switches 0:5c4d7b2438d3 688 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
switches 0:5c4d7b2438d3 689 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
switches 0:5c4d7b2438d3 690
switches 0:5c4d7b2438d3 691 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
switches 0:5c4d7b2438d3 692 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
switches 0:5c4d7b2438d3 693
switches 0:5c4d7b2438d3 694 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
switches 0:5c4d7b2438d3 695 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
switches 0:5c4d7b2438d3 696
switches 0:5c4d7b2438d3 697 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
switches 0:5c4d7b2438d3 698 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
switches 0:5c4d7b2438d3 699
switches 0:5c4d7b2438d3 700 /*@} end of group CMSIS_SCnotSCB */
switches 0:5c4d7b2438d3 701
switches 0:5c4d7b2438d3 702
switches 0:5c4d7b2438d3 703 /** \ingroup CMSIS_core_register
switches 0:5c4d7b2438d3 704 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
switches 0:5c4d7b2438d3 705 \brief Type definitions for the System Timer Registers.
switches 0:5c4d7b2438d3 706 @{
switches 0:5c4d7b2438d3 707 */
switches 0:5c4d7b2438d3 708
switches 0:5c4d7b2438d3 709 /** \brief Structure type to access the System Timer (SysTick).
switches 0:5c4d7b2438d3 710 */
switches 0:5c4d7b2438d3 711 typedef struct
switches 0:5c4d7b2438d3 712 {
switches 0:5c4d7b2438d3 713 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
switches 0:5c4d7b2438d3 714 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
switches 0:5c4d7b2438d3 715 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
switches 0:5c4d7b2438d3 716 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
switches 0:5c4d7b2438d3 717 } SysTick_Type;
switches 0:5c4d7b2438d3 718
switches 0:5c4d7b2438d3 719 /* SysTick Control / Status Register Definitions */
switches 0:5c4d7b2438d3 720 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
switches 0:5c4d7b2438d3 721 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
switches 0:5c4d7b2438d3 722
switches 0:5c4d7b2438d3 723 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
switches 0:5c4d7b2438d3 724 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
switches 0:5c4d7b2438d3 725
switches 0:5c4d7b2438d3 726 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
switches 0:5c4d7b2438d3 727 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
switches 0:5c4d7b2438d3 728
switches 0:5c4d7b2438d3 729 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
switches 0:5c4d7b2438d3 730 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
switches 0:5c4d7b2438d3 731
switches 0:5c4d7b2438d3 732 /* SysTick Reload Register Definitions */
switches 0:5c4d7b2438d3 733 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
switches 0:5c4d7b2438d3 734 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
switches 0:5c4d7b2438d3 735
switches 0:5c4d7b2438d3 736 /* SysTick Current Register Definitions */
switches 0:5c4d7b2438d3 737 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
switches 0:5c4d7b2438d3 738 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
switches 0:5c4d7b2438d3 739
switches 0:5c4d7b2438d3 740 /* SysTick Calibration Register Definitions */
switches 0:5c4d7b2438d3 741 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
switches 0:5c4d7b2438d3 742 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
switches 0:5c4d7b2438d3 743
switches 0:5c4d7b2438d3 744 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
switches 0:5c4d7b2438d3 745 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
switches 0:5c4d7b2438d3 746
switches 0:5c4d7b2438d3 747 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
switches 0:5c4d7b2438d3 748 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
switches 0:5c4d7b2438d3 749
switches 0:5c4d7b2438d3 750 /*@} end of group CMSIS_SysTick */
switches 0:5c4d7b2438d3 751
switches 0:5c4d7b2438d3 752
switches 0:5c4d7b2438d3 753 /** \ingroup CMSIS_core_register
switches 0:5c4d7b2438d3 754 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
switches 0:5c4d7b2438d3 755 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
switches 0:5c4d7b2438d3 756 @{
switches 0:5c4d7b2438d3 757 */
switches 0:5c4d7b2438d3 758
switches 0:5c4d7b2438d3 759 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
switches 0:5c4d7b2438d3 760 */
switches 0:5c4d7b2438d3 761 typedef struct
switches 0:5c4d7b2438d3 762 {
switches 0:5c4d7b2438d3 763 __O union
switches 0:5c4d7b2438d3 764 {
switches 0:5c4d7b2438d3 765 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
switches 0:5c4d7b2438d3 766 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
switches 0:5c4d7b2438d3 767 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
switches 0:5c4d7b2438d3 768 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
switches 0:5c4d7b2438d3 769 uint32_t RESERVED0[864];
switches 0:5c4d7b2438d3 770 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
switches 0:5c4d7b2438d3 771 uint32_t RESERVED1[15];
switches 0:5c4d7b2438d3 772 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
switches 0:5c4d7b2438d3 773 uint32_t RESERVED2[15];
switches 0:5c4d7b2438d3 774 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
switches 0:5c4d7b2438d3 775 uint32_t RESERVED3[29];
switches 0:5c4d7b2438d3 776 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
switches 0:5c4d7b2438d3 777 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
switches 0:5c4d7b2438d3 778 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
switches 0:5c4d7b2438d3 779 uint32_t RESERVED4[43];
switches 0:5c4d7b2438d3 780 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
switches 0:5c4d7b2438d3 781 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
switches 0:5c4d7b2438d3 782 uint32_t RESERVED5[6];
switches 0:5c4d7b2438d3 783 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
switches 0:5c4d7b2438d3 784 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
switches 0:5c4d7b2438d3 785 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
switches 0:5c4d7b2438d3 786 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
switches 0:5c4d7b2438d3 787 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
switches 0:5c4d7b2438d3 788 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
switches 0:5c4d7b2438d3 789 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
switches 0:5c4d7b2438d3 790 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
switches 0:5c4d7b2438d3 791 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
switches 0:5c4d7b2438d3 792 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
switches 0:5c4d7b2438d3 793 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
switches 0:5c4d7b2438d3 794 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
switches 0:5c4d7b2438d3 795 } ITM_Type;
switches 0:5c4d7b2438d3 796
switches 0:5c4d7b2438d3 797 /* ITM Trace Privilege Register Definitions */
switches 0:5c4d7b2438d3 798 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
switches 0:5c4d7b2438d3 799 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
switches 0:5c4d7b2438d3 800
switches 0:5c4d7b2438d3 801 /* ITM Trace Control Register Definitions */
switches 0:5c4d7b2438d3 802 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
switches 0:5c4d7b2438d3 803 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
switches 0:5c4d7b2438d3 804
switches 0:5c4d7b2438d3 805 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
switches 0:5c4d7b2438d3 806 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
switches 0:5c4d7b2438d3 807
switches 0:5c4d7b2438d3 808 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
switches 0:5c4d7b2438d3 809 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
switches 0:5c4d7b2438d3 810
switches 0:5c4d7b2438d3 811 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
switches 0:5c4d7b2438d3 812 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
switches 0:5c4d7b2438d3 813
switches 0:5c4d7b2438d3 814 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
switches 0:5c4d7b2438d3 815 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
switches 0:5c4d7b2438d3 816
switches 0:5c4d7b2438d3 817 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
switches 0:5c4d7b2438d3 818 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
switches 0:5c4d7b2438d3 819
switches 0:5c4d7b2438d3 820 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
switches 0:5c4d7b2438d3 821 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
switches 0:5c4d7b2438d3 822
switches 0:5c4d7b2438d3 823 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
switches 0:5c4d7b2438d3 824 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
switches 0:5c4d7b2438d3 825
switches 0:5c4d7b2438d3 826 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
switches 0:5c4d7b2438d3 827 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
switches 0:5c4d7b2438d3 828
switches 0:5c4d7b2438d3 829 /* ITM Integration Write Register Definitions */
switches 0:5c4d7b2438d3 830 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
switches 0:5c4d7b2438d3 831 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
switches 0:5c4d7b2438d3 832
switches 0:5c4d7b2438d3 833 /* ITM Integration Read Register Definitions */
switches 0:5c4d7b2438d3 834 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
switches 0:5c4d7b2438d3 835 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
switches 0:5c4d7b2438d3 836
switches 0:5c4d7b2438d3 837 /* ITM Integration Mode Control Register Definitions */
switches 0:5c4d7b2438d3 838 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
switches 0:5c4d7b2438d3 839 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
switches 0:5c4d7b2438d3 840
switches 0:5c4d7b2438d3 841 /* ITM Lock Status Register Definitions */
switches 0:5c4d7b2438d3 842 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
switches 0:5c4d7b2438d3 843 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
switches 0:5c4d7b2438d3 844
switches 0:5c4d7b2438d3 845 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
switches 0:5c4d7b2438d3 846 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
switches 0:5c4d7b2438d3 847
switches 0:5c4d7b2438d3 848 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
switches 0:5c4d7b2438d3 849 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
switches 0:5c4d7b2438d3 850
switches 0:5c4d7b2438d3 851 /*@}*/ /* end of group CMSIS_ITM */
switches 0:5c4d7b2438d3 852
switches 0:5c4d7b2438d3 853
switches 0:5c4d7b2438d3 854 /** \ingroup CMSIS_core_register
switches 0:5c4d7b2438d3 855 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
switches 0:5c4d7b2438d3 856 \brief Type definitions for the Data Watchpoint and Trace (DWT)
switches 0:5c4d7b2438d3 857 @{
switches 0:5c4d7b2438d3 858 */
switches 0:5c4d7b2438d3 859
switches 0:5c4d7b2438d3 860 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
switches 0:5c4d7b2438d3 861 */
switches 0:5c4d7b2438d3 862 typedef struct
switches 0:5c4d7b2438d3 863 {
switches 0:5c4d7b2438d3 864 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
switches 0:5c4d7b2438d3 865 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
switches 0:5c4d7b2438d3 866 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
switches 0:5c4d7b2438d3 867 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
switches 0:5c4d7b2438d3 868 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
switches 0:5c4d7b2438d3 869 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
switches 0:5c4d7b2438d3 870 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
switches 0:5c4d7b2438d3 871 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
switches 0:5c4d7b2438d3 872 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
switches 0:5c4d7b2438d3 873 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
switches 0:5c4d7b2438d3 874 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
switches 0:5c4d7b2438d3 875 uint32_t RESERVED0[1];
switches 0:5c4d7b2438d3 876 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
switches 0:5c4d7b2438d3 877 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
switches 0:5c4d7b2438d3 878 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
switches 0:5c4d7b2438d3 879 uint32_t RESERVED1[1];
switches 0:5c4d7b2438d3 880 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
switches 0:5c4d7b2438d3 881 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
switches 0:5c4d7b2438d3 882 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
switches 0:5c4d7b2438d3 883 uint32_t RESERVED2[1];
switches 0:5c4d7b2438d3 884 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
switches 0:5c4d7b2438d3 885 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
switches 0:5c4d7b2438d3 886 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
switches 0:5c4d7b2438d3 887 } DWT_Type;
switches 0:5c4d7b2438d3 888
switches 0:5c4d7b2438d3 889 /* DWT Control Register Definitions */
switches 0:5c4d7b2438d3 890 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
switches 0:5c4d7b2438d3 891 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
switches 0:5c4d7b2438d3 892
switches 0:5c4d7b2438d3 893 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
switches 0:5c4d7b2438d3 894 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
switches 0:5c4d7b2438d3 895
switches 0:5c4d7b2438d3 896 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
switches 0:5c4d7b2438d3 897 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
switches 0:5c4d7b2438d3 898
switches 0:5c4d7b2438d3 899 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
switches 0:5c4d7b2438d3 900 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
switches 0:5c4d7b2438d3 901
switches 0:5c4d7b2438d3 902 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
switches 0:5c4d7b2438d3 903 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
switches 0:5c4d7b2438d3 904
switches 0:5c4d7b2438d3 905 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
switches 0:5c4d7b2438d3 906 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
switches 0:5c4d7b2438d3 907
switches 0:5c4d7b2438d3 908 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
switches 0:5c4d7b2438d3 909 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
switches 0:5c4d7b2438d3 910
switches 0:5c4d7b2438d3 911 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
switches 0:5c4d7b2438d3 912 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
switches 0:5c4d7b2438d3 913
switches 0:5c4d7b2438d3 914 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
switches 0:5c4d7b2438d3 915 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
switches 0:5c4d7b2438d3 916
switches 0:5c4d7b2438d3 917 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
switches 0:5c4d7b2438d3 918 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
switches 0:5c4d7b2438d3 919
switches 0:5c4d7b2438d3 920 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
switches 0:5c4d7b2438d3 921 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
switches 0:5c4d7b2438d3 922
switches 0:5c4d7b2438d3 923 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
switches 0:5c4d7b2438d3 924 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
switches 0:5c4d7b2438d3 925
switches 0:5c4d7b2438d3 926 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
switches 0:5c4d7b2438d3 927 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
switches 0:5c4d7b2438d3 928
switches 0:5c4d7b2438d3 929 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
switches 0:5c4d7b2438d3 930 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
switches 0:5c4d7b2438d3 931
switches 0:5c4d7b2438d3 932 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
switches 0:5c4d7b2438d3 933 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
switches 0:5c4d7b2438d3 934
switches 0:5c4d7b2438d3 935 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
switches 0:5c4d7b2438d3 936 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
switches 0:5c4d7b2438d3 937
switches 0:5c4d7b2438d3 938 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
switches 0:5c4d7b2438d3 939 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
switches 0:5c4d7b2438d3 940
switches 0:5c4d7b2438d3 941 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
switches 0:5c4d7b2438d3 942 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
switches 0:5c4d7b2438d3 943
switches 0:5c4d7b2438d3 944 /* DWT CPI Count Register Definitions */
switches 0:5c4d7b2438d3 945 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
switches 0:5c4d7b2438d3 946 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
switches 0:5c4d7b2438d3 947
switches 0:5c4d7b2438d3 948 /* DWT Exception Overhead Count Register Definitions */
switches 0:5c4d7b2438d3 949 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
switches 0:5c4d7b2438d3 950 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
switches 0:5c4d7b2438d3 951
switches 0:5c4d7b2438d3 952 /* DWT Sleep Count Register Definitions */
switches 0:5c4d7b2438d3 953 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
switches 0:5c4d7b2438d3 954 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
switches 0:5c4d7b2438d3 955
switches 0:5c4d7b2438d3 956 /* DWT LSU Count Register Definitions */
switches 0:5c4d7b2438d3 957 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
switches 0:5c4d7b2438d3 958 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
switches 0:5c4d7b2438d3 959
switches 0:5c4d7b2438d3 960 /* DWT Folded-instruction Count Register Definitions */
switches 0:5c4d7b2438d3 961 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
switches 0:5c4d7b2438d3 962 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
switches 0:5c4d7b2438d3 963
switches 0:5c4d7b2438d3 964 /* DWT Comparator Mask Register Definitions */
switches 0:5c4d7b2438d3 965 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
switches 0:5c4d7b2438d3 966 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
switches 0:5c4d7b2438d3 967
switches 0:5c4d7b2438d3 968 /* DWT Comparator Function Register Definitions */
switches 0:5c4d7b2438d3 969 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
switches 0:5c4d7b2438d3 970 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
switches 0:5c4d7b2438d3 971
switches 0:5c4d7b2438d3 972 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
switches 0:5c4d7b2438d3 973 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
switches 0:5c4d7b2438d3 974
switches 0:5c4d7b2438d3 975 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
switches 0:5c4d7b2438d3 976 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
switches 0:5c4d7b2438d3 977
switches 0:5c4d7b2438d3 978 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
switches 0:5c4d7b2438d3 979 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
switches 0:5c4d7b2438d3 980
switches 0:5c4d7b2438d3 981 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
switches 0:5c4d7b2438d3 982 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
switches 0:5c4d7b2438d3 983
switches 0:5c4d7b2438d3 984 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
switches 0:5c4d7b2438d3 985 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
switches 0:5c4d7b2438d3 986
switches 0:5c4d7b2438d3 987 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
switches 0:5c4d7b2438d3 988 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
switches 0:5c4d7b2438d3 989
switches 0:5c4d7b2438d3 990 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
switches 0:5c4d7b2438d3 991 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
switches 0:5c4d7b2438d3 992
switches 0:5c4d7b2438d3 993 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
switches 0:5c4d7b2438d3 994 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
switches 0:5c4d7b2438d3 995
switches 0:5c4d7b2438d3 996 /*@}*/ /* end of group CMSIS_DWT */
switches 0:5c4d7b2438d3 997
switches 0:5c4d7b2438d3 998
switches 0:5c4d7b2438d3 999 /** \ingroup CMSIS_core_register
switches 0:5c4d7b2438d3 1000 \defgroup CMSIS_TPI Trace Port Interface (TPI)
switches 0:5c4d7b2438d3 1001 \brief Type definitions for the Trace Port Interface (TPI)
switches 0:5c4d7b2438d3 1002 @{
switches 0:5c4d7b2438d3 1003 */
switches 0:5c4d7b2438d3 1004
switches 0:5c4d7b2438d3 1005 /** \brief Structure type to access the Trace Port Interface Register (TPI).
switches 0:5c4d7b2438d3 1006 */
switches 0:5c4d7b2438d3 1007 typedef struct
switches 0:5c4d7b2438d3 1008 {
switches 0:5c4d7b2438d3 1009 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
switches 0:5c4d7b2438d3 1010 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
switches 0:5c4d7b2438d3 1011 uint32_t RESERVED0[2];
switches 0:5c4d7b2438d3 1012 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
switches 0:5c4d7b2438d3 1013 uint32_t RESERVED1[55];
switches 0:5c4d7b2438d3 1014 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
switches 0:5c4d7b2438d3 1015 uint32_t RESERVED2[131];
switches 0:5c4d7b2438d3 1016 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
switches 0:5c4d7b2438d3 1017 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
switches 0:5c4d7b2438d3 1018 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
switches 0:5c4d7b2438d3 1019 uint32_t RESERVED3[759];
switches 0:5c4d7b2438d3 1020 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
switches 0:5c4d7b2438d3 1021 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
switches 0:5c4d7b2438d3 1022 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
switches 0:5c4d7b2438d3 1023 uint32_t RESERVED4[1];
switches 0:5c4d7b2438d3 1024 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
switches 0:5c4d7b2438d3 1025 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
switches 0:5c4d7b2438d3 1026 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
switches 0:5c4d7b2438d3 1027 uint32_t RESERVED5[39];
switches 0:5c4d7b2438d3 1028 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
switches 0:5c4d7b2438d3 1029 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
switches 0:5c4d7b2438d3 1030 uint32_t RESERVED7[8];
switches 0:5c4d7b2438d3 1031 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
switches 0:5c4d7b2438d3 1032 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
switches 0:5c4d7b2438d3 1033 } TPI_Type;
switches 0:5c4d7b2438d3 1034
switches 0:5c4d7b2438d3 1035 /* TPI Asynchronous Clock Prescaler Register Definitions */
switches 0:5c4d7b2438d3 1036 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
switches 0:5c4d7b2438d3 1037 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
switches 0:5c4d7b2438d3 1038
switches 0:5c4d7b2438d3 1039 /* TPI Selected Pin Protocol Register Definitions */
switches 0:5c4d7b2438d3 1040 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
switches 0:5c4d7b2438d3 1041 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
switches 0:5c4d7b2438d3 1042
switches 0:5c4d7b2438d3 1043 /* TPI Formatter and Flush Status Register Definitions */
switches 0:5c4d7b2438d3 1044 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
switches 0:5c4d7b2438d3 1045 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
switches 0:5c4d7b2438d3 1046
switches 0:5c4d7b2438d3 1047 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
switches 0:5c4d7b2438d3 1048 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
switches 0:5c4d7b2438d3 1049
switches 0:5c4d7b2438d3 1050 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
switches 0:5c4d7b2438d3 1051 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
switches 0:5c4d7b2438d3 1052
switches 0:5c4d7b2438d3 1053 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
switches 0:5c4d7b2438d3 1054 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
switches 0:5c4d7b2438d3 1055
switches 0:5c4d7b2438d3 1056 /* TPI Formatter and Flush Control Register Definitions */
switches 0:5c4d7b2438d3 1057 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
switches 0:5c4d7b2438d3 1058 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
switches 0:5c4d7b2438d3 1059
switches 0:5c4d7b2438d3 1060 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
switches 0:5c4d7b2438d3 1061 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
switches 0:5c4d7b2438d3 1062
switches 0:5c4d7b2438d3 1063 /* TPI TRIGGER Register Definitions */
switches 0:5c4d7b2438d3 1064 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
switches 0:5c4d7b2438d3 1065 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
switches 0:5c4d7b2438d3 1066
switches 0:5c4d7b2438d3 1067 /* TPI Integration ETM Data Register Definitions (FIFO0) */
switches 0:5c4d7b2438d3 1068 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
switches 0:5c4d7b2438d3 1069 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
switches 0:5c4d7b2438d3 1070
switches 0:5c4d7b2438d3 1071 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
switches 0:5c4d7b2438d3 1072 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
switches 0:5c4d7b2438d3 1073
switches 0:5c4d7b2438d3 1074 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
switches 0:5c4d7b2438d3 1075 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
switches 0:5c4d7b2438d3 1076
switches 0:5c4d7b2438d3 1077 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
switches 0:5c4d7b2438d3 1078 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
switches 0:5c4d7b2438d3 1079
switches 0:5c4d7b2438d3 1080 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
switches 0:5c4d7b2438d3 1081 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
switches 0:5c4d7b2438d3 1082
switches 0:5c4d7b2438d3 1083 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
switches 0:5c4d7b2438d3 1084 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
switches 0:5c4d7b2438d3 1085
switches 0:5c4d7b2438d3 1086 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
switches 0:5c4d7b2438d3 1087 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
switches 0:5c4d7b2438d3 1088
switches 0:5c4d7b2438d3 1089 /* TPI ITATBCTR2 Register Definitions */
switches 0:5c4d7b2438d3 1090 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
switches 0:5c4d7b2438d3 1091 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
switches 0:5c4d7b2438d3 1092
switches 0:5c4d7b2438d3 1093 /* TPI Integration ITM Data Register Definitions (FIFO1) */
switches 0:5c4d7b2438d3 1094 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
switches 0:5c4d7b2438d3 1095 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
switches 0:5c4d7b2438d3 1096
switches 0:5c4d7b2438d3 1097 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
switches 0:5c4d7b2438d3 1098 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
switches 0:5c4d7b2438d3 1099
switches 0:5c4d7b2438d3 1100 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
switches 0:5c4d7b2438d3 1101 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
switches 0:5c4d7b2438d3 1102
switches 0:5c4d7b2438d3 1103 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
switches 0:5c4d7b2438d3 1104 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
switches 0:5c4d7b2438d3 1105
switches 0:5c4d7b2438d3 1106 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
switches 0:5c4d7b2438d3 1107 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
switches 0:5c4d7b2438d3 1108
switches 0:5c4d7b2438d3 1109 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
switches 0:5c4d7b2438d3 1110 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
switches 0:5c4d7b2438d3 1111
switches 0:5c4d7b2438d3 1112 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
switches 0:5c4d7b2438d3 1113 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
switches 0:5c4d7b2438d3 1114
switches 0:5c4d7b2438d3 1115 /* TPI ITATBCTR0 Register Definitions */
switches 0:5c4d7b2438d3 1116 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
switches 0:5c4d7b2438d3 1117 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
switches 0:5c4d7b2438d3 1118
switches 0:5c4d7b2438d3 1119 /* TPI Integration Mode Control Register Definitions */
switches 0:5c4d7b2438d3 1120 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
switches 0:5c4d7b2438d3 1121 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
switches 0:5c4d7b2438d3 1122
switches 0:5c4d7b2438d3 1123 /* TPI DEVID Register Definitions */
switches 0:5c4d7b2438d3 1124 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
switches 0:5c4d7b2438d3 1125 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
switches 0:5c4d7b2438d3 1126
switches 0:5c4d7b2438d3 1127 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
switches 0:5c4d7b2438d3 1128 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
switches 0:5c4d7b2438d3 1129
switches 0:5c4d7b2438d3 1130 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
switches 0:5c4d7b2438d3 1131 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
switches 0:5c4d7b2438d3 1132
switches 0:5c4d7b2438d3 1133 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
switches 0:5c4d7b2438d3 1134 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
switches 0:5c4d7b2438d3 1135
switches 0:5c4d7b2438d3 1136 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
switches 0:5c4d7b2438d3 1137 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
switches 0:5c4d7b2438d3 1138
switches 0:5c4d7b2438d3 1139 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
switches 0:5c4d7b2438d3 1140 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
switches 0:5c4d7b2438d3 1141
switches 0:5c4d7b2438d3 1142 /* TPI DEVTYPE Register Definitions */
switches 0:5c4d7b2438d3 1143 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
switches 0:5c4d7b2438d3 1144 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
switches 0:5c4d7b2438d3 1145
switches 0:5c4d7b2438d3 1146 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
switches 0:5c4d7b2438d3 1147 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
switches 0:5c4d7b2438d3 1148
switches 0:5c4d7b2438d3 1149 /*@}*/ /* end of group CMSIS_TPI */
switches 0:5c4d7b2438d3 1150
switches 0:5c4d7b2438d3 1151
switches 0:5c4d7b2438d3 1152 #if (__MPU_PRESENT == 1)
switches 0:5c4d7b2438d3 1153 /** \ingroup CMSIS_core_register
switches 0:5c4d7b2438d3 1154 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
switches 0:5c4d7b2438d3 1155 \brief Type definitions for the Memory Protection Unit (MPU)
switches 0:5c4d7b2438d3 1156 @{
switches 0:5c4d7b2438d3 1157 */
switches 0:5c4d7b2438d3 1158
switches 0:5c4d7b2438d3 1159 /** \brief Structure type to access the Memory Protection Unit (MPU).
switches 0:5c4d7b2438d3 1160 */
switches 0:5c4d7b2438d3 1161 typedef struct
switches 0:5c4d7b2438d3 1162 {
switches 0:5c4d7b2438d3 1163 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
switches 0:5c4d7b2438d3 1164 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
switches 0:5c4d7b2438d3 1165 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
switches 0:5c4d7b2438d3 1166 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
switches 0:5c4d7b2438d3 1167 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
switches 0:5c4d7b2438d3 1168 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
switches 0:5c4d7b2438d3 1169 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
switches 0:5c4d7b2438d3 1170 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
switches 0:5c4d7b2438d3 1171 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
switches 0:5c4d7b2438d3 1172 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
switches 0:5c4d7b2438d3 1173 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
switches 0:5c4d7b2438d3 1174 } MPU_Type;
switches 0:5c4d7b2438d3 1175
switches 0:5c4d7b2438d3 1176 /* MPU Type Register */
switches 0:5c4d7b2438d3 1177 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
switches 0:5c4d7b2438d3 1178 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
switches 0:5c4d7b2438d3 1179
switches 0:5c4d7b2438d3 1180 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
switches 0:5c4d7b2438d3 1181 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
switches 0:5c4d7b2438d3 1182
switches 0:5c4d7b2438d3 1183 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
switches 0:5c4d7b2438d3 1184 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
switches 0:5c4d7b2438d3 1185
switches 0:5c4d7b2438d3 1186 /* MPU Control Register */
switches 0:5c4d7b2438d3 1187 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
switches 0:5c4d7b2438d3 1188 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
switches 0:5c4d7b2438d3 1189
switches 0:5c4d7b2438d3 1190 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
switches 0:5c4d7b2438d3 1191 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
switches 0:5c4d7b2438d3 1192
switches 0:5c4d7b2438d3 1193 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
switches 0:5c4d7b2438d3 1194 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
switches 0:5c4d7b2438d3 1195
switches 0:5c4d7b2438d3 1196 /* MPU Region Number Register */
switches 0:5c4d7b2438d3 1197 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
switches 0:5c4d7b2438d3 1198 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
switches 0:5c4d7b2438d3 1199
switches 0:5c4d7b2438d3 1200 /* MPU Region Base Address Register */
switches 0:5c4d7b2438d3 1201 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
switches 0:5c4d7b2438d3 1202 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
switches 0:5c4d7b2438d3 1203
switches 0:5c4d7b2438d3 1204 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
switches 0:5c4d7b2438d3 1205 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
switches 0:5c4d7b2438d3 1206
switches 0:5c4d7b2438d3 1207 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
switches 0:5c4d7b2438d3 1208 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
switches 0:5c4d7b2438d3 1209
switches 0:5c4d7b2438d3 1210 /* MPU Region Attribute and Size Register */
switches 0:5c4d7b2438d3 1211 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
switches 0:5c4d7b2438d3 1212 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
switches 0:5c4d7b2438d3 1213
switches 0:5c4d7b2438d3 1214 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
switches 0:5c4d7b2438d3 1215 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
switches 0:5c4d7b2438d3 1216
switches 0:5c4d7b2438d3 1217 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
switches 0:5c4d7b2438d3 1218 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
switches 0:5c4d7b2438d3 1219
switches 0:5c4d7b2438d3 1220 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
switches 0:5c4d7b2438d3 1221 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
switches 0:5c4d7b2438d3 1222
switches 0:5c4d7b2438d3 1223 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
switches 0:5c4d7b2438d3 1224 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
switches 0:5c4d7b2438d3 1225
switches 0:5c4d7b2438d3 1226 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
switches 0:5c4d7b2438d3 1227 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
switches 0:5c4d7b2438d3 1228
switches 0:5c4d7b2438d3 1229 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
switches 0:5c4d7b2438d3 1230 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
switches 0:5c4d7b2438d3 1231
switches 0:5c4d7b2438d3 1232 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
switches 0:5c4d7b2438d3 1233 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
switches 0:5c4d7b2438d3 1234
switches 0:5c4d7b2438d3 1235 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
switches 0:5c4d7b2438d3 1236 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
switches 0:5c4d7b2438d3 1237
switches 0:5c4d7b2438d3 1238 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
switches 0:5c4d7b2438d3 1239 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
switches 0:5c4d7b2438d3 1240
switches 0:5c4d7b2438d3 1241 /*@} end of group CMSIS_MPU */
switches 0:5c4d7b2438d3 1242 #endif
switches 0:5c4d7b2438d3 1243
switches 0:5c4d7b2438d3 1244
switches 0:5c4d7b2438d3 1245 #if (__FPU_PRESENT == 1)
switches 0:5c4d7b2438d3 1246 /** \ingroup CMSIS_core_register
switches 0:5c4d7b2438d3 1247 \defgroup CMSIS_FPU Floating Point Unit (FPU)
switches 0:5c4d7b2438d3 1248 \brief Type definitions for the Floating Point Unit (FPU)
switches 0:5c4d7b2438d3 1249 @{
switches 0:5c4d7b2438d3 1250 */
switches 0:5c4d7b2438d3 1251
switches 0:5c4d7b2438d3 1252 /** \brief Structure type to access the Floating Point Unit (FPU).
switches 0:5c4d7b2438d3 1253 */
switches 0:5c4d7b2438d3 1254 typedef struct
switches 0:5c4d7b2438d3 1255 {
switches 0:5c4d7b2438d3 1256 uint32_t RESERVED0[1];
switches 0:5c4d7b2438d3 1257 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
switches 0:5c4d7b2438d3 1258 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
switches 0:5c4d7b2438d3 1259 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
switches 0:5c4d7b2438d3 1260 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
switches 0:5c4d7b2438d3 1261 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
switches 0:5c4d7b2438d3 1262 } FPU_Type;
switches 0:5c4d7b2438d3 1263
switches 0:5c4d7b2438d3 1264 /* Floating-Point Context Control Register */
switches 0:5c4d7b2438d3 1265 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
switches 0:5c4d7b2438d3 1266 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
switches 0:5c4d7b2438d3 1267
switches 0:5c4d7b2438d3 1268 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
switches 0:5c4d7b2438d3 1269 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
switches 0:5c4d7b2438d3 1270
switches 0:5c4d7b2438d3 1271 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
switches 0:5c4d7b2438d3 1272 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
switches 0:5c4d7b2438d3 1273
switches 0:5c4d7b2438d3 1274 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
switches 0:5c4d7b2438d3 1275 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
switches 0:5c4d7b2438d3 1276
switches 0:5c4d7b2438d3 1277 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
switches 0:5c4d7b2438d3 1278 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
switches 0:5c4d7b2438d3 1279
switches 0:5c4d7b2438d3 1280 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
switches 0:5c4d7b2438d3 1281 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
switches 0:5c4d7b2438d3 1282
switches 0:5c4d7b2438d3 1283 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
switches 0:5c4d7b2438d3 1284 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
switches 0:5c4d7b2438d3 1285
switches 0:5c4d7b2438d3 1286 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
switches 0:5c4d7b2438d3 1287 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
switches 0:5c4d7b2438d3 1288
switches 0:5c4d7b2438d3 1289 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
switches 0:5c4d7b2438d3 1290 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
switches 0:5c4d7b2438d3 1291
switches 0:5c4d7b2438d3 1292 /* Floating-Point Context Address Register */
switches 0:5c4d7b2438d3 1293 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
switches 0:5c4d7b2438d3 1294 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
switches 0:5c4d7b2438d3 1295
switches 0:5c4d7b2438d3 1296 /* Floating-Point Default Status Control Register */
switches 0:5c4d7b2438d3 1297 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
switches 0:5c4d7b2438d3 1298 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
switches 0:5c4d7b2438d3 1299
switches 0:5c4d7b2438d3 1300 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
switches 0:5c4d7b2438d3 1301 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
switches 0:5c4d7b2438d3 1302
switches 0:5c4d7b2438d3 1303 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
switches 0:5c4d7b2438d3 1304 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
switches 0:5c4d7b2438d3 1305
switches 0:5c4d7b2438d3 1306 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
switches 0:5c4d7b2438d3 1307 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
switches 0:5c4d7b2438d3 1308
switches 0:5c4d7b2438d3 1309 /* Media and FP Feature Register 0 */
switches 0:5c4d7b2438d3 1310 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
switches 0:5c4d7b2438d3 1311 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
switches 0:5c4d7b2438d3 1312
switches 0:5c4d7b2438d3 1313 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
switches 0:5c4d7b2438d3 1314 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
switches 0:5c4d7b2438d3 1315
switches 0:5c4d7b2438d3 1316 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
switches 0:5c4d7b2438d3 1317 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
switches 0:5c4d7b2438d3 1318
switches 0:5c4d7b2438d3 1319 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
switches 0:5c4d7b2438d3 1320 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
switches 0:5c4d7b2438d3 1321
switches 0:5c4d7b2438d3 1322 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
switches 0:5c4d7b2438d3 1323 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
switches 0:5c4d7b2438d3 1324
switches 0:5c4d7b2438d3 1325 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
switches 0:5c4d7b2438d3 1326 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
switches 0:5c4d7b2438d3 1327
switches 0:5c4d7b2438d3 1328 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
switches 0:5c4d7b2438d3 1329 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
switches 0:5c4d7b2438d3 1330
switches 0:5c4d7b2438d3 1331 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
switches 0:5c4d7b2438d3 1332 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
switches 0:5c4d7b2438d3 1333
switches 0:5c4d7b2438d3 1334 /* Media and FP Feature Register 1 */
switches 0:5c4d7b2438d3 1335 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
switches 0:5c4d7b2438d3 1336 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
switches 0:5c4d7b2438d3 1337
switches 0:5c4d7b2438d3 1338 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
switches 0:5c4d7b2438d3 1339 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
switches 0:5c4d7b2438d3 1340
switches 0:5c4d7b2438d3 1341 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
switches 0:5c4d7b2438d3 1342 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
switches 0:5c4d7b2438d3 1343
switches 0:5c4d7b2438d3 1344 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
switches 0:5c4d7b2438d3 1345 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
switches 0:5c4d7b2438d3 1346
switches 0:5c4d7b2438d3 1347 /*@} end of group CMSIS_FPU */
switches 0:5c4d7b2438d3 1348 #endif
switches 0:5c4d7b2438d3 1349
switches 0:5c4d7b2438d3 1350
switches 0:5c4d7b2438d3 1351 /** \ingroup CMSIS_core_register
switches 0:5c4d7b2438d3 1352 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
switches 0:5c4d7b2438d3 1353 \brief Type definitions for the Core Debug Registers
switches 0:5c4d7b2438d3 1354 @{
switches 0:5c4d7b2438d3 1355 */
switches 0:5c4d7b2438d3 1356
switches 0:5c4d7b2438d3 1357 /** \brief Structure type to access the Core Debug Register (CoreDebug).
switches 0:5c4d7b2438d3 1358 */
switches 0:5c4d7b2438d3 1359 typedef struct
switches 0:5c4d7b2438d3 1360 {
switches 0:5c4d7b2438d3 1361 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
switches 0:5c4d7b2438d3 1362 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
switches 0:5c4d7b2438d3 1363 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
switches 0:5c4d7b2438d3 1364 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
switches 0:5c4d7b2438d3 1365 } CoreDebug_Type;
switches 0:5c4d7b2438d3 1366
switches 0:5c4d7b2438d3 1367 /* Debug Halting Control and Status Register */
switches 0:5c4d7b2438d3 1368 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
switches 0:5c4d7b2438d3 1369 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
switches 0:5c4d7b2438d3 1370
switches 0:5c4d7b2438d3 1371 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
switches 0:5c4d7b2438d3 1372 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
switches 0:5c4d7b2438d3 1373
switches 0:5c4d7b2438d3 1374 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
switches 0:5c4d7b2438d3 1375 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
switches 0:5c4d7b2438d3 1376
switches 0:5c4d7b2438d3 1377 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
switches 0:5c4d7b2438d3 1378 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
switches 0:5c4d7b2438d3 1379
switches 0:5c4d7b2438d3 1380 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
switches 0:5c4d7b2438d3 1381 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
switches 0:5c4d7b2438d3 1382
switches 0:5c4d7b2438d3 1383 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
switches 0:5c4d7b2438d3 1384 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
switches 0:5c4d7b2438d3 1385
switches 0:5c4d7b2438d3 1386 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
switches 0:5c4d7b2438d3 1387 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
switches 0:5c4d7b2438d3 1388
switches 0:5c4d7b2438d3 1389 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
switches 0:5c4d7b2438d3 1390 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
switches 0:5c4d7b2438d3 1391
switches 0:5c4d7b2438d3 1392 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
switches 0:5c4d7b2438d3 1393 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
switches 0:5c4d7b2438d3 1394
switches 0:5c4d7b2438d3 1395 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
switches 0:5c4d7b2438d3 1396 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
switches 0:5c4d7b2438d3 1397
switches 0:5c4d7b2438d3 1398 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
switches 0:5c4d7b2438d3 1399 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
switches 0:5c4d7b2438d3 1400
switches 0:5c4d7b2438d3 1401 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
switches 0:5c4d7b2438d3 1402 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
switches 0:5c4d7b2438d3 1403
switches 0:5c4d7b2438d3 1404 /* Debug Core Register Selector Register */
switches 0:5c4d7b2438d3 1405 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
switches 0:5c4d7b2438d3 1406 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
switches 0:5c4d7b2438d3 1407
switches 0:5c4d7b2438d3 1408 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
switches 0:5c4d7b2438d3 1409 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
switches 0:5c4d7b2438d3 1410
switches 0:5c4d7b2438d3 1411 /* Debug Exception and Monitor Control Register */
switches 0:5c4d7b2438d3 1412 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
switches 0:5c4d7b2438d3 1413 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
switches 0:5c4d7b2438d3 1414
switches 0:5c4d7b2438d3 1415 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
switches 0:5c4d7b2438d3 1416 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
switches 0:5c4d7b2438d3 1417
switches 0:5c4d7b2438d3 1418 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
switches 0:5c4d7b2438d3 1419 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
switches 0:5c4d7b2438d3 1420
switches 0:5c4d7b2438d3 1421 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
switches 0:5c4d7b2438d3 1422 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
switches 0:5c4d7b2438d3 1423
switches 0:5c4d7b2438d3 1424 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
switches 0:5c4d7b2438d3 1425 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
switches 0:5c4d7b2438d3 1426
switches 0:5c4d7b2438d3 1427 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
switches 0:5c4d7b2438d3 1428 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
switches 0:5c4d7b2438d3 1429
switches 0:5c4d7b2438d3 1430 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
switches 0:5c4d7b2438d3 1431 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
switches 0:5c4d7b2438d3 1432
switches 0:5c4d7b2438d3 1433 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
switches 0:5c4d7b2438d3 1434 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
switches 0:5c4d7b2438d3 1435
switches 0:5c4d7b2438d3 1436 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
switches 0:5c4d7b2438d3 1437 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
switches 0:5c4d7b2438d3 1438
switches 0:5c4d7b2438d3 1439 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
switches 0:5c4d7b2438d3 1440 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
switches 0:5c4d7b2438d3 1441
switches 0:5c4d7b2438d3 1442 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
switches 0:5c4d7b2438d3 1443 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
switches 0:5c4d7b2438d3 1444
switches 0:5c4d7b2438d3 1445 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
switches 0:5c4d7b2438d3 1446 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
switches 0:5c4d7b2438d3 1447
switches 0:5c4d7b2438d3 1448 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
switches 0:5c4d7b2438d3 1449 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
switches 0:5c4d7b2438d3 1450
switches 0:5c4d7b2438d3 1451 /*@} end of group CMSIS_CoreDebug */
switches 0:5c4d7b2438d3 1452
switches 0:5c4d7b2438d3 1453
switches 0:5c4d7b2438d3 1454 /** \ingroup CMSIS_core_register
switches 0:5c4d7b2438d3 1455 \defgroup CMSIS_core_base Core Definitions
switches 0:5c4d7b2438d3 1456 \brief Definitions for base addresses, unions, and structures.
switches 0:5c4d7b2438d3 1457 @{
switches 0:5c4d7b2438d3 1458 */
switches 0:5c4d7b2438d3 1459
switches 0:5c4d7b2438d3 1460 /* Memory mapping of Cortex-M4 Hardware */
switches 0:5c4d7b2438d3 1461 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
switches 0:5c4d7b2438d3 1462 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
switches 0:5c4d7b2438d3 1463 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
switches 0:5c4d7b2438d3 1464 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
switches 0:5c4d7b2438d3 1465 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
switches 0:5c4d7b2438d3 1466 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
switches 0:5c4d7b2438d3 1467 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
switches 0:5c4d7b2438d3 1468 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
switches 0:5c4d7b2438d3 1469
switches 0:5c4d7b2438d3 1470 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
switches 0:5c4d7b2438d3 1471 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
switches 0:5c4d7b2438d3 1472 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
switches 0:5c4d7b2438d3 1473 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
switches 0:5c4d7b2438d3 1474 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
switches 0:5c4d7b2438d3 1475 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
switches 0:5c4d7b2438d3 1476 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
switches 0:5c4d7b2438d3 1477 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
switches 0:5c4d7b2438d3 1478
switches 0:5c4d7b2438d3 1479 #if (__MPU_PRESENT == 1)
switches 0:5c4d7b2438d3 1480 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
switches 0:5c4d7b2438d3 1481 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
switches 0:5c4d7b2438d3 1482 #endif
switches 0:5c4d7b2438d3 1483
switches 0:5c4d7b2438d3 1484 #if (__FPU_PRESENT == 1)
switches 0:5c4d7b2438d3 1485 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
switches 0:5c4d7b2438d3 1486 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
switches 0:5c4d7b2438d3 1487 #endif
switches 0:5c4d7b2438d3 1488
switches 0:5c4d7b2438d3 1489 /*@} */
switches 0:5c4d7b2438d3 1490
switches 0:5c4d7b2438d3 1491
switches 0:5c4d7b2438d3 1492
switches 0:5c4d7b2438d3 1493 /*******************************************************************************
switches 0:5c4d7b2438d3 1494 * Hardware Abstraction Layer
switches 0:5c4d7b2438d3 1495 Core Function Interface contains:
switches 0:5c4d7b2438d3 1496 - Core NVIC Functions
switches 0:5c4d7b2438d3 1497 - Core SysTick Functions
switches 0:5c4d7b2438d3 1498 - Core Debug Functions
switches 0:5c4d7b2438d3 1499 - Core Register Access Functions
switches 0:5c4d7b2438d3 1500 ******************************************************************************/
switches 0:5c4d7b2438d3 1501 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
switches 0:5c4d7b2438d3 1502 */
switches 0:5c4d7b2438d3 1503
switches 0:5c4d7b2438d3 1504
switches 0:5c4d7b2438d3 1505
switches 0:5c4d7b2438d3 1506 /* ########################## NVIC functions #################################### */
switches 0:5c4d7b2438d3 1507 /** \ingroup CMSIS_Core_FunctionInterface
switches 0:5c4d7b2438d3 1508 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
switches 0:5c4d7b2438d3 1509 \brief Functions that manage interrupts and exceptions via the NVIC.
switches 0:5c4d7b2438d3 1510 @{
switches 0:5c4d7b2438d3 1511 */
switches 0:5c4d7b2438d3 1512
switches 0:5c4d7b2438d3 1513 #ifdef CMSIS_NVIC_VIRTUAL
switches 0:5c4d7b2438d3 1514 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
switches 0:5c4d7b2438d3 1515 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
switches 0:5c4d7b2438d3 1516 #endif
switches 0:5c4d7b2438d3 1517 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
switches 0:5c4d7b2438d3 1518 #else
switches 0:5c4d7b2438d3 1519 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
switches 0:5c4d7b2438d3 1520 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
switches 0:5c4d7b2438d3 1521 #define NVIC_EnableIRQ __NVIC_EnableIRQ
switches 0:5c4d7b2438d3 1522 #define NVIC_DisableIRQ __NVIC_DisableIRQ
switches 0:5c4d7b2438d3 1523 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
switches 0:5c4d7b2438d3 1524 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
switches 0:5c4d7b2438d3 1525 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
switches 0:5c4d7b2438d3 1526 #define NVIC_GetActive __NVIC_GetActive
switches 0:5c4d7b2438d3 1527 #define NVIC_SetPriority __NVIC_SetPriority
switches 0:5c4d7b2438d3 1528 #define NVIC_GetPriority __NVIC_GetPriority
switches 0:5c4d7b2438d3 1529 #define NVIC_SystemReset __NVIC_SystemReset
switches 0:5c4d7b2438d3 1530 #endif /* CMSIS_NVIC_VIRTUAL */
switches 0:5c4d7b2438d3 1531
switches 0:5c4d7b2438d3 1532 #ifdef CMSIS_VECTAB_VIRTUAL
switches 0:5c4d7b2438d3 1533 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
switches 0:5c4d7b2438d3 1534 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
switches 0:5c4d7b2438d3 1535 #endif
switches 0:5c4d7b2438d3 1536 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
switches 0:5c4d7b2438d3 1537 #else
switches 0:5c4d7b2438d3 1538 #define NVIC_SetVector __NVIC_SetVector
switches 0:5c4d7b2438d3 1539 #define NVIC_GetVector __NVIC_GetVector
switches 0:5c4d7b2438d3 1540 #endif /* CMSIS_VECTAB_VIRTUAL */
switches 0:5c4d7b2438d3 1541
switches 0:5c4d7b2438d3 1542
switches 0:5c4d7b2438d3 1543 /** \brief Set Priority Grouping
switches 0:5c4d7b2438d3 1544
switches 0:5c4d7b2438d3 1545 The function sets the priority grouping field using the required unlock sequence.
switches 0:5c4d7b2438d3 1546 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
switches 0:5c4d7b2438d3 1547 Only values from 0..7 are used.
switches 0:5c4d7b2438d3 1548 In case of a conflict between priority grouping and available
switches 0:5c4d7b2438d3 1549 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
switches 0:5c4d7b2438d3 1550
switches 0:5c4d7b2438d3 1551 \param [in] PriorityGroup Priority grouping field.
switches 0:5c4d7b2438d3 1552 */
switches 0:5c4d7b2438d3 1553 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
switches 0:5c4d7b2438d3 1554 {
switches 0:5c4d7b2438d3 1555 uint32_t reg_value;
switches 0:5c4d7b2438d3 1556 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
switches 0:5c4d7b2438d3 1557
switches 0:5c4d7b2438d3 1558 reg_value = SCB->AIRCR; /* read old register configuration */
switches 0:5c4d7b2438d3 1559 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
switches 0:5c4d7b2438d3 1560 reg_value = (reg_value |
switches 0:5c4d7b2438d3 1561 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
switches 0:5c4d7b2438d3 1562 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
switches 0:5c4d7b2438d3 1563 SCB->AIRCR = reg_value;
switches 0:5c4d7b2438d3 1564 }
switches 0:5c4d7b2438d3 1565
switches 0:5c4d7b2438d3 1566
switches 0:5c4d7b2438d3 1567 /** \brief Get Priority Grouping
switches 0:5c4d7b2438d3 1568
switches 0:5c4d7b2438d3 1569 The function reads the priority grouping field from the NVIC Interrupt Controller.
switches 0:5c4d7b2438d3 1570
switches 0:5c4d7b2438d3 1571 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
switches 0:5c4d7b2438d3 1572 */
switches 0:5c4d7b2438d3 1573 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
switches 0:5c4d7b2438d3 1574 {
switches 0:5c4d7b2438d3 1575 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
switches 0:5c4d7b2438d3 1576 }
switches 0:5c4d7b2438d3 1577
switches 0:5c4d7b2438d3 1578
switches 0:5c4d7b2438d3 1579 /** \brief Enable External Interrupt
switches 0:5c4d7b2438d3 1580
switches 0:5c4d7b2438d3 1581 The function enables a device-specific interrupt in the NVIC interrupt controller.
switches 0:5c4d7b2438d3 1582
switches 0:5c4d7b2438d3 1583 \param [in] IRQn External interrupt number. Value cannot be negative.
switches 0:5c4d7b2438d3 1584 */
switches 0:5c4d7b2438d3 1585 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
switches 0:5c4d7b2438d3 1586 {
switches 0:5c4d7b2438d3 1587 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
switches 0:5c4d7b2438d3 1588 }
switches 0:5c4d7b2438d3 1589
switches 0:5c4d7b2438d3 1590
switches 0:5c4d7b2438d3 1591 /** \brief Disable External Interrupt
switches 0:5c4d7b2438d3 1592
switches 0:5c4d7b2438d3 1593 The function disables a device-specific interrupt in the NVIC interrupt controller.
switches 0:5c4d7b2438d3 1594
switches 0:5c4d7b2438d3 1595 \param [in] IRQn External interrupt number. Value cannot be negative.
switches 0:5c4d7b2438d3 1596 */
switches 0:5c4d7b2438d3 1597 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
switches 0:5c4d7b2438d3 1598 {
switches 0:5c4d7b2438d3 1599 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
switches 0:5c4d7b2438d3 1600 }
switches 0:5c4d7b2438d3 1601
switches 0:5c4d7b2438d3 1602
switches 0:5c4d7b2438d3 1603 /** \brief Get Pending Interrupt
switches 0:5c4d7b2438d3 1604
switches 0:5c4d7b2438d3 1605 The function reads the pending register in the NVIC and returns the pending bit
switches 0:5c4d7b2438d3 1606 for the specified interrupt.
switches 0:5c4d7b2438d3 1607
switches 0:5c4d7b2438d3 1608 \param [in] IRQn Interrupt number.
switches 0:5c4d7b2438d3 1609
switches 0:5c4d7b2438d3 1610 \return 0 Interrupt status is not pending.
switches 0:5c4d7b2438d3 1611 \return 1 Interrupt status is pending.
switches 0:5c4d7b2438d3 1612 */
switches 0:5c4d7b2438d3 1613 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
switches 0:5c4d7b2438d3 1614 {
switches 0:5c4d7b2438d3 1615 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
switches 0:5c4d7b2438d3 1616 }
switches 0:5c4d7b2438d3 1617
switches 0:5c4d7b2438d3 1618
switches 0:5c4d7b2438d3 1619 /** \brief Set Pending Interrupt
switches 0:5c4d7b2438d3 1620
switches 0:5c4d7b2438d3 1621 The function sets the pending bit of an external interrupt.
switches 0:5c4d7b2438d3 1622
switches 0:5c4d7b2438d3 1623 \param [in] IRQn Interrupt number. Value cannot be negative.
switches 0:5c4d7b2438d3 1624 */
switches 0:5c4d7b2438d3 1625 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
switches 0:5c4d7b2438d3 1626 {
switches 0:5c4d7b2438d3 1627 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
switches 0:5c4d7b2438d3 1628 }
switches 0:5c4d7b2438d3 1629
switches 0:5c4d7b2438d3 1630
switches 0:5c4d7b2438d3 1631 /** \brief Clear Pending Interrupt
switches 0:5c4d7b2438d3 1632
switches 0:5c4d7b2438d3 1633 The function clears the pending bit of an external interrupt.
switches 0:5c4d7b2438d3 1634
switches 0:5c4d7b2438d3 1635 \param [in] IRQn External interrupt number. Value cannot be negative.
switches 0:5c4d7b2438d3 1636 */
switches 0:5c4d7b2438d3 1637 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
switches 0:5c4d7b2438d3 1638 {
switches 0:5c4d7b2438d3 1639 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
switches 0:5c4d7b2438d3 1640 }
switches 0:5c4d7b2438d3 1641
switches 0:5c4d7b2438d3 1642
switches 0:5c4d7b2438d3 1643 /** \brief Get Active Interrupt
switches 0:5c4d7b2438d3 1644
switches 0:5c4d7b2438d3 1645 The function reads the active register in NVIC and returns the active bit.
switches 0:5c4d7b2438d3 1646
switches 0:5c4d7b2438d3 1647 \param [in] IRQn Interrupt number.
switches 0:5c4d7b2438d3 1648
switches 0:5c4d7b2438d3 1649 \return 0 Interrupt status is not active.
switches 0:5c4d7b2438d3 1650 \return 1 Interrupt status is active.
switches 0:5c4d7b2438d3 1651 */
switches 0:5c4d7b2438d3 1652 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
switches 0:5c4d7b2438d3 1653 {
switches 0:5c4d7b2438d3 1654 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
switches 0:5c4d7b2438d3 1655 }
switches 0:5c4d7b2438d3 1656
switches 0:5c4d7b2438d3 1657
switches 0:5c4d7b2438d3 1658 /** \brief Set Interrupt Priority
switches 0:5c4d7b2438d3 1659
switches 0:5c4d7b2438d3 1660 The function sets the priority of an interrupt.
switches 0:5c4d7b2438d3 1661
switches 0:5c4d7b2438d3 1662 \note The priority cannot be set for every core interrupt.
switches 0:5c4d7b2438d3 1663
switches 0:5c4d7b2438d3 1664 \param [in] IRQn Interrupt number.
switches 0:5c4d7b2438d3 1665 \param [in] priority Priority to set.
switches 0:5c4d7b2438d3 1666 */
switches 0:5c4d7b2438d3 1667 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
switches 0:5c4d7b2438d3 1668 {
switches 0:5c4d7b2438d3 1669 if((int32_t)IRQn < 0) {
switches 0:5c4d7b2438d3 1670 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
switches 0:5c4d7b2438d3 1671 }
switches 0:5c4d7b2438d3 1672 else {
switches 0:5c4d7b2438d3 1673 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
switches 0:5c4d7b2438d3 1674 }
switches 0:5c4d7b2438d3 1675 }
switches 0:5c4d7b2438d3 1676
switches 0:5c4d7b2438d3 1677
switches 0:5c4d7b2438d3 1678 /** \brief Get Interrupt Priority
switches 0:5c4d7b2438d3 1679
switches 0:5c4d7b2438d3 1680 The function reads the priority of an interrupt. The interrupt
switches 0:5c4d7b2438d3 1681 number can be positive to specify an external (device specific)
switches 0:5c4d7b2438d3 1682 interrupt, or negative to specify an internal (core) interrupt.
switches 0:5c4d7b2438d3 1683
switches 0:5c4d7b2438d3 1684
switches 0:5c4d7b2438d3 1685 \param [in] IRQn Interrupt number.
switches 0:5c4d7b2438d3 1686 \return Interrupt Priority. Value is aligned automatically to the implemented
switches 0:5c4d7b2438d3 1687 priority bits of the microcontroller.
switches 0:5c4d7b2438d3 1688 */
switches 0:5c4d7b2438d3 1689 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
switches 0:5c4d7b2438d3 1690 {
switches 0:5c4d7b2438d3 1691
switches 0:5c4d7b2438d3 1692 if((int32_t)IRQn < 0) {
switches 0:5c4d7b2438d3 1693 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
switches 0:5c4d7b2438d3 1694 }
switches 0:5c4d7b2438d3 1695 else {
switches 0:5c4d7b2438d3 1696 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
switches 0:5c4d7b2438d3 1697 }
switches 0:5c4d7b2438d3 1698 }
switches 0:5c4d7b2438d3 1699
switches 0:5c4d7b2438d3 1700
switches 0:5c4d7b2438d3 1701 /** \brief Encode Priority
switches 0:5c4d7b2438d3 1702
switches 0:5c4d7b2438d3 1703 The function encodes the priority for an interrupt with the given priority group,
switches 0:5c4d7b2438d3 1704 preemptive priority value, and subpriority value.
switches 0:5c4d7b2438d3 1705 In case of a conflict between priority grouping and available
switches 0:5c4d7b2438d3 1706 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
switches 0:5c4d7b2438d3 1707
switches 0:5c4d7b2438d3 1708 \param [in] PriorityGroup Used priority group.
switches 0:5c4d7b2438d3 1709 \param [in] PreemptPriority Preemptive priority value (starting from 0).
switches 0:5c4d7b2438d3 1710 \param [in] SubPriority Subpriority value (starting from 0).
switches 0:5c4d7b2438d3 1711 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
switches 0:5c4d7b2438d3 1712 */
switches 0:5c4d7b2438d3 1713 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
switches 0:5c4d7b2438d3 1714 {
switches 0:5c4d7b2438d3 1715 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
switches 0:5c4d7b2438d3 1716 uint32_t PreemptPriorityBits;
switches 0:5c4d7b2438d3 1717 uint32_t SubPriorityBits;
switches 0:5c4d7b2438d3 1718
switches 0:5c4d7b2438d3 1719 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
switches 0:5c4d7b2438d3 1720 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
switches 0:5c4d7b2438d3 1721
switches 0:5c4d7b2438d3 1722 return (
switches 0:5c4d7b2438d3 1723 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
switches 0:5c4d7b2438d3 1724 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
switches 0:5c4d7b2438d3 1725 );
switches 0:5c4d7b2438d3 1726 }
switches 0:5c4d7b2438d3 1727
switches 0:5c4d7b2438d3 1728
switches 0:5c4d7b2438d3 1729 /** \brief Decode Priority
switches 0:5c4d7b2438d3 1730
switches 0:5c4d7b2438d3 1731 The function decodes an interrupt priority value with a given priority group to
switches 0:5c4d7b2438d3 1732 preemptive priority value and subpriority value.
switches 0:5c4d7b2438d3 1733 In case of a conflict between priority grouping and available
switches 0:5c4d7b2438d3 1734 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
switches 0:5c4d7b2438d3 1735
switches 0:5c4d7b2438d3 1736 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
switches 0:5c4d7b2438d3 1737 \param [in] PriorityGroup Used priority group.
switches 0:5c4d7b2438d3 1738 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
switches 0:5c4d7b2438d3 1739 \param [out] pSubPriority Subpriority value (starting from 0).
switches 0:5c4d7b2438d3 1740 */
switches 0:5c4d7b2438d3 1741 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
switches 0:5c4d7b2438d3 1742 {
switches 0:5c4d7b2438d3 1743 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
switches 0:5c4d7b2438d3 1744 uint32_t PreemptPriorityBits;
switches 0:5c4d7b2438d3 1745 uint32_t SubPriorityBits;
switches 0:5c4d7b2438d3 1746
switches 0:5c4d7b2438d3 1747 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
switches 0:5c4d7b2438d3 1748 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
switches 0:5c4d7b2438d3 1749
switches 0:5c4d7b2438d3 1750 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
switches 0:5c4d7b2438d3 1751 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
switches 0:5c4d7b2438d3 1752 }
switches 0:5c4d7b2438d3 1753
switches 0:5c4d7b2438d3 1754
switches 0:5c4d7b2438d3 1755 /** \brief System Reset
switches 0:5c4d7b2438d3 1756
switches 0:5c4d7b2438d3 1757 The function initiates a system reset request to reset the MCU.
switches 0:5c4d7b2438d3 1758 */
switches 0:5c4d7b2438d3 1759 __STATIC_INLINE void __NVIC_SystemReset(void)
switches 0:5c4d7b2438d3 1760 {
switches 0:5c4d7b2438d3 1761 __DSB(); /* Ensure all outstanding memory accesses included
switches 0:5c4d7b2438d3 1762 buffered write are completed before reset */
switches 0:5c4d7b2438d3 1763 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
switches 0:5c4d7b2438d3 1764 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
switches 0:5c4d7b2438d3 1765 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
switches 0:5c4d7b2438d3 1766 __DSB(); /* Ensure completion of memory access */
switches 0:5c4d7b2438d3 1767 while(1) { __NOP(); } /* wait until reset */
switches 0:5c4d7b2438d3 1768 }
switches 0:5c4d7b2438d3 1769
switches 0:5c4d7b2438d3 1770 /*@} end of CMSIS_Core_NVICFunctions */
switches 0:5c4d7b2438d3 1771
switches 0:5c4d7b2438d3 1772
switches 0:5c4d7b2438d3 1773
switches 0:5c4d7b2438d3 1774 /* ################################## SysTick function ############################################ */
switches 0:5c4d7b2438d3 1775 /** \ingroup CMSIS_Core_FunctionInterface
switches 0:5c4d7b2438d3 1776 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
switches 0:5c4d7b2438d3 1777 \brief Functions that configure the System.
switches 0:5c4d7b2438d3 1778 @{
switches 0:5c4d7b2438d3 1779 */
switches 0:5c4d7b2438d3 1780
switches 0:5c4d7b2438d3 1781 #if (__Vendor_SysTickConfig == 0)
switches 0:5c4d7b2438d3 1782
switches 0:5c4d7b2438d3 1783 /** \brief System Tick Configuration
switches 0:5c4d7b2438d3 1784
switches 0:5c4d7b2438d3 1785 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
switches 0:5c4d7b2438d3 1786 Counter is in free running mode to generate periodic interrupts.
switches 0:5c4d7b2438d3 1787
switches 0:5c4d7b2438d3 1788 \param [in] ticks Number of ticks between two interrupts.
switches 0:5c4d7b2438d3 1789
switches 0:5c4d7b2438d3 1790 \return 0 Function succeeded.
switches 0:5c4d7b2438d3 1791 \return 1 Function failed.
switches 0:5c4d7b2438d3 1792
switches 0:5c4d7b2438d3 1793 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
switches 0:5c4d7b2438d3 1794 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
switches 0:5c4d7b2438d3 1795 must contain a vendor-specific implementation of this function.
switches 0:5c4d7b2438d3 1796
switches 0:5c4d7b2438d3 1797 */
switches 0:5c4d7b2438d3 1798 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
switches 0:5c4d7b2438d3 1799 {
switches 0:5c4d7b2438d3 1800 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
switches 0:5c4d7b2438d3 1801
switches 0:5c4d7b2438d3 1802 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
switches 0:5c4d7b2438d3 1803 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
switches 0:5c4d7b2438d3 1804 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
switches 0:5c4d7b2438d3 1805 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
switches 0:5c4d7b2438d3 1806 SysTick_CTRL_TICKINT_Msk |
switches 0:5c4d7b2438d3 1807 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
switches 0:5c4d7b2438d3 1808 return (0UL); /* Function successful */
switches 0:5c4d7b2438d3 1809 }
switches 0:5c4d7b2438d3 1810
switches 0:5c4d7b2438d3 1811 #endif
switches 0:5c4d7b2438d3 1812
switches 0:5c4d7b2438d3 1813 /*@} end of CMSIS_Core_SysTickFunctions */
switches 0:5c4d7b2438d3 1814
switches 0:5c4d7b2438d3 1815
switches 0:5c4d7b2438d3 1816
switches 0:5c4d7b2438d3 1817 /* ##################################### Debug In/Output function ########################################### */
switches 0:5c4d7b2438d3 1818 /** \ingroup CMSIS_Core_FunctionInterface
switches 0:5c4d7b2438d3 1819 \defgroup CMSIS_core_DebugFunctions ITM Functions
switches 0:5c4d7b2438d3 1820 \brief Functions that access the ITM debug interface.
switches 0:5c4d7b2438d3 1821 @{
switches 0:5c4d7b2438d3 1822 */
switches 0:5c4d7b2438d3 1823
switches 0:5c4d7b2438d3 1824 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
switches 0:5c4d7b2438d3 1825 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
switches 0:5c4d7b2438d3 1826
switches 0:5c4d7b2438d3 1827
switches 0:5c4d7b2438d3 1828 /** \brief ITM Send Character
switches 0:5c4d7b2438d3 1829
switches 0:5c4d7b2438d3 1830 The function transmits a character via the ITM channel 0, and
switches 0:5c4d7b2438d3 1831 \li Just returns when no debugger is connected that has booked the output.
switches 0:5c4d7b2438d3 1832 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
switches 0:5c4d7b2438d3 1833
switches 0:5c4d7b2438d3 1834 \param [in] ch Character to transmit.
switches 0:5c4d7b2438d3 1835
switches 0:5c4d7b2438d3 1836 \returns Character to transmit.
switches 0:5c4d7b2438d3 1837 */
switches 0:5c4d7b2438d3 1838 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
switches 0:5c4d7b2438d3 1839 {
switches 0:5c4d7b2438d3 1840 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
switches 0:5c4d7b2438d3 1841 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
switches 0:5c4d7b2438d3 1842 {
switches 0:5c4d7b2438d3 1843 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
switches 0:5c4d7b2438d3 1844 ITM->PORT[0].u8 = (uint8_t)ch;
switches 0:5c4d7b2438d3 1845 }
switches 0:5c4d7b2438d3 1846 return (ch);
switches 0:5c4d7b2438d3 1847 }
switches 0:5c4d7b2438d3 1848
switches 0:5c4d7b2438d3 1849
switches 0:5c4d7b2438d3 1850 /** \brief ITM Receive Character
switches 0:5c4d7b2438d3 1851
switches 0:5c4d7b2438d3 1852 The function inputs a character via the external variable \ref ITM_RxBuffer.
switches 0:5c4d7b2438d3 1853
switches 0:5c4d7b2438d3 1854 \return Received character.
switches 0:5c4d7b2438d3 1855 \return -1 No character pending.
switches 0:5c4d7b2438d3 1856 */
switches 0:5c4d7b2438d3 1857 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
switches 0:5c4d7b2438d3 1858 int32_t ch = -1; /* no character available */
switches 0:5c4d7b2438d3 1859
switches 0:5c4d7b2438d3 1860 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
switches 0:5c4d7b2438d3 1861 ch = ITM_RxBuffer;
switches 0:5c4d7b2438d3 1862 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
switches 0:5c4d7b2438d3 1863 }
switches 0:5c4d7b2438d3 1864
switches 0:5c4d7b2438d3 1865 return (ch);
switches 0:5c4d7b2438d3 1866 }
switches 0:5c4d7b2438d3 1867
switches 0:5c4d7b2438d3 1868
switches 0:5c4d7b2438d3 1869 /** \brief ITM Check Character
switches 0:5c4d7b2438d3 1870
switches 0:5c4d7b2438d3 1871 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
switches 0:5c4d7b2438d3 1872
switches 0:5c4d7b2438d3 1873 \return 0 No character available.
switches 0:5c4d7b2438d3 1874 \return 1 Character available.
switches 0:5c4d7b2438d3 1875 */
switches 0:5c4d7b2438d3 1876 __STATIC_INLINE int32_t ITM_CheckChar (void) {
switches 0:5c4d7b2438d3 1877
switches 0:5c4d7b2438d3 1878 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
switches 0:5c4d7b2438d3 1879 return (0); /* no character available */
switches 0:5c4d7b2438d3 1880 } else {
switches 0:5c4d7b2438d3 1881 return (1); /* character available */
switches 0:5c4d7b2438d3 1882 }
switches 0:5c4d7b2438d3 1883 }
switches 0:5c4d7b2438d3 1884
switches 0:5c4d7b2438d3 1885 /*@} end of CMSIS_core_DebugFunctions */
switches 0:5c4d7b2438d3 1886
switches 0:5c4d7b2438d3 1887
switches 0:5c4d7b2438d3 1888
switches 0:5c4d7b2438d3 1889
switches 0:5c4d7b2438d3 1890 #ifdef __cplusplus
switches 0:5c4d7b2438d3 1891 }
switches 0:5c4d7b2438d3 1892 #endif
switches 0:5c4d7b2438d3 1893
switches 0:5c4d7b2438d3 1894 #endif /* __CORE_CM4_H_DEPENDANT */
switches 0:5c4d7b2438d3 1895
switches 0:5c4d7b2438d3 1896 #endif /* __CMSIS_GENERIC */