Greg Steiert / pegasus_dev

Development mbed library for MAX32630FTHR

Dependents:   blinky_max32630fthr

cmsis/core_ca_mmu.h@3:1198227e6421, 2016-12-16 (annotated)

Committer:
switches
Date:
Fri Dec 16 16:27:57 2016 +0000
Revision:
3:1198227e6421
Parent:
0:5c4d7b2438d3 
Changed ADC scale for MAX32625 platforms to 1.2V full scale to match MAX32630 platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 ;/**************************************************************************//**
switches 0:5c4d7b2438d3 2 ; * @file core_ca_mmu.h
switches 0:5c4d7b2438d3 3 ; * @brief MMU Startup File for A9_MP Device Series
switches 0:5c4d7b2438d3 4 ; * @version V1.01
switches 0:5c4d7b2438d3 5 ; * @date 10 Sept 2014
switches 0:5c4d7b2438d3 6 ; *
switches 0:5c4d7b2438d3 7 ; * @note
switches 0:5c4d7b2438d3 8 ; *
switches 0:5c4d7b2438d3 9 ; ******************************************************************************/
switches 0:5c4d7b2438d3 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
switches 0:5c4d7b2438d3 11 ;
switches 0:5c4d7b2438d3 12 ; All rights reserved.
switches 0:5c4d7b2438d3 13 ; Redistribution and use in source and binary forms, with or without
switches 0:5c4d7b2438d3 14 ; modification, are permitted provided that the following conditions are met:
switches 0:5c4d7b2438d3 15 ; - Redistributions of source code must retain the above copyright
switches 0:5c4d7b2438d3 16 ; notice, this list of conditions and the following disclaimer.
switches 0:5c4d7b2438d3 17 ; - Redistributions in binary form must reproduce the above copyright
switches 0:5c4d7b2438d3 18 ; notice, this list of conditions and the following disclaimer in the
switches 0:5c4d7b2438d3 19 ; documentation and/or other materials provided with the distribution.
switches 0:5c4d7b2438d3 20 ; - Neither the name of ARM nor the names of its contributors may be used
switches 0:5c4d7b2438d3 21 ; to endorse or promote products derived from this software without
switches 0:5c4d7b2438d3 22 ; specific prior written permission.
switches 0:5c4d7b2438d3 23 ; *
switches 0:5c4d7b2438d3 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
switches 0:5c4d7b2438d3 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
switches 0:5c4d7b2438d3 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
switches 0:5c4d7b2438d3 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
switches 0:5c4d7b2438d3 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
switches 0:5c4d7b2438d3 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
switches 0:5c4d7b2438d3 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
switches 0:5c4d7b2438d3 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
switches 0:5c4d7b2438d3 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
switches 0:5c4d7b2438d3 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
switches 0:5c4d7b2438d3 34 ; POSSIBILITY OF SUCH DAMAGE.
switches 0:5c4d7b2438d3 35 ; ---------------------------------------------------------------------------*/
switches 0:5c4d7b2438d3 36
switches 0:5c4d7b2438d3 37 #ifdef __cplusplus
switches 0:5c4d7b2438d3 38 extern "C" {
switches 0:5c4d7b2438d3 39 #endif
switches 0:5c4d7b2438d3 40
switches 0:5c4d7b2438d3 41 #ifndef _MMU_FUNC_H
switches 0:5c4d7b2438d3 42 #define _MMU_FUNC_H
switches 0:5c4d7b2438d3 43
switches 0:5c4d7b2438d3 44 #define SECTION_DESCRIPTOR (0x2)
switches 0:5c4d7b2438d3 45 #define SECTION_MASK (0xFFFFFFFC)
switches 0:5c4d7b2438d3 46
switches 0:5c4d7b2438d3 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
switches 0:5c4d7b2438d3 48 #define SECTION_B_SHIFT (2)
switches 0:5c4d7b2438d3 49 #define SECTION_C_SHIFT (3)
switches 0:5c4d7b2438d3 50 #define SECTION_TEX0_SHIFT (12)
switches 0:5c4d7b2438d3 51 #define SECTION_TEX1_SHIFT (13)
switches 0:5c4d7b2438d3 52 #define SECTION_TEX2_SHIFT (14)
switches 0:5c4d7b2438d3 53
switches 0:5c4d7b2438d3 54 #define SECTION_XN_MASK (0xFFFFFFEF)
switches 0:5c4d7b2438d3 55 #define SECTION_XN_SHIFT (4)
switches 0:5c4d7b2438d3 56
switches 0:5c4d7b2438d3 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
switches 0:5c4d7b2438d3 58 #define SECTION_DOMAIN_SHIFT (5)
switches 0:5c4d7b2438d3 59
switches 0:5c4d7b2438d3 60 #define SECTION_P_MASK (0xFFFFFDFF)
switches 0:5c4d7b2438d3 61 #define SECTION_P_SHIFT (9)
switches 0:5c4d7b2438d3 62
switches 0:5c4d7b2438d3 63 #define SECTION_AP_MASK (0xFFFF73FF)
switches 0:5c4d7b2438d3 64 #define SECTION_AP_SHIFT (10)
switches 0:5c4d7b2438d3 65 #define SECTION_AP2_SHIFT (15)
switches 0:5c4d7b2438d3 66
switches 0:5c4d7b2438d3 67 #define SECTION_S_MASK (0xFFFEFFFF)
switches 0:5c4d7b2438d3 68 #define SECTION_S_SHIFT (16)
switches 0:5c4d7b2438d3 69
switches 0:5c4d7b2438d3 70 #define SECTION_NG_MASK (0xFFFDFFFF)
switches 0:5c4d7b2438d3 71 #define SECTION_NG_SHIFT (17)
switches 0:5c4d7b2438d3 72
switches 0:5c4d7b2438d3 73 #define SECTION_NS_MASK (0xFFF7FFFF)
switches 0:5c4d7b2438d3 74 #define SECTION_NS_SHIFT (19)
switches 0:5c4d7b2438d3 75
switches 0:5c4d7b2438d3 76
switches 0:5c4d7b2438d3 77 #define PAGE_L1_DESCRIPTOR (0x1)
switches 0:5c4d7b2438d3 78 #define PAGE_L1_MASK (0xFFFFFFFC)
switches 0:5c4d7b2438d3 79
switches 0:5c4d7b2438d3 80 #define PAGE_L2_4K_DESC (0x2)
switches 0:5c4d7b2438d3 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
switches 0:5c4d7b2438d3 82
switches 0:5c4d7b2438d3 83 #define PAGE_L2_64K_DESC (0x1)
switches 0:5c4d7b2438d3 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
switches 0:5c4d7b2438d3 85
switches 0:5c4d7b2438d3 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
switches 0:5c4d7b2438d3 87 #define PAGE_4K_B_SHIFT (2)
switches 0:5c4d7b2438d3 88 #define PAGE_4K_C_SHIFT (3)
switches 0:5c4d7b2438d3 89 #define PAGE_4K_TEX0_SHIFT (6)
switches 0:5c4d7b2438d3 90 #define PAGE_4K_TEX1_SHIFT (7)
switches 0:5c4d7b2438d3 91 #define PAGE_4K_TEX2_SHIFT (8)
switches 0:5c4d7b2438d3 92
switches 0:5c4d7b2438d3 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
switches 0:5c4d7b2438d3 94 #define PAGE_64K_B_SHIFT (2)
switches 0:5c4d7b2438d3 95 #define PAGE_64K_C_SHIFT (3)
switches 0:5c4d7b2438d3 96 #define PAGE_64K_TEX0_SHIFT (12)
switches 0:5c4d7b2438d3 97 #define PAGE_64K_TEX1_SHIFT (13)
switches 0:5c4d7b2438d3 98 #define PAGE_64K_TEX2_SHIFT (14)
switches 0:5c4d7b2438d3 99
switches 0:5c4d7b2438d3 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
switches 0:5c4d7b2438d3 101 #define PAGE_B_SHIFT (2)
switches 0:5c4d7b2438d3 102 #define PAGE_C_SHIFT (3)
switches 0:5c4d7b2438d3 103 #define PAGE_TEX_SHIFT (12)
switches 0:5c4d7b2438d3 104
switches 0:5c4d7b2438d3 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
switches 0:5c4d7b2438d3 106 #define PAGE_XN_4K_SHIFT (0)
switches 0:5c4d7b2438d3 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
switches 0:5c4d7b2438d3 108 #define PAGE_XN_64K_SHIFT (15)
switches 0:5c4d7b2438d3 109
switches 0:5c4d7b2438d3 110
switches 0:5c4d7b2438d3 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
switches 0:5c4d7b2438d3 112 #define PAGE_DOMAIN_SHIFT (5)
switches 0:5c4d7b2438d3 113
switches 0:5c4d7b2438d3 114 #define PAGE_P_MASK (0xFFFFFDFF)
switches 0:5c4d7b2438d3 115 #define PAGE_P_SHIFT (9)
switches 0:5c4d7b2438d3 116
switches 0:5c4d7b2438d3 117 #define PAGE_AP_MASK (0xFFFFFDCF)
switches 0:5c4d7b2438d3 118 #define PAGE_AP_SHIFT (4)
switches 0:5c4d7b2438d3 119 #define PAGE_AP2_SHIFT (9)
switches 0:5c4d7b2438d3 120
switches 0:5c4d7b2438d3 121 #define PAGE_S_MASK (0xFFFFFBFF)
switches 0:5c4d7b2438d3 122 #define PAGE_S_SHIFT (10)
switches 0:5c4d7b2438d3 123
switches 0:5c4d7b2438d3 124 #define PAGE_NG_MASK (0xFFFFF7FF)
switches 0:5c4d7b2438d3 125 #define PAGE_NG_SHIFT (11)
switches 0:5c4d7b2438d3 126
switches 0:5c4d7b2438d3 127 #define PAGE_NS_MASK (0xFFFFFFF7)
switches 0:5c4d7b2438d3 128 #define PAGE_NS_SHIFT (3)
switches 0:5c4d7b2438d3 129
switches 0:5c4d7b2438d3 130 #define OFFSET_1M (0x00100000)
switches 0:5c4d7b2438d3 131 #define OFFSET_64K (0x00010000)
switches 0:5c4d7b2438d3 132 #define OFFSET_4K (0x00001000)
switches 0:5c4d7b2438d3 133
switches 0:5c4d7b2438d3 134 #define DESCRIPTOR_FAULT (0x00000000)
switches 0:5c4d7b2438d3 135
switches 0:5c4d7b2438d3 136 /* ########################### MMU Function Access ########################### */
switches 0:5c4d7b2438d3 137 /** \ingroup MMU_FunctionInterface
switches 0:5c4d7b2438d3 138 \defgroup MMU_Functions MMU Functions Interface
switches 0:5c4d7b2438d3 139 @{
switches 0:5c4d7b2438d3 140 */
switches 0:5c4d7b2438d3 141
switches 0:5c4d7b2438d3 142 /* Attributes enumerations */
switches 0:5c4d7b2438d3 143
switches 0:5c4d7b2438d3 144 /* Region size attributes */
switches 0:5c4d7b2438d3 145 typedef enum
switches 0:5c4d7b2438d3 146 {
switches 0:5c4d7b2438d3 147 SECTION,
switches 0:5c4d7b2438d3 148 PAGE_4k,
switches 0:5c4d7b2438d3 149 PAGE_64k,
switches 0:5c4d7b2438d3 150 } mmu_region_size_Type;
switches 0:5c4d7b2438d3 151
switches 0:5c4d7b2438d3 152 /* Region type attributes */
switches 0:5c4d7b2438d3 153 typedef enum
switches 0:5c4d7b2438d3 154 {
switches 0:5c4d7b2438d3 155 NORMAL,
switches 0:5c4d7b2438d3 156 DEVICE,
switches 0:5c4d7b2438d3 157 SHARED_DEVICE,
switches 0:5c4d7b2438d3 158 NON_SHARED_DEVICE,
switches 0:5c4d7b2438d3 159 STRONGLY_ORDERED
switches 0:5c4d7b2438d3 160 } mmu_memory_Type;
switches 0:5c4d7b2438d3 161
switches 0:5c4d7b2438d3 162 /* Region cacheability attributes */
switches 0:5c4d7b2438d3 163 typedef enum
switches 0:5c4d7b2438d3 164 {
switches 0:5c4d7b2438d3 165 NON_CACHEABLE,
switches 0:5c4d7b2438d3 166 WB_WA,
switches 0:5c4d7b2438d3 167 WT,
switches 0:5c4d7b2438d3 168 WB_NO_WA,
switches 0:5c4d7b2438d3 169 } mmu_cacheability_Type;
switches 0:5c4d7b2438d3 170
switches 0:5c4d7b2438d3 171 /* Region parity check attributes */
switches 0:5c4d7b2438d3 172 typedef enum
switches 0:5c4d7b2438d3 173 {
switches 0:5c4d7b2438d3 174 ECC_DISABLED,
switches 0:5c4d7b2438d3 175 ECC_ENABLED,
switches 0:5c4d7b2438d3 176 } mmu_ecc_check_Type;
switches 0:5c4d7b2438d3 177
switches 0:5c4d7b2438d3 178 /* Region execution attributes */
switches 0:5c4d7b2438d3 179 typedef enum
switches 0:5c4d7b2438d3 180 {
switches 0:5c4d7b2438d3 181 EXECUTE,
switches 0:5c4d7b2438d3 182 NON_EXECUTE,
switches 0:5c4d7b2438d3 183 } mmu_execute_Type;
switches 0:5c4d7b2438d3 184
switches 0:5c4d7b2438d3 185 /* Region global attributes */
switches 0:5c4d7b2438d3 186 typedef enum
switches 0:5c4d7b2438d3 187 {
switches 0:5c4d7b2438d3 188 GLOBAL,
switches 0:5c4d7b2438d3 189 NON_GLOBAL,
switches 0:5c4d7b2438d3 190 } mmu_global_Type;
switches 0:5c4d7b2438d3 191
switches 0:5c4d7b2438d3 192 /* Region shareability attributes */
switches 0:5c4d7b2438d3 193 typedef enum
switches 0:5c4d7b2438d3 194 {
switches 0:5c4d7b2438d3 195 NON_SHARED,
switches 0:5c4d7b2438d3 196 SHARED,
switches 0:5c4d7b2438d3 197 } mmu_shared_Type;
switches 0:5c4d7b2438d3 198
switches 0:5c4d7b2438d3 199 /* Region security attributes */
switches 0:5c4d7b2438d3 200 typedef enum
switches 0:5c4d7b2438d3 201 {
switches 0:5c4d7b2438d3 202 SECURE,
switches 0:5c4d7b2438d3 203 NON_SECURE,
switches 0:5c4d7b2438d3 204 } mmu_secure_Type;
switches 0:5c4d7b2438d3 205
switches 0:5c4d7b2438d3 206 /* Region access attributes */
switches 0:5c4d7b2438d3 207 typedef enum
switches 0:5c4d7b2438d3 208 {
switches 0:5c4d7b2438d3 209 NO_ACCESS,
switches 0:5c4d7b2438d3 210 RW,
switches 0:5c4d7b2438d3 211 READ,
switches 0:5c4d7b2438d3 212 } mmu_access_Type;
switches 0:5c4d7b2438d3 213
switches 0:5c4d7b2438d3 214 /* Memory Region definition */
switches 0:5c4d7b2438d3 215 typedef struct RegionStruct {
switches 0:5c4d7b2438d3 216 mmu_region_size_Type rg_t;
switches 0:5c4d7b2438d3 217 mmu_memory_Type mem_t;
switches 0:5c4d7b2438d3 218 uint8_t domain;
switches 0:5c4d7b2438d3 219 mmu_cacheability_Type inner_norm_t;
switches 0:5c4d7b2438d3 220 mmu_cacheability_Type outer_norm_t;
switches 0:5c4d7b2438d3 221 mmu_ecc_check_Type e_t;
switches 0:5c4d7b2438d3 222 mmu_execute_Type xn_t;
switches 0:5c4d7b2438d3 223 mmu_global_Type g_t;
switches 0:5c4d7b2438d3 224 mmu_secure_Type sec_t;
switches 0:5c4d7b2438d3 225 mmu_access_Type priv_t;
switches 0:5c4d7b2438d3 226 mmu_access_Type user_t;
switches 0:5c4d7b2438d3 227 mmu_shared_Type sh_t;
switches 0:5c4d7b2438d3 228
switches 0:5c4d7b2438d3 229 } mmu_region_attributes_Type;
switches 0:5c4d7b2438d3 230
switches 0:5c4d7b2438d3 231 /** \brief Set section execution-never attribute
switches 0:5c4d7b2438d3 232
switches 0:5c4d7b2438d3 233 The function sets section execution-never attribute
switches 0:5c4d7b2438d3 234
switches 0:5c4d7b2438d3 235 \param [out] descriptor_l1 L1 descriptor.
switches 0:5c4d7b2438d3 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
switches 0:5c4d7b2438d3 237
switches 0:5c4d7b2438d3 238 \return 0
switches 0:5c4d7b2438d3 239 */
switches 0:5c4d7b2438d3 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
switches 0:5c4d7b2438d3 241 {
switches 0:5c4d7b2438d3 242 *descriptor_l1 &= SECTION_XN_MASK;
switches 0:5c4d7b2438d3 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
switches 0:5c4d7b2438d3 244 return 0;
switches 0:5c4d7b2438d3 245 }
switches 0:5c4d7b2438d3 246
switches 0:5c4d7b2438d3 247 /** \brief Set section domain
switches 0:5c4d7b2438d3 248
switches 0:5c4d7b2438d3 249 The function sets section domain
switches 0:5c4d7b2438d3 250
switches 0:5c4d7b2438d3 251 \param [out] descriptor_l1 L1 descriptor.
switches 0:5c4d7b2438d3 252 \param [in] domain Section domain
switches 0:5c4d7b2438d3 253
switches 0:5c4d7b2438d3 254 \return 0
switches 0:5c4d7b2438d3 255 */
switches 0:5c4d7b2438d3 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
switches 0:5c4d7b2438d3 257 {
switches 0:5c4d7b2438d3 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
switches 0:5c4d7b2438d3 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
switches 0:5c4d7b2438d3 260 return 0;
switches 0:5c4d7b2438d3 261 }
switches 0:5c4d7b2438d3 262
switches 0:5c4d7b2438d3 263 /** \brief Set section parity check
switches 0:5c4d7b2438d3 264
switches 0:5c4d7b2438d3 265 The function sets section parity check
switches 0:5c4d7b2438d3 266
switches 0:5c4d7b2438d3 267 \param [out] descriptor_l1 L1 descriptor.
switches 0:5c4d7b2438d3 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
switches 0:5c4d7b2438d3 269
switches 0:5c4d7b2438d3 270 \return 0
switches 0:5c4d7b2438d3 271 */
switches 0:5c4d7b2438d3 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
switches 0:5c4d7b2438d3 273 {
switches 0:5c4d7b2438d3 274 *descriptor_l1 &= SECTION_P_MASK;
switches 0:5c4d7b2438d3 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
switches 0:5c4d7b2438d3 276 return 0;
switches 0:5c4d7b2438d3 277 }
switches 0:5c4d7b2438d3 278
switches 0:5c4d7b2438d3 279 /** \brief Set section access privileges
switches 0:5c4d7b2438d3 280
switches 0:5c4d7b2438d3 281 The function sets section access privileges
switches 0:5c4d7b2438d3 282
switches 0:5c4d7b2438d3 283 \param [out] descriptor_l1 L1 descriptor.
switches 0:5c4d7b2438d3 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
switches 0:5c4d7b2438d3 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
switches 0:5c4d7b2438d3 286 \param [in] afe Access flag enable
switches 0:5c4d7b2438d3 287
switches 0:5c4d7b2438d3 288 \return 0
switches 0:5c4d7b2438d3 289 */
switches 0:5c4d7b2438d3 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
switches 0:5c4d7b2438d3 291 {
switches 0:5c4d7b2438d3 292 uint32_t ap = 0;
switches 0:5c4d7b2438d3 293
switches 0:5c4d7b2438d3 294 if (afe == 0) { //full access
switches 0:5c4d7b2438d3 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
switches 0:5c4d7b2438d3 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
switches 0:5c4d7b2438d3 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
switches 0:5c4d7b2438d3 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
switches 0:5c4d7b2438d3 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
switches 0:5c4d7b2438d3 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
switches 0:5c4d7b2438d3 301 }
switches 0:5c4d7b2438d3 302
switches 0:5c4d7b2438d3 303 else { //Simplified access
switches 0:5c4d7b2438d3 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
switches 0:5c4d7b2438d3 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
switches 0:5c4d7b2438d3 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
switches 0:5c4d7b2438d3 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
switches 0:5c4d7b2438d3 308 }
switches 0:5c4d7b2438d3 309
switches 0:5c4d7b2438d3 310 *descriptor_l1 &= SECTION_AP_MASK;
switches 0:5c4d7b2438d3 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
switches 0:5c4d7b2438d3 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
switches 0:5c4d7b2438d3 313
switches 0:5c4d7b2438d3 314 return 0;
switches 0:5c4d7b2438d3 315 }
switches 0:5c4d7b2438d3 316
switches 0:5c4d7b2438d3 317 /** \brief Set section shareability
switches 0:5c4d7b2438d3 318
switches 0:5c4d7b2438d3 319 The function sets section shareability
switches 0:5c4d7b2438d3 320
switches 0:5c4d7b2438d3 321 \param [out] descriptor_l1 L1 descriptor.
switches 0:5c4d7b2438d3 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
switches 0:5c4d7b2438d3 323
switches 0:5c4d7b2438d3 324 \return 0
switches 0:5c4d7b2438d3 325 */
switches 0:5c4d7b2438d3 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
switches 0:5c4d7b2438d3 327 {
switches 0:5c4d7b2438d3 328 *descriptor_l1 &= SECTION_S_MASK;
switches 0:5c4d7b2438d3 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
switches 0:5c4d7b2438d3 330 return 0;
switches 0:5c4d7b2438d3 331 }
switches 0:5c4d7b2438d3 332
switches 0:5c4d7b2438d3 333 /** \brief Set section Global attribute
switches 0:5c4d7b2438d3 334
switches 0:5c4d7b2438d3 335 The function sets section Global attribute
switches 0:5c4d7b2438d3 336
switches 0:5c4d7b2438d3 337 \param [out] descriptor_l1 L1 descriptor.
switches 0:5c4d7b2438d3 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
switches 0:5c4d7b2438d3 339
switches 0:5c4d7b2438d3 340 \return 0
switches 0:5c4d7b2438d3 341 */
switches 0:5c4d7b2438d3 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
switches 0:5c4d7b2438d3 343 {
switches 0:5c4d7b2438d3 344 *descriptor_l1 &= SECTION_NG_MASK;
switches 0:5c4d7b2438d3 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
switches 0:5c4d7b2438d3 346 return 0;
switches 0:5c4d7b2438d3 347 }
switches 0:5c4d7b2438d3 348
switches 0:5c4d7b2438d3 349 /** \brief Set section Security attribute
switches 0:5c4d7b2438d3 350
switches 0:5c4d7b2438d3 351 The function sets section Global attribute
switches 0:5c4d7b2438d3 352
switches 0:5c4d7b2438d3 353 \param [out] descriptor_l1 L1 descriptor.
switches 0:5c4d7b2438d3 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
switches 0:5c4d7b2438d3 355
switches 0:5c4d7b2438d3 356 \return 0
switches 0:5c4d7b2438d3 357 */
switches 0:5c4d7b2438d3 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
switches 0:5c4d7b2438d3 359 {
switches 0:5c4d7b2438d3 360 *descriptor_l1 &= SECTION_NS_MASK;
switches 0:5c4d7b2438d3 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
switches 0:5c4d7b2438d3 362 return 0;
switches 0:5c4d7b2438d3 363 }
switches 0:5c4d7b2438d3 364
switches 0:5c4d7b2438d3 365 /* Page 4k or 64k */
switches 0:5c4d7b2438d3 366 /** \brief Set 4k/64k page execution-never attribute
switches 0:5c4d7b2438d3 367
switches 0:5c4d7b2438d3 368 The function sets 4k/64k page execution-never attribute
switches 0:5c4d7b2438d3 369
switches 0:5c4d7b2438d3 370 \param [out] descriptor_l2 L2 descriptor.
switches 0:5c4d7b2438d3 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
switches 0:5c4d7b2438d3 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
switches 0:5c4d7b2438d3 373
switches 0:5c4d7b2438d3 374 \return 0
switches 0:5c4d7b2438d3 375 */
switches 0:5c4d7b2438d3 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
switches 0:5c4d7b2438d3 377 {
switches 0:5c4d7b2438d3 378 if (page == PAGE_4k)
switches 0:5c4d7b2438d3 379 {
switches 0:5c4d7b2438d3 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
switches 0:5c4d7b2438d3 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
switches 0:5c4d7b2438d3 382 }
switches 0:5c4d7b2438d3 383 else
switches 0:5c4d7b2438d3 384 {
switches 0:5c4d7b2438d3 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
switches 0:5c4d7b2438d3 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
switches 0:5c4d7b2438d3 387 }
switches 0:5c4d7b2438d3 388 return 0;
switches 0:5c4d7b2438d3 389 }
switches 0:5c4d7b2438d3 390
switches 0:5c4d7b2438d3 391 /** \brief Set 4k/64k page domain
switches 0:5c4d7b2438d3 392
switches 0:5c4d7b2438d3 393 The function sets 4k/64k page domain
switches 0:5c4d7b2438d3 394
switches 0:5c4d7b2438d3 395 \param [out] descriptor_l1 L1 descriptor.
switches 0:5c4d7b2438d3 396 \param [in] domain Page domain
switches 0:5c4d7b2438d3 397
switches 0:5c4d7b2438d3 398 \return 0
switches 0:5c4d7b2438d3 399 */
switches 0:5c4d7b2438d3 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
switches 0:5c4d7b2438d3 401 {
switches 0:5c4d7b2438d3 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
switches 0:5c4d7b2438d3 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
switches 0:5c4d7b2438d3 404 return 0;
switches 0:5c4d7b2438d3 405 }
switches 0:5c4d7b2438d3 406
switches 0:5c4d7b2438d3 407 /** \brief Set 4k/64k page parity check
switches 0:5c4d7b2438d3 408
switches 0:5c4d7b2438d3 409 The function sets 4k/64k page parity check
switches 0:5c4d7b2438d3 410
switches 0:5c4d7b2438d3 411 \param [out] descriptor_l1 L1 descriptor.
switches 0:5c4d7b2438d3 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
switches 0:5c4d7b2438d3 413
switches 0:5c4d7b2438d3 414 \return 0
switches 0:5c4d7b2438d3 415 */
switches 0:5c4d7b2438d3 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
switches 0:5c4d7b2438d3 417 {
switches 0:5c4d7b2438d3 418 *descriptor_l1 &= SECTION_P_MASK;
switches 0:5c4d7b2438d3 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
switches 0:5c4d7b2438d3 420 return 0;
switches 0:5c4d7b2438d3 421 }
switches 0:5c4d7b2438d3 422
switches 0:5c4d7b2438d3 423 /** \brief Set 4k/64k page access privileges
switches 0:5c4d7b2438d3 424
switches 0:5c4d7b2438d3 425 The function sets 4k/64k page access privileges
switches 0:5c4d7b2438d3 426
switches 0:5c4d7b2438d3 427 \param [out] descriptor_l2 L2 descriptor.
switches 0:5c4d7b2438d3 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
switches 0:5c4d7b2438d3 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
switches 0:5c4d7b2438d3 430 \param [in] afe Access flag enable
switches 0:5c4d7b2438d3 431
switches 0:5c4d7b2438d3 432 \return 0
switches 0:5c4d7b2438d3 433 */
switches 0:5c4d7b2438d3 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
switches 0:5c4d7b2438d3 435 {
switches 0:5c4d7b2438d3 436 uint32_t ap = 0;
switches 0:5c4d7b2438d3 437
switches 0:5c4d7b2438d3 438 if (afe == 0) { //full access
switches 0:5c4d7b2438d3 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
switches 0:5c4d7b2438d3 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
switches 0:5c4d7b2438d3 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
switches 0:5c4d7b2438d3 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
switches 0:5c4d7b2438d3 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
switches 0:5c4d7b2438d3 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
switches 0:5c4d7b2438d3 445 }
switches 0:5c4d7b2438d3 446
switches 0:5c4d7b2438d3 447 else { //Simplified access
switches 0:5c4d7b2438d3 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
switches 0:5c4d7b2438d3 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
switches 0:5c4d7b2438d3 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
switches 0:5c4d7b2438d3 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
switches 0:5c4d7b2438d3 452 }
switches 0:5c4d7b2438d3 453
switches 0:5c4d7b2438d3 454 *descriptor_l2 &= PAGE_AP_MASK;
switches 0:5c4d7b2438d3 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
switches 0:5c4d7b2438d3 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
switches 0:5c4d7b2438d3 457
switches 0:5c4d7b2438d3 458 return 0;
switches 0:5c4d7b2438d3 459 }
switches 0:5c4d7b2438d3 460
switches 0:5c4d7b2438d3 461 /** \brief Set 4k/64k page shareability
switches 0:5c4d7b2438d3 462
switches 0:5c4d7b2438d3 463 The function sets 4k/64k page shareability
switches 0:5c4d7b2438d3 464
switches 0:5c4d7b2438d3 465 \param [out] descriptor_l2 L2 descriptor.
switches 0:5c4d7b2438d3 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
switches 0:5c4d7b2438d3 467
switches 0:5c4d7b2438d3 468 \return 0
switches 0:5c4d7b2438d3 469 */
switches 0:5c4d7b2438d3 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
switches 0:5c4d7b2438d3 471 {
switches 0:5c4d7b2438d3 472 *descriptor_l2 &= PAGE_S_MASK;
switches 0:5c4d7b2438d3 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
switches 0:5c4d7b2438d3 474 return 0;
switches 0:5c4d7b2438d3 475 }
switches 0:5c4d7b2438d3 476
switches 0:5c4d7b2438d3 477 /** \brief Set 4k/64k page Global attribute
switches 0:5c4d7b2438d3 478
switches 0:5c4d7b2438d3 479 The function sets 4k/64k page Global attribute
switches 0:5c4d7b2438d3 480
switches 0:5c4d7b2438d3 481 \param [out] descriptor_l2 L2 descriptor.
switches 0:5c4d7b2438d3 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
switches 0:5c4d7b2438d3 483
switches 0:5c4d7b2438d3 484 \return 0
switches 0:5c4d7b2438d3 485 */
switches 0:5c4d7b2438d3 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
switches 0:5c4d7b2438d3 487 {
switches 0:5c4d7b2438d3 488 *descriptor_l2 &= PAGE_NG_MASK;
switches 0:5c4d7b2438d3 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
switches 0:5c4d7b2438d3 490 return 0;
switches 0:5c4d7b2438d3 491 }
switches 0:5c4d7b2438d3 492
switches 0:5c4d7b2438d3 493 /** \brief Set 4k/64k page Security attribute
switches 0:5c4d7b2438d3 494
switches 0:5c4d7b2438d3 495 The function sets 4k/64k page Global attribute
switches 0:5c4d7b2438d3 496
switches 0:5c4d7b2438d3 497 \param [out] descriptor_l1 L1 descriptor.
switches 0:5c4d7b2438d3 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
switches 0:5c4d7b2438d3 499
switches 0:5c4d7b2438d3 500 \return 0
switches 0:5c4d7b2438d3 501 */
switches 0:5c4d7b2438d3 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
switches 0:5c4d7b2438d3 503 {
switches 0:5c4d7b2438d3 504 *descriptor_l1 &= PAGE_NS_MASK;
switches 0:5c4d7b2438d3 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
switches 0:5c4d7b2438d3 506 return 0;
switches 0:5c4d7b2438d3 507 }
switches 0:5c4d7b2438d3 508
switches 0:5c4d7b2438d3 509
switches 0:5c4d7b2438d3 510 /** \brief Set Section memory attributes
switches 0:5c4d7b2438d3 511
switches 0:5c4d7b2438d3 512 The function sets section memory attributes
switches 0:5c4d7b2438d3 513
switches 0:5c4d7b2438d3 514 \param [out] descriptor_l1 L1 descriptor.
switches 0:5c4d7b2438d3 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
switches 0:5c4d7b2438d3 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
switches 0:5c4d7b2438d3 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
switches 0:5c4d7b2438d3 518
switches 0:5c4d7b2438d3 519 \return 0
switches 0:5c4d7b2438d3 520 */
switches 0:5c4d7b2438d3 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
switches 0:5c4d7b2438d3 522 {
switches 0:5c4d7b2438d3 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
switches 0:5c4d7b2438d3 524
switches 0:5c4d7b2438d3 525 if (STRONGLY_ORDERED == mem)
switches 0:5c4d7b2438d3 526 {
switches 0:5c4d7b2438d3 527 return 0;
switches 0:5c4d7b2438d3 528 }
switches 0:5c4d7b2438d3 529 else if (SHARED_DEVICE == mem)
switches 0:5c4d7b2438d3 530 {
switches 0:5c4d7b2438d3 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
switches 0:5c4d7b2438d3 532 }
switches 0:5c4d7b2438d3 533 else if (NON_SHARED_DEVICE == mem)
switches 0:5c4d7b2438d3 534 {
switches 0:5c4d7b2438d3 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
switches 0:5c4d7b2438d3 536 }
switches 0:5c4d7b2438d3 537 else if (NORMAL == mem)
switches 0:5c4d7b2438d3 538 {
switches 0:5c4d7b2438d3 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
switches 0:5c4d7b2438d3 540 switch(inner)
switches 0:5c4d7b2438d3 541 {
switches 0:5c4d7b2438d3 542 case NON_CACHEABLE:
switches 0:5c4d7b2438d3 543 break;
switches 0:5c4d7b2438d3 544 case WB_WA:
switches 0:5c4d7b2438d3 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
switches 0:5c4d7b2438d3 546 break;
switches 0:5c4d7b2438d3 547 case WT:
switches 0:5c4d7b2438d3 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
switches 0:5c4d7b2438d3 549 break;
switches 0:5c4d7b2438d3 550 case WB_NO_WA:
switches 0:5c4d7b2438d3 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
switches 0:5c4d7b2438d3 552 break;
switches 0:5c4d7b2438d3 553 }
switches 0:5c4d7b2438d3 554 switch(outer)
switches 0:5c4d7b2438d3 555 {
switches 0:5c4d7b2438d3 556 case NON_CACHEABLE:
switches 0:5c4d7b2438d3 557 break;
switches 0:5c4d7b2438d3 558 case WB_WA:
switches 0:5c4d7b2438d3 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
switches 0:5c4d7b2438d3 560 break;
switches 0:5c4d7b2438d3 561 case WT:
switches 0:5c4d7b2438d3 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
switches 0:5c4d7b2438d3 563 break;
switches 0:5c4d7b2438d3 564 case WB_NO_WA:
switches 0:5c4d7b2438d3 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
switches 0:5c4d7b2438d3 566 break;
switches 0:5c4d7b2438d3 567 }
switches 0:5c4d7b2438d3 568 }
switches 0:5c4d7b2438d3 569
switches 0:5c4d7b2438d3 570 return 0;
switches 0:5c4d7b2438d3 571 }
switches 0:5c4d7b2438d3 572
switches 0:5c4d7b2438d3 573 /** \brief Set 4k/64k page memory attributes
switches 0:5c4d7b2438d3 574
switches 0:5c4d7b2438d3 575 The function sets 4k/64k page memory attributes
switches 0:5c4d7b2438d3 576
switches 0:5c4d7b2438d3 577 \param [out] descriptor_l2 L2 descriptor.
switches 0:5c4d7b2438d3 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
switches 0:5c4d7b2438d3 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
switches 0:5c4d7b2438d3 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
switches 0:5c4d7b2438d3 581
switches 0:5c4d7b2438d3 582 \return 0
switches 0:5c4d7b2438d3 583 */
switches 0:5c4d7b2438d3 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
switches 0:5c4d7b2438d3 585 {
switches 0:5c4d7b2438d3 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
switches 0:5c4d7b2438d3 587
switches 0:5c4d7b2438d3 588 if (page == PAGE_64k)
switches 0:5c4d7b2438d3 589 {
switches 0:5c4d7b2438d3 590 //same as section
switches 0:5c4d7b2438d3 591 __memory_section(descriptor_l2, mem, outer, inner);
switches 0:5c4d7b2438d3 592 }
switches 0:5c4d7b2438d3 593 else
switches 0:5c4d7b2438d3 594 {
switches 0:5c4d7b2438d3 595 if (STRONGLY_ORDERED == mem)
switches 0:5c4d7b2438d3 596 {
switches 0:5c4d7b2438d3 597 return 0;
switches 0:5c4d7b2438d3 598 }
switches 0:5c4d7b2438d3 599 else if (SHARED_DEVICE == mem)
switches 0:5c4d7b2438d3 600 {
switches 0:5c4d7b2438d3 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
switches 0:5c4d7b2438d3 602 }
switches 0:5c4d7b2438d3 603 else if (NON_SHARED_DEVICE == mem)
switches 0:5c4d7b2438d3 604 {
switches 0:5c4d7b2438d3 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
switches 0:5c4d7b2438d3 606 }
switches 0:5c4d7b2438d3 607 else if (NORMAL == mem)
switches 0:5c4d7b2438d3 608 {
switches 0:5c4d7b2438d3 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
switches 0:5c4d7b2438d3 610 switch(inner)
switches 0:5c4d7b2438d3 611 {
switches 0:5c4d7b2438d3 612 case NON_CACHEABLE:
switches 0:5c4d7b2438d3 613 break;
switches 0:5c4d7b2438d3 614 case WB_WA:
switches 0:5c4d7b2438d3 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
switches 0:5c4d7b2438d3 616 break;
switches 0:5c4d7b2438d3 617 case WT:
switches 0:5c4d7b2438d3 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
switches 0:5c4d7b2438d3 619 break;
switches 0:5c4d7b2438d3 620 case WB_NO_WA:
switches 0:5c4d7b2438d3 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
switches 0:5c4d7b2438d3 622 break;
switches 0:5c4d7b2438d3 623 }
switches 0:5c4d7b2438d3 624 switch(outer)
switches 0:5c4d7b2438d3 625 {
switches 0:5c4d7b2438d3 626 case NON_CACHEABLE:
switches 0:5c4d7b2438d3 627 break;
switches 0:5c4d7b2438d3 628 case WB_WA:
switches 0:5c4d7b2438d3 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
switches 0:5c4d7b2438d3 630 break;
switches 0:5c4d7b2438d3 631 case WT:
switches 0:5c4d7b2438d3 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
switches 0:5c4d7b2438d3 633 break;
switches 0:5c4d7b2438d3 634 case WB_NO_WA:
switches 0:5c4d7b2438d3 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
switches 0:5c4d7b2438d3 636 break;
switches 0:5c4d7b2438d3 637 }
switches 0:5c4d7b2438d3 638 }
switches 0:5c4d7b2438d3 639 }
switches 0:5c4d7b2438d3 640
switches 0:5c4d7b2438d3 641 return 0;
switches 0:5c4d7b2438d3 642 }
switches 0:5c4d7b2438d3 643
switches 0:5c4d7b2438d3 644 /** \brief Create a L1 section descriptor
switches 0:5c4d7b2438d3 645
switches 0:5c4d7b2438d3 646 The function creates a section descriptor.
switches 0:5c4d7b2438d3 647
switches 0:5c4d7b2438d3 648 Assumptions:
switches 0:5c4d7b2438d3 649 - 16MB super sections not supported
switches 0:5c4d7b2438d3 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
switches 0:5c4d7b2438d3 651 - Functions always return 0
switches 0:5c4d7b2438d3 652
switches 0:5c4d7b2438d3 653 \param [out] descriptor L1 descriptor
switches 0:5c4d7b2438d3 654 \param [out] descriptor2 L2 descriptor
switches 0:5c4d7b2438d3 655 \param [in] reg Section attributes
switches 0:5c4d7b2438d3 656
switches 0:5c4d7b2438d3 657 \return 0
switches 0:5c4d7b2438d3 658 */
switches 0:5c4d7b2438d3 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
switches 0:5c4d7b2438d3 660 {
switches 0:5c4d7b2438d3 661 *descriptor = 0;
switches 0:5c4d7b2438d3 662
switches 0:5c4d7b2438d3 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
switches 0:5c4d7b2438d3 664 __xn_section(descriptor,reg.xn_t);
switches 0:5c4d7b2438d3 665 __domain_section(descriptor, reg.domain);
switches 0:5c4d7b2438d3 666 __p_section(descriptor, reg.e_t);
switches 0:5c4d7b2438d3 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
switches 0:5c4d7b2438d3 668 __shared_section(descriptor,reg.sh_t);
switches 0:5c4d7b2438d3 669 __global_section(descriptor,reg.g_t);
switches 0:5c4d7b2438d3 670 __secure_section(descriptor,reg.sec_t);
switches 0:5c4d7b2438d3 671 *descriptor &= SECTION_MASK;
switches 0:5c4d7b2438d3 672 *descriptor |= SECTION_DESCRIPTOR;
switches 0:5c4d7b2438d3 673
switches 0:5c4d7b2438d3 674 return 0;
switches 0:5c4d7b2438d3 675
switches 0:5c4d7b2438d3 676 }
switches 0:5c4d7b2438d3 677
switches 0:5c4d7b2438d3 678
switches 0:5c4d7b2438d3 679 /** \brief Create a L1 and L2 4k/64k page descriptor
switches 0:5c4d7b2438d3 680
switches 0:5c4d7b2438d3 681 The function creates a 4k/64k page descriptor.
switches 0:5c4d7b2438d3 682 Assumptions:
switches 0:5c4d7b2438d3 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
switches 0:5c4d7b2438d3 684 - Functions always return 0
switches 0:5c4d7b2438d3 685
switches 0:5c4d7b2438d3 686 \param [out] descriptor L1 descriptor
switches 0:5c4d7b2438d3 687 \param [out] descriptor2 L2 descriptor
switches 0:5c4d7b2438d3 688 \param [in] reg 4k/64k page attributes
switches 0:5c4d7b2438d3 689
switches 0:5c4d7b2438d3 690 \return 0
switches 0:5c4d7b2438d3 691 */
switches 0:5c4d7b2438d3 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
switches 0:5c4d7b2438d3 693 {
switches 0:5c4d7b2438d3 694 *descriptor = 0;
switches 0:5c4d7b2438d3 695 *descriptor2 = 0;
switches 0:5c4d7b2438d3 696
switches 0:5c4d7b2438d3 697 switch (reg.rg_t)
switches 0:5c4d7b2438d3 698 {
switches 0:5c4d7b2438d3 699 case PAGE_4k:
switches 0:5c4d7b2438d3 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
switches 0:5c4d7b2438d3 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
switches 0:5c4d7b2438d3 702 __domain_page(descriptor, reg.domain);
switches 0:5c4d7b2438d3 703 __p_page(descriptor, reg.e_t);
switches 0:5c4d7b2438d3 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
switches 0:5c4d7b2438d3 705 __shared_page(descriptor2,reg.sh_t);
switches 0:5c4d7b2438d3 706 __global_page(descriptor2,reg.g_t);
switches 0:5c4d7b2438d3 707 __secure_page(descriptor,reg.sec_t);
switches 0:5c4d7b2438d3 708 *descriptor &= PAGE_L1_MASK;
switches 0:5c4d7b2438d3 709 *descriptor |= PAGE_L1_DESCRIPTOR;
switches 0:5c4d7b2438d3 710 *descriptor2 &= PAGE_L2_4K_MASK;
switches 0:5c4d7b2438d3 711 *descriptor2 |= PAGE_L2_4K_DESC;
switches 0:5c4d7b2438d3 712 break;
switches 0:5c4d7b2438d3 713
switches 0:5c4d7b2438d3 714 case PAGE_64k:
switches 0:5c4d7b2438d3 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
switches 0:5c4d7b2438d3 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
switches 0:5c4d7b2438d3 717 __domain_page(descriptor, reg.domain);
switches 0:5c4d7b2438d3 718 __p_page(descriptor, reg.e_t);
switches 0:5c4d7b2438d3 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
switches 0:5c4d7b2438d3 720 __shared_page(descriptor2,reg.sh_t);
switches 0:5c4d7b2438d3 721 __global_page(descriptor2,reg.g_t);
switches 0:5c4d7b2438d3 722 __secure_page(descriptor,reg.sec_t);
switches 0:5c4d7b2438d3 723 *descriptor &= PAGE_L1_MASK;
switches 0:5c4d7b2438d3 724 *descriptor |= PAGE_L1_DESCRIPTOR;
switches 0:5c4d7b2438d3 725 *descriptor2 &= PAGE_L2_64K_MASK;
switches 0:5c4d7b2438d3 726 *descriptor2 |= PAGE_L2_64K_DESC;
switches 0:5c4d7b2438d3 727 break;
switches 0:5c4d7b2438d3 728
switches 0:5c4d7b2438d3 729 case SECTION:
switches 0:5c4d7b2438d3 730 //error
switches 0:5c4d7b2438d3 731 break;
switches 0:5c4d7b2438d3 732
switches 0:5c4d7b2438d3 733 }
switches 0:5c4d7b2438d3 734
switches 0:5c4d7b2438d3 735 return 0;
switches 0:5c4d7b2438d3 736
switches 0:5c4d7b2438d3 737 }
switches 0:5c4d7b2438d3 738
switches 0:5c4d7b2438d3 739 /** \brief Create a 1MB Section
switches 0:5c4d7b2438d3 740
switches 0:5c4d7b2438d3 741 \param [in] ttb Translation table base address
switches 0:5c4d7b2438d3 742 \param [in] base_address Section base address
switches 0:5c4d7b2438d3 743 \param [in] count Number of sections to create
switches 0:5c4d7b2438d3 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
switches 0:5c4d7b2438d3 745
switches 0:5c4d7b2438d3 746 */
switches 0:5c4d7b2438d3 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
switches 0:5c4d7b2438d3 748 {
switches 0:5c4d7b2438d3 749 uint32_t offset;
switches 0:5c4d7b2438d3 750 uint32_t entry;
switches 0:5c4d7b2438d3 751 uint32_t i;
switches 0:5c4d7b2438d3 752
switches 0:5c4d7b2438d3 753 offset = base_address >> 20;
switches 0:5c4d7b2438d3 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
switches 0:5c4d7b2438d3 755
switches 0:5c4d7b2438d3 756 //4 bytes aligned
switches 0:5c4d7b2438d3 757 ttb = ttb + offset;
switches 0:5c4d7b2438d3 758
switches 0:5c4d7b2438d3 759 for (i = 0; i < count; i++ )
switches 0:5c4d7b2438d3 760 {
switches 0:5c4d7b2438d3 761 //4 bytes aligned
switches 0:5c4d7b2438d3 762 *ttb++ = entry;
switches 0:5c4d7b2438d3 763 entry += OFFSET_1M;
switches 0:5c4d7b2438d3 764 }
switches 0:5c4d7b2438d3 765 }
switches 0:5c4d7b2438d3 766
switches 0:5c4d7b2438d3 767 /** \brief Create a 4k page entry
switches 0:5c4d7b2438d3 768
switches 0:5c4d7b2438d3 769 \param [in] ttb L1 table base address
switches 0:5c4d7b2438d3 770 \param [in] base_address 4k base address
switches 0:5c4d7b2438d3 771 \param [in] count Number of 4k pages to create
switches 0:5c4d7b2438d3 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
switches 0:5c4d7b2438d3 773 \param [in] ttb_l2 L2 table base address
switches 0:5c4d7b2438d3 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
switches 0:5c4d7b2438d3 775
switches 0:5c4d7b2438d3 776 */
switches 0:5c4d7b2438d3 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
switches 0:5c4d7b2438d3 778 {
switches 0:5c4d7b2438d3 779
switches 0:5c4d7b2438d3 780 uint32_t offset, offset2;
switches 0:5c4d7b2438d3 781 uint32_t entry, entry2;
switches 0:5c4d7b2438d3 782 uint32_t i;
switches 0:5c4d7b2438d3 783
switches 0:5c4d7b2438d3 784
switches 0:5c4d7b2438d3 785 offset = base_address >> 20;
switches 0:5c4d7b2438d3 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
switches 0:5c4d7b2438d3 787
switches 0:5c4d7b2438d3 788 //4 bytes aligned
switches 0:5c4d7b2438d3 789 ttb += offset;
switches 0:5c4d7b2438d3 790 //create l1_entry
switches 0:5c4d7b2438d3 791 *ttb = entry;
switches 0:5c4d7b2438d3 792
switches 0:5c4d7b2438d3 793 offset2 = (base_address & 0xff000) >> 12;
switches 0:5c4d7b2438d3 794 ttb_l2 += offset2;
switches 0:5c4d7b2438d3 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
switches 0:5c4d7b2438d3 796 for (i = 0; i < count; i++ )
switches 0:5c4d7b2438d3 797 {
switches 0:5c4d7b2438d3 798 //4 bytes aligned
switches 0:5c4d7b2438d3 799 *ttb_l2++ = entry2;
switches 0:5c4d7b2438d3 800 entry2 += OFFSET_4K;
switches 0:5c4d7b2438d3 801 }
switches 0:5c4d7b2438d3 802 }
switches 0:5c4d7b2438d3 803
switches 0:5c4d7b2438d3 804 /** \brief Create a 64k page entry
switches 0:5c4d7b2438d3 805
switches 0:5c4d7b2438d3 806 \param [in] ttb L1 table base address
switches 0:5c4d7b2438d3 807 \param [in] base_address 64k base address
switches 0:5c4d7b2438d3 808 \param [in] count Number of 64k pages to create
switches 0:5c4d7b2438d3 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
switches 0:5c4d7b2438d3 810 \param [in] ttb_l2 L2 table base address
switches 0:5c4d7b2438d3 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
switches 0:5c4d7b2438d3 812
switches 0:5c4d7b2438d3 813 */
switches 0:5c4d7b2438d3 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
switches 0:5c4d7b2438d3 815 {
switches 0:5c4d7b2438d3 816 uint32_t offset, offset2;
switches 0:5c4d7b2438d3 817 uint32_t entry, entry2;
switches 0:5c4d7b2438d3 818 uint32_t i,j;
switches 0:5c4d7b2438d3 819
switches 0:5c4d7b2438d3 820
switches 0:5c4d7b2438d3 821 offset = base_address >> 20;
switches 0:5c4d7b2438d3 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
switches 0:5c4d7b2438d3 823
switches 0:5c4d7b2438d3 824 //4 bytes aligned
switches 0:5c4d7b2438d3 825 ttb += offset;
switches 0:5c4d7b2438d3 826 //create l1_entry
switches 0:5c4d7b2438d3 827 *ttb = entry;
switches 0:5c4d7b2438d3 828
switches 0:5c4d7b2438d3 829 offset2 = (base_address & 0xff000) >> 12;
switches 0:5c4d7b2438d3 830 ttb_l2 += offset2;
switches 0:5c4d7b2438d3 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
switches 0:5c4d7b2438d3 832 for (i = 0; i < count; i++ )
switches 0:5c4d7b2438d3 833 {
switches 0:5c4d7b2438d3 834 //create 16 entries
switches 0:5c4d7b2438d3 835 for (j = 0; j < 16; j++)
switches 0:5c4d7b2438d3 836 //4 bytes aligned
switches 0:5c4d7b2438d3 837 *ttb_l2++ = entry2;
switches 0:5c4d7b2438d3 838 entry2 += OFFSET_64K;
switches 0:5c4d7b2438d3 839 }
switches 0:5c4d7b2438d3 840 }
switches 0:5c4d7b2438d3 841
switches 0:5c4d7b2438d3 842 /*@} end of MMU_Functions */
switches 0:5c4d7b2438d3 843 #endif
switches 0:5c4d7b2438d3 844
switches 0:5c4d7b2438d3 845 #ifdef __cplusplus
switches 0:5c4d7b2438d3 846 }
switches 0:5c4d7b2438d3 847 #endif